Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device.An active layer of the array substrate comprises a channel region, a source electrode connecting region and a drain electrode connecting region, the source electrode connecting region and the drain electrode connecting region are located on the two opposite sides of the channel region, a source electrode is connected with the source electrode connecting region, a drain electrode is connected with the drain electrode connecting region, and the active layer is provided with at least one through hole; the orthographic projection of the through hole on the substrate is at least partially located in the orthographic projection range of the channel region on the substrate or the orthographic projection range of the drain electrode connection region on the substrate; holes are punched in the channel region or the drain electrode connecting region of the active layer so as to disperse a transverse electric field, reduce the hot carrier effect and improve the performance of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] For a low temperature poly silicon (LTPS) thin film transistor (TFT), as a source-drain voltage (V ds ) increases, a channel lateral electric field increases, a carrier accelerates to obtain energy to form a knock-on ionization phenomenon, and extra carriers are formed. When V ds is large, the lateral electric field is too strong, which easily leads to a hot carrier effect, and further leads to device aging, threshold voltage (V th ) shift, screen brightness non-uniformity and other problems. SUMMARY

[0003] Embodiments of the present application provide an array substrate, a display panel and a display device, which can effectively improve the hot carrier effect caused by the too strong lateral electric field, and further improve the performance of the display panel.

[0004] The present application provides an array substrate, which comprises: a substrate; an active layer disposed above the substrate; and a source and a drain disposed on a side of the active layer away from the substrate; wherein the active layer comprises a channel region and a source connection region and a drain connection region located on opposite sides of the channel region in a first direction, the first direction being an extension direction from the source to the drain, the source being connected to the source connection region, and the drain being connected to the drain connection region; The active layer is provided with at least one through hole, and a projection of the through hole on the substrate is at least partially located in a projection range of the channel region on the substrate or a projection range of the drain connection region on the substrate.

[0005] In some embodiments, the projection of the through hole on the substrate is located between the projection of the source on the substrate and the projection of the drain on the substrate; wherein a minimum distance between the projection of the through hole on the substrate and the projection of the drain on the substrate is less than or equal to a minimum distance between the projection of the through hole on the substrate and the projection of the source on the substrate.

[0006] In some embodiments, the center of the orthographic projection of the via on the substrate is located on the line connecting the center of the orthographic projection of the source electrode on the substrate and the center of the orthographic projection of the drain electrode on the substrate.

[0007] In some embodiments, the orthogonal projection of the via on the substrate lies within the orthogonal projection range of the drain on the substrate.

[0008] In some embodiments, the array substrate further includes: An insulating layer is disposed on the side of the active layer near the source and the drain. The insulating layer has a via, and the orthographic projection of the via on the substrate is within the orthographic projection range of the via on the substrate. The drain electrode extends through the via into the through hole and is connected to the active layer.

[0009] In some embodiments, the drain electrode includes a first sub-part and a second sub-part disposed around the first sub-part, the first sub-part being disposed within the through hole, and the second sub-part extending along the inner sidewall of the through hole and the inner sidewall of the through hole, wherein one end of the second sub-part extends into the through hole and connects to the first sub-part, and the other end of the second sub-part extends above the insulating layer.

[0010] In some embodiments, the orthographic projection of the through-hole onto the substrate is circular; And / or, the orthographic projection of the source electrode onto the substrate is circular; And / or, the orthogonal projection of the drain on the substrate is circular.

[0011] In some embodiments, the active layer includes a main body and at least one extension connected to the main body, the extension being located on at least one side of the main body in a second direction perpendicular to the first direction; The extension is located on at least one side of the through hole in the second direction, and in the second direction, the minimum distance from the edge of the extension to the through hole is greater than the minimum distance from the edge of the main body portion on the same side to the through hole.

[0012] This application provides a display panel, which includes an array substrate as described above, and a display layer disposed on the array substrate.

[0013] This application provides a display device, which includes a display panel as described above.

[0014] This application provides an array substrate, a display panel, and a display device. The active layer of the array substrate includes a channel region and source connection regions and drain connection regions located on opposite sides of the channel region. The source and source connection regions are connected, and the drain and drain connection regions are connected. The active layer has at least one via, and the orthographic projection of the via onto the substrate is at least partially within the orthographic projection range of the channel region or the drain connection region onto the substrate. By creating a via in the channel region or drain connection region of the active layer, this application disperses the lateral electric field, weakens the lateral electric field, effectively reduces the hot carrier effect, and thus improves the performance of the thin-film transistor, enhancing the display effect of the display panel and display device. This avoids aging and threshold voltage (V) issues caused by the hot carrier effect. th Issues such as screen offset and uneven screen brightness. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0017] Figure 1 This is a top view schematic diagram of the active layer, source, and drain of a thin-film transistor in the prior art; Figure 2 It is a current-voltage (I) ... ds -V ds (Line graph) Figure 3 This is a schematic cross-sectional view of an array substrate provided in an embodiment of this application; Figure 4 yes Figure 3 A top view of the active layer, source, and drain of an array substrate provided in the embodiment; Figure 5 This is a cross-sectional structural diagram of another array substrate provided in an embodiment of this application; Figure 6 yes Figure 5 A top view of the active layer, source, and drain of an array substrate provided in the embodiment; Figure 7 yes Figure 6 Schematic diagram of the cross section at point AA; Figure 8This is a schematic diagram of the structure of a display device provided in an embodiment of this application; Figure 9 This is a schematic diagram of another display device provided in an embodiment of this application.

[0018] Explanation of reference numerals in the attached figures: 10. Display panel; 100. Array substrate; 110. Substrate; 120. Active layer; 121. Channel region; 122. Source connection region; 123. Drain connection region; 124. Main body; 125. Extension; 130. Gate; 131. First gate; 132. Second gate; 141. Source; 142. Drain; 1421. First sub-section; 1422. Second sub-section; 150. Through-hole; 160. Insulation Layers; 161, First gate insulating layer; 162, Second gate insulating layer; 163, Interlayer insulating layer; 164, Via; 171, Passivation layer; 172, First planarization layer; 173, Second planarization layer; 174, Connecting electrode; 175, Third planarization layer; 180, Display layer; 181, Anode; 182, Pixel definition layer; 183, Light-emitting functional layer; 184, Cathode; 185, Encapsulation layer; 190, Opposing substrate. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0020] Please refer to Figures 1-2 , Figure 1 This is a top view of an active layer 120, a source 141, and a drain 142 of a thin-film transistor in the prior art. The thin-film transistor includes an active layer 120 and a source 141 and a drain 142 disposed on the active layer 120. Figure 2 yes Figure 1 The thin-film transistor shown has I ds -V ds The graph shows the change in source-drain voltage (V) ds ) increases, the transverse electric field of the channel (such as Figure 2 As the dashed line E increases, charge carriers accelerate and gain energy, undergoing impact ionization to form excess charge carriers. These excess charge carriers are separated by the electric field and participate in conduction, contributing additional current. This additional current, combined with the intrinsic current in the saturation region, causes the output current I to increase. ds With V ds The increase and continuous rise indicate current unsaturation (e.g.) Figure 2The curve follows V ds (Significant warping appeared in the later stages of the increase). Furthermore, the excessively strong lateral electric field leading to hot carrier effects and unsaturated output current can cause device aging and a decrease in threshold voltage (V). th Issues such as screen offset and uneven screen brightness.

[0021] To address the aforementioned problems, this application provides an array substrate 100, please refer to... Figures 3-4 The array substrate 100 includes a substrate 110, an active layer 120, a gate 130, a source 141, and a drain 142. The active layer 120 is disposed above the substrate 110; the gate 130 is disposed on the side of the active layer 120 near the substrate 110, or on the side of the active layer 120 away from the substrate 110; the source 141 and drain 142 are disposed on the side of the active layer 120 away from the substrate 110; wherein, the active layer 120 includes a channel region 121 and source connection regions 122 and drain connection regions 123 located on opposite sides of the channel region 121 in a first direction X, where the first direction X is from the source 141... In the extension direction from 41 to the drain 142, the source 141 is connected to the source connection region 122, and the drain 142 is connected to the drain connection region 123; the active layer 120 is provided with at least one via 150, that is, the via 150 penetrates the active layer 120 along the thickness direction of the active layer 120, and the orthogonal projection of the via 150 on the substrate 110 is at least partially located within the orthogonal projection range of the channel region 121 on the substrate 110 or the orthogonal projection range of the drain connection region 123 on the substrate 110.

[0022] The substrate 110 can be a rigid substrate, such as glass, or a flexible substrate, such as polyimide, but is not limited thereto.

[0023] The active layer 120 includes a channel region 121, a source connection region 122, and a drain connection region 123. The channel region 121 is the active layer 120 region located between the source 141 and the drain 142, and serves as the core channel for carrier (electron or hole) migration under the voltage control of the gate 130. The source connection region 122 is the transition region where the source 141 and the active layer 120 are electrically connected, i.e., the starting point for carrier injection into the channel region 121. The drain connection region 123 is the transition region where the drain 142 and the active layer 120 are electrically connected, i.e., the terminal point for carrier exiting the channel region 121. The material of the active layer 120 can be low-temperature polysilicon (LTPS), but is not limited to this.

[0024] The gate 130 can be disposed on the side of the active layer 120 near the substrate 110 to form a bottom gate structure, or the gate 130 can be disposed on the side of the active layer 120 away from the substrate 110 to form a top gate structure; this application does not impose any limitations. The material of the gate 130 can be a metal or a metal alloy, such as aluminum, molybdenum, or an aluminum-molybdenum alloy, but is not limited thereto. It is understood that the array substrate 100 may include one or more gates 130, for example, as... Figure 3 As shown, the array substrate 100 may include a first gate 131 and a second gate 132, with the second gate 132 located on the side of the first gate 131 away from the substrate 110.

[0025] The source 141 and drain 142 can be disposed on the side of the gate 130 away from the active layer 120. The source 141 is electrically connected to the source connection region 122 of the active layer 120, and the drain 142 is electrically connected to the drain connection region 123 of the active layer 120 to achieve carrier transport. The materials of the source 141 and drain 142 can be metals or metal alloys, such as copper, molybdenum, titanium, or alloys of the above metals, but are not limited thereto.

[0026] The active layer 120, gate 130, source 141 and drain 142 constitute a thin film transistor (TFT). One or more thin film transistors may be disposed on the substrate 110, that is, the array substrate 100 may include one or more thin film transistors. Specifically, the number of thin film transistors included in the array substrate 100 is not limited in this application.

[0027] Furthermore, the array substrate 100 also includes an insulating layer 160, which is disposed on the side of the active layer 120 near the source electrode 141 and the drain electrode 142. The insulating layer 160 may include one or more film layers. For example, such as Figure 3 As shown, the insulating layer 160 may include a first gate insulating layer 161, a second gate insulating layer 162, and an interlayer insulating layer 163, etc. The first gate insulating layer 161 is disposed between the active layer 120 and the first gate 131, the second gate insulating layer 162 is disposed between the second gate 132 and the first gate insulating layer 161, and the interlayer insulating layer 163 is disposed between the second gate 132 and the source 141 and the drain 142.

[0028] This application utilizes vias 150 in the channel region 121 or drain connection region 123 of the active layer 120 to disperse the lateral electric field, thereby weakening the lateral electric field and effectively reducing the hot carrier effect. This improves the performance of the thin-film transistor, avoiding aging and threshold voltage (V) issues caused by the hot carrier effect and current unsaturation. th Issues such as screen offset and uneven screen brightness. For details, please refer to... Figure 4 and Figure 6When a via 150 is provided on the active layer 120, the original horizontal straight electric field path between the source 141 and the drain 142 will change and be dispersed to both sides of the via 150 to form a curved electric field path. By dispersing the lateral electric field, the electric field strength between the source 141 and the drain 142 can be weakened, thereby reducing the hot carrier effect.

[0029] In this application, the via 150 being at least partially located in the channel region 121 or the drain connection region 123 means that the via 150 may be completely located within the channel region 121 or completely located within the drain connection region 123; or, the via 150 may be partially located within the channel region 121 and partially located outside the channel region 121; or, the via 150 may be partially located within the drain connection region 123 and partially located outside the drain connection region 123. Having the via 150 at least partially located in the channel region 121 or the drain connection region 123 can alter the original lateral electric field path, dispersing the lateral electric field and weakening its intensity, thereby reducing the hot carrier effect.

[0030] In some embodiments, please refer to Figures 3-4 The orthographic projection of via 150 on substrate 110 lies between the orthographic projections of source 141 and drain 142 on substrate 110, meaning via 150 is located in channel region 121 and does not overlap with source connection region 122 and drain connection region 123. Please refer to... Figure 4 By providing a via 150 in the channel region 121 of the active layer 120 between the source 141 and the drain 142, the electric field between the source 141 and the drain 142 is dispersed to both sides of the via 150 when passing through it (e.g., ...). Figure 4 As shown by the dashed line E, a curved electric field path is formed. The dispersion of the electric field and the extension of the electric field path weaken the electric field strength, thereby reducing the hot carrier effect. By setting a via 150 in the channel region 121, the hot carrier effect is effectively improved without affecting the fabrication process of other structures such as the source 141 and drain 142, making the process simple to operate.

[0031] In some embodiments, the channel region 121 of the active layer 120 may also be provided with a plurality of vias 150. Furthermore, the plurality of vias may be arranged along the first direction X. When a plurality of vias 150 are provided, the lateral electric field can also be dispersed, and the hot carrier effect can be improved.

[0032] In some embodiments, please refer to Figure 4The minimum distance L1 between the orthographic projection of via 150 on substrate 110 and the orthographic projection of drain 142 on substrate 110 is less than or equal to the minimum distance L2 between the orthographic projection of via 150 on substrate 110 and the orthographic projection of source 141 on substrate 110. Specifically, the minimum distance L1 between the orthographic projection of via 150 on substrate 110 and the orthographic projection of drain 142 on substrate 110 refers to the minimum distance between the edge of the orthographic projection of via 150 and the edge of the orthographic projection of drain 142, and the minimum distance L2 between the orthographic projection of via 150 on substrate 110 and the orthographic projection of source 141 on substrate 110 refers to the minimum distance between the edge of the orthographic projection of via 150 and the edge of the orthographic projection of source 141. Because the electric field strength is greater near the drain 142, charge carriers are accelerated and undergo impact ionization in this electric field, making it easier to form excess charge carriers. When the via 150 is positioned close to the drain 142, it is more beneficial to reduce the electric field strength near the drain 142, thereby effectively improving the hot carrier effect. Specifically, the distance L1 between the via 150 and the drain 142 is 20% to 50% of the distance L between the source 141 and the drain 142. For example, L1 / L can be 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc., but is not limited to these. When the ratio of L1 / L is in the range of 20% to 50%, it is more beneficial to reduce the transverse electric field strength, thereby effectively improving the hot carrier effect.

[0033] In some embodiments, please refer to Figure 4 The distance between the source 141 and the drain 142 ranges from 2 μm to 20 μm. The distance between the source 141 and the drain 142 is also the length L of the channel region 121, which ranges from 2 μm to 20 μm. For example, L can be 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, etc., but is not limited to this.

[0034] In some embodiments, please refer to Figure 4 The center O of the orthographic projection of the via 150 onto the substrate 110 is located at the line O connecting the center of the orthographic projection of the source 141 onto the substrate 110 and the center of the orthographic projection of the drain 142 onto the substrate 110. S -O D Above, i.e., O, O S And O D Being on the same straight line helps to evenly distribute the transverse electric field.

[0035] For further details, please refer to Figure 4 The orthographic projection of the via 150 onto the substrate 110 can be about the center line O. S -O DSymmetrical arrangement. When via 150 is located between source 141 and drain 142, and via 150 is about the center line O S -O D When symmetrically arranged, the electric field between the source 141 and the drain 142 can be uniformly distributed on both sides of the via 150, so as to ensure the uniformity and stability of the electric field distribution between the source 141 and the drain 142, thereby ensuring the stability of the thin film transistor.

[0036] For further details, please refer to Figure 4 The source 141 and drain 142 have the same size to further improve the uniformity of electric field distribution, thereby improving the electrical performance of the thin film transistor.

[0037] In some embodiments, please refer to Figures 5-6 The orthographic projection of via 150 on substrate 110 lies within the orthographic projection range of drain 142 on substrate 110, in order to reduce the electric field strength at drain 142. Please refer to... Figure 6 At the drain 142 end, the electric field will be dispersed on both sides of the via 150. The dispersion of the electric field at the drain 142 end effectively reduces the electric field strength at the drain 142 end, thereby effectively reducing the hot carrier effect.

[0038] In some embodiments, please refer to Figure 5 The insulating layer 160 is provided with a via 164. The orthographic projection of the via 150 on the substrate 110 is within the orthographic projection range of the via 164 on the substrate 110, that is, the via 150 and the via 164 are connected. The via 164 penetrates the insulating layer 160 and communicates with the via 150, so that the drain 142 extends through the via 164 into the via 150 and connects with the active layer 120. Specifically, the drain 142 contacts the sidewall of the active layer 120 exposed in the via 150 to achieve an electrical connection between the drain 142 and the active layer 120.

[0039] In some embodiments, please refer to Figure 5 The drain 142 can completely fill the via 164 and the through-hole 150 to achieve electrical connection between the drain 142 and the active layer 120.

[0040] In some embodiments, please refer to Figure 7The drain 142 can also be partially disposed within the via 164 and the through-hole 150 to achieve electrical connection between the drain 142 and the active layer 120. Specifically, the drain 142 includes a first sub-part 1421 and a second sub-part 1422 disposed around the first sub-part 1421; the first sub-part 1421 is disposed within the through-hole 150, for example, the first sub-part 1421 can contact the surface of the substrate 110 exposed by the through-hole 150; the second sub-part 1422 extends along the inner sidewall of the via 164 and the inner sidewall of the through-hole 150, wherein one end of the second sub-part 1422 extends into the through-hole 150 and connects with the first sub-part 1421, and the other end of the second sub-part 1422 extends above the insulating layer 160, reserving a portion of the drain 142 above the insulating layer 160 to facilitate connection between the drain 142 and the electrode layer above it. During the process of forming the insulating layer, since the via 150 has a certain size, when the via 150 is large and the thickness of the deposited drain electrode 142 metal layer is thin, the drain electrode 142 metal layer deposited at the via 150 will be laid along the inner sidewall of the via 164 and the inner sidewall of the via 150, without completely filling the entire space of the via 164 and the via 150. That is, the drain electrode 142 forms as shown in the image. Figure 7 The hollow U-shaped cross-section is shown.

[0041] In some embodiments, please refer to Figure 4 and Figure 6 The orthographic projection of the via 150 onto the substrate 110 is circular, meaning the via 150 is a cylindrical via 150. Since the circular hole has no sharp edges, when the electric field passes through the circular hole area, it will be evenly distributed along the arc contour, preventing the electric field lines from excessively clustering at a certain point. This avoids the problem of electric field concentration at the "tip" of a right-angled "sharp structure".

[0042] In some embodiments, please refer to Figure 4 and Figure 6 The orthographic projection of source 141 onto substrate 110 is circular, and the orthographic projection of drain 142 onto substrate 110 is also circular. Similarly, as with via 150, the cross-sections of source 141 and drain 142 are circular. This eliminates the electric field concentration effect at the electrode edges, optimizes carrier injection or extraction efficiency, and matches the circular via 150 to optimize the electric field distribution, achieving electric field dispersion at drain 142, further reducing hot carrier effects and improving the reliability of the thin-film transistor.

[0043] In some embodiments, please refer to Figure 4 and Figure 6The radius R of the via 150 is less than or equal to the width W of the channel region 121, where the width W of the channel region 121 is the width of the active layer 120 in the second direction Y, which is perpendicular to the first direction X. Specifically, the radius R of the via 150 can be 0.25 to 0.5 times the width W of the channel region 121. For example, the radius R of the via 150 can be 0.25, 0.3, 0.35, 0.4, or 0.5 times the width W of the channel region 121, but is not limited to these values.

[0044] In some embodiments, please refer to Figure 6 When the orthographic projection of the via 150 on the substrate 110 is within the range of the orthographic projection of the drain 142 on the substrate 110, the coverage area of ​​the drain 142 can be increased, that is, the radius R of the orthographic projection of the drain 142 on the substrate 110. D The radius R of the orthogonal projection of the source 141 onto the substrate 110 is greater than or equal to that of the source 141. S This design benefits both the dispersion of the electric field at the drain 142 and the guarantee of the electrical performance of the drain 142. Specifically, the radius R of the orthographic projection of the drain 142 onto the substrate 110... D It can be the radius R of the orthogonal projection of source 141 onto substrate 110. S One to 1.5 times, for example, the radius R of the orthogonal projection of the drain 142 onto the substrate 110. D It can be the radius R of the orthogonal projection of source 141 onto substrate 110. S The multipliers can be 1x, 1.1x, 1.2x, 1.3x, 1.4x, 1.5x, etc., but are not limited to these.

[0045] In some embodiments, please refer to Figure 6 When the orthographic projection of the via 150 on the substrate 110 is within the range of the orthographic projection of the drain 142 on the substrate 110, the center O of the orthographic projection of the drain 142 on the substrate 110 is... D The center O of the orthographic projection of the via 150 onto the substrate 110 can coincide with the center of the orthographic projection of the drain 142 onto the substrate 110. The distance from the edge of the orthographic projection of the drain 142 onto the substrate 110 to the edge of the orthographic projection of the via 150 onto the substrate 110 can be equal and greater than zero to ensure uniform electric field distribution. For example, please refer to... Figure 6 The orthographic projection of drain 142 onto substrate 110 and the orthographic projection of via 150 onto substrate 110 can be concentric circles, and R D >R.

[0046] In some embodiments, please refer to Figure 4 and Figure 6The active layer 120 includes a main body 124 and at least one extension 125 connected to the main body 124. The extension 125 is located on at least one side of the main body 124 in the second direction Y, and the extension 125 is located on at least one side of the through hole 150 in the second direction Y. In the second direction Y, the minimum distance H1 from the edge of the extension 125 to the edge of the through hole 150 is greater than the minimum distance H2 from the edge of the main body 124 on the same side to the edge of the through hole 150. That is, the extension 125 is provided to protrude from the edge of the main body 124. By providing the extension 125, the distance from the through hole 150 to the edge of the active layer 120 is increased, thus avoiding wire breakage at the drilling point.

[0047] In some embodiments, when the position of the through hole 150 is biased toward one side of the main body portion 124 in the second direction Y, the extension portion 125 can be provided only on that side of the main body portion 124 to ensure that the through hole 150 on that side has sufficient width with the edge of the active layer 120, so as to avoid the wire breakage caused by drilling.

[0048] In some embodiments, when the via 150 is located towards the center of the main body 124 in the second direction Y, or when the via 150 is large, extensions 125 can be provided on both sides (in the second direction Y) of the main body 124 to avoid insufficient width of the active layer 120 on both sides (in the second direction Y) of the via 150, which could cause a broken wire. Specifically, please refer to... Figure 4 The extension 125 is located on opposite sides of the through hole 150 in the second direction Y. In the second direction Y, the minimum distance H1 from the edge of the extension 125 to the edge of the through hole 150 is greater than the minimum distance H2 from the edge of the main body 124 on the same side to the edge of the through hole 150. Both distances H1 and H2 refer to the vertical distance along the second direction Y. By adding extensions 125 on both sides of the active layer 120 corresponding to the through hole 150 (in the second direction Y), the active layer on both sides of the through hole 150 is widened to avoid problems such as wire breakage.

[0049] Furthermore, the width W1 of the extension portion 125 extending out of the edge of the via 150 in the first direction X is greater than or equal to the radius R of the via 150, and the width W2 of the extension portion 125 in the second direction Y is greater than or equal to the radius R of the via 150, so as to avoid the problem of wire breakage when drilling holes in the active layer 120, while ensuring the carrier transport efficiency of the active layer 120 and ensuring the reliability of the thin film transistor.

[0050] In some embodiments, please refer to Figure 3 and Figure 5The array substrate 100 also includes a passivation layer 171, a planarization layer, and a connection electrode 174. For example, the array substrate 100 further includes a passivation layer 171, a first planarization layer 172, a second planarization layer 173, and a connection electrode 174. The passivation layer 171 is disposed on the side of the source electrode 141 and the drain electrode 142 away from the interlayer insulating layer 163. The first planarization layer 172 is disposed on the side of the passivation layer 171 away from the source electrode 141 and the drain electrode 142. The connection electrode 174 is disposed on the side of the first planarization layer 172 away from the passivation layer 171 and is connected to the drain electrode 142 through a hole penetrating the first planarization layer 172 and the passivation layer 171. The second planarization layer 173 is disposed on the side of the connection electrode 174 away from the first planarization layer 172.

[0051] This application also provides a display panel 10, please refer to... Figure 8 and Figure 9 The display panel 10 includes the array substrate 100 as described above, and the display layer 180 disposed on the array substrate 100.

[0052] In some embodiments, please refer to Figure 8 The display panel 10 may be an organic light-emitting diode (OLED) display panel. The display layer 180 includes an anode 181, a pixel definition layer 182, a light-emitting functional layer 183, and a cathode 184. The anode 181 is disposed on the array substrate 100 and electrically connected to the connecting electrode 174 through holes penetrating the third planarization layer 175 and the second planarization layer 173. The pixel definition layer 182 is disposed on the array substrate 100 and has multiple pixel openings, which expose the surface of the anode 181. The light-emitting functional layer 183 is disposed in the pixel openings and is located above the anode 181. The cathode 184 is disposed on the side of the light-emitting functional layer 183 away from the anode 181. Furthermore, the display panel 10 also includes an encapsulation layer 185, which is disposed on the side of the organic light-emitting device away from the array substrate 100 and covers the organic light-emitting device.

[0053] In some embodiments, please refer to Figure 9 The display panel 10 can also be a liquid crystal display panel, and the display layer 180 can be a liquid crystal layer; furthermore, the display panel 10 also includes an opposing substrate 190, which is disposed on the side of the liquid crystal layer away from the array substrate 100.

[0054] This application also provides a display device, which includes the display panel 10 as described above. The display device can be a mobile phone, tablet, computer, television, or other display products, but is not limited thereto.

[0055] This application provides an array substrate, a display panel, and a display device. The active layer of the array substrate includes a channel region and source connection regions and drain connection regions located on opposite sides of the channel region. The source terminals are connected to the source connection regions, and the drain terminals are connected to the drain connection regions. The active layer has at least one via, and the orthogonal projection of the via onto the substrate is at least partially located in the channel region or the drain connection region. By creating a via in the channel region or drain connection region of the active layer, this application disperses the lateral electric field, weakens the lateral electric field, effectively reduces the hot carrier effect, and thus improves the performance of the thin-film transistor, enhancing the display effect of the display panel and display device. This avoids aging and threshold voltage (V) degradation caused by the hot carrier effect. th Issues such as screen offset and uneven screen brightness.

[0056] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0057] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0058] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0059] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, characterized in that, include: Substrate; An active layer is disposed above the substrate; as well as The source and drain electrodes are disposed on the side of the active layer away from the substrate; The active layer includes a channel region and a source connection region and a drain connection region located on opposite sides of the channel region in a first direction. The first direction is the extension direction from the source to the drain. The source is connected to the source connection region, and the drain is connected to the drain connection region. The active layer is provided with at least one via, and the orthographic projection of the via on the substrate is at least partially located within the orthographic projection range of the channel region on the substrate or the orthographic projection range of the drain connection region on the substrate.

2. The array substrate according to claim 1, characterized in that, The orthographic projection of the via on the substrate is located between the orthographic projection of the source electrode on the substrate and the orthographic projection of the drain electrode on the substrate; Wherein, the minimum distance between the orthographic projection of the via on the substrate and the orthographic projection of the drain on the substrate is less than or equal to the minimum distance between the orthographic projection of the via on the substrate and the orthographic projection of the source on the substrate.

3. The array substrate according to claim 2, characterized in that, The center of the orthographic projection of the via on the substrate is located on the line connecting the center of the orthographic projection of the source electrode on the substrate and the center of the orthographic projection of the drain electrode on the substrate.

4. The array substrate according to claim 1, characterized in that, The orthogonal projection of the via on the substrate lies within the orthogonal projection range of the drain electrode on the substrate.

5. The array substrate according to claim 4, characterized in that, The array substrate further includes: An insulating layer is disposed on the side of the active layer near the source and the drain. The insulating layer has a via, and the orthographic projection of the via on the substrate is within the orthographic projection range of the via on the substrate. The drain electrode extends through the via into the through hole and is connected to the active layer.

6. The array substrate according to claim 5, characterized in that, The drain electrode includes a first sub-part and a second sub-part disposed around the first sub-part. The first sub-part is disposed within the through hole, and the second sub-part extends along the inner sidewall of the through hole and the inner sidewall of the through hole. One end of the second sub-part extends into the through hole and connects with the first sub-part, and the other end of the second sub-part extends above the insulating layer.

7. The array substrate according to any one of claims 1 to 6, characterized in that, The orthographic projection of the through-hole onto the substrate is circular; And / or, the orthographic projection of the source electrode onto the substrate is circular; And / or, the orthogonal projection of the drain on the substrate is circular.

8. The array substrate according to any one of claims 1 to 6, characterized in that, The active layer includes a main body and at least one extension connected to the main body, the extension being located on at least one side of the main body in a second direction, the second direction being perpendicular to the first direction; The extension is located on at least one side of the through hole in the second direction, and in the second direction, the minimum distance from the edge of the extension to the through hole is greater than the minimum distance from the edge of the main body portion on the same side to the through hole.

9. A display panel, characterized in that, It includes an array substrate as described in any one of claims 1 to 8, and a display layer disposed on the array substrate.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

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