Array substrate, preparation method of array substrate and display panel of array substrate

Abstract

The invention discloses an array substrate, a preparation method of the array substrate and a display panel of the array substrate, and the array substrate comprises a first active layer, a plurality of conductive layers and a second active layer which are arranged on one side of the substrate in a stacked manner, the first active layer is adjacent to the substrate, and the second active layer is adjacent to the plurality of conductive layers. The first active layer, the multiple conductive layers and the second active layer form at least one pixel circuit, and the pixel circuit comprises a driving transistor, a first transistor, a first capacitor and a second capacitor; wherein the second polar plate of the second capacitor is multiplexed as the second polar plate of the first capacitor, and the vertical projection of the first polar plate of the first capacitor on the second polar plate of the second capacitor is at least partially overlapped with the vertical projection of the first polar plate of the second capacitor on the common polar plate, so that a more compact capacitor stacking structure is formed. The space competition on a transverse plane is reduced, so that the polar plate areas of the first capacitor and the second capacitor can be maximized in a limited pixel region, and the PPI of AR / VR and other near-to-eye display applications is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a method for preparing the array substrate, and a display panel thereof. Background Technology

[0002] With the continuous advancement of display technology and the ever-increasing demand for interactive information experiences, virtual reality (VR) and augmented reality (AR) devices are reshaping how humans perceive the world at an unprecedented pace. These technologies show broad application prospects in fields such as healthcare, industry, education, and consumer electronics, and are expected to bring users a more immersive, realistic, and vivid life experience.

[0003] Because AR / VR displays are extremely close to the user's eyes, and the optical lenses have a magnifying effect, the human eye can easily perceive the pixel structure, thus placing higher demands on display resolution. However, current mainstream pixel circuit layout designs still have shortcomings and cannot meet the requirements for achieving high pixel density (Pixels Per Inch, PPI). Summary of the Invention

[0004] This invention provides an array substrate, a method for fabricating the array substrate, and a display panel thereof, which reduces the spatial competition between the capacitor area and the TFT device area in the lateral plane and improves the PPI of near-eye display applications such as AR / VR.

[0005] In a first aspect, embodiments of the present invention provide an array substrate, comprising:

[0006] Substrate;

[0007] A first active layer, a multilayer conductive layer, and a second active layer are stacked on one side of the substrate. The first active layer is adjacent to the substrate. The first active layer, the multilayer conductive layer, and the second active layer constitute at least one pixel circuit. The pixel circuit includes a driving transistor, a first transistor, a first capacitor, and a second capacitor.

[0008] The multilayer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked sequentially. The first conductive layer is adjacent to the first active layer. The gate of the first transistor is located on the first conductive layer. The second conductive layer includes a data signal line. The data signal line is connected to the first electrode of the first transistor through a first via. The first electrode of the second capacitor is located on the third conductive layer. The second electrode of the second capacitor is located on the fourth conductive layer. The first gate of the driving transistor and the first electrode of the first capacitor connected to the first gate of the driving transistor are located on the fifth conductive layer. The first gate of the driving transistor is multiplexed as the first electrode of the first capacitor. The first gate of the driving transistor is connected to the second electrode of the first transistor through a second via.

[0009] The second plate of the second capacitor is reused as a common plate as the second plate of the first capacitor; the vertical projection of the first plate of the first capacitor onto the second plate of the second capacitor overlaps at least partially with the vertical projection of the first plate of the second capacitor onto the second plate of the second capacitor.

[0010] Optionally, the first active layer includes a first sub-active layer extending along a first direction, and the first conductive layer includes a first trace extending along a second direction; the first direction intersects the second direction.

[0011] The orthographic projection of the first trace on the substrate and the orthographic projection of the first sub-active layer on the substrate have a first intersection region, and the portion of the first trace corresponding to the first intersection region serves as the gate of the first transistor.

[0012] Optionally, the first trace is used to transmit the second scan signal of the first transistor;

[0013] Optionally, the portion of the first sub-active layer located below the orthographic projection of the gate of the first transistor is the first channel region of the first transistor, and the two sides of the first channel region are the first electrode and the second electrode of the first transistor, respectively.

[0014] Optionally, a first extension portion extending along the second direction is provided at one end of the first sub-active layer corresponding to the first electrode of the first transistor. The data signal line extends along the first direction, and the orthographic projection of the data signal line on the substrate overlaps with the orthographic projection of the first extension portion on the substrate. The first via is disposed at the overlap position between the data signal line and the first extension portion, and the data signal line is connected to the first electrode of the first transistor through the first via.

[0015] Optionally, the pixel circuit further includes a second transistor; the first terminal of the second transistor is connected to an initialization signal, and the second terminal of the second transistor is connected to the first gate of the driving transistor;

[0016] Optionally, the first active layer includes a second sub-active layer extending along the first direction, and the first sub-active layer and the second sub-active layer are arranged along the first direction;

[0017] Optionally, the gate of the second transistor is located in the first conductive layer; the first conductive layer includes a second trace extending along the second direction; in the first direction, the second trace is located on the side of the first trace away from the first extension, the orthographic projection of the second trace on the substrate and the orthographic projection of the second sub-active layer on the substrate have a second intersection region, and the portion of the second trace corresponding to the second intersection region serves as the gate of the second transistor.

[0018] Optionally, the second trace is used to transmit control signals for the second transistor;

[0019] Optionally, the portion of the second sub-active layer located below the orthogonal projection of the gate of the second transistor is the second channel region of the second transistor, and the two sides of the second channel region are the first electrode and the second electrode of the second transistor, respectively.

[0020] Optionally, the side of the second channel region closest to the first channel region is the second electrode of the second transistor;

[0021] Optionally, the first sub-active layer is connected to the second sub-active layer so that the second electrode of the first transistor and the second electrode of the second transistor are connected;

[0022] Optionally, the third conductive layer includes an initialization signal line extending along the second direction. The orthographic projection of the initialization signal line on the substrate overlaps with the orthographic projection of the first electrode of the second transistor of the second sub-active layer on the substrate. A third via is provided at the overlap position between the initialization signal line and the second sub-active layer, and the initialization signal line is connected to the first electrode of the second transistor through the third via.

[0023] Optionally, the first transistor and the second transistor are transistors of the same conductivity type.

[0024] Optionally, the orthographic projection of the first plate of the second capacitor at least covers the region of the first electrode of the first transistor corresponding to the first sub-active layer, as well as a portion of the data signal line; and the orthographic projection of the first plate of the second capacitor does not overlap with the region of the second electrode of the first transistor corresponding to the first sub-active layer.

[0025] Optionally, the orthographic projection of the first plate of the second capacitor onto the substrate at least covers the orthographic projection of the second plate of the second capacitor onto the substrate; wherein, in the second direction, the width dimension of the first plate of the second capacitor is greater than the width dimension of the second plate of the second capacitor.

[0026] Optionally, the fifth conductive layer includes a first conductive sublayer and a second conductive sublayer, the first conductive sublayer and the second conductive sublayer are arranged along the first direction, and the first conductive sublayer and the second conductive sublayer are connected, the first conductive sublayer and the second conductive sublayer constitute the first gate of the driving transistor;

[0027] Wherein, the orthographic projection of the first conductive sublayer covers at least part of the second plate of the second capacitor, and the first conductive sublayer serves as the first plate of the first capacitor.

[0028] The orthographic projection of the second conductive sub-layer on the substrate overlaps with the orthographic projection of the first sub-active layer corresponding to the second electrode of the first transistor on the substrate. The second via is disposed at the overlap position between the second conductive sub-layer and the first sub-active layer. The second electrode of the first transistor is connected to the first gate of the driving transistor through the second via.

[0029] Optionally, in the second direction, the width of the first plate of the first capacitor is greater than the width of the second plate of the second capacitor;

[0030] Optionally, in the second direction, the width of the first conductive sublayer is greater than the width of the second conductive sublayer, such that the vertical distance between the edge of the first conductive sublayer and the edge of the adjacent data signal line in the second direction is greater than the vertical distance between the edge of the second conductive sublayer and the edge of the same data signal line in the second direction.

[0031] Optionally, the second active layer extends along the first direction, and the second active layer includes the third channel region of the driving transistor and the first and second electrodes of the driving transistor located on both sides of the third channel region.

[0032] The orthographic projection of the third channel region of the driving transistor onto the substrate lies within the orthographic projections of the first conductive layer and the second conductive layer onto the substrate.

[0033] Optionally, the driving transistor further includes a second gate, which is connected to the second terminal of the driving transistor and the second plate of the second capacitor;

[0034] Optionally, the array substrate further includes a sixth conductive layer, which is located on the side of the second active layer away from the substrate, and the second gate is located in the sixth conductive layer;

[0035] Optionally, in the first direction, the second electrode of the driving transistor is located on the side of the third channel region away from the second conductive layer;

[0036] Optionally, the orthographic projection of the second gate on the substrate and the orthographic projection of the second electrode of the driving transistor on the substrate have a first overlapping region, the orthographic projection of the first overlapping region on the substrate overlaps with the orthographic projection of the second plate of the second capacitor on the substrate, and the orthographic projection of the first overlapping region on the substrate does not overlap with the orthographic projection of the first gate on the substrate; a fifth via is provided between the second gate and the second plate of the second capacitor at a position corresponding to the first overlapping region; wherein, the fifth via penetrates the second active layer, and the vertical projection of the fifth via on the substrate does not overlap with the vertical projection of the first gate on the substrate; the second gate of the driving transistor is connected to the second electrode of the driving transistor and the second plate of the second capacitor through the fifth via;

[0037] Optionally, the orthogonal projection of the second gate at least covers the third channel region of the driving transistor.

[0038] Optionally, the array substrate further includes a seventh conductive layer, which is located on the side of the sixth conductive layer away from the substrate;

[0039] The seventh conductive layer includes a connecting sublayer;

[0040] The vertical projection of the connecting sublayer on the substrate overlaps with the vertical projection of the second gate on the substrate, and a sixth via is provided at the overlapping position between the connecting sublayer and the second gate; the connecting sublayer is connected to the second gate through the sixth via;

[0041] Optionally, the array substrate further includes a planarization layer, a conductive material layer, and an anode layer. The planarization layer is located on the side of the seventh conductive layer away from the substrate. The planarization layer includes an eighth via that penetrates the planarization layer and exposes a portion of the connecting sublayer. The conductive material layer covers the bottom and sidewalls of the eighth via, and at least a portion of the conductive material layer covers the surface of the planarization layer and is connected to the anode layer.

[0042] Optionally, the seventh conductive layer further includes a first power line; the first power line extends along the second direction, and the vertical projection of the first power line on the substrate overlaps with the vertical projection of the first electrode of the driving transistor on the substrate. A seventh via is provided at the overlap position between the first power line and the first electrode of the driving transistor, and the first power line is connected to the first electrode of the driving transistor through the seventh via. The orthographic projection of the seventh via on the substrate does not overlap with the orthographic projection of the second gate on the substrate.

[0043] Optionally, the conductive material layer includes indium tin oxide.

[0044] Optionally, the pixel circuit includes a third transistor; the first terminal of the third transistor is connected to a first power supply line, and the second terminal of the third transistor is connected to the first terminal of the driving transistor;

[0045] Optionally, the first active layer includes a third sub-active layer extending along the first direction, and the first sub-active layer and the third sub-active layer are arranged at intervals along the first direction.

[0046] Optionally, the gate of the third transistor is located in the first conductive layer; the first conductive layer includes a third trace extending along the second direction; in the first direction, the third trace is located on the side of the first trace away from the first extension, and the orthographic projection of the third trace on the substrate and the orthographic projection of the third sub-active layer on the substrate have a third intersection region, and the portion of the third trace corresponding to the third intersection region serves as the gate of the third transistor.

[0047] Optionally, the third trace is used to transmit control signals for the third transistor;

[0048] Optionally, the portion of the third sub-active layer located below the orthogonal projection of the gate of the third transistor is the fourth channel region of the third transistor, and the two sides of the fourth channel region are the first electrode and the second electrode of the third transistor, respectively.

[0049] Optionally, the side of the fourth channel region closest to the first channel region is the second electrode of the third transistor;

[0050] Optionally, the third conductive layer includes a first power trace extending along the second direction. The orthographic projection of the first power trace on the substrate overlaps with the orthographic projection of the first electrode of the third transistor in the third sub-active layer on the substrate. A ninth via is provided at the overlap position between the first power trace and the third sub-active layer. The first power trace is connected to the first electrode of the third transistor through the ninth via. The second electrode of the third transistor is connected to the first electrode of the driving transistor through a tenth via.

[0051] Optionally, the first transistor and the third transistor are transistors of the same conductivity type.

[0052] Secondly, embodiments of the present invention provide a method for fabricating an array substrate, comprising:

[0053] A first active layer, a multilayer conductive layer, and a second active layer are sequentially formed on the substrate;

[0054] The first active layer, the multilayer conductive layer, and the second active layer constitute at least one pixel circuit, and the pixel circuit includes a driving transistor, a first transistor, a first capacitor, and a second capacitor.

[0055] The multilayer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked sequentially. The first conductive layer is adjacent to the first active layer. The gate of the first transistor is located on the first conductive layer. The second conductive layer includes a data signal line. The data signal line is connected to the first electrode of the first transistor through a first via. The first electrode of the second capacitor is located on the third conductive layer. The second electrode of the second capacitor is located on the fourth conductive layer. The first gate of the driving transistor and the first electrode of the first capacitor connected to the first gate of the driving transistor are located on the fifth conductive layer. The first gate of the driving transistor is multiplexed as the first electrode of the first capacitor. The first gate of the driving transistor is connected to the second electrode of the first transistor through a second via.

[0056] The second plate of the second capacitor is reused as a common plate as the second plate of the first capacitor; the vertical projection of the first plate of the first capacitor onto the second plate of the second capacitor overlaps at least partially with the vertical projection of the first plate of the second capacitor onto the second plate of the second capacitor.

[0057] Optionally, the driving transistor further includes a second gate;

[0058] The preparation method includes:

[0059] A sixth conductive layer is formed on the side of the second active layer away from the substrate, and the second gate is located on the sixth conductive layer; the orthographic projection of the second gate on the substrate overlaps with the orthographic projections of the second electrode and the third channel region of the driving transistor on the substrate;

[0060] Optionally, before forming the sixth conductive layer, the method further includes:

[0061] A shielding layer is provided on the surface of the third channel region defined on the second active layer, and conductive injection is performed on both sides of the third channel region of the second active layer to form the first electrode and the second electrode of the driving transistor.

[0062] Thirdly, embodiments of the present invention provide a display panel including the array substrate described in any embodiment of the present invention.

[0063] The array substrate provided in this embodiment of the invention comprises a first active layer and a second active layer respectively disposed on both sides of a multilayer conductive structure. The first active layer is located on one side of the substrate and is used to form a first transistor, while the second active layer is used to form a driving transistor. In the multilayer conductive layers, the gate of the first transistor is located in the first conductive layer, and the second conductive layer includes a data signal line. The data signal line is vertically electrically connected to the first electrode of the first transistor through a first via penetrating the intermediate insulating layer, thereby replacing the traditional lateral wiring with a thickness-direction interconnection method, effectively saving lateral space within the pixel. A first capacitor and a second capacitor are formed by stacking a third, fourth, and fifth conductive layer in the thickness direction. The second electrode of the second capacitor is reused as the second electrode of the first capacitor, serving as a common electrode of the first and second capacitors. The vertical projection of the first electrode of the first capacitor onto the second electrode of the second capacitor at least partially overlaps with the vertical projection of the first electrode of the second capacitor onto this common electrode, forming a more compact capacitor stack structure. The driving transistor, the first capacitor, the second capacitor, and the first transistor are arranged in a three-layer thickness direction of "top, middle, and bottom". The capacitor area and the TFT device area do not overlap or compete in the horizontal plane, so that the plate area of ​​the first capacitor and the second capacitor can be maximized within a limited pixel area, which is beneficial to improving the PPI of near-eye display applications such as AR / VR. Attached Figure Description

[0064] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0065] Figure 2 This is a schematic diagram of the control timing of a pixel circuit provided in an embodiment of the present invention;

[0066] Figure 3A schematic diagram of a pixel circuit stacking structure provided in an embodiment of the present invention;

[0067] Figure 4 This is a top view of an array substrate provided in an embodiment of the present invention;

[0068] Figure 5 This is a top view of the structure of the first to third conductive layers in the array substrate provided in an embodiment of the present invention;

[0069] Figure 6 This is a top view schematic diagram of a third conductive layer and a fourth conductive layer provided in an embodiment of the present invention;

[0070] Figure 7 This is a top view of an array substrate provided in an embodiment of the present invention;

[0071] Figure 8 This is a top view of the third to fifth conductive layers in the array substrate provided in an embodiment of the present invention;

[0072] Figure 9 This is a top view of the sixth conductive layer in the array substrate provided in an embodiment of the present invention;

[0073] Figure 10 This is a top view of the seventh conductive layer in the array substrate provided in an embodiment of the present invention;

[0074] Figure 11 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0075] Figure 12 This is a control timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0076] Figure 13 A schematic diagram of another pixel circuit stacking structure provided in an embodiment of the present invention;

[0077] Figure 14 This is a schematic flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present invention;

[0078] Figure 15 This is a schematic diagram illustrating an intermediate fabrication process of an array substrate according to an embodiment of the present invention;

[0079] Figure 16 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0081] Because AR / VR displays are extremely close to the user's eyes and optical lenses have a magnifying effect, the human eye can easily perceive the pixel structure. Currently mature OLED pixel driving circuits, such as the 7T1C circuit, have complete functions, but due to the large number of TFTs, they are limited by array and OLED process capabilities and cannot achieve a high PPI. On the other hand, the conventional 2T1C circuit solution has fewer TFT devices and can significantly improve the PPI, but this solution lacks gate initialization, anode initialization, or cannot achieve Vth compensation inside the pixel, which often causes display problems such as image retention and uneven display, and cannot meet application requirements.

[0082] In view of this, Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 1 The pixel circuit includes a driving transistor T1, a first transistor T2, a second transistor T3, a first capacitor C1, and a second capacitor C2.

[0083] In this configuration, the first terminal of the first transistor T2 is connected to the data signal line, which provides the data signal Vdata. The gate G1 of the first transistor T2 is connected to the first scan signal S2. The second terminal of the first transistor T2 is connected to the first gate of the driving transistor T1. The first terminal of the driving transistor T1 is connected to the first power supply signal AC_VDD. The second terminal of the driving transistor T1 is connected to the anode of the light-emitting diode (LED). The cathode of the LED is connected to the second power supply signal AC_VSS. The first capacitor C1 is connected between the first gate of the driving transistor T1 and the second terminal of the driving transistor T1. The second capacitor C2 is connected between the second terminal of the driving transistor T1 and the first terminal of the second transistor T3. The second terminal of the second transistor T3 is connected to the second terminal of the first transistor T2. The gate G2 of the second transistor T3 is connected to the second scan signal S1. Figure 2 This invention provides a control timing diagram for a pixel circuit, applicable to various applications. Figure 1 In the pixel circuit shown in this embodiment of the invention, the first transistor T2 and the second transistor T3 are P-type transistors. (See also...) Figure 1 and Figure 2, the working process of the pixel circuit provided in this embodiment includes an initialization stage t1, a compensation stage t2, a row-by-row data writing stage t3, and a light-emitting stage t4. Among them, the second scan signal S1 is a global signal for controlling reset and compensation; the first scan signal S2 is a GIP signal for row-by-row shifting, and the first power supply signal AC_VDD, the second power supply signal AC_VSS, and the initialization signal AC_Vini are all global signals Common. Among them, the first power supply signal AC_VDD includes three voltage values with different functions, namely VDDH, VDDM, and VDDL, and VDDL < VDDM < VDDH. The second power supply signal AC_VSS includes VSSH and VSSL, and VSSL < VSSH. The initialization signal AC_Vini includes Vini and Vini_H, and Vini < Vini_H.

[0084] In the initialization stage t1, the first scan signal S2 is at an off level, such as a low level, and the first transistor T2 is turned off; the second scan signal S1 is at an on level, such as a high level, and the second transistor T3 is turned on to initialize the anode of the light-emitting diode. In the compensation stage t2, the first power supply signal AC_VDD and the initialization signal AC_Vini jump. The first scan signal S2 is at an off level, and the first transistor T2 is turned off; the second scan signal S1 is at an on level, and the second transistor T3 is turned on to achieve threshold compensation for the driving transistor T1. In the row-by-row data writing stage t3, the first scan signal S2 is at an on level, and the first transistor T2 is turned on for row-by-row data writing; the second scan signal S1 is at an off level, and the second transistor T3 is turned off. In the light-emitting stage t4, the first scan signal S2 is at an off level, and the first transistor T2 is turned off; the second scan signal S1 is at an off level, and the second transistor T3 is turned off. The first power supply signal AC_VDD provides a driving power supply signal to drive the light-emitting diode to emit light. The pixel circuit provided in the embodiment of the present invention can realize gate initialization, anode initialization, and threshold compensation inside the pixel while reducing the number of TFT devices, effectively reducing the number of TFT devices and being beneficial to the improvement of PPI. It should be noted that in some embodiments, the second transistor T3 may not be provided, and the second capacitor C2 is connected to the initialization signal AC_Vini. The data signal line needs to transmit the initialization signal AC_Vini in the initialization stage t1 and the compensation stage t2, and transmit the data signal Vdata in the row-by-row data writing stage t3.

[0085] Furthermore, the embodiment of the present invention also provides an array substrate, which reduces the spatial interference between transistors and capacitors by optimizing the layout of the pixel circuit, thereby improving PPI. Figure 3 Schematic diagram of the stacked structure of a pixel circuit provided in the embodiment of the present invention, refer to Figure 3 , the array substrate provided in the embodiment of the present invention includes:

[0086] Substrate 110;

[0087] A first active layer 120, a multilayer conductive layer, and a second active layer 130 are stacked on one side of the substrate 110. The first active layer 120 is adjacent to the substrate 110. The first active layer 120, the multilayer conductive layer, and the second active layer 130 constitute at least one pixel circuit. The pixel circuit includes a driving transistor T1, a first transistor T2, a first capacitor C1, and a second capacitor C2.

[0088] The multilayer conductive layer includes a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, a fourth conductive layer M4, and a fifth conductive layer M5 stacked sequentially. The first conductive layer M1 is adjacent to the first active layer 120. The gate G1 of the first transistor T2 is located in the first conductive layer M1. The second conductive layer M2 includes a data signal line 140. The data signal line 140 is connected to the first electrode of the first transistor T2 through a first via K1. The first electrode C21 of the second capacitor C2 is located in the third conductive layer M3. The second electrode C22 of the second capacitor C2 is located in the fourth conductive layer M4. The first gate of the driving transistor T1 and the first electrode C11 of the first capacitor C1 connected to the first gate of the driving transistor T1 are located in the fifth conductive layer M5. The first gate of the driving transistor T1 is multiplexed as the first electrode C11 of the first capacitor C1. The first gate of the driving transistor T1 is connected to the second electrode of the first transistor T2 through a second via K2.

[0089] The second plate C22 of the second capacitor C2 is reused as a common plate as the second plate of the first capacitor C1; the vertical projection of the first plate C11 of the first capacitor C1 onto the second plate C22 of the second capacitor C2 at least partially overlaps with the vertical projection of the first plate C21 of the second capacitor C2 onto the second plate C22 of the second capacitor C2.

[0090] Specifically, the substrate 110 can provide protection and support for the display panel. For example, the substrate 110 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a rigid substrate formed of materials such as glass, to meet the flexibility or stability requirements of different application scenarios. A first active layer 120 is disposed on one side of the substrate 110. The first active layer 120 can be made of low-temperature polycrystalline silicon (LTPS) and is used to form the active region of the first transistor T2. Multiple conductive layers are stacked on the side of the first active layer 120 away from the substrate 110. For example, the multiple conductive layers include a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, a fourth conductive layer M4, and a fifth conductive layer M5. Each conductive layer is isolated from the others by an insulating layer. The first conductive layer M1 is located on the side close to the first active layer 120 and is used to form the gate G1 of the first transistor T2. The orthographic projection of the gate G1 of the first transistor T2 on the substrate 110 overlaps with the orthographic projection of the first active layer 120 on the substrate 110. The first active layer 120 corresponding to the part directly below the overlapping area is the first channel region of the first transistor T2. The first active layers 120 on both sides of the first channel region are the first electrode and the second electrode of the first transistor T2, respectively.

[0091] The second conductive layer M2 includes a data signal line 140. The orthographic projection of the data signal line 140 on the substrate 110 overlaps with the orthographic projection of the first electrode of the first transistor T2 on the substrate 110. A first via K1 is provided in the insulating layer between the orthographic projection of the data signal line 140 on the substrate 110 and the first electrode of the first transistor T2. The data signal line 140 is connected to the first electrode of the first transistor T2 through the first via K1, realizing a thickness-direction interconnection layout. The thickness-direction interconnection structure effectively reduces the space required for lateral wiring, which helps to improve pixel density (PPI).

[0092] The first electrode C21 of the second capacitor C2 is located in the third conductive layer M3; the second electrode C22 of the second capacitor C2 is located in the fourth conductive layer M4; the orthographic projection of the first electrode C21 of the second capacitor C2 on the substrate 110 at least partially overlaps with the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate 110, and the overlapping area constitutes the effective capacitance of the second capacitor C2. The first electrode C11 of the first capacitor C1 is located in the fifth conductive layer M5; the orthographic projection of the first electrode C11 of the first capacitor C1 on the substrate 110 at least partially overlaps with the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate 110, and the overlapping area constitutes the effective capacitance of the first capacitor C1. That is to say, the second electrode C22 of the second capacitor C2 here serves as a common electrode and can be reused as the second electrode of the first capacitor C1. The first capacitor C1 and the second capacitor C2 are formed simultaneously in the thickness direction of the array substrate. The vertically stacked capacitor structure can significantly save lateral layout space.

[0093] Furthermore, the vertical projection of the first plate C11 of the first capacitor C1 onto the second plate C22 of the second capacitor C2 at least partially overlaps with the vertical projection of the first plate C21 of the second capacitor C2 onto the second plate C22 of the second capacitor C2, thereby realizing the arrangement of the first capacitor C1 and the second capacitor C2 stacked vertically in the thickness direction, further compressing the lateral occupied area and providing a structural basis for the high-resolution display panel.

[0094] The second active layer 130 is located on the side of the fifth conductive layer M5 away from the substrate 110. The second active layer 130 is used to form the active region of the driving transistor T1. The orthographic projection of the first plate C11 of the first capacitor C1 on the substrate 110 overlaps with the orthographic projection of the second active layer 130 on the substrate 110. The first plate C11 of the first capacitor C1 can be reused as the first gate of the driving transistor T1. Therefore, it is not necessary to separately set a conductive layer to prepare the first gate of the driving transistor T1, which not only simplifies the process, but also further optimizes the space utilization inside the pixel.

[0095] The array substrate provided in this embodiment of the invention has a first active layer 120 and a second active layer 130 respectively disposed on both sides of a multilayer conductive structure. The first active layer 120 is located on one side of the substrate 110 and is used to form a first transistor T2, while the second active layer 130 is used to form a driving transistor T1. In the multilayer conductive layers, the gate G1 of the first transistor T2 is located in the first conductive layer M1, and the second conductive layer M2 includes a data signal line 140. The data signal line 140 is vertically electrically connected to the first electrode of the first transistor T2 through a first via K1 penetrating the intermediate insulating layer, thereby replacing the traditional lateral wiring with a thickness-direction interconnection method, effectively saving lateral space within the pixel. A first capacitor C1 and a second capacitor C2 are formed using the third, fourth, and fifth conductive layers stacked in the thickness direction. In this design, the second electrode C22 of the second capacitor C2 is reused as the second electrode of the first capacitor C1, serving as a common electrode for both capacitors C1 and C2. The vertical projection of the first electrode C11 of the first capacitor C1 onto the second electrode of the second capacitor C2 at least partially overlaps with the vertical projection of the first electrode C21 of the second capacitor C2 onto this common electrode, forming a more compact capacitor stack structure. The driving transistor T1, the first capacitor C1, the second capacitor C2, and the first transistor T2 exhibit a three-layer thickness-direction arrangement, with no overlap or competition between the capacitor area and the TFT device area in the lateral plane. This allows the electrode areas of both capacitors C1 and C2 to be maximized within a limited pixel area, which is beneficial for improving the PPI of near-eye display applications such as AR / VR.

[0096] Figure 4 This is a top view of an array substrate provided in an embodiment of the present invention. Figure 5 This is a top view of the first to third conductive layers in the array substrate provided in an embodiment of the present invention. See also: Figure 4 and Figure 5 The first active layer 120 includes a first sub-active layer 121 extending along the first direction X, and the first conductive layer M1 includes a first trace 210 extending along the second direction Y; the first direction X and the second direction Y intersect.

[0097] The orthographic projection of the first trace 210 on the substrate 110 and the orthographic projection of the first sub-active layer 121 on the substrate 110 have a first intersection region, and the portion of the first trace 210 corresponding to the first intersection region serves as the gate G1 of the first transistor T2.

[0098] Specifically, in this embodiment of the invention, the first sub-active layer 121 can be formed by etching or patterning the first active layer 120 through a patterning process, thereby precisely defining the active region of the first defined transistor. For example, in this embodiment of the invention, the first direction X is perpendicular to the second direction Y. For instance, the first direction X is a column direction, and the second direction Y is a row direction. The first trace 210 extends along the second direction Y, and the first trace 210 and the first sub-active layer 121 form at least one first intersection region on the plane. Within the first intersection region, the first trace 210 covers the first sub-active layer 121 and is isolated from it by an insulating layer. The first trace 210 corresponding to the first intersection region can be used as the gate G1 of the first transistor T2. The portion of the first sub-active layer 121 located below the orthogonal projection of the gate G1 of the first transistor T2 is the first channel region of the first transistor T2. The two sides of the first channel region are the first electrode and the second electrode of the first transistor T2, respectively.

[0099] Optionally, the first trace 210 can be configured to transmit the second scan signal S1 of the first transistor T2. The first trace 210 can serve as the gate G1 of the first transistor T2 to regulate the conduction state of the first channel region, or it can serve as the transmission path of the scan signal. This eliminates the need for additional independent traces, significantly reducing the lateral space occupied by redundant wiring.

[0100] Optionally, a first extension portion 1210 extending along the second direction Y is provided at one end of the first sub-active layer 121 corresponding to the first electrode of the first transistor T2. The data signal line 140 extends along the first direction X. The orthographic projection of the data signal line 140 on the substrate 110 overlaps with the orthographic projection of the first extension portion 1210 on the substrate 110. A first via K1 is provided at the overlapping position between the data signal line 140 and the first extension portion 1210. The data signal line 140 is connected to the first electrode of the first transistor T2 through the first via K1.

[0101] Specifically, in this embodiment of the invention, one end of the first sub-active layer 121 extends along the second direction Y and is provided with a first extension portion 1210. Its main function is to offset the position of the main body of the first sub-active layer 121 on one side in the planar layout, thereby reserving a connection area for the sub-layer. Through the offset design, sufficient and independent wiring windows can be provided for establishing electrical connections with the data signal lines 140 in the second conductive layer M2, effectively avoiding large-area overlap between the data signal lines 140 and the main body area of ​​the first sub-active layer 121, thereby preventing interference with the arrangement of other functional wiring due to excessive overlap and improving the flexibility of the overall pixel layout.

[0102] In this embodiment of the invention, the data signal line 140 extends along a first direction X and is arranged adjacent to the first sub-active layer 121 in a plane. In the thickness direction, the orthographic projection of the data signal line 140 on the substrate 110 at least partially overlaps with the orthographic projection of the first extension 1210 on the substrate 110. A first via K1 is formed in the insulating layer between the data signal line 140 and the first extension 1210, so that the data signal line 140 is electrically connected to the first extension 1210 through the via. The first extension 1210 is electrically connected to the first electrode of the first transistor T2, and structurally forms a thickness-direction interconnect between the data signal line 140 and the first electrode of the first transistor T2.

[0103] Combination Figure 1 and Figure 4 Optionally, the pixel circuit also includes a second transistor T3; the first terminal of the second transistor T3 is connected to the initialization signal AC_Vini, and the second terminal of the second transistor T3 is connected to the first gate G3 of the driving transistor T1.

[0104] In the layout structure, the first active layer 120 includes a second sub-active layer 122 extending along the first direction X. The first sub-active layer 121 and the second sub-active layer 122 are arranged along the first direction X. The second sub-active layer 122 can be formed by patterning the entire first active layer 120 through a patterning process, thereby precisely defining the active region of the second transistor T3.

[0105] To facilitate circuit connection and optimize wiring efficiency, the second sub-active layer 122 can be disposed on the side of the first sub-active layer 121 away from its first extension 1210, so that the second electrode of the second transistor T3 and the second electrode of the first transistor T2 are more spatially adjacent, thus facilitating wiring. For example... Figure 4 As shown, when the second sub-active layer 122 is directly connected to the first sub-active layer 121, the electrical connection between the second electrode of the second transistor T3 and the second electrode of the first transistor T2 can be directly realized, avoiding the introduction of additional metal traces and effectively saving lateral space.

[0106] Optionally, the gate G2 of the second transistor T3 is located in the first conductive layer M1; the first conductive layer M1 includes a second trace 220 extending along the second direction Y; in the first direction X, the second trace 220 is located on the side of the first trace 210 away from the first extension 1210, the orthographic projection of the second trace 220 on the substrate 110 and the orthographic projection of the second sub-active layer 122 on the substrate 110 have a second intersection region, and the portion of the second trace 220 corresponding to the second intersection region serves as the gate G2 of the second transistor T3;

[0107] Specifically, the second trace 220 extends along the second direction Y. The second trace 220 and the second sub-active layer 122 form at least one second intersection region on the plane. In the second intersection region, the second trace 220 covers the second sub-active layer 122 and is isolated from it by an insulating layer. The second trace 220 in the corresponding second intersection region can be used as the gate G2 of the second transistor T3. The part of the second sub-active layer 122 located below the orthogonal projection of the gate G2 of the second transistor T3 is the second channel region of the second transistor T3. The two sides of the second channel region are the first electrode of the second transistor T3 and the second electrode of the second transistor T3, respectively.

[0108] Optionally, the second trace 220 can be configured to transmit the first scan signal of the second transistor T3. The second trace 220 can serve as the gate G2 of the second transistor T3 to regulate the conduction state of the second channel region, or it can serve as the transmission path for the scan signal. This eliminates the need for additional independent traces, significantly reducing the lateral space occupied by redundant wiring.

[0109] To further reduce the space required in the first direction X, this invention proposes an optimized connection method: defining the side of the second channel region closest to the first channel region as the second electrode of the second transistor T3, and connecting the first sub-active layer 121 and the second sub-active layer 122 in the first direction X. Thus, the second electrode of the second transistor T3 and the second electrode of the first transistor T2 can be directly electrically connected through a short-range doped region, eliminating the need for cross-layer vias or additional metal interconnects. This simplifies the interconnect structure while reducing contact resistance and process complexity.

[0110] Optionally, the third conductive layer M3 includes an initialization signal line 230, which is used to transmit an initialization signal AC_Vini. The initialization signal line 230 extends along the second direction Y, and its orthographic projection on the substrate 110 overlaps with the orthographic projection of the first electrode of the second transistor T3 of the second sub-active layer 122 on the substrate 110. A third via is provided at the overlap position between the initialization signal line 230 and the second sub-active layer 122, and the initialization signal line 230 is connected to the first electrode of the second transistor T3 through the third via.

[0111] Specifically, in this embodiment of the invention, the initialization signal line 230 extends along the second direction Y. The initialization signal line 230 provides an initialization signal AC_Vini to the second transistor T3 and the second capacitor C2 in the pixel circuit. On the plane, the initialization signal line 230 is arranged adjacent to the second channel region. Depending on design requirements, the initialization signal line AC_Vini 230 may partially obscure the second channel region or not; no specific limitation is made here. The orthographic projection of the initialization signal line 230 onto the substrate 110 overlaps at least partially with the orthographic projection of the second sub-active layer 122 onto the substrate 110. This overlap corresponds to the first electrode of the second transistor T3. A third via K3 is formed in the insulating layer between the initialization signal line 230 and the second sub-active layer 122, allowing the initialization signal line 230 to be electrically connected to the first electrode of the second transistor T3 through the third via K3. This utilizes the third via K3 to achieve vertical interconnection, effectively avoiding the occupation of limited space within the pixel by traditional lateral leads.

[0112] Combination Figure 1 and Figure 4 Optionally, the first transistor T2 and the second transistor T3 are transistors of the same conductivity type. In this embodiment of the invention, the first transistor T2 and the second transistor T3 are P-type transistors for example. In other embodiments, the first transistor T2 and the second transistor T3 can also be N-type transistors, which can improve leakage current. When the transistor type is switched from P-type to N-type, the corresponding control logic also needs to be adjusted accordingly. Specifically, the timing of the scan signals received by the first transistor T2 and the second transistor T3 needs to be reversed compared to the P-type case, requiring adaptation design. From a manufacturing process perspective, for N-type TFT devices, a nanoscale local deposition and doping (NLDD) process needs to be introduced. This process can precisely introduce n-type dopants in specific regions of the active layer (such as source / drain regions) and, combined with local dielectric layer or metal-induced crystallization technology, optimize contact resistance and channel characteristics, thereby improving the device's on / off ratio and stability.

[0113] Optionally, the orthographic projection of the first plate C21 of the second capacitor C2 at least covers the region of the first electrode of the first transistor T2 corresponding to the first sub-active layer 121, as well as part of the data signal line 140; and the orthographic projection of the first plate C21 of the second capacitor C2 does not overlap with the region of the second electrode of the first transistor T2 corresponding to the first sub-active layer 121.

[0114] Specifically, the first plate C21 of the second capacitor C2 is located in the upper region of the first sub-active layer 121, and can largely cover the first sub-active layer 121. The orthographic projection of the first plate C21 of the second capacitor C2 at least covers the region of the first electrode of the first transistor T2 corresponding to the first sub-active layer 121. This allows for a more compact spatial arrangement and maximizes the effective planar area of ​​the first plate C21 of the second capacitor C2, thereby significantly increasing the capacitance value within a limited pixel area, enhancing the voltage holding capability of the driving node, and improving display uniformity and grayscale stability. The first plate C21 of the second capacitor C2 can also extend to cover part of the data signal line 140, shielding the coupling effect of the data signal Vdata on the voltage of the upper first gate G3, reducing the parasitic capacitance between the data signal line 140 and the first gate G3, thereby reducing signal crosstalk, improving pixel charging accuracy, and enhancing display stability at high refresh rates. In the thickness direction, the regions of the first plate C21 of the second capacitor C2 and the first electrode of the first transistor T2 corresponding to the first sub-active layer 121 do not overlap, thereby avoiding the space for the connection line of the first transistor T2 in the thickness direction.

[0115] See also Figure 4 In this embodiment of the invention, the first plate C21 of the second capacitor C2 and the initialization signal line 230 are both disposed on the third conductive layer M3 and are adjacent in the first direction X. Based on the circuit connection, the first plate C21 of the second capacitor C2 is electrically connected to the initialization signal AC_Vini, therefore the potential of the first plate C21 of the second capacitor C2 is consistent with that of the initialization signal line 230. In the layout design of the array substrate, the first plates C21 of the second capacitor C2 and the initialization signal line 230 adjacent in the first direction X can be integrated on the same continuous conductive plane, i.e., merged into a large conductive area. This not only simplifies the mask pattern and etching process but also significantly expands the effective coverage area of ​​the first plates C21 of the second capacitor C2, thereby increasing the capacitance value and enhancing the voltage retention capability of the pixel driving node. Furthermore, the continuous conductive plane can cover a large area of ​​the data signal line 140 below, effectively suppressing the electric field coupling interference of the data signal Vdata transition to the gate of the driving transistor T1 above, further reducing the parasitic capacitance between the data signal line 140 and the first gate G3, reducing signal crosstalk, and improving pixel charging accuracy and display stability.

[0116] Figure 6 This is a top view schematic diagram of a third conductive layer and a fourth conductive layer provided in an embodiment of the present invention, combined with... Figure 4 See Figure 6The second electrode C22 of the second capacitor C2 is located in the fourth conductive layer M4, and the orthographic projection of the first electrode C21 of the second capacitor C2 on the substrate 110 at least covers the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate 110; wherein, in the second direction Y, the width dimension of the first electrode C21 of the second capacitor C2 is greater than the width dimension of the second electrode C22 of the second capacitor C2.

[0117] Specifically, by limiting the width of the first plate C21 of the second capacitor C2 to the second direction Y, the width of the first plate C21 of the second capacitor C2 is larger than the width of the second plate C22 of the second capacitor C2. This ensures that the first plate C21 of the second capacitor C2 completely covers the second plate C22 of the second capacitor C2 in the second direction Y, thereby ensuring that the two form an effective capacitor structure in the vertical stacking structure. In the actual manufacturing process, due to the existence of photolithographic alignment error (OVL), the second plate C22 of the second capacitor C2 may have a slight offset in the plane relative to the first plate C21 of the second capacitor C2. If the two plates are of similar size, the OVL offset will directly lead to a reduction in the effective overlap area, which in turn causes fluctuations in the capacitance value, affecting the voltage holding capability of the pixel circuit and display consistency.

[0118] Therefore, when the first plate C21 of the second capacitor C2 completely covers the second plate C22 of the second capacitor C2 in the second direction Y, the actual overlap area between the first plate C21 and the second plate C22 of the second capacitor C2 can be adjusted by adjusting the width of the first plate C21 in the first direction X. This improves the adaptability to OVL process deviations and provides a flexible means of controlling the data voltage range.

[0119] Figure 7 This is a top view schematic diagram of an array substrate provided in an embodiment of the present invention. For ease of understanding, Figure 7 The text primarily reflects the relationship between the third to fifth conductive layers and the first active layer. Figure 8 This is a top view of the third to fifth conductive layers in the array substrate provided in an embodiment of the present invention. See also: Figure 7 and Figure 8 The fifth conductive layer M5 includes a first conductive sublayer M51 and a second conductive sublayer M52. The first conductive sublayer M51 and the second conductive sublayer M52 are arranged along the first direction X and are connected. The first conductive sublayer M51 and the second conductive sublayer M52 constitute the first gate G3 of the driving transistor T1.

[0120] Wherein, the orthographic projection of the first conductive sublayer M51 covers at least part of the second plate C22 of the second capacitor C2, and the first conductive sublayer M51 serves as the first plate C11 of the first capacitor C1.

[0121] The orthographic projection of the second conductive sublayer M52 on the substrate 110 overlaps with the orthographic projection of the first sub-active layer 121 corresponding to the second electrode of the first transistor T2 on the substrate 110. The second via K2 is disposed at the overlapping position between the second conductive sublayer M52 and the first sub-active layer 121. The second electrode of the first transistor T2 is connected to the first gate G3 of the driving transistor T1 through the second via K2.

[0122] Specifically, the first conductive sublayer M51 and the second conductive sublayer M52 form a continuous conductive plane in the first direction X. The first conductive sublayer M51 can serve as the first electrode C11 of the first capacitor C1. Its orthogonal projection on the substrate 110 overlaps with the second electrode C22 of the second capacitor C2 located in the fourth conductive layer M4, thereby forming the first capacitor C1. The conductive plane formed by the first conductive sublayer M51 and the second conductive sublayer M52 is reused as the first gate G3 of the driving transistor T1, realizing the integration of device functions.

[0123] Optionally, in the second direction Y, the width of the first electrode C11 of the first capacitor C1 is larger than the width of the second electrode C22 of the second capacitor C2. This ensures that the first electrode C11 of the first capacitor C1 completely covers the second electrode C22 of the second capacitor C2 in the second direction Y, thereby forming an effective capacitor area in the vertical stacking structure. In actual mass production, the linewidth of the second electrode of the second capacitor C2 may change slightly due to fluctuations in photolithography or etching processes. Through the width redundancy design of the first electrode C11 of the first capacitor C1, when the linewidth of the second electrode of the second capacitor C2 changes, the effective overlap area of ​​the first electrode C11 and the second electrode C22 of the second capacitor C2, as well as the effective overlap area of ​​the first electrode C21 and the second electrode C22 of the second capacitor C2, can change synchronously and in the same direction, for example, simultaneously increasing or simultaneously decreasing. This maintains a consistent trend in capacitance changes, effectively avoiding drastic fluctuations in drive current caused by capacitor mismatch, and enhancing the consistency of product yield and display performance.

[0124] The orthographic projection of the second conductive sublayer M52 onto the substrate 110 includes a region that overlaps only with the first sub-active layer 121, and the overlapping region corresponds to the second electrode of the first transistor T2. A second via K2 is provided in the multilayer insulating layer at the overlapping location. The second via K2 penetrates the multilayer insulating layer, and the second conductive sublayer M52 connects the second electrode of the first transistor T2 to the first gate G3 of the driving transistor T1 through the second via K2. Based on the above overall layout, the second electrodes of the first transistor T2 and the second electrodes of the second transistor T3 are connected at a common junction, so the first gate G3 of the driving transistor T1 and the second electrode of the second transistor T3 can be connected simultaneously, further improving space utilization. The first electrode C21 and the second electrode C22 of the second capacitor C2, the first trace 210 and the second trace 220 actively avoid the area where the second via K2 is located in the layout design to ensure that the via opening is complete and the contact is reliable, avoiding increased contact resistance or process defects caused by metal coverage.

[0125] Optionally, in the second direction Y, the width of the first conductive sublayer M51 is greater than the width of the second conductive sublayer M52, so that the vertical distance between the edge of the first conductive sublayer M51 and the edge of the adjacent data signal line 140 in the second direction Y is greater than the vertical distance between the edge of the second conductive sublayer M52 and the edge of the same data signal line 140 in the second direction Y.

[0126] Specifically, in combination Figure 4 and Figure 7 In the thickness direction, the orthographic projection of the first conductive sublayer M51 onto the substrate 110 overlaps with the first electrode C21 of the second capacitor C2 located in the third conductive layer M3. Since the first electrode C21 of the second capacitor C2 itself covers part of the underlying data signal line 140, and is at a fixed or controlled potential (e.g., initialization voltage), it effectively provides electrostatic shielding, suppressing electric field coupling interference generated by the data signal Vdata on the first gate G3 of the driving transistor T1 above, and reducing the vertical parasitic capacitance between the data signal line 140 and the first gate G3. Based on this, the width of the first conductive sublayer M51 can be maximized, without needing to deliberately reduce its area to avoid parasitic coupling. This not only ensures the functional integrity of the first electrode of the first capacitor C1, but also maximizes the effective overlapping area of ​​the first capacitor C1, significantly increasing the storage capacitance value and enhancing the voltage holding capability of the driving node.

[0127] Furthermore, since the orthographic projection of the second conductive sublayer M52 onto the substrate 110 does not overlap with the first electrode C21 of the second capacitor C2 in the third conductive layer M3, this region lacks the shielding structure protection of the first electrode C21 of the second capacitor C2. If the width of the second conductive sublayer M52 is too large, its edge will be closer to the data signal line 140, thereby aggravating lateral electric field coupling and increasing lateral parasitic capacitance. Therefore, in this embodiment of the invention, the second conductive sublayer M52 is designed to be narrower, that is, the width of the second conductive sublayer M52 is appropriately reduced in the second direction Y, thereby effectively increasing the lateral spacing between the second conductive sublayer M52 and the adjacent data signal line 140, thereby reducing lateral parasitic capacitance, suppressing signal crosstalk, and avoiding affecting the area of ​​the first capacitor C1.

[0128] See also Figure 8 The second active layer 130 extends along the first direction X. The second active layer 130 includes a third channel region 131 of the driving transistor T1 and a first electrode and a second electrode of the driving transistor T1 located on both sides of the third channel region 131.

[0129] The orthographic projection of the third channel region 131 of the driving transistor T1 onto the substrate 110 lies within the orthographic projection of the first conductive sublayer M51 and the second conductive sublayer M52 onto the substrate 110. In other words, the first gate G3 of the driving transistor T1, formed by the first conductive sublayer M51 and the second conductive sublayer M52, completely covers the underlying third channel region 131 on the plane. The shielding of the third channel region 131 by the first gate G3 effectively blocks electromagnetic interference from ambient light and the influence of photogenerated carriers, significantly improving the device's operational stability under complex electromagnetic environments or strong light conditions.

[0130] Optionally, the driving transistor T1 further includes a second gate G4, which is connected to the second terminal of the driving transistor T1 and the second plate C22 of the second capacitor C2.

[0131] Figure 9 This is a top view of the sixth conductive layer in the array substrate provided in an embodiment of the present invention. See also: Figure 9 The array substrate also includes a sixth conductive layer M6, which is located on the side of the second active layer 130 away from the substrate 110. The second gate G4 is located on the sixth conductive layer M6. The orthographic projection of the second gate G4 on the substrate 110 overlaps with the orthographic projection of the third channel region 131 on the substrate 110. Similarly, the second gate G4 can shield the third channel region 131, effectively shielding the electromagnetic interference of ambient light and the influence of photogenerated carriers, further improving the working stability of the device.

[0132] Optionally, in the first direction X, the second electrode of the driving transistor T1 is located on the side of the third channel region 131 away from the second conductive layer M52.

[0133] Specifically, in combination Figure 1 In the pixel circuit design shown, the second electrode C22 of the second capacitor C2 is electrically connected to the anode of the light-emitting diode. In the layout design, the second electrode C22 of the second capacitor C2 can further transmit the anode potential, realizing the integration of the capacitor electrode and the power supply trace, effectively reducing wiring requirements and improving the space utilization efficiency within the pixel. In the layout design, to minimize the lateral wiring density and avoid interlayer interconnection conflicts, in this embodiment of the invention, the second electrode of the driving transistor T1 is located on the side of the third channel region 131 away from the second conductive sublayer M52, which can be located close to the upper layer of the second electrode C22 of the second capacitor C2, reserving interconnection channel space for the anode connection, thereby facilitating low-resistance connection through short vertical vias. Setting the second electrode of the driving transistor T1 on the side of the third channel region 131 away from the second conductive sublayer M52 can also effectively avoid overlapping with the first electrode of the first capacitor C1 in the thickness direction, avoiding the need to separately lead out connection traces again.

[0134] Optionally, the orthographic projection of the second gate G4 on the substrate 110 and the orthographic projection of the second electrode of the driving transistor T1 on the substrate 110 have a first overlapping region 240. The orthographic projection of the first overlapping region 240 on the substrate 110 overlaps with the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate 110, and the orthographic projection of the first overlapping region 240 on the substrate 110 does not overlap with the orthographic projection of the first gate G3 on the substrate 110. That is, in the thickness direction, the first overlapping region 240 avoids overlapping with the first electrode C11 of the first capacitor C1, ensuring that the interconnection path between the second gate G4 and the second electrode C22 of the second capacitor C2 does not penetrate the first electrode C11 of the first capacitor C1 in the thickness direction.

[0135] Based on this layout, at the position corresponding to the first overlapping region 240, a fifth via K5 is formed in the interlayer dielectric between the second gate G4 and the second electrode plate of the second capacitor C2. The fifth via K5 is a deep hole, and the vertical projection of the fifth via K5 on the substrate 110 does not overlap with the vertical projection of the first gate G3 on the substrate 110, so as to achieve vertical penetration from the top second gate G4 to the bottom second electrode plate of the second capacitor C2.

[0136] Through the fifth via K5, the three conductive layers—the second gate G4, the second electrode of the driving transistor T1, and the second plate C22 of the second capacitor C2—are effectively connected and enable signal communication. Specifically, the second gate G4 and the second electrode of the driving transistor T1 have a sidewall overlap structure, meaning they are in lateral contact and connected to the lower capacitor plate via a via, rather than the traditional multi-level via stacking scheme. This design reduces the number of via structures and simplifies the fabrication process. Furthermore, since the first overlapping region 240 avoids the first gate G3, the lateral area of ​​the first capacitor C1 formed by the overlap of the first gate G3 and the second plate C22 of the second capacitor C2 is maximized, further improving the compensation effect and reducing current variations caused by process fluctuations.

[0137] Figure 10 This is a top view of the seventh conductive layer in the array substrate provided in an embodiment of the present invention. See also: Figure 10 The array substrate also includes a seventh conductive layer M7, which is located on the side of the sixth conductive layer M6 away from the substrate 110.

[0138] The seventh conductive layer M7 includes a connecting sublayer M71;

[0139] The vertical projection of the connecting sublayer M71 on the substrate 110 overlaps with the vertical projection of the second gate G4 on the substrate 110. A sixth via K6 is provided at the overlapping position between the connecting sublayer M71 and the second gate G4. The connecting sublayer M71 is connected to the second gate G4 through the sixth via K6.

[0140] Specifically, the seventh conductive layer M7 is patterned to form a connecting sublayer M71. The connecting sublayer M71 is located above the second gate G4 and serves as a transfer layer for the anode signal, used to lead the anode electrical signal to the anode of the light-emitting diode. The connecting sublayer M71 is connected to the second gate G4 through the sixth via K6 to achieve the transfer of the anode signal.

[0141] Optionally, the array substrate further includes a planarization layer, a conductive material layer D1, and an anode layer. The planarization layer is located on the side of the seventh conductive layer M7 away from the substrate 110. The planarization layer includes an eighth via, which penetrates the planarization layer and exposes part of the connection surface of the connecting sub-layer M71, establishing a vertical channel for the anode signal output. The conductive material layer D1 is formed in the eighth via and on the surface of the planarization layer. The conductive material layer D1 at least covers the bottom wall and sidewall of the eighth via, and at least part of the conductive material layer D1 covers the surface of the planarization layer. The anode layer includes multiple independent anodes, each corresponding to a light-emitting diode. The anode of the light-emitting diode is indirectly connected to the connecting sub-layer M71 through the conductive material layer D1. The connecting sub-layer M71 is connected to the second gate G4 through the sixth via K6. The second gate G4 is further electrically connected to the second electrode C22 of the second capacitor C2, realizing the connection between the anode of the light-emitting diode and the anode signal.

[0142] Optionally, the conductive material layer D1 can be made of transparent conductive materials such as indium tin oxide (ITO), which balances high conductivity, optical transmittance, and good compatibility with OLED processes. The transition through the conductive material layer D1 avoids interference or short-circuit problems that may arise from excessive density caused by traditional direct anode wiring, thereby freeing up planar space to achieve higher PPI.

[0143] Optionally, the seventh conductive layer M7 further includes a first power supply trace M72; the first power supply trace M72 extends along the second direction Y and is used to transmit the first power signal AC_VDD. In the layout, the vertical projection of the first power supply trace M72 on the substrate 110 overlaps with the vertical projection of the first electrode of the driving transistor T1 on the substrate 110. A seventh via K7 is provided at the overlapping position, through which the first power supply trace M72 is connected to the first electrode of the driving transistor T1. By utilizing local vertical connections, the low impedance characteristics of the power supply are ensured, and the lateral space occupied by the pixel is minimized. The orthographic projection of the seventh via K7 on the substrate 110 does not overlap with the orthographic projection of the second gate G4 on the substrate 110, thus avoiding potential electrical interference or short-circuit risks between the first power supply trace M72 and the second gate G4 in the thickness direction.

[0144] Figure 11 For another structural schematic diagram of a pixel circuit provided in an embodiment of the present invention, see [link to schematic diagram]. Figure 11 The embodiments of the present invention and Figure 1 The difference in the embodiment is that the pixel circuit includes a third transistor T4; the first terminal of the third transistor T4 is connected to the first power supply line M72, and the second terminal of the third transistor T4 is connected to the first terminal of the driving transistor T1.

[0145] Specifically, the gate control signal EM of the third transistor T4 is the global signal Common. The third transistor T4 improves the compensation effect by addressing the voltage Vgs loss between the first gate G3 and the second electrode of the driving transistor T1 caused by the anode potential rise due to the large current of the driving transistor T1 during the high grayscale data writing process. Figure 12 This is another control timing diagram of a pixel circuit provided in an embodiment of the present invention, which can be applied to... Figure 11 In the pixel circuit shown in this embodiment of the invention, the first transistor T2 and the third transistor T4 are P-type transistors. (See [link to relevant documentation]). Figure 11 and Figure 12 In this configuration, the initialization signal AC_Vini and the data signal Vdata of the first gate G3 of the driving transistor T1 are both controlled by the gate G1 control signal of the first transistor T2, i.e., the first scan signal S2, which is a composite GIP signal. Other AC signal voltage settings and functional timing are... Figure 2 The same applies here, so I will not repeat it further.

[0146] Optionally, the first transistor T2 and the third transistor T4 are transistors of the same conductivity type. In this embodiment of the invention, the first transistor T2 and the third transistor T4 are P-type transistors as an example. In other embodiments, the first transistor T2 and the third transistor T4 can also be N-type transistors, which can improve leakage current. When the transistor type is switched from P-type to N-type, the corresponding control logic also needs to be adjusted accordingly. Specifically, the timing of the scan signal received by the first transistor T2 and the third transistor T4 needs to be reversed compared to the P-type case, requiring adaptation design. From a manufacturing process perspective, N-type TFT devices require the introduction of NLDD (Neutral Non-Drain) technology. This process can precisely introduce N-type dopants in specific regions of the active layer (such as source / drain regions) and, combined with local dielectric layer or metal-induced crystallization technology, optimize contact resistance and channel characteristics, thereby improving the device's on / off ratio and stability.

[0147] Figure 13 This is a schematic diagram of another pixel circuit stacking structure provided in an embodiment of the present invention, with reference to... Figure 13 In the layout structure, the first active layer 120 includes a third sub-active layer 123 extending along the first direction X, and the first sub-active layer 121 and the third sub-active layer 123 are arranged at intervals along the first direction X; wherein, the driving transistor T1, the first capacitor C1, the second capacitor C2 and the first transistor T2 are still arranged in an architecture of upper, middle and lower layers in the thickness direction.

[0148] Optionally, the gate of the third transistor T4 is located in the first conductive layer M1; the first conductive layer M1 includes a third trace extending along the second direction Y; the third trace can be configured to transmit the gate control signal of the third transistor T4, thereby eliminating the need for additional independent traces and significantly reducing the occupancy of redundant wiring in the pixel's lateral space. In the first direction X, the third trace is located on the side of the first trace 210 away from the first extension 1210, and the orthographic projection of the third trace on the substrate 110 and the orthographic projection of the third sub-active layer 123 on the substrate 110 have a third intersection region, and the portion of the third trace corresponding to the third intersection region serves as the gate of the third transistor T4; the portion of the third sub-active layer 123 located below the orthographic projection of the gate of the third transistor T4 is the fourth channel region of the third transistor T4, and the two sides of the fourth channel region are the first electrode and the second electrode of the third transistor T4, respectively;

[0149] The fourth channel region is located on the side closest to the first channel region, which is the second terminal of the third transistor T4, facilitating the vertical wiring connection between the second terminal of the third transistor T4 and the driving transistor T1.

[0150] Combination Figure 14 The embodiments of the present invention and Figure 3 The difference lies in that the third conductive layer M3 includes a first power supply trace M72, which is used to transmit the first power signal AC_VDD. The first power supply trace M72 extends along the second direction Y. The orthographic projection of the first power supply trace M72 on the substrate 110 overlaps with the orthographic projection of the first electrode of the third transistor T4 of the third sub-active layer 123 on the substrate 110. A ninth via K9 is provided at the overlap position between the first power supply trace M72 and the third sub-active layer 123, and the first power supply trace M72 is connected to the first electrode of the third transistor T4 through the ninth via K9. Figure 14 It should be noted that, with Figure 4 Unlike other power supply lines, the first power supply line M72 and the first plate C21 of the second capacitor C2 have different potentials. Therefore, adjacent first power supply lines M72 and the first plate C21 of the second capacitor C2 in the first direction X cannot form a continuous conductive plane. Instead, a certain gap space needs to be set to avoid causing a signal short circuit.

[0151] The second terminal of the third transistor T4 is connected to the first terminal of the driving transistor T1 through the tenth via. It should be noted that a connecting sublayer M71 can be set in the sixth conductive layer M6, and a tenth via can be set between the connecting sublayer M71 and the first terminal of the driving transistor T1. The tenth via penetrates the second active layer 130 corresponding to the first terminal of the driving transistor T1, and the connecting sublayer M71 and the first terminal of the driving transistor T1 have a sidewall overlap structure, simplifying the fabrication process. Since the tenth via is a deep via structure, to improve connection stability, a transition sublayer can be set in the fifth conductive layer M5. The connecting sublayer M71 is then connected to the second terminal of the third transistor T4 through the transition sublayer, thus realizing the connection between the second terminal of the third transistor T4 and the first terminal of the driving transistor T1 in the circuit structure.

[0152] Figure 14 This is a schematic flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present invention. See also... Figure 14 The array substrate includes a first active layer 120, multiple conductive layers and a second active layer 130, wherein the first active layer 120, multiple conductive layers and the second active layer 130 constitute at least one pixel circuit, and the pixel circuit includes a driving transistor T1, a first transistor T2, a first capacitor C1 and a second capacitor C2.

[0153] Preparation methods include:

[0154] S110, A first active layer 120 is formed on the substrate 110;

[0155] Specifically, a first active layer 120 is formed on one side of the substrate 110. The first active layer 120 can be made using LTPS and the corresponding pattern of the active region of the first transistor T2 is formed by patterning.

[0156] S120, a multilayer conductive layer and a second active layer 130 are sequentially formed on the side of the first active layer 120 away from the substrate;

[0157] The multilayer conductive layer includes a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, a fourth conductive layer M4, and a fifth conductive layer M5 stacked sequentially. The first conductive layer M1 is adjacent to the first active layer 120. The gate G1 of the first transistor T2 is located in the first conductive layer M1. The second conductive layer M2 includes a data signal line 140. The data signal line 140 is connected to the first electrode of the first transistor T2 through a first via K1. The first electrode C21 of the second capacitor C2 is located in the third conductive layer M3. The second electrode C22 of the second capacitor C2 is located in the fourth conductive layer M4. The first gate G3 of the driving transistor T1 and the first electrode C11 of the first capacitor C1 connected to the first gate G3 of the driving transistor T1 are located in the fifth conductive layer M5. The first gate G3 of the driving transistor T1 is multiplexed as the first electrode C11 of the first capacitor C1. The first gate G3 of the driving transistor T1 is connected to the second electrode of the first transistor T2 through a second via K2.

[0158] The second plate C22 of the second capacitor C2 is reused as a common plate as the second plate of the first capacitor C1; the vertical projection of the first plate C11 of the first capacitor C1 onto the second plate C22 of the second capacitor C2 at least partially overlaps with the vertical projection of the first plate C21 of the second capacitor C2 onto the second plate C22 of the second capacitor C2.

[0159] Specifically, a first conductive layer M1 is formed on the side of the first active layer 120 away from the substrate 110, and the gate G1 of the first transistor T2 is formed by patterning. The material of the first conductive layer M1 can be metals such as Mo, Al, and Cu, or alloys of these metals.

[0160] The material of the second conductive layer M2 can be metals such as Mo, Ti, Al, Cu and their alloys. The second conductive layer M2 includes a data signal line 140. The orthographic projection of the data signal line 140 on the substrate 110 overlaps with the orthographic projection of the first electrode of the first transistor T2 on the substrate 110. A first via K1 is provided in the insulating layer between the orthographic projection of the data signal line 140 on the substrate 110 and the first electrode of the first transistor T2. The data signal line 140 is connected to the first electrode of the first transistor T2 through the first via K1, realizing the interconnection layout in the thickness direction.

[0161] The first electrode C21 of the second capacitor C2 is located in the third conductive layer M3. The material of the third conductive layer M3 can be metals such as Mo, Ti, Al, Cu and their alloys. The third conductive layer M3 also includes an initialization signal line 230. The initialization signal line 230 is used to provide an initialization signal AC_Vini to the second transistor T3 and the second capacitor C2 in the pixel circuit. Referring to the figure, the initialization signal line 230 is electrically connected to the first electrode of the second transistor T3 through the third via K3, thereby realizing vertical interconnection by using the third via K3, effectively avoiding the occupation of the limited space within the pixel by traditional horizontal leads.

[0162] The second electrode C22 of the second capacitor C2 is located in the fourth conductive layer M4; the orthographic projection of the first electrode C21 of the second capacitor C2 on the substrate 110 and the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate 110 at least partially overlap, and the overlapping area constitutes the effective capacitance of the second capacitor C2.

[0163] The first electrode C11 of the first capacitor C1 is located in the fifth conductive layer M5. The orthographic projection of the first electrode C11 of the first capacitor C1 on the substrate 110 at least partially overlaps with the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate 110. The overlapping area constitutes the effective capacitance of the first capacitor C1. That is, the second electrode C22 of the second capacitor C2 is reused as the second electrode of the first capacitor C1. As a common electrode, the first capacitor C1 and the second capacitor C2 are formed simultaneously in the thickness direction of the array substrate. The vertically stacked capacitor structure can significantly save lateral layout space.

[0164] Furthermore, the vertical projection of the first plate C11 of the first capacitor C1 onto the second plate C22 of the second capacitor C2 at least partially overlaps with the vertical projection of the first plate C21 of the second capacitor C2 onto the second plate C22 of the second capacitor C2, thereby realizing the arrangement of the first capacitor C1 and the second capacitor C2 stacked vertically in the thickness direction, further compressing the lateral occupied area and providing a structural basis for the high-resolution display panel.

[0165] The second active layer 130 is located on the side of the fifth conductive layer M5 away from the substrate 110. The second active layer 130 is used to form the active region of the driving transistor T1, and the second active layer 130 can be made of IGZO material. The orthographic projection of the first electrode C11 of the first capacitor C1 onto the substrate 110 overlaps with the orthographic projection of the second active layer 130 onto the substrate 110. The first electrode C11 of the first capacitor C1 can be reused as the first gate G3 of the driving transistor T1. Therefore, it is not necessary to separately set a conductive layer to prepare the first gate G3 of the driving transistor T1, which not only simplifies the manufacturing process but also further optimizes the space utilization within the pixel.

[0166] Optionally, the array substrate includes: the driving transistor T1 further includes a second gate G4;

[0167] Preparation methods include:

[0168] A sixth conductive layer M6 is formed on the side of the second active layer 130 away from the substrate 110, and the second gate G4 is located in the sixth conductive layer M6. The orthogonal projection of the second gate G4 on the substrate 110 overlaps with the orthogonal projections of the second electrode and the third channel region 131 of the driving transistor T1 on the substrate 110. The second gate G4 can shield the third channel region 131, effectively shielding the electromagnetic interference of ambient light and the influence of photogenerated carriers, and further improving the working stability of the device.

[0169] Because the second gate G4 blocks the second electrode of the driving transistor T1, it is impossible to use the second gate G4 to block the third channel region 131 during the process fabrication, thus preventing the active layer from being conductively fabricated.

[0170] Before the formation of the sixth conductive layer M6, the following is also included:

[0171] A shielding layer is provided on the surface of the third channel region 131 defined on the second active layer 130, and conductive injection is performed on both sides of the third channel region 131 of the second active layer 130 to form the first electrode and the second electrode of the driving transistor T1.

[0172] Specifically, Figure 15 This is a schematic diagram of an intermediate fabrication process for an array substrate according to an embodiment of the present invention. See also... Figure 15 The masking layer 310 can be made of photoresist. The masking layer 310 is used to shield the third channel region 131, and then the first and second electrodes of the driving transistor T1 are implanted on both sides of the third channel region 131 to ensure a conductive effect. Structurally, the first gate G3 and the second gate G4 can completely cover the third channel region 131 defined on the second active layer 130, thereby achieving a light-shielding effect and improving the reliability of the driving transistor T1.

[0173] This invention also provides a display panel comprising the array substrate provided in any embodiment of the invention. Therefore, this display panel also possesses the beneficial effects described in any of the above embodiments. The display panel can be a flexible display panel or a rigid display panel. By employing the array substrate provided in any of the above embodiments, the display panel formed can effectively increase the PPI and improve the display effect. Figure 16This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. In this embodiment, the display panel 200 can be a mobile phone panel, or it can be applied to any electronic product with display function, including but not limited to the following categories: display panels in products such as televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, and touch interactive terminals. The present invention does not impose any special limitations on this.

[0174] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An array substrate, characterized in that, include: Substrate; A first active layer, a multilayer conductive layer, and a second active layer are stacked on one side of the substrate, wherein the first active layer is adjacent to the substrate, and the first active layer, the multilayer conductive layer, and the second active layer constitute at least one pixel circuit, the pixel circuit including a driving transistor, a first transistor, a first capacitor, and a second capacitor. The multilayer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked sequentially. The first conductive layer is adjacent to the first active layer. The gate of the first transistor is located on the first conductive layer. The second conductive layer includes a data signal line. The data signal line is connected to the first electrode of the first transistor through a first via. The first electrode of the second capacitor is located on the third conductive layer. The second electrode of the second capacitor is located on the fourth conductive layer. The first gate of the driving transistor and the first electrode of the first capacitor connected to the first gate of the driving transistor are located on the fifth conductive layer. The first gate of the driving transistor is multiplexed as the first electrode of the first capacitor. The first gate of the driving transistor is connected to the second electrode of the first transistor through a second via. The second plate of the second capacitor is reused as a common plate as the second plate of the first capacitor; the vertical projection of the first plate of the first capacitor onto the second plate of the second capacitor overlaps at least partially with the vertical projection of the first plate of the second capacitor onto the second plate of the second capacitor.

2. The array substrate according to claim 1, characterized in that, The first active layer includes a first sub-active layer extending along a first direction, and the first conductive layer includes a first trace extending along a second direction; the first direction intersects the second direction. The orthographic projection of the first trace on the substrate and the orthographic projection of the first sub-active layer on the substrate have a first intersection region, and the portion of the first trace corresponding to the first intersection region serves as the gate of the first transistor. Preferably, the first trace is used to transmit the second scan signal of the first transistor; Preferably, the portion of the first sub-active layer located below the orthographic projection of the gate of the first transistor is the first channel region of the first transistor, and the two sides of the first channel region are the first electrode and the second electrode of the first transistor, respectively. Preferably, a first extension portion extending along the second direction is provided at one end of the first sub-active layer corresponding to the first electrode of the first transistor. The data signal line extends along the first direction, and the orthographic projection of the data signal line on the substrate overlaps with the orthographic projection of the first extension portion on the substrate. The first via is disposed at the overlapping position between the data signal line and the first extension portion, and the data signal line is connected to the first electrode of the first transistor through the first via.

3. The array substrate according to claim 2, characterized in that, The pixel circuit further includes a second transistor; the first terminal of the second transistor is connected to an initialization signal, and the second terminal of the second transistor is connected to the first gate of the driving transistor. Preferably, the first active layer includes a second sub-active layer extending along the first direction, and the first sub-active layer and the second sub-active layer are arranged along the first direction; Preferably, the gate of the second transistor is located in the first conductive layer; the first conductive layer includes a second trace extending along the second direction; in the first direction, the second trace is located on the side of the first trace away from the first extension, the orthographic projection of the second trace on the substrate and the orthographic projection of the second sub-active layer on the substrate have a second intersection region, and the portion of the second trace corresponding to the second intersection region serves as the gate of the second transistor. Preferably, the second trace is used to transmit control signals for the second transistor; Preferably, the portion of the second sub-active layer located below the orthographic projection of the gate of the second transistor is the second channel region of the second transistor, and the two sides of the second channel region are the first electrode and the second electrode of the second transistor, respectively. Preferably, the side of the second channel region closest to the first channel region is the second electrode of the second transistor; Preferably, the first sub-active layer is connected to the second sub-active layer so that the second electrode of the first transistor and the second electrode of the second transistor are connected; Preferably, the third conductive layer includes an initialization signal line extending along the second direction. The orthographic projection of the initialization signal line on the substrate overlaps with the orthographic projection of the first electrode of the second transistor of the second sub-active layer on the substrate. A third via is provided at the overlap position between the initialization signal line and the second sub-active layer, and the initialization signal line is connected to the first electrode of the second transistor through the third via. Preferably, the first transistor and the second transistor are transistors of the same conductivity type.

4. The array substrate according to claim 2, characterized in that, The orthographic projection of the first plate of the second capacitor at least covers the region of the first electrode of the first transistor corresponding to the first sub-active layer, as well as a portion of the data signal lines; and the orthographic projection of the first plate of the second capacitor does not overlap with the region of the second electrode of the first transistor corresponding to the first sub-active layer. Preferably, the orthographic projection of the first plate of the second capacitor onto the substrate at least covers the orthographic projection of the second plate of the second capacitor onto the substrate; wherein, in the second direction, the width dimension of the first plate of the second capacitor is greater than the width dimension of the second plate of the second capacitor.

5. The array substrate according to claim 4, characterized in that, The fifth conductive layer includes a first conductive sublayer and a second conductive sublayer, the first conductive sublayer and the second conductive sublayer are arranged along the first direction and are connected, the first conductive sublayer and the second conductive sublayer constitute the first gate of the driving transistor; Wherein, the orthographic projection of the first conductive sublayer at least covers part of the second plate of the second capacitor, and the first conductive sublayer serves as the first plate of the first capacitor; The orthographic projection of the second conductive sub-layer on the substrate overlaps with the orthographic projection of the first sub-active layer corresponding to the second electrode of the first transistor on the substrate. The second via is disposed at the overlap position between the second conductive sub-layer and the first sub-active layer. The second electrode of the first transistor is connected to the first gate of the driving transistor through the second via. Preferably, in the second direction, the width of the first plate of the first capacitor is greater than the width of the second plate of the second capacitor; Preferably, in the second direction, the width of the first conductive sublayer is greater than the width of the second conductive sublayer, such that the vertical distance between the edge of the first conductive sublayer and the edge of the adjacent data signal line in the second direction is greater than the vertical distance between the edge of the second conductive sublayer and the edge of the same data signal line in the second direction.

6. The array substrate according to claim 5, characterized in that, The second active layer extends along the first direction, and the second active layer includes the third channel region of the driving transistor and the first electrode and the second electrode of the driving transistor located on both sides of the third channel region; The orthographic projection of the third channel region of the driving transistor onto the substrate lies within the orthographic projections of the first conductive layer and the second conductive layer onto the substrate.

7. The array substrate according to claim 6, characterized in that, The driving transistor further includes a second gate, which is connected to the second electrode of the driving transistor and the second plate of the second capacitor. Preferably, the array substrate further includes a sixth conductive layer, which is located on the side of the second active layer away from the substrate, and the second gate is located in the sixth conductive layer; Preferably, in the first direction, the second electrode of the driving transistor is located on the side of the third channel region away from the second conductive layer; Preferably, the orthographic projection of the second gate on the substrate and the orthographic projection of the second electrode of the driving transistor on the substrate have a first overlapping region, the orthographic projection of the first overlapping region on the substrate overlaps with the orthographic projection of the second plate of the second capacitor on the substrate, and the orthographic projection of the first overlapping region on the substrate does not overlap with the orthographic projection of the first gate on the substrate; a fifth via is provided between the second gate and the second plate of the second capacitor at a position corresponding to the first overlapping region; wherein, the fifth via penetrates the second active layer, and the vertical projection of the fifth via on the substrate does not overlap with the vertical projection of the first gate on the substrate; the second gate of the driving transistor is connected to the second electrode of the driving transistor and the second plate of the second capacitor through the fifth via; Preferably, the orthogonal projection of the second gate at least covers the third channel region of the driving transistor.

8. The array substrate according to claim 7, characterized in that, The array substrate further includes a seventh conductive layer, which is located on the side of the sixth conductive layer away from the substrate; The seventh conductive layer includes a connecting sublayer; The vertical projection of the connecting sublayer on the substrate overlaps with the vertical projection of the second gate on the substrate, and a sixth via is provided at the overlapping position between the connecting sublayer and the second gate; the connecting sublayer is connected to the second gate through the sixth via; Preferably, the array substrate further includes a planarization layer, a conductive material layer, and an anode layer. The planarization layer is located on the side of the seventh conductive layer away from the substrate. The planarization layer includes an eighth via that penetrates the planarization layer and exposes a portion of the connecting sublayer. The conductive material layer covers the bottom and sidewalls of the eighth via, and at least a portion of the conductive material layer covers the surface of the planarization layer and is connected to the anode layer. Preferably, the seventh conductive layer further includes a first power line; the first power line extends along the second direction, and the vertical projection of the first power line on the substrate overlaps with the vertical projection of the first electrode of the driving transistor on the substrate. A seventh via is provided at the overlap position between the first power line and the first electrode of the driving transistor, and the first power line is connected to the first electrode of the driving transistor through the seventh via. The orthographic projection of the seventh via on the substrate does not overlap with the orthographic projection of the second gate on the substrate. Preferably, the conductive material layer comprises indium tin oxide.

9. The array substrate according to claim 2, characterized in that, The pixel circuit includes a third transistor; the first terminal of the third transistor is connected to a first power supply line, and the second terminal of the third transistor is connected to the first terminal of the driving transistor. Preferably, the first active layer includes a third sub-active layer extending along the first direction, and the first sub-active layer and the third sub-active layer are arranged at intervals along the first direction. Preferably, the gate of the third transistor is located in the first conductive layer; the first conductive layer includes a third trace extending along the second direction; in the first direction, the third trace is located on the side of the first trace away from the first extension, the orthographic projection of the third trace on the substrate and the orthographic projection of the third sub-active layer on the substrate have a third intersection region, and the portion of the third trace corresponding to the third intersection region serves as the gate of the third transistor. Preferably, the third trace is used to transmit control signals for the third transistor; Preferably, the portion of the third sub-active layer located below the orthogonal projection of the gate of the third transistor is the fourth channel region of the third transistor, and the two sides of the fourth channel region are the first electrode and the second electrode of the third transistor, respectively. Preferably, the side of the fourth channel region closest to the first channel region is the second electrode of the third transistor; Preferably, the third conductive layer includes a first power trace extending along the second direction. The orthographic projection of the first power trace on the substrate overlaps with the orthographic projection of the first electrode of the third transistor in the third sub-active layer on the substrate. A ninth via is provided at the overlap position between the first power trace and the third sub-active layer. The first power trace is connected to the first electrode of the third transistor through the ninth via. The second electrode of the third transistor is connected to the first electrode of the driving transistor through a tenth via. Preferably, the first transistor and the third transistor are transistors of the same conductivity type.

10. A method for fabricating an array substrate, characterized in that, include: A first active layer, a multilayer conductive layer, and a second active layer are sequentially formed on the substrate; The first active layer, the multilayer conductive layer, and the second active layer constitute at least one pixel circuit, and the pixel circuit includes a driving transistor, a first transistor, a first capacitor, and a second capacitor. The multilayer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked sequentially. The first conductive layer is adjacent to the first active layer. The gate of the first transistor is located on the first conductive layer. The second conductive layer includes a data signal line. The data signal line is connected to the first electrode of the first transistor through a first via. The first electrode of the second capacitor is located on the third conductive layer. The second electrode of the second capacitor is located on the fourth conductive layer. The first gate of the driving transistor and the first electrode of the first capacitor connected to the first gate of the driving transistor are located on the fifth conductive layer. The first gate of the driving transistor is multiplexed as the first electrode of the first capacitor. The first gate of the driving transistor is connected to the second electrode of the first transistor through a second via. The second plate of the second capacitor is reused as a common plate as the second plate of the first capacitor; the vertical projection of the first plate of the first capacitor onto the second plate of the second capacitor overlaps at least partially with the vertical projection of the first plate of the second capacitor onto the second plate of the second capacitor.

11. The method for fabricating an array substrate according to claim 10, characterized in that, include: The driving transistor further includes a second gate; The preparation method includes: A sixth conductive layer is formed on the side of the second active layer away from the substrate, and the second gate is located on the sixth conductive layer; the orthographic projection of the second gate on the substrate overlaps with the orthographic projections of the second electrode and the third channel region of the driving transistor on the substrate; Preferably, before forming the sixth conductive layer, the method further includes: A shielding layer is provided on the surface of the third channel region defined on the second active layer, and conductive injection is performed on both sides of the third channel region of the second active layer to form the first electrode and the second electrode of the driving transistor.

12. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

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