Protection circuit and electronic assembly

Abstract

The invention provides a protection circuit and an electronic assembly. The protection circuit comprises a plurality of connection ends used for receiving electrical signals; the plurality of first one-way conducting elements are in one-to-one correspondence with the plurality of connecting ends, the input end of each first one-way conducting element is connected with the corresponding connecting end, and the first one-way conducting element has internal resistance and is used for conducting current from the input end to the output end in a one-way manner; the drain electrode of the first N-type metal oxide semiconductor field effect transistor is connected with the output end of each first one-way conduction element, and the first N-type metal oxide semiconductor field effect transistor is used for being conducted when the voltage of the drain electrode reaches a first protection threshold value so as to discharge electrostatic discharge received by the connecting end.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of electrostatic protection, and in particular to a protection circuit and an electronic assembly. BACKGROUND

[0002] The USB (Universal Serial Bus) electronic tag chip (commonly referred to as E-Marker) is an electronic identity tag of the USB Type-C cable, through which various attributes of the cable can be read, including power transmission capability, information transmission capability, and identification code and other information. In this way, the output end (such as a charger or a computer) can adjust the matching voltage / current signal according to the parsed information. Since the E-Marker chip is used as a system external port and may be frequently hot-plugged in a special application environment, the risk of damage to its internal elements by electrostatic surge is greatly increased during high-power transmission.

[0003] In the related art, an electrostatic discharge protection circuit is usually used to protect electronic elements, but it is difficult to withstand a large voltage impact and has poor electrostatic discharge protection effect. SUMMARY

[0004] To overcome the problems in the related art, the present disclosure provides a protection circuit and an electronic assembly.

[0005] The first aspect of the present disclosure provides a protection circuit, which comprises:

[0006] a plurality of connection terminals for receiving electrical signals;

[0007] a plurality of first unidirectional conduction elements corresponding to the plurality of connection terminals, an input end of each first unidirectional conduction element being connected to a corresponding connection terminal, the first unidirectional conduction element having an internal resistance and being used to conduct current from the input end to the output end in one direction.

[0008] a first N-type metal oxide semiconductor field effect transistor, a drain of the first N-type metal oxide semiconductor field effect transistor being connected to an output end of each first unidirectional conduction element, the first N-type metal oxide semiconductor field effect transistor being used to conduct when the voltage at the drain reaches a first protection threshold, so as to discharge the electrostatic discharge received by the connection terminal.

[0009] Optionally, the circuit further comprises:

[0010] a plurality of second unidirectional conduction elements corresponding to the plurality of connection terminals, an input end of each second unidirectional conduction element being connected to ground and an output end of each second unidirectional conduction element being connected to a corresponding connection terminal, the second unidirectional conduction element being used to conduct current from the input end to the output end in one direction.

[0011] Optionally, the second unidirectional conducting element comprises a parasitic diode.

[0012] Optionally, the electrical signal received by each connection end is conducted to the corresponding logic circuit of the connection end.

[0013] For each connection end, the circuit further comprises:

[0014] a second N-type metal oxide semiconductor field effect transistor, a drain of the second N-type metal oxide semiconductor field effect transistor and the logic circuit being connected in parallel to the connection end, the second N-type metal oxide semiconductor field effect transistor being used to turn on when a voltage of the drain reaches a second protection threshold, so as to discharge an electrostatic discharge received by the connection end.

[0015] Optionally, for each connection end, the circuit further comprises:

[0016] a current-limiting resistor, one end of the current-limiting resistor being connected to the connection end.

[0017] a third unidirectional conducting element, an input end of the third unidirectional conducting element being connected to the other end of the current-limiting resistor, the third unidirectional conducting element being used to unidirectionally conduct a current path of the connection end to the logic circuit.

[0018] wherein the drain of the second N-type metal oxide semiconductor field effect transistor and the logic circuit are connected in parallel to an output end of the third unidirectional conducting element.

[0019] Optionally, the electrical signal received by each connection end is conducted to the corresponding logic circuit of the connection end.

[0020] For each connection end, the circuit further comprises:

[0021] a third unidirectional conducting element, the connection end being connected to the logic circuit through the third unidirectional conducting element, the third unidirectional conducting element being used to unidirectionally conduct a current path of the connection end to the logic circuit.

[0022] Optionally, the third unidirectional conducting element comprises an N-type metal oxide semiconductor field effect transistor, a drain of the N-type metal oxide semiconductor field effect transistor being connected to the other end of the current-limiting resistor, and a source of the N-type metal oxide semiconductor field effect transistor being connected to the logic circuit.

[0023] Optionally, the electrical signal received by each connection end is conducted to the corresponding logic circuit of the connection end.

[0024] For each connection end, the circuit further comprises:

[0025] a current-limiting resistor, the connection end being connected to the logic circuit through the current-limiting resistor.

[0026] Optionally, each first unidirectional conducting element is any one of a diode, a parasitic diode, and a triode.

[0027] Optionally, the connection end corresponds to an interface pin; and / or,

[0028] Each first N-type metal oxide semiconductor field effect transistor is a gate-ground N-type metal oxide semiconductor field effect transistor (GG NMOS) or a gate-coupled N-type metal oxide semiconductor field effect transistor (GC NMOS).

[0029] Optionally, the plurality of connection ends include a connection end corresponding to at least one pin of: a data positive pin; a data negative pin; and a configuration channel pin.

[0030] The second aspect of the present disclosure provides an electronic assembly equipped with the protection circuit according to the first aspect.

[0031] The technical solutions provided by the embodiments of the present disclosure can have the following beneficial effects:

[0032] In the embodiments of the present disclosure, the plurality of connection ends for receiving electrical signals are connected to the first N-type metal oxide semiconductor field effect transistor (hereinafter referred to as the first NMOS) through the corresponding first unidirectional conducting element, and the first NMOS is used to conduct when the voltage at the drain reaches the first protection threshold, so as to discharge the electrostatic discharge received by the connection end. In this circuit, the ESD (electrostatic discharge) protection first unidirectional conducting element is added to the discharge path of the plurality of connection ends. When a surge voltage is encountered, the added first unidirectional conducting element can bear a part of the voltage (because the first unidirectional conducting element itself carries impedance), thereby improving the voltage withstand capability of the ESD protection circuit itself. At the same time, the impedance of the first unidirectional conducting element in series in the discharge path can reduce the discharge current of the surge voltage, further improving the tolerance of the ESD protection circuit to ESD events. Due to the unidirectional conducting property of the first unidirectional conducting element, the voltages on different connection ends connected to the same first NMOS are isolated from each other. In combination with the characteristics of the electrostatic surge event that the voltage usually suddenly appears on one pin when the event occurs and is discharged through only one pin at the same time, a plurality of connection ends (for example, two) can be connected to the same first NMOS without affecting the voltage withstand capability of the ESD protection circuit itself. In summary, compared with the scheme in the related art in which the first NMOS is directly connected to each connection end, the above-mentioned embodiments solve the conflict between cost, circuit area, and ESD protection effect, greatly improve the ESD protection effect, greatly save the cost, and reduce the area of the ESD protection circuit, thereby facilitating the design and wiring of the chip.

[0033] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure, in which, like reference numerals designate corresponding parts throughout the several views.

[0035] Figure 1 is a schematic diagram of a protection circuit according to some example embodiments.

[0036] Figure 2 is a schematic diagram of another protection circuit according to some example embodiments.

[0037] Figure 3 is a schematic diagram of yet another protection circuit according to some example embodiments.

[0038] Figure 4 is a schematic diagram of still another protection circuit according to some example embodiments.

[0039] Figure 5 is a hardware structure diagram of an electronic assembly according to some example embodiments. DETAILED DESCRIPTION

[0040] The example embodiments will be described in detail herein with reference to the attached drawings. The description of the example embodiments is intended to apply to all alternative modifications and examples of the example embodiments. The following description is not intended to be limited to one example embodiment presented, but is intended to apply generally to all example embodiments and examples presented. The following description is presented for the purpose of clarity and explanation only and is not intended to limit the scope of the disclosure.

[0041] A surge is a system-level EOS (Electrical Overstress) event, unlike the nanosecond-level discharge time of a component-level ESD (Electrostatic Discharge) event, the pulse width of a surge test waveform can reach the microsecond level, and this high-energy EOS tends to more easily cause damage to integrated circuits, increasing the difficulty of protection circuit design. For a general system, a discrete transient voltage suppressor (TVS) is usually used to discharge the energy of a surge, but for electronic components such as USB electronic marker chips (E-Marker chips), the chip itself is often required to have surge resistance.

[0042] For example, for the E-Marker chip, the protection against surges is generally by means of an ESD protection circuit to discharge the surge energy; and due to considerations in terms of cost, process, etc., the USB data line and the E-Marker chip generally have high-voltage pins (pins can be understood as pins, such as the power supply bus VBUS pin, the ground GND pin, etc.) that can adapt to high voltage and low-voltage pins (such as the data positive D+ pin, the data negative D- pin, the configuration channel CC pin, etc.) that have relatively low voltage acceptance.

[0043] As shown in Figure 1 VCC (Volt Current Condenser, power supply voltage of the circuit) can be a positive voltage to the reference ground (generally GND, GND is also used to refer to the ground) for the power supply voltage of the circuit. The ESD protection of the low-voltage pin in the traditional mixed voltage domain generally adopts a pad base structure, and the ESD protection device generally adopts a GGNMOS (Gate-Ground N-type Metal-Oxide-Semiconductor, Gate-Ground N-type Metal-Oxide-Semiconductor Field Effect Transistor). Different low-voltage pins (the Lv pad shown in the figure can be understood as the pad of the chip, each pad corresponds to a pin, of course, it can also be a pin) discharge ESD and EOS energy through their respective GGNMOS. Compared with high-voltage pins, low-voltage pins themselves do not have high-voltage resistance, which also leads to more damage when encountering high surge voltage.

[0044] GGNMOS (Gate-Ground N-type Metal-Oxide-Semiconductor) is a special NMOS (N-type Metal-Oxide-Semiconductor) structure, which can be used for ESD (Electro-Static Discharge) protection. Its terminals can be the same as a normal NMOS, but the gate (G) is directly grounded. Current flows from the drain (D) to the source (S), and the ESD current is discharged through the opening of a parasitic NPN triode (the source is usually grounded, and the drain can be connected to a node that needs to be protected). GCNMOS (Gate-Coupled N-type Metal-Oxide-Semiconductor) is also a special NMOS, and its gate (Gate) is usually connected to the drain (Drain) through a coupling capacitor (or connected through other media, or directly connected), and the source (Source) is usually grounded, while the drain (Drain) is connected to a node that needs to be protected; GCNMOS can use the coupling capacitor to couple the voltage to the gate to turn on the NMOS, thereby forming a discharge channel. GCNMOS and GGNMOS can both be regarded as ESD protection devices (elements).

[0045] When the low-voltage pin encounters a surge voltage, the ESD protection device will first open to discharge current, but due to the small internal resistance of the surge discharge process, as the voltage increases, the current will also increase, and when the current reaches the secondary breakdown current of the ESD device, the ESD device will burn out. Generally, in order for the chip to withstand higher ESD protection capability, the on-resistance of the ESD protection device will be relatively low, thereby providing better protection to the internal circuit. However, a small resistance will have a larger current under a surge voltage, and to withstand a larger current requires a larger area of the ESD device, but an increase in area will lead to uneven conduction, which also doubles the area cost required to increase the current capacity.

[0046] In summary, the current protection circuit for E-Marker chips (as well as other protection circuits, the present disclosure does not limit the application scenarios of the protection circuit) has a high cost, is difficult to withstand a large voltage impact, and has poor ESD protection effect.

[0047] Therefore, the present disclosure provides a protection circuit and an electronic assembly. Next, the embodiments of the present disclosure will be described in detail.

[0048] The first aspect of the present disclosure provides a protection circuit, which can be applied to electronic components such as mobile phones, tablets, USB Type-C cables, E-Marker chips, etc. The electronic components can include a plurality of connection terminals, a plurality of first unidirectional conduction elements corresponding to the plurality of connection terminals one by one, and a first N-type metal oxide semiconductor field effect transistor. Wherein, the connection terminal is used to receive an electrical signal; the input end of each first unidirectional conduction element is connected to the corresponding connection terminal, and the first unidirectional conduction element has an internal resistance and is used to conduct the current from the input end to the output end in one direction; the drain of the first N-type metal oxide semiconductor field effect transistor is connected to the output end of each first unidirectional conduction element, and the first N-type metal oxide semiconductor field effect transistor is used to conduct when the voltage at the drain reaches a first protection threshold, so as to discharge the electrostatic discharge received by the connection terminal.

[0049] Please refer to Figure 2 Wherein, pad1 and pad2 are two exemplary connection terminals, diodes D1 and D2 are first unidirectional conduction elements corresponding to pad1 and pad2, NM0 is a first NMOS (NMOS is N-type metal oxide semiconductor field effect transistor) corresponding to D1 and D2, and the logic circuit is a post-stage circuit of pad1 and pad2, i.e. a circuit for processing the electrical signal received by the corresponding pad (i.e. the electrical signal received by each connection terminal is used to be conducted to the logic circuit corresponding to the connection terminal), which is also a circuit that needs ESD protection.

[0050] When the protection circuit is applied to chips such as E-Marker, the plurality of connection terminals can be pads (pads) or pins (pins) of the chip, or can be a node in the circuit. When the protection circuit is applied to an interface, the plurality of connection terminals can be interface pins, or can be other connection terminals that need ESD protection (i.e. may receive electrostatic discharge). In general, as the outer part of the electronic system for receiving electrical signals, the connection terminals can correspond to interface pins, such as a plurality of connection terminals including connection terminals corresponding to at least one of the following pins: data positive pin D+; data negative pin D-; configuration channel pin CC. These pins are usually not used for power supply, grounding discharge, and transmission of high-voltage signals, so the corresponding interface pins, signal transmission lines, and chip pads usually do not undergo special high-voltage processing, and their ESD protection needs are more intense.

[0051] The first unidirectional conducting element is used to cut off reverse current (i.e. cut off current flowing to the pad) and provide certain internal resistance. For example, each first unidirectional conducting element is any one of a diode, a parasitic diode, and a triode. When the first unidirectional conducting element is a triode, the emitter of the triode can be left open or shorted with the base, the base and the collector are used as two ends of the diode, and the withstand voltage of this method is higher; or the base and the emitter can be used: the collector is left open or shorted with the base, and the base and the emitter are used as two ends of the diode. When the first unidirectional conducting element is a diode or a parasitic diode (i.e. a diode naturally formed in a semiconductor device due to manufacturing process and structure), the cost of the first unidirectional conducting element can be further reduced. At the same time, the diode, the parasitic diode, and the triode also produce corresponding voltage drop effects (i.e. after conduction, the voltage of the output end relative to the input end is reduced), reducing the voltage and current borne by the first NMOS, and strengthening the ESD protection effect of the circuit. Of course, the first unidirectional conducting element can also be implemented based on other elements, such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) controlled based on other logic, etc.

[0052] The first NMOS can be an element that is turned on based on a certain logic to discharge electrical energy from the connection end. Its corresponding first protection threshold is usually related to its process and specific implementation principle, such as its doping concentration, oxide layer thickness, electrode connection mode, etc., but the first protection threshold usually needs to be higher than the voltage of the electrical signal and lower than the maximum voltage that the logic circuit (and other electronic elements that need to be protected) can bear (in some cases, the first protection threshold can also be artificially set by introducing other control circuits, and the present disclosure is not limited thereto; the second protection threshold in the following is the same as the first protection threshold, and will not be repeated here). For example, each first NMOS can be a gate-grounded N-type metal-oxide-semiconductor field-effect transistor (GGNMOS) or a gate-coupled N-type metal-oxide-semiconductor field-effect transistor (GCNMOS) (hereinafter and in the accompanying drawings, GGNMOS is taken as an example). Based on this, the circuit can be maximally simplified and the cost can be reduced, while having a higher ESD protection effect.

[0053] In the circuit provided in the present disclosure, the first unidirectional conducting element is added in the discharge path of the multiple connection terminals. When a surge voltage is encountered, the added first unidirectional conducting element can bear a part of the voltage (because the first unidirectional conducting element itself carries impedance), thereby improving the voltage withstand capability of the ESD protection circuit itself. Meanwhile, the impedance of the first unidirectional conducting element in series in the discharge path can reduce the discharge current of the surge voltage, further improving the tolerance of the ESD protection circuit to ESD events. Because the unidirectional conducting characteristic of the first unidirectional conducting element ensures that the voltages on different connection terminals connected to the same first NMOS are isolated from each other, and in combination with the characteristic that the static surge event usually has "its voltage often suddenly appears on one pin when it occurs, and is discharged through only one pin at the same time", then multiple connection terminals (for example, two) can be connected to the same first NMOS, without affecting the voltage withstand capability of the ESD protection circuit itself. In summary, compared with the scheme in the related art that the first NMOS is directly connected to each connection terminal, the above-mentioned embodiment solves the conflict among cost, circuit area and ESD protection effect, greatly improves the ESD protection effect, greatly saves the cost and reduces the area of the ESD protection circuit, and facilitates the design and wiring of the chip.

[0054] In order to better control the voltage of the connection terminal, the circuit can further include a plurality of second unidirectional conducting elements corresponding to the plurality of connection terminals one by one, the input end of each second unidirectional conducting element is grounded, the output end is connected to the corresponding connection terminal, and the second unidirectional conducting element is used for unidirectional conduction of the current from the input end to the output end.

[0055] Please refer to Figure 3 Among them, the diodes D3 and D4 shown in dashed lines are the second unidirectional conducting elements corresponding to pad1 and pad2 respectively. For circuits such as E-Marker chips, a parasitic diode is usually formed between GND (ground) and the connection terminal. In this case, a separate element can not be introduced as a second unidirectional conducting element, but the parasitic diode existing in the circuit can be directly used as a second unidirectional conducting element. If some connection terminals do not have a parasitic diode pointing to them from the ground, a diode (of course, a triode or other equivalent circuit can also be used) can be introduced as a second unidirectional conducting element. Based on the above-mentioned embodiment, when the potential of the connection terminal is lower than the ground, the second unidirectional conducting element will be turned on and the phenomenon of negative potential of the connection terminal will be avoided, thereby better clamping the voltage of the connection terminal to ensure the normal work of the entire circuit and improve the robustness of the circuit.

[0056] In some embodiments, in order to avoid a high protection threshold existing in the electrostatic discharge discharge path composed of the first NMOS and the first unidirectional conducting element (because the voltage division of the first unidirectional conducting element can cause the turn-on of the NM0 to require a larger voltage to trigger, and according to different specific embodiments, the first unidirectional conducting element can have a voltage drop effect and a certain minimum turn-on voltage), thereby further improving the ESD protection effect of the circuit, for each connection terminal, the circuit provided by the present disclosure can further include: a second N-type metal oxide semiconductor field effect transistor, the drain of the second N-type metal oxide semiconductor field effect transistor and the logic circuit are connected in parallel to the connection terminal, and the second N-type metal oxide semiconductor field effect transistor is used to turn on when the voltage of the drain reaches a second protection threshold, so as to discharge the electrostatic discharge received by the connection terminal.

[0057] For ease of understanding, please refer to Figure 4 For the connection terminal pad1, in addition to the ESD discharge path composed of D1, NM0 (hereinafter referred to as the first discharge path; the floating node in the figure means that there is no element connected here), an internal clamping circuit can be added on the path through which pad1 is connected to the logic circuit, thereby further clamping the voltage of pad1. Figure 4 In the

[0058] In Figure 4 , NM2 is a second NMOS, which can also be a GGNMOS, a GCNMOS or other electronic elements with the same function. For example, the second NMOS can be connected in parallel to a certain endpoint of the logic circuit, and then the endpoint is connected to other electronic elements (i.e. Figure 4 The connection mode shown). Since the second NMOS is connected in parallel to the logic circuit on the path from the connection terminal to the logic circuit, the second NMOS can serve as another layer of protection to discharge the charge and further protect the gate oxide of the internal logic circuit. At the same time, when the turn-on voltage of the second NMOS (hereinafter referred to as the second discharge path) is inconsistent with the turn-on voltage of the first discharge path, a multi-level ESD discharge path can be formed, that is, when the ESD event is relatively mild, the electrostatic charge can be discharged through one of the first discharge path and the second discharge path, and when the ESD event is relatively serious, the first discharge path and the second discharge path will be turned on, and then the current flowing through the first discharge path and the second discharge path will be reduced (relative to the turn-on alone), thereby further improving the tolerance of the circuit to the ESD event.

[0059] In some embodiments, the circuit provided in this disclosure may further include a current-limiting resistor (e.g., Figure 4 R1 shown) and the third unidirectional conducting element (e.g. Figure 4 The NM1 shown is shown.

[0060] The value of a current-limiting resistor is typically several hundred ohms or several thousand ohms (of course, this value can be adjusted according to the actual situation). It can limit the current flowing into the logic circuit, further avoid damage to the logic circuit, and improve the robustness of the circuit.

[0061] The third unidirectional conducting element can reverse-block the current flowing from the logic circuit to the connection terminal, further improving the robustness of the circuit and preventing the generation of current flowing from the logic current to the connection terminal. Since the third conducting element is located in the path from the connection terminal to the logic circuit, in order to avoid the voltage drop effect generated by components such as diodes from having too much impact on signal transmission, and to avoid the minimum conduction voltage of the diodes from blocking the normal transmission of signals, the third unidirectional conducting element can optionally be implemented using an N-type metal-oxide-semiconductor field-effect transistor (NMOS) (of course, a P-type metal-oxide-semiconductor field-effect transistor or other similar components can also be used, with no change in function; similarly, the first NMOS, second NMOS, and other NMOS mentioned in this disclosure can also be PMOS, with adaptive modifications to the circuit, such as swapping the descriptions of the source and drain in the above text), and the gate is connected to a power supply line such as VCC to keep it in the conducting state, thereby achieving reverse current blocking without causing a large voltage drop or blocking signal transmission.

[0062] In this disclosure, the current-limiting resistor, the third unidirectional conducting element, and the second NMOS can exist individually or in any combination.

[0063] For example, when the current-limiting resistor exists alone, its two ends can be connected to the connection terminal and the logic circuit respectively; when the third unidirectional conducting element exists alone, its input terminal (e.g., the drain of an NMOS) can be connected to the connection terminal and its output terminal can be connected to the logic circuit; and when both the current-limiting resistor and the third unidirectional conducting element exist, they can be connected in sequence as "connection terminal - current-limiting resistor - third unidirectional conducting element - logic circuit" (this can better protect the third unidirectional conducting element), or in sequence as "connection terminal - third unidirectional conducting element - current-limiting resistor - logic circuit".

[0064] When a second NMOS is present, it can be connected to a lower level (i.e., closer to the logic circuit) of the current-limiting resistor and the third unidirectional conducting element. The same approach can be used when only the second NMOS and the current-limiting resistor, or only the second NMOS and the third unidirectional conducting element, are present. Figure 4The connection method is shown. Specifically, for each connection terminal, the circuit further includes: a current-limiting resistor with one end connected to the connection terminal; and a third unidirectional conducting element with its input terminal connected to the other end of the current-limiting resistor, used to unidirectionally conduct the current path from the connection terminal to the logic circuit; wherein the drain of the second NMOS and the logic circuit are connected in parallel to the output terminal of the third unidirectional conducting element. Based on this, high-voltage events that the logic circuit may receive can be discharged via a second discharge path, thereby maximizing the protection of the logic circuit.

[0065] Secondly, this disclosure also provides an electronic component equipped with the protection circuit described in the first aspect, which can be a data line, a connecting line, a connector, an interface module, an E-Marker chip (here, "chip" can refer to the chip itself and its pins), or something similar. Figure 5 The electronic device shown. Please refer to [link / reference]. Figure 4 The illustration exemplifies a hardware schematic of an electronic device. For example, device 500 could be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0066] Device 500 may include one or more of the following components: processing component 501, memory 502, power supply component 503, multimedia component 504, audio component 505, input / output (I / O) interface 506, sensor component 507, and communication component 508.

[0067] Processing component 501 typically controls the overall operation of device 500, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 501 may include one or more processors 509 to execute instructions to perform the control logic associated with the aforementioned circuitry. Furthermore, processing component 501 may include one or more modules to facilitate interaction between processing component 501 and other components. For example, processing component 501 may include a multimedia module to facilitate interaction between multimedia component 504 and processing component 501.

[0068] Memory 502 is configured to store various types of data to support the operation of device 500. Examples of this data include instructions for any application or circuitry operating on device 500, contact data, phonebook data, messages, pictures, videos, etc. Memory 502 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0069] The power supply component 503 provides power to the various components of the device 500. The power supply component 503 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device 500.

[0070] Multimedia component 504 includes a screen that provides an output interface between the device 500 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, swipe, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 504 includes a front-facing camera and / or a rear-facing camera. When the device 500 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0071] Audio component 505 is configured to output and / or input audio signals. For example, audio component 505 includes a microphone (MIC) configured to receive external audio signals when device 500 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 502 or transmitted via communication component 508. In some embodiments, audio component 505 also includes a speaker for outputting audio signals.

[0072] I / O interface 506 provides an interface between processing component 501 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0073] Sensor assembly 507 includes one or more sensors for providing state assessments of various aspects of device 500. For example, sensor assembly 507 can detect the on / off state of device 500, the relative positioning of components such as the display and keypad of device 500, changes in the position of device 500 or a component of device 500, the presence or absence of user contact with device 500, the orientation or acceleration / deceleration of device 500, and temperature changes of device 500. Sensor assembly 507 may also include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 507 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 507 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0074] Communication component 508 is configured to facilitate wired or wireless communication between device 500 and other devices. Device 500 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G or 5G, or combinations thereof. In one exemplary embodiment, communication component 508 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 508 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IRDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0075] In an exemplary embodiment, device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to support the aforementioned protection circuit.

[0076] The foregoing has described specific embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0077] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention applied herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0078] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0079] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A protection circuit, characterized in that, The circuit includes: Multiple connection terminals, which are used to receive electrical signals; A plurality of first unidirectional conducting elements are provided, each corresponding to one of the plurality of connection terminals. The input terminal of each first unidirectional conducting element is connected to the corresponding connection terminal. The first unidirectional conducting element has internal resistance and is used to conduct current from the input terminal to the output terminal in a unidirectional manner. The drain of the first N-type metal-oxide-semiconductor field-effect transistor is connected to the output terminal of each first unidirectional conducting element, and is used to conduct when the voltage at the drain reaches a first protection threshold, so as to discharge the electrostatic discharge received at the connection terminal.

2. The protection circuit according to claim 1, characterized in that, The circuit also includes: A plurality of second unidirectional conducting elements are provided, each corresponding to one of the plurality of connection terminals. The input terminal of each second unidirectional conducting element is grounded and the output terminal is connected to the corresponding connection terminal. The second unidirectional conducting element is used to conduct the current from the input terminal to the output terminal in one direction.

3. The protection circuit according to claim 2, characterized in that, The second unidirectional conducting element includes a parasitic diode.

4. The protection circuit according to claim 1, characterized in that, The electrical signals received at each connection terminal are used to transmit to the logic circuit corresponding to that connection terminal; For each connection terminal, the circuit further includes: The drain of the second N-type metal-oxide-semiconductor field-effect transistor and the logic circuit are connected in parallel to the connection terminal. The second N-type metal-oxide-semiconductor field-effect transistor is used to conduct when the voltage at the drain reaches a second protection threshold to discharge the electrostatic discharge received at the connection terminal.

5. The protection circuit according to claim 4, characterized in that, For each connection terminal, the circuit further includes: A current-limiting resistor with one end connected to the connection terminal; A third unidirectional conducting element, whose input terminal is connected to the other end of the current-limiting resistor, is used to unidirectionally conduct the current path from the connection terminal to the logic circuit. The drain of the second N-type metal-oxide-semiconductor field-effect transistor and the logic circuit are connected in parallel to the output terminal of the third unidirectional conducting element.

6. The protection circuit according to claim 1, characterized in that, The electrical signals received at each connection terminal are used to transmit to the logic circuit corresponding to that connection terminal; For each connection terminal, the circuit further includes: A third unidirectional conducting element is used to conduct the current path from the connection terminal to the logic circuit.

7. The protection circuit according to claim 5 or 6, characterized in that, The third unidirectional conducting element includes an N-type metal-oxide-semiconductor field-effect transistor, the drain of which is connected to the other end of the current-limiting resistor and the source of which is connected to the logic circuit.

8. The protection circuit according to claim 1, characterized in that, The electrical signals received at each connection terminal are used to transmit to the logic circuit corresponding to that connection terminal; For each connection terminal, the circuit further includes: A current-limiting resistor is provided, and the connection terminal is connected to the logic circuit through the current-limiting resistor.

9. The protection circuit according to claim 1, characterized in that, Each first unidirectional conducting element is any one of a diode, a parasitic diode, or a transistor.

10. The protection circuit according to claim 1, characterized in that, The connection terminal corresponds to an interface pin; and / or, Each first N-type metal-oxide-semiconductor field-effect transistor is either a gate-grounded N-type metal-oxide-semiconductor field-effect transistor or a gate-coupled N-type metal-oxide-semiconductor field-effect transistor.

11. The protection circuit according to claim 1, characterized in that, The plurality of connection terminals include a connection terminal corresponding to at least one of the following pins: Data positive pin; Data negative pin; Configure the channel pins.

12. An electronic component, characterized in that, The electronic component is equipped with a protection circuit as described in any one of claims 1 to 11.

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