Low-noise near-infrared single-photon avalanche detector and preparation method thereof

Abstract

The invention discloses a low-noise near-infrared single-photon avalanche detector and a preparation method thereof, the low-noise near-infrared single-photon avalanche detector comprises an n-type InP substrate, and an InP buffer layer, a GaAs < 0.51 > Sb < 0.49 > absorption layer, an In Ga < 1-a > As Sb < 1-b > energy band gradient layer, a composite charge layer containing an indium quantum dot array, an InP avalanche layer and an i-InP diffusion layer which grow on the front surface of the n-type InP substrate from bottom to top in sequence, the composite charge layer containing the indium quantum dot array comprises an InP gradient charge layer, an In quantum dot deposition layer and an InP constant charge thin layer which are sequentially grown from bottom to top. On the premise of keeping high photon detection efficiency of the detector, the dark counting rate and the post-pulse probability of the detector can be effectively reduced, and the performance and the reliability of the detector are remarkably improved.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor optoelectronic devices, and in particular to a low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping, and its fabrication method. Background Technology

[0002] Photon avalanche detectors (SPADs) are core components in systems such as quantum communication, lidar, and precision analytical instruments. Currently, commercially available SPADs targeting the 1550 nm band are mainly based on the InGaAs / InP material system. However, this system has inherent drawbacks: the narrow bandgap InGaAs absorption layer leads to high thermal dark counts and interband tunneling dark counts; the heterojunction between InGaAs and InP exhibits band mismatch, which easily leads to carrier trapping and causes severe afterpulse noise.

[0003] To reduce dark counts, existing technologies primarily focus on cooling and quenching circuits, increasing system complexity and cost. While some research has proposed using wide-bandgap materials such as AlInAs or GaAsSb as absorption layers, addressing the bandgap mismatch between these materials and the InP avalanche layer, while simultaneously optimizing the electric field during the avalanche process to suppress noise, remains a technological bottleneck for the industry. Therefore, there is an urgent need for a novel SPAD structure that can comprehensively address these issues at the device physics level.

[0004] Quantum dots, as a type of nanostructure, have attracted widespread attention in the optoelectronic field due to their quantum confinement effect and localized field enhancement effect. Combining the properties of quantum dots with the avalanche process of SPADs holds promise for providing a new path to performance breakthroughs. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping. This detector can effectively reduce its dark count rate and afterpulse probability while maintaining high photon detection efficiency, thus significantly improving the performance and reliability of the detector.

[0006] Another objective of this invention is to provide a method for fabricating a low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping.

[0007] The objective of this invention is achieved through the following technical solution: A low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping includes an n-type InP substrate and an InP buffer layer and a GaAs layer grown sequentially from bottom to top on the positive surface of the n-type InP substrate. 0.51 Sb 0.49 Absorbing layer, In a Ga 1-a Asb Sb 1-b The device comprises a bandgap layer, a composite charge layer containing an indium quantum dot array, an InP avalanche layer, and an i-InP diffusion layer, wherein the composite charge layer containing the indium quantum dot array includes, from bottom to top, an InP bandgap charge layer, an In quantum dot deposition layer, and an InP constant charge thin layer.

[0008] Furthermore, the InP buffer layer is an undoped InP buffer layer with a thickness of 200 nm to 600 nm.

[0009] Furthermore, the GaAs 0.51 Sb 0.49 The thickness of the absorption layer is 500 nm to 2500 nm.

[0010] Furthermore, the In a Ga 1-a As b Sb 1-b The thickness of the bandgap layer is 100 nm to 500 nm, where a = 1.0 to 0.5 and b = 1.0 to 0.5.

[0011] Furthermore, the thickness of the composite charge layer containing the indium quantum dot array is 160 nm to 250 nm.

[0012] Furthermore, the InP graded charge layer is n-type doped, with an impurity atom density ranging from 5 × 10⁻⁶. 16 ~2×10 17 cm -3 Its thickness is 150 nm to 200 nm; the In quantum dot deposition comprises 1.5 to 2.8 monoatom layers of indium with a density ranging from 4 × 10⁻⁶. 10 ~8×10 11 cm -2 The InP constant-charge thin layer is n-type doped, with an impurity atom density ranging from 1 × 10⁻⁶. 17 ~3×10 17 cm -3 Its thickness is 10nm~50nm.

[0013] Furthermore, the thickness of the InP avalanche layer is 1 μm to 2 μm.

[0014] Furthermore, the thickness of the i-InP diffusion layer is 2μm to 5μm.

[0015] Another objective of this invention is achieved through the following technical solution: A method for fabricating a low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping, comprising the following steps: S1. On the front surface of a single-sided polished n-type InP substrate, an undoped InP buffer layer and a GaAs layer are sequentially fabricated from bottom to top. 0.51 Sb 0.49 Absorbing layer, In a Ga 1-a As b Sb 1-b An InP / GaAsSb epitaxial wafer was prepared by comprising a band gradient layer, a composite charge layer containing an indium quantum dot array, an InP avalanche layer, and an i-InP diffusion layer. S2. A high-temperature resistant dielectric film SiN is grown on the substrate of the prepared InP / GaAsSb epitaxial wafer, and then diffusion holes are processed by photolithography etching technology to obtain a chip with diffusion holes. S3. Perform Zn diffusion on the chip with the prepared diffusion holes to form the P region; S4. After diffusion is complete, the inside of the diffusion pore is micro-treated with an acidic solution to reduce the high defect layer on the upper surface of the diffusion zone and avoid the formation of leakage channels under high voltage. S5. The chip is subjected to sulfur treatment to form a passivation layer, and then SiO2 passivation layer is grown using a PECVD machine. S6. Contact holes and P / N electrodes are fabricated on the chip using photolithography, etching, and vapor deposition to complete the fabrication of the detector.

[0016] Furthermore, in step S1, the growth process of the composite charge layer containing the indium quantum dot array is as follows: First, an InP graded charge layer of 150 nm to 200 nm is grown in a reaction chamber at 600 °C. The InP graded charge layer is n-type doped, with an impurity atom density ranging from 5 × 10⁻⁶. 16 ~2×10 17 cm -3 Growth was then halted, and the reaction chamber temperature was lowered to 400°C. Under indium-rich conditions, approximately 1.5–2.8 monolayers of indium were deposited, self-assembling to form indium quantum dots with a density ranging from 4 × 10⁻⁶. 10 ~8×10 11 cm -2 Finally, the temperature is restored to the growth temperature, and a 10 nm to 50 nm InP constant-charge thin layer is grown to cover the quantum dots. The InP constant-charge thin layer is n-type doped, with an impurity atom density ranging from 1 × 10⁻⁶. 17 ~3×10 17 cm -3 .

[0017] Compared with the prior art, the present invention has the following advantages and beneficial effects: 1. This invention uses GaAsSb (GaAs) with a band gap width of approximately 0.8 eV.0.51 Sb 0.49 It replaces traditional InGaAs. The wider bandgap significantly reduces the thermally generated carrier concentration and increases the electric field threshold of the tunneling effect, laying a material basis for reducing dark count from a physical perspective.

[0018] 2. This invention addresses the significant hole barrier created by the type II heterojunction formed between GaAsSb and InP by innovatively introducing a compositionally graded GaInAsSb quaternary alloy layer as a band gradient layer. This layer, through continuous compositional variation, achieves a smooth transition of the valence band, acting like a "bridge" that allows photogenerated holes to be efficiently extracted to the avalanche region. This solves the problem of low detection efficiency and significantly reduces interfacial recombination and afterpulse probability.

[0019] 3. This invention introduces a special charge layer between the InP avalanche layer and the n-type contact layer (n-type InP substrate). This layer is not a traditional highly doped field-terminating layer, but rather a lightly n-type doped InP layer combined with In quantum dots. Its core function is to "shape" the electric field distribution in the avalanche region and introduce indium quantum dots to reduce the avalanche breakdown voltage, improve the avalanche triggering probability and uniformity, and further suppress the afterpulse probability. Due to the difference in dielectric constant between the indium quantum dots and the InP matrix, a localized, enhanced electric field region is formed around each indium quantum dot when a reverse bias is applied, as if countless tiny "electric field spikes" are established within the avalanche region. These locally high electric field regions become preferential and predetermined avalanche triggering points. Due to the existence of these predetermined high electric field regions, charge carriers (holes), after entering the avalanche region, do not need to travel a long distance to accumulate energy and can quickly reach the ionization threshold near the first quantum dot they encounter, triggering an avalanche. This significantly reduces the overall avalanche breakdown voltage of the device. Therefore, avalanche triggering is no longer completely random, but is guided to the quantum dot location. This significantly increases the probability of single-photon triggering, resulting in higher photon detection efficiency under the same overbias voltage. Simultaneously, due to the relatively uniform distribution of the quantum dot array, the avalanche process is also more spatially consistent, improving the uniformity of device performance. Because the avalanche is localized near the quantum dots and triggered more efficiently, the total amount of charge injected to complete one avalanche multiplication is reduced. This means that the total number of carriers trapped by the traps is also reduced accordingly, effectively lowering the afterpulse probability. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the detector structure of the present invention.

[0021] Figure 2 This is a schematic diagram illustrating the Zn diffusion process of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0023] like Figure 1 As shown, this embodiment provides a low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping, including an n-type InP substrate 1 and an InP buffer layer 2 and a GaAs layer grown sequentially from bottom to top on the positive surface of the n-type InP substrate 1. 0.51 Sb 0.49 Absorbing layer 3, In a Ga 1-a As b Sb 1-b The structure includes a band gradient layer 4, a composite charge layer containing an indium quantum dot array, an InP avalanche layer 8, and an i-InP diffusion layer 9. The composite charge layer containing the indium quantum dot array comprises, from bottom to top, an InP gradient charge layer 5, an In quantum dot deposition layer 6, and an InP constant charge thin layer 7.

[0024] Specifically, InP buffer layer 2 is an undoped InP buffer layer with a thickness of 200 nm to 600 nm; GaAs 0.51 Sb 0.49 The thickness of the absorber layer 3 is 500 nm ~ 2500 nm; In a Ga 1-a As b Sb 1-b The band gradient layer 4 has a thickness of 100 nm to 500 nm, where a = 1.0 to 0.5 and b = 1.0 to 0.5; the total thickness of the composite charge layer containing the indium quantum dot array is 160 nm to 250 nm; the thickness of the InP avalanche layer 8 is 1 μm to 2 μm; and the thickness of the i-InP diffusion layer 9 is 2 μm to 5 μm.

[0025] Specifically, the InP graded charge layer 5 is n-type doped, with an impurity atom density ranging from 5 × 10⁵. 16 ~2×10 17 cm -3 Its thickness is 150 nm to 200 nm; In quantum dot deposition 6 consists of 1.5 to 2.8 monoatom layers of indium, with a density ranging from 4 × 10⁶. 10 ~8×10 11 cm -2The InP constant-charge thin layer 7 is n-type doped, with an impurity atom density ranging from 1 × 10⁻⁶. 17 ~3×10 17 cm -3 Its thickness is 10nm~50nm.

[0026] This embodiment also provides a method for fabricating a low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping, including the following steps: S1. Using MOCVD or MBE technology, fabricate undoped InP buffer layer 2 and GaAs layer 2 sequentially from bottom to top on the front surface of a single-sided polished n-type InP substrate 1. 0.51 Sb 0.49 Absorbing layer 3, In a Ga 1-a As b Sb 1-b An InP / GaAsSb epitaxial wafer was prepared by comprising a band gradient layer 4, a composite charge layer containing an indium quantum dot array, an InP avalanche layer 8, and an i-InP diffusion layer 9. The growth process of the composite charge layer containing the indium quantum dot array is as follows: First, an InP graded charge layer 5 with a diameter of 150 nm to 200 nm was grown in a reaction chamber at 600 °C. The InP graded charge layer 5 was n-type doped, and its impurity atom density ranged from 5 × 10⁻⁶. 16 ~2×10 17 cm -3 Growth was then halted, and the reaction chamber temperature was lowered to 400°C. Under indium-rich conditions, approximately 1.5–2.8 monolayers of indium were deposited, self-assembling to form indium quantum dots with a density ranging from 4 × 10⁻⁶. 10 ~8×10 11 cm -2 Finally, the temperature was restored to the growth temperature, and a 10 nm to 50 nm InP constant-charge thin layer 7 was grown to cover the quantum dots. The InP constant-charge thin layer 7 was n-type doped, and its impurity atom density ranged from 1 × 10⁻⁶. 17 ~3×10 17 cm -3 ; S2. A high-temperature resistant dielectric film SiN is grown on the substrate of the prepared InP / GaAsSb epitaxial wafer by PECVD, and then diffusion holes are processed by photolithography etching technology to obtain a chip with diffusion holes. S3. The chip with the prepared diffusion holes is subjected to Zn diffusion 10 by MOCVD to form a P-region, such as... Figure 2 As shown: S4. After diffusion is complete, the inside of the diffusion pore is micro-treated with an acidic solution to reduce the high defect layer on the upper surface of the diffusion zone and avoid the formation of leakage channels under high voltage. S5. The chip is subjected to sulfidation treatment through electrochemical process to form a passivation layer, and then SiO2 passivation layer is grown by PECVD machine. S6. Use semiconductor technologies such as photolithography, etching, and vapor deposition to process contact holes and P / N electrodes on the chip, and then perform PDE testing.

[0027] This invention achieves dual suppression of thermal noise and tunneling noise through the synergistic effect of a wide bandgap absorption layer and electric field shaping, resulting in an extremely low dark count rate. The band gradient layer solves the carrier transport bottleneck of the type II heterojunction, ensuring high photon detection efficiency and significantly reducing the afterpulse probability. The local field enhancement of quantum dots significantly improves the avalanche triggering probability, thereby achieving high photon detection efficiency at a lower overbias voltage.

[0028] Compared to similar devices without quantum dots, the SPAD of this invention is expected to reduce avalanche breakdown voltage by 10% to 15%. At an operating temperature of 200 K and an overbias voltage of 1.5 V, the photon detection efficiency at 1550 nm is expected to exceed 40%. The device's dark count rate is not only significantly better than similar products (<50 cps), but its subsequent pulse probability is also reduced to an extremely low level of less than 0.1%, significantly improving the performance and reliability of the detector.

[0029] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope disclosed in the present invention, based on the technical solution and inventive concept of the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping, characterized in that: Includes an n-type InP substrate and an InP buffer layer and GaAs layer grown sequentially from bottom to top on the front surface of the n-type InP substrate. 0.51 Sb 0.49 Absorbing layer, In a Ga 1-a As b Sb 1-b The device comprises a bandgap layer, a composite charge layer containing an indium quantum dot array, an InP avalanche layer, and an i-InP diffusion layer, wherein the composite charge layer containing the indium quantum dot array includes, from bottom to top, an InP bandgap charge layer, an In quantum dot deposition layer, and an InP constant charge thin layer.

2. The low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping according to claim 1, characterized in that: The InP buffer layer is an undoped InP buffer layer with a thickness of 200 nm to 600 nm.

3. The low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping according to claim 1, characterized in that: The GaAs 0.51 Sb 0.49 The thickness of the absorption layer is 500 nm to 2500 nm.

4. The low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping according to claim 1, characterized in that: The In a Ga 1-a As b Sb 1-b The thickness of the bandgap layer is 100 nm to 500 nm, where a = 1.0 to 0.5 and b = 1.0 to 0.

5.

5. The low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping according to claim 1, characterized in that: The thickness of the composite charge layer containing the indium quantum dot array is 160 nm to 250 nm.

6. The low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping according to claim 1, characterized in that: The InP graded charge layer is n-type doped, with an impurity atom density ranging from 5 × 10⁻⁶. 16 ~2×10 17 cm -3 Its thickness is 150 nm to 200 nm; the In quantum dot deposition comprises 1.5 to 2.8 monoatom layers of indium with a density ranging from 4 × 10⁻⁶. 10 ~8×10 11 cm -2 The InP constant-charge thin layer is n-type doped, with an impurity atom density ranging from 1 × 10⁻⁶. 17 ~3×10 17 cm -3 Its thickness is 10nm~50nm.

7. The low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping according to claim 1, characterized in that: The thickness of the InP avalanche layer is 1 μm to 2 μm.

8. The low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping according to claim 1, characterized in that: The thickness of the i-InP diffusion layer is 2μm to 5μm.

9. The method for fabricating a low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping according to any one of claims 1 to 8, characterized in that, Including steps, S1. On the front surface of a single-sided polished n-type InP substrate, an undoped InP buffer layer and a GaAs layer are sequentially fabricated from bottom to top. 0.51 Sb 0.49 Absorbing layer, In a Ga 1-a As b Sb 1-b An InP / GaAsSb epitaxial wafer was prepared by comprising a band gradient layer, a composite charge layer containing an indium quantum dot array, an InP avalanche layer, and an i-InP diffusion layer. S2. A high-temperature resistant dielectric film SiN is grown on the substrate of the prepared InP / GaAsSb epitaxial wafer, and then diffusion holes are processed by photolithography etching technology to obtain a chip with diffusion holes. S3. Perform Zn diffusion on the chip with the prepared diffusion holes to form the P region; S4. After diffusion is complete, the inside of the diffusion pore is micro-treated with an acidic solution to reduce the high defect layer on the upper surface of the diffusion zone and avoid the formation of leakage channels under high voltage. S5. The chip is subjected to sulfur treatment to form a passivation layer, and then SiO2 passivation layer is grown using a PECVD machine. S6. Contact holes and P / N electrodes are fabricated on the chip using photolithography, etching, and vapor deposition to complete the fabrication of the detector.

10. The fabrication method of the low-noise near-infrared single-photon avalanche detector based on band engineering and electric field shaping according to claim 9, characterized in that, In step S1, the growth process of the composite charge layer containing the indium quantum dot array is as follows: First, an InP graded charge layer of 150 nm to 200 nm is grown in a reaction chamber at 600 °C. The InP graded charge layer is n-type doped, with an impurity atom density ranging from 5 × 10⁻⁶. 16 ~2×10 17 cm -3 Growth was then halted, and the reaction chamber temperature was lowered to 400°C. Under indium-rich conditions, approximately 1.5–2.8 monolayers of indium were deposited, self-assembling to form indium quantum dots with a density ranging from 4 × 10⁻⁶. 10 ~8×10 11 cm -2 Finally, the temperature is restored to the growth temperature, and a 10 nm to 50 nm InP constant-charge thin layer is grown to cover the quantum dots. The InP constant-charge thin layer is n-type doped, with an impurity atom density ranging from 1 × 10⁻⁶. 17 ~3×10 17 cm -3 .

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