Display panel and display device including same

Abstract

The present disclosure relates to a display panel and a display device including the same, and each sub-pixel of the display panel includes a first light emitting element, a second light emitting element, and a first transistor connected to the first light emitting element and the second light emitting element. A first AC voltage applied to one of an anode electrode and a cathode electrode of the first light emitting element periodically changes between a first voltage and a second voltage. A second AC voltage applied to one of the anode electrode and the cathode electrode of the second light emitting element periodically changes between the first voltage and the second voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0134839, filed on October 4, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a display panel capable of changing viewing angle and perspective, and a display device including the display panel. Background Technology

[0004] Variable viewing angle technology is being applied to display devices. Variable viewing angle technology allows video content or visual information reproduced on a display device to be visible to the user only within a narrow viewing angle range, or to be visible to multiple users within a wide viewing angle range.

[0005] With the market expansion of future vehicles such as electric and autonomous vehicles, the demand for in-vehicle display devices is growing rapidly. Research is underway on how to divide the screen of an in-vehicle display device so that one part of the screen is controlled to have a narrow viewing angle, while another part is controlled to have a wide viewing angle. This technology can display private content or information that only a specific user can see on pixels driven by a narrow viewing angle, while displaying shared content that multiple users can view together on pixels driven by a wide viewing angle. To achieve this, a pixel technology is needed that can freely control each pixel to be in a narrow or wide viewing angle. Various studies have been conducted on viewing angle modes for electrically switched pixels. However, to implement methods for electrically switched pixel viewing angle modes, additional light-emitting elements, switching elements, and gate signals and control signals for mode switching need to be provided to the pixel circuitry. Therefore, there are problems with the pixel circuitry configuration becoming complex and requiring additional gate driving circuitry. Summary of the Invention

[0006] The embodiments disclosed herein address the aforementioned disadvantages and / or problems.

[0007] This disclosure provides a display panel and a display device including the display panel, which can easily perform viewing angle control and has a simple-configured pixel circuit.

[0008] The problems addressed by the embodiments of this disclosure are not limited to those described above, and other problems not described will be clearly understood by those skilled in the art from the following description.

[0009] A display panel according to one embodiment includes: multiple data lines; multiple gate lines; multiple power lines; and multiple sub-pixels, each sub-pixel being electrically connected to the data lines, gate lines, and power lines. Each sub-pixel includes: a first light-emitting element, a second light-emitting element, and a first transistor connected to the first and second light-emitting elements. A first AC voltage applied to one of the anode and cathode electrodes of the first light-emitting element periodically changes between a first voltage and a second voltage. A second AC voltage applied to one of the anode and cathode electrodes of the second light-emitting element periodically changes between the first voltage and a second voltage. The second voltage is a voltage lower than the first voltage.

[0010] The display panel may further include: a first lens that overlaps with the light-emitting area of ​​the first light-emitting element; and a second lens that overlaps with the light-emitting area of ​​the second light-emitting element.

[0011] The first AC voltage applied to the first light-emitting element and the second AC voltage applied to the second light-emitting element can have waveforms with opposite phases to each other.

[0012] When the first AC voltage applied to the first light-emitting element is a first voltage, the second AC voltage applied to the second light-emitting element can be a second voltage.

[0013] The display panel may further include: a first switching element configured to select one of a first voltage and a second voltage and supply the selected voltage to a first light-emitting element; and a second switching element configured to select one of the first voltage and a second voltage and supply the selected voltage to a second light-emitting element.

[0014] The sub-pixel may further include: a capacitor connected between the first node and the second node; a second transistor turned on in response to a gate-on voltage applied to a gate signal on the gate line to electrically connect the data line to the second node; and a third transistor turned on in response to a gate-on voltage applied to the gate signal to electrically connect the first node to a reference voltage line. The cathode electrodes of the first and second light-emitting elements may be connected to the first node. A first power supply line applying a first AC voltage may be connected to the anode electrode of the first light-emitting element. A second power supply line applying a second AC voltage may be connected to the anode electrode of the second light-emitting element. A third power supply line applying a pixel ground voltage may be connected to the third node.

[0015] The first transistor may include a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node. The second transistor may include a first electrode connected to a data line, a gate electrode connected to a gate line, and a second electrode connected to the second node. The third transistor may include a first electrode connected to the first node, a gate electrode connected to a gate line, and a second electrode connected to a reference voltage line. A data voltage or black / grayscale voltage for the pixel data is applied to the data line.

[0016] The pixel ground voltage can have the same voltage level as the second voltage.

[0017] The sub-pixel may further include: a capacitor connected between the second node and the third node; a second transistor turned on in response to a gate-on voltage of a gate signal applied to the gate line to electrically connect the data line to the second node; and a third transistor turned on in response to a gate-on voltage of the gate signal to electrically connect the third node to a reference voltage line. The anode electrodes of the first and second light-emitting elements may be connected to the third node. A first power supply line to which a pixel driving voltage is applied may be connected to the first node. A second power supply line to which a first AC voltage is applied may be connected to the cathode electrode of the first light-emitting element. A third power supply line to which a second AC voltage is applied may be connected to the cathode electrode of the second light-emitting element.

[0018] The first transistor may include a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node. The second transistor includes a first electrode connected to a data line, a gate electrode connected to a gate line, and a second electrode connected to the second node. The third transistor may include a first electrode connected to a third node, a gate electrode connected to a gate line, and a second electrode connected to a reference voltage line. The data voltage or black / grayscale voltage of the pixel data can be applied to the data line.

[0019] The pixel driving voltage can have the same voltage level as the first voltage.

[0020] The first light-emitting element can emit light in a first-viewpoint mode. The second light-emitting element can emit light in a second-viewpoint mode, which has a different viewpoint than the first-viewpoint mode.

[0021] A display device according to one embodiment includes: a display panel, wherein a plurality of data lines, a plurality of gate lines, a plurality of power lines and a plurality of sub-pixels are disposed, each sub-pixel being electrically connected to the data lines, the gate lines and the power lines; a data driver being electrically connected to the data lines; and a gate driver being electrically connected to the gate lines.

[0022] The display device may further include: a timing controller configured to send pixel data of the input video to a data driver and control the operating timing of the data driver and the gate driver. The timing controller may divide a frame period into at least a first subframe period, a second subframe period, a third subframe period, and a fourth subframe period.

[0023] During the first subframe period, a data voltage or black / grayscale voltage of the first pixel data can be applied to the data line. During the second subframe period, a black / grayscale voltage can be applied to the data line. During the third subframe period, a data voltage or black / grayscale voltage of the second pixel data can be applied to the data line. During the fourth subframe period, a black / grayscale voltage can be applied to the data line. A first AC voltage can be applied to the anode electrode of the first light-emitting element. A second AC voltage can be applied to the anode electrode of the second light-emitting element. A pixel ground voltage, set as the second voltage, can be applied to the cathode electrodes of the first and second light-emitting elements. During the first and second subframe periods, the first AC voltage can be the first voltage, and the second AC voltage can be the second voltage. During the third and fourth subframe periods, the first AC voltage can be the second voltage, and the second AC voltage can be the first voltage.

[0024] During the first subframe period, a data voltage or black / grayscale voltage of the first pixel data can be applied to the data line. During the second subframe period, a black / grayscale voltage can be applied to the data line. During the third subframe period, a data voltage or black / grayscale voltage of the second pixel data can be applied to the data line. During the fourth subframe period, a black / grayscale voltage can be applied to the data line. A pixel driving voltage set as a first voltage can be applied to the anode electrode of the first light-emitting element and the anode electrode of the second light-emitting element. A first AC voltage can be applied to the cathode electrode of the first light-emitting element. A second AC voltage can be applied to the cathode electrode of the second light-emitting element. During the first and second subframe periods, the first AC voltage can be the second voltage, and the second AC voltage can be the first voltage. During the third and fourth subframe periods, the first AC voltage can be the first voltage, and the second AC voltage can be the second voltage.

[0025] The display panel may further include: a first switching element configured to select one of a first voltage and a second voltage and supply the selected voltage to a first light-emitting element; and a second switching element configured to select one of the first voltage and a second voltage and supply the selected voltage to a second light-emitting element.

[0026] According to embodiments of this disclosure, the power consumption of a display device can be reduced by driving the light-emitting elements of each color at maximum luminous efficiency. Therefore, this disclosure enables the use of low-power driving for display devices.

[0027] According to embodiments of this disclosure, the viewing angle of each sub-pixel can be freely switched using a pixel circuit with a simple structure.

[0028] According to embodiments of this disclosure, a display device capable of switching the viewing mode of each sub-pixel can be realized without providing additional gate driving circuitry.

[0029] The effects of this disclosure are not limited to those described above, and those skilled in the art will understand from the following description and the appended claims other effects not described. Attached Figure Description

[0030] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0031] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0032] Figure 2 This is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure;

[0033] Figure 3 This is a diagram showing an example of a lens set in each sub-pixel;

[0034] Figure 4 This is a graph showing an example of the current density-efficiency ratio of light-emitting elements by color;

[0035] Figure 5 This is a diagram showing examples of microLEDs with different duty cycles at the same target brightness;

[0036] Figure 6 This is a diagram illustrating the frame period according to an embodiment of the present disclosure;

[0037] Figure 7 It is shown in Figure 6 Waveform diagrams of examples of signals applied to the data lines and gate lines during the first and second subframe periods shown;

[0038] Figure 8 It shows that it is applied to Figure 2 Waveform diagrams of example first and second pixel drive voltages of the pixel circuit shown;

[0039] Figure 9 This is a diagram illustrating an example of pixels that independently control the viewing angle within the display area of ​​a display panel;

[0040] Figures 10 to 12 yes Figure 9The diagram shows the view control method for the first and second sub-pixels.

[0041] Figure 13 This is a diagram illustrating the connection structure of the display panel and the circuit board in a display device according to an embodiment of the present disclosure;

[0042] Figure 14 This is a diagram illustrating the paths of the first and second pixel driving voltages according to embodiments of the present disclosure;

[0043] Figure 15 This is a diagram illustrating the paths of the first and second pixel driving voltages according to another embodiment of the present disclosure;

[0044] Figure 16 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure;

[0045] Figure 17 It is shown in Figure 16 Waveform diagrams of examples of signals applied to the data lines and gate lines during the first and second subframe periods shown;

[0046] Figure 18 It shows that it is applied to Figure 16 Waveform diagrams of example first and second pixel ground voltages of the pixel circuit shown;

[0047] Figures 19 to 21 This shows the application. Figure 16 A diagram illustrating the viewing angle control method for the first and second sub-pixels of the pixel circuit shown.

[0048] Figure 22 It is a diagram illustrating the paths of the first and second pixel ground voltages according to embodiments of the present disclosure; and

[0049] Figure 23 This is a diagram illustrating the paths of the ground voltages of the first and second pixels according to another embodiment of this disclosure. Detailed Implementation

[0050] The advantages and features of this disclosure and its implementation methods will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will make the disclosure complete and allow those skilled in the art to fully understand its scope.

[0051] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0052] Terms such as “comprising,” “including,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless the term is used only in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0053] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0054] When describing the location or connection between two components, terms such as "on top of," "above," "below," "next to," "connected to or coupled to," "cross," "intersect," etc., may allow one or more other components to be inserted between them unless "immediately adjacent" or "directly" is used.

[0055] When describing time-prior relationships, such as "after," "following," "next," "before," etc., they may not be sequential on a temporal basis unless "immediately" or "directly" is used.

[0056] The terms “first”, “second”, etc., can be used to distinguish elements from one another, but the function or structure of a component is not limited by the ordinal number preceding the component or the component name.

[0057] The following embodiments may be combined or integrated with each other in part or in whole, and may be linked and operated in various technical ways. The embodiments may be performed independently or in relation to each other.

[0058] The pixel circuit and gate drive circuit of the display device may include multiple transistors. The transistors may be implemented as thin-film transistors (TFTs). The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon TFTs (LTPS TFTs) including low-temperature polycrystalline silicon, etc.

[0059] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers flow from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide-semiconductor), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0060] The gate signal oscillates between the gate on-state voltage and the gate off-state voltage. The transistor turns on in response to the gate on-state voltage and turns off in response to the gate off-state voltage. In the case of an n-channel transistor, the gate on-state voltage can be the gate high voltage VGH, and the gate off-state voltage can be the gate low voltage VGL. In the case of a p-channel transistor, the gate on-state voltage can be the gate low voltage VGL, and the gate off-state voltage can be the gate high voltage VGH.

[0061] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0062] refer to Figure 1 A display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data to pixels 101 of the display panel 100, and a power supply 140 for generating power required to drive the pixels 101 and the display panel driving circuit.

[0063] The substrate of the display panel 100 may be, but is not limited to, a plastic substrate, a thin glass substrate, or a metal substrate. The display panel 100 may be, but is not limited to, a rectangular panel having a length in the X-axis direction (or a first direction), a width in the Y-axis direction (or a second direction), and a thickness in the Z-axis direction (or a third direction). For example, at least a portion of the display panel 100 may have a curved outer periphery.

[0064] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be used in a transparent display device, where an image is displayed on a screen and the actual object is visible outside the display panel. The display panel 100 can be made as a flexible display panel. Alternatively, the display panel 100 can be made from a stretchable panel.

[0065] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The display area AA includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix. The display panel 100 may further include power lines and reference voltage lines connected to the pixels 101. The power lines are collectively connected to the pixels and supply the voltage required to drive the pixels 101. The power lines may be implemented as long conductors along a first or second direction, or as a mesh of conductors in the first and second directions electrically connected.

[0066] Each of pixel 101 can be divided into red (R) subpixels, green (G) subpixels, and blue (B) subpixels for color implementation. Each pixel may further include white subpixels. Each subpixel includes pixel circuitry for driving a light-emitting element. Each pixel circuit is connected to data lines, gate lines, and power lines. In the following text, "pixel" may be interpreted as "subpixel".

[0067] like Figure 2 and Figure 16 As shown, the pixel circuit of a sub-pixel may include a first light-emitting element LD1, a second light-emitting element LD2, and first transistors M01 and M11 connected to the light-emitting elements LD1 and LD2. An AC voltage applied to either the anode or cathode electrode of the first light-emitting element LD1 may periodically vary between a first voltage and a second voltage. Similarly, an AC voltage applied to either the anode or cathode electrode of the second light-emitting element LD2 may periodically vary between a first voltage and a second voltage. The AC voltages applied to the first light-emitting element LD1 and the second light-emitting element LD2 may have waveforms with opposite phases. Therefore, when the AC voltage applied to the first light-emitting element LD1 is the first voltage, the AC voltage applied to the second light-emitting element LD2 may be the second voltage. Conversely, when the AC voltage applied to the first light-emitting element LD1 is the second voltage, the AC voltage applied to the second light-emitting element LD2 may be the first voltage.

[0068] When driven in the first viewing mode, each sub-pixel emits light from the first light-emitting element with a wide viewing angle by diffusing it. Conversely, when driven in the second viewing mode, each sub-pixel emits light from the second light-emitting element with a narrow viewing angle by focusing it. The viewing mode of the sub-pixel can be electrically controlled and switched.

[0069] The pixel array includes multiple pixel lines L1 to L(n). Each of the pixel lines L1 to L(n) includes a pixel arranged along a line direction (X-axis direction) in the pixel array of the display panel 100. Pixels arranged in a pixel line can share a gate line 103. Sub-pixels arranged along the data line direction in the column direction (Y-axis direction) can share a data line 102. A horizontal period is the time obtained by dividing a frame period by the total number of pixel lines L1 to L(n).

[0070] Touch sensors can be arranged on the display panel 100 to sense touch input. The touch sensors can be arranged on the display panel 100 as on-cell type or add-on type, or implemented as in-cell type touch sensors embedded in the pixel array.

[0071] Power supply 140 uses a DC-DC converter to generate a constant voltage (or direct current (DC) voltage) required to drive the pixel array and display panel driving circuitry of display panel 100. The DC-DC converter may include a charge pump, rectifier, buck converter, boost converter, etc. Power supply 140 can adjust the level of the DC input voltage from host system 200 to output a constant voltage, such as a gamma reference voltage, gate cutoff voltage, gate on voltage, pixel drive voltage, pixel ground voltage, etc. The gamma reference voltage is supplied to data driver 110. The dynamic range of the data voltage output from data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the highest and lowest grayscale voltages.

[0072] Gate on and gate off voltages are supplied to level shifter 150 and gate driver 120. For example, a constant voltage, including pixel drive voltage and pixel ground voltage, is supplied to pixel 101 via a power line commonly connected to pixel 101. Pixel ground voltage can be, but is not limited to, ground voltage. The pixel drive voltage can be supplied to display panel 100 from the main power supply of host system 200. In this case, power supply 140 does not need to output pixel drive voltage.

[0073] Power supply 140 can output a gamma reference voltage using a programmable gamma voltage circuit. The programmable gamma voltage circuit can change the voltage level of the gamma reference voltage supplied to data driver 110 based on digital data from timing controller 130.

[0074] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image into the pixels of the display panel 100. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0075] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver can be integrated into a single driver IC (integrated circuit). The timing controller 130, power supply 140, level shifter 150, data driver 110, and touch sensor driver can be further integrated into the driver IC.

[0076] Data driver 110 receives pixel data of the input image provided as a digital signal from timing controller 130 and outputs a data voltage of the pixel data. Data driver 110 uses a digital-to-analog converter (DAC) to convert the pixel data of the input image into a gamma-compensated voltage to output a data voltage. A gamma reference voltage is divided into gamma-compensated voltages for each grayscale level by a voltage divider circuit in data driver 110 and supplied to the DAC. The DAC generates the data voltage as a gamma-compensated voltage corresponding to the grayscale value of the pixel data. The data voltage output from the DAC is output to data line 102 through an output buffer in each data output channel of data driver 110.

[0077] The data driver 110 may include a sensing channel of an external compensation circuit electrically connected to a reference voltage line of the display panel 100. The sensing channel may include an analog-to-digital converter (hereinafter referred to as "ADC") to convert current or voltage from the reference voltage line into digital data and to send the digital data to the timing controller 130.

[0078] Each of the red, green, and blue light-emitting elements can have a different data voltage during its maximum luminous efficiency period. The data driver 110 can change at least one of the dynamic range, maximum voltage, and minimum voltage of the red data voltage supplied to the red sub-pixel, the green data voltage supplied to the green sub-pixel, and the blue data voltage supplied to the blue sub-pixel, so as to drive each of the red, green, and blue light-emitting elements during its maximum luminous efficiency period.

[0079] The gate driver 120 may be formed on the display panel 100. For example, the gate driver 120 may be arranged in a non-display area NA outside the display area AA in the display panel 100, or at least a portion thereof may be disposed in the display area AA.

[0080] Gate driver 120 can be disposed in the left non-display area NA or right non-display area NA outside the display area AA in the display panel 100 to supply a gate signal to gate line 103 in a single-feed method. In the single-feed method, the gate signal is applied to one end of the gate line. Gate driver 120 can also be disposed in the left non-display area NA and right non-display area NA in the display panel 100 to apply the gate signal to gate line 103 in a dual-feed method. In the dual-feed method, the gate signal is applied to both ends of gate line 103 simultaneously. At least some circuitry of gate driver 120 can be disposed within the display area AA.

[0081] The gate driver 120 can output pulses of the gate signal and, under the control of the timing controller 130, use one or more shift registers to shift the pulses of the gate signal.

[0082] The timing controller 130 receives pixel data of the input image and timing signals synchronized with the pixel data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. By counting the data enable signal DE, the vertical and horizontal periods can be determined, thus the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has an interval of one horizontal period (1H).

[0083] The timing controller 130 can control the operating timing of the data driver 110 and the gate driver 120 based on the timing signals Vsync, Hsync and DE received from the host system 200.

[0084] The gate timing control signal output from timing controller 130 can be input to the shift register of gate driver 120 via level shifter 150. Level shifter 150 can receive the gate timing control signal and generate a start pulse and clock to provide them to gate driver 120. The input signal of level shifter 150 is a digital signal voltage level signal. The clock output from level shifter 150 can swing between the gate on-voltage and the gate off-voltage. The data timing control signal generated from timing controller 130 is sent to data driver 110.

[0085] The timing controller 130 can send black grayscale data, set independently of the input image, to the data driver 110. When the black grayscale data generated from the timing controller 130 is input to the data driver 110, the data driver 110 converts the black grayscale data into a black grayscale voltage. Under the control of the timing controller 130, the data driver 110 can output a black grayscale voltage independent of the input image during a subframe period in which the black grayscale data is addressed to the subpixel at an increased frame rate. The black grayscale voltage can be applied to the pixel 101 via a data line. The black grayscale voltage can be, but is not limited to, the black grayscale or the lowest grayscale voltage of the pixel data. Since both the first and second light-emitting elements are turned off in the subpixel to which the black grayscale voltage is applied, the subpixel does not emit light and is controlled to remain in the off state.

[0086] The host system 200 can scale the image signal from the video source to match the resolution of the display panel 100, and can send it to the timing controller 130 along with timing control signals.

[0087] Figure 2 This is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure. Figure 3 This is a diagram showing an example of a lens disposed in a light-emitting element.

[0088] refer to Figure 2 and Figure 3 The pixel circuit includes a first light-emitting element LD1 that emits light in a first viewing mode, a second light-emitting element LD2 that emits light in a second viewing mode, a first transistor M01 that drives the first light-emitting element LD1 and the second light-emitting element LD2, a capacitor Cst connected between a first node n1 and a second node n2, a second transistor M02 that is turned on in response to a gate on-state voltage of the gate signal SCAN to electrically connect the data line 102 to the second node n2, and a third transistor M03 that is turned on in response to a gate on-state voltage of the gate signal SCAN to electrically connect the first node n1 to the reference voltage line 107. Transistors M01, M02, and M03 can be implemented by p-channel transistors. In this case, the gate on-state voltage is a gate low voltage, and the gate off-state voltage is a gate high voltage.

[0089] The second transistor M02 and the third transistor M03 can be controlled by the same gate signal SCAN, but this disclosure is not limited thereto. For example, the second transistor M02 can be controlled by a first gate signal, and the third transistor M03 can be controlled by a second gate signal. In this case, the second transistor M02 and the third transistor M03 can be connected to different gate lines.

[0090] The pixel circuit can be connected to wires such as a data line 102 that applies a data voltage Vdata and a black grayscale voltage Vblack, a gate line 103 that applies a gate signal SCAN, a first power supply line 104 that applies a first pixel drive voltage EVDD1, a second power supply line 105 that applies a second pixel drive voltage EVDD2, a third power supply line 106 that applies a pixel ground voltage EVSS, and a reference voltage line 107 that applies a reference voltage Vref.

[0091] The first pixel driving voltage EVDD1 may have a first voltage level for turning on the first light-emitting element LD1 by increasing the anode voltage of the first light-emitting element LD1 in a first viewing angle mode, and a second voltage level for turning off the first light-emitting element LD1 by decreasing the anode voltage of the first light-emitting element LD1 in a second viewing angle mode. The second pixel driving voltage EVDD2 may have a first voltage level for turning on the second light-emitting element LD2 by increasing the anode voltage of the second light-emitting element LD2 in a second viewing angle mode, and a second voltage level for turning off the second light-emitting element LD2 by decreasing the anode voltage of the second light-emitting element LD2 in a first viewing angle mode. The first voltage level of each of the first pixel driving voltage EVDD1 and the second pixel driving voltage EVDD2 may be 9V, but this disclosure is not limited thereto. The first voltage level may be analyzed as a high voltage level, and the second voltage level may be analyzed as a low voltage level. The second voltage level of each of the first pixel driving voltage EVDD1 and the second pixel driving voltage EVDD2 may be 0V, but this disclosure is not limited thereto. The pixel ground voltage EVSS can be a voltage lower than a first voltage level of each of the first pixel drive voltage EVDD1 and the second pixel drive voltage EVDD2, for example, it can be a second voltage level or 0V, but this disclosure is not limited thereto.

[0092] The data voltage Vdata can be selectively set to a voltage corresponding to the grayscale value of the pixel data within a dynamic range of 2V to 9V, but this disclosure is not limited thereto. The reference voltage Vref can be the same voltage level as a first voltage level or 9V for each of the first pixel drive voltage EVDD1 and the second pixel drive voltage EVDD2, but this disclosure is not limited thereto. The voltage of the gate signal SCAN includes pulses oscillating between a gate high voltage and a gate low voltage. The gate high voltage is 13V and the gate low voltage is -13V, but this disclosure is not limited thereto.

[0093] Each of the first light-emitting element LD1 and the second light-emitting element LD2 may include an anode electrode, a cathode electrode, and a light-emitting layer. The first light-emitting element LD1 and the second light-emitting element LD2 may be light-emitting diodes, such as organic light-emitting diodes (OLEDs) or micro-LEDs, but embodiments of this disclosure are not limited thereto. The micro-LED chip may be implemented as a lateral structure or a flip-chip structure. The micro-LED chip may be connected to a first node n1 in a transfer process. The cathode electrode of each of the first light-emitting element LD1 and the second light-emitting element LD2 is connected to the first node n1. A first pixel driving voltage EVDD1 is applied to the anode electrode of the first light-emitting element LD1, and a second pixel driving voltage EVDD2 is applied to the anode electrode of the second light-emitting element LD2.

[0094] like Figure 3 As shown, each sub-pixel may include lenses 32 and 34. The first lens 32 is a wide-viewing-angle lens disposed above the first light-emitting element LD1. The first lens 32 overlaps with the light-emitting area of ​​the first light-emitting element LD1. The first lens 32 may be implemented as a semi-cylindrical lens to limit the upper and lower viewing angles and widen the right and left viewing angles. The first lens 32 is long in the left-right direction (or X-axis direction) of the display panel 100 and narrow in the up-down direction (Y-axis direction) of the display panel 100. The first lens 32 converges the light from the first light-emitting element LD1 in the up-down direction and diffuses the light with a wide viewing angle in the left-right direction, so that the light from the first light-emitting element LD1 travels with a wide viewing angle in the left-right direction.

[0095] The second lens 34 is a wide-viewing-angle lens disposed above the second light-emitting element LD2. The second lens 34 overlaps with the light-emitting area of ​​the second light-emitting element LD2. The second lens 34 may be a hemispherical lens, which is thicker in the central part and thinner towards the edges in the vertical and horizontal directions. The second lens 34 converges the light from the second light-emitting element LD2 so that the light emitted from the second light-emitting element LD2 travels with a narrow viewing angle in the vertical and horizontal directions.

[0096] The first lens 32 and the second lens 34 can be implemented by a transparent medium or transparent insulating layer pattern disposed in the display panel 100, but this disclosure is not limited thereto. The first lens 32 and the second lens 34 can prevent light from the pixels from being reflected on the windshield of the vehicle and thus prevent the screen of the display device from being seen by limiting the upper and lower viewing angles of the pixels.

[0097] The first transistor M01 includes a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3. A third power supply line 106, to which a pixel ground voltage EVSS is applied, is connected to the third node n3. A capacitor Cst is connected between the first node n1 and the second node n2 and is charged with the gate-source voltage of the first transistor M01.

[0098] The second transistor M02 is connected between the data line 102, to which pixel data data or black / grayscale voltage Vblack is applied, and the second node n2, and is turned on in response to the gate turn-on voltage of the gate signal SCAN. When the second transistor M02 is turned on, the data line 102 is electrically connected to the second node n2. The second transistor M02 includes a first electrode connected to the data line 102, a gate electrode connected to the gate line 103 to which the gate signal SCAN is applied, and a second electrode connected to the second node n2.

[0099] The third transistor M03 is connected between the reference voltage line 107, to which the reference voltage Vref is applied, and the first node n1, and is turned on in response to the gate turn-on voltage of the gate signal SCAN. When the third transistor M03 is turned on, the first node n1 can be electrically connected to the reference voltage line 107. The third transistor M03 includes a first electrode connected to the first node n1, a gate electrode connected to the gate line 103 to which the gate signal SCAN is applied, and a second electrode connected to the reference voltage line 107.

[0100] Reference voltage line 107 can be connected to an external compensation circuit. The ADC of the external compensation circuit can be located in the sensing channel of data driver 110 and can be connected to the compensation circuit of timing controller 130. In sensing mode, the ADC converts the voltage received via reference voltage line 107 into a digital signal and outputs a digital signal indicating the electrical characteristics (e.g., threshold voltage, mobility, etc.) of the first transistor M01. The compensation circuit of timing controller 130 modulates pixel data using a compensation value selected based on the digital signal input from the ADC. The external compensation circuit can compensate for deviations (changes) in the electrical characteristics of the first transistor M01 in each pixel by modulating the pixel data (digital data) of the input video according to deviations (or changes) in the electrical characteristics of the first transistor M01.

[0101] The display panel driving circuit can implement pixel duty cycle driving to drive the light-emitting elements (such as the first light-emitting element LD1 or the second light-emitting element LD2) at their maximum luminous efficiency. To implement pixel duty cycle driving, the timing controller 130 can divide a frame period into two or more sub-frame periods in a time-division manner. For example, a frame period may include at least a first sub-frame period and a second sub-frame period. During the first sub-frame, the data voltage Vdata of the pixel data can be charged into the sub-pixel, and then the light-emitting element can emit light and be turned on with a brightness corresponding to the grayscale value of the pixel data. During the second sub-frame period, the black grayscale voltage Vblack can be charged into the sub-pixel, and the sub-pixel can be turned off. The on-time period of the first sub-frame period and the off-time period of the second sub-frame period determine the duty cycle of the light-emitting element. The timing controller 130 can set or change the on-time period of the first sub-frame period and the on-time period of the second sub-frame period by controlling the display panel driving circuit according to the duty cycle of the light-emitting element. The larger the duty cycle of the light-emitting element, the longer the on-time of the light-emitting element in a frame period; conversely, the smaller the duty cycle of the light-emitting element, the shorter the off-time of the light-emitting element.

[0102] The grayscale of a pixel can be represented by the brightness of the pixel based on the voltage level or amplitude of the data voltage, which is selected based on the grayscale value of the pixel data. Each sub-pixel can emit light with a brightness that varies depending on the voltage level of the data voltage Vdata applied to the data line 102, and can be turned off by applying a black grayscale voltage Vblack to the data line 102.

[0103] Figure 4 This is a graph showing the current density versus efficiency characteristics of a micro-LED used as a light-emitting element. Figure 4 In the diagram, the horizontal axis represents the current density (A / cm²). 2 The vertical axis is the ratio of the efficiency of the light-emitting element by color to the reference efficiency when the reference efficiency is "1". Figure 4 The current density to efficiency ratios of the light-emitting elements by color shown are standardized values. For example... Figure 4 As shown, the periods of maximum luminous efficiency can differ between the micro-LEDs in the red, green, and blue sub-pixels. When the driving current region for each color-coded micro-LED is set according to its maximum luminous efficiency period, power consumption can be reduced.

[0104] Figure 5 This is a diagram illustrating examples of microLEDs with different duty cycles at the same target brightness. Figure 5 In the diagram, the horizontal axis represents time, and the vertical axis represents current.

[0105] like Figure 5 As shown, the longer the on-time of the micro-LED used as the light-emitting element and the higher the current flowing in the light-emitting element, the higher the brightness of the pixel becomes; therefore, brightness can be expressed as time x current. When the micro-LED is driven with a high current density for a short period, the luminous efficiency is very high. Therefore, compared to driving the micro-LED with a low current for a long time, power consumption can be reduced at the same target brightness. For example, when the duty cycle is 100%, as shown by the solid line, the micro-LED is on for about one frame cycle, and when the duty cycle is 25%, as shown by the dashed line, the micro-LED is on for about 1 / 4 frame cycle. When the duty cycle is 50%, the micro-LED is on for about 1 / 2 frame cycle.

[0106] In the following text, a subpixel driven in a first-view mode is referred to as a "first subpixel," and a subpixel driven in a second-view mode is referred to as a "second subpixel." Pixel data applied to the first subpixel is referred to as "first pixel data," and pixel data applied to the second subpixel is referred to as "second pixel data." The first pixel data may be video data of shared content, but this disclosure is not limited thereto. The second pixel data may be video data of private content or content requiring privacy protection, but this disclosure is not limited thereto. The first subpixel is a subpixel in which a first light-emitting element LD1 can be turned on and its brightness corresponds to the grayscale of the first pixel data, while a second light-emitting element LD2 is turned off. The second subpixel is a subpixel in which a second light-emitting element LD2 can be turned on and its brightness corresponds to the grayscale of the second pixel data, while a first light-emitting element LD1 is turned off. When the first pixel driving voltage EVDD1 has a first voltage level and the second pixel driving voltage EVDD2 has a second voltage level, the first light-emitting element LD1 can be turned on and emit light, and the second light-emitting element LD2 is turned off and extinguished. Simultaneously, when the second pixel driving voltage EVDD2 has a first voltage level and the first pixel driving voltage EVDD1 has a second voltage level, the second light-emitting element LD2 can be turned on and emit light, while the first light-emitting element LD1 is turned off and extinguished.

[0107] Figure 6 This is a diagram illustrating a frame period according to an embodiment of the present disclosure. Figure 7 This is a waveform diagram showing an example of the signals applied to the data lines and gate lines during the first and second subframe periods. Figure 7 In this context, "VGL" represents the gate low voltage of the gate signal, and "VGH" represents the gate high voltage of the gate signal. "SCAN1 to SCAN(n)" indicate gate signals shifted sequentially in units of one pixel line, and D1 to D(m) represent data lines for which pixel data voltage Vdata or black / grayscale voltage Vblack is applied. Figure 6 and Figure 7In this context, "DA1" indicates the first data addressing direction for writing pixel data or black / grayscale data to a subpixel during the first subframe period SF1, and "BA1" indicates the second data addressing direction for writing black / grayscale data to a subpixel during the second subframe period SF2. "DA2" indicates the third data addressing direction for writing pixel data or black / grayscale data to a subpixel during the third subframe period SF3, and "BA2" indicates the fourth data addressing direction for writing black / grayscale data to a subpixel during the fourth subframe period SF4.

[0108] refer to Figures 6 to 8 A frame period can be divided into four subframe periods in a time-division manner: the first subframe period SF1, the second subframe period SF2, the third subframe period SF3, and the fourth subframe period SF4.

[0109] During the first subframe period SF1, first pixel data can be written to the first subpixel, and the first subpixel can be turned on in the first view mode (S mode). The first pixel data is charged into the first subpixel as a data voltage Vdata. During the first subframe period SF1, black grayscale data can be written to the second subpixel. The black grayscale data is charged into the second subpixel as a black grayscale voltage Vblack. Therefore, during the first subframe period SF1, after data addressing DA1, the first subpixel can be turned on and the second subpixel can be turned off in the first view mode (S mode).

[0110] During the second subframe period SF2, black grayscale data can be written to the first and second subpixels. During the second subframe period SF2, the first and second subpixels are turned off by the black grayscale data. Even when a first pixel drive voltage EVDD1 with a first voltage level is applied to the first subpixel, the first subpixel can be turned off during the second subframe period SF2 because the first transistor M01 with the applied black grayscale voltage is turned off. Therefore, during the second subframe period SF2, all subpixels are turned off after data addressing BA1.

[0111] During the third subframe period SF3, second pixel data can be written to the second subpixel, and the second subpixel can be enabled in the second view mode (P mode). The second pixel data is charged into the second subpixel as a data voltage Vdata. During the third subframe period SF3, black grayscale data can be written to the first subpixel. The black grayscale data is charged into the first subpixel as a black grayscale voltage Vblack. Therefore, during the third subframe period SF3, after data addressing DA2, the second subpixel can be enabled and the first subpixel can be disabled in the second view mode (P mode).

[0112] During the fourth subframe period SF4, black grayscale data can be written to the first and second subpixels. During the fourth subframe period SF4, the first and second subpixels are turned off by the black grayscale data. Even when a second pixel drive voltage EVDD2 with a first voltage level is applied to the second subpixel, the second subpixel can be turned off during the fourth subframe period SF4 because the first transistor M01 with the applied black grayscale voltage is turned off. Therefore, during the fourth subframe period SF4, all subpixels are turned off after data addressing BA1.

[0113] Figure 8 It shows that it is applied to Figure 2 The waveform diagram shows an example of the first and second pixel drive voltages of the pixel circuit shown. Figure 8 In this code, "S mode" indicates first-person perspective mode, and "P mode" indicates second-person perspective mode. "ON" indicates the on state of a subpixel, and "OFF" indicates the off state of a subpixel.

[0114] refer to Figure 8 The first pixel driving voltage EVDD1 can have a first voltage level H during the first subframe period SF1 and the second subframe period SF2, and a second voltage level L during the third subframe period SF3 and the fourth subframe period SF4. The second pixel driving voltage EVDD2 can have a second voltage level L during the first subframe period SF1 and the second subframe period SF2, and a first voltage level H during the third subframe period SF3 and the fourth subframe period SF4. The first pixel driving voltage EVDD1 with the first voltage level H can turn on the first sub-pixel by causing the first light-emitting element LD1 in the first sub-pixel to emit light.

[0115] The first subpixel can be driven and enabled during the first subframe period SF1 of a frame period, and can be disabled during the second subframe periods SF2, SF3, and SF4. Therefore, the first subpixel can be enabled with a 25% duty cycle. The second subpixel can be driven and enabled during the third subframe period SF3 of a frame period, and can be disabled during the first subframe period SF1, the second subframe period SF2, and the fourth subframe period SF4. Therefore, the second subpixel can be enabled with a 25% duty cycle.

[0116] Figure 9 This is a diagram illustrating an example of pixels that independently control the viewing angle within the display area of ​​a display panel. Figure 9In the example, the display area AA may include a first sub-pixel P1 and a second sub-pixel P2, in which the viewing angle is independently controlled. It should be noted that the first sub-pixel P1 and the second sub-pixel P2 are not fixed to a particular viewing angle mode. The first sub-pixel P1 and the second sub-pixel P2 can be driven according to the voltages EVDD1 and EVDD2 respectively applied to the light-emitting elements LD1 and LD2 in either a first viewing angle mode (S-mode) or a second viewing angle mode (P-mode). This will be combined with... Figures 10 to 12 Describe the view control method for each of the first sub-pixel P1 and the second sub-pixel P2.

[0117] refer to Figure 2 , Figure 9 and Figure 10 During the first subframe period SF1, first pixel data can be written to first subpixel P1 and second subpixel P2, and then black / grayscale data can be written to first subpixel P1 and second subpixel P2 during the second subframe period SF2. During both the first and second subframe periods SF1 and SF2, when the first pixel driving voltage EVDD1 has a first voltage level H, the second pixel driving voltage EVDD2 has a second voltage level L. Therefore, first subpixel P1 and second subpixel P2 can be turned on (ON) in the first viewing mode (S mode) during the first subframe period SF1 and turned off (OFF) during the second subframe period SF2.

[0118] During the third subframe period SF3 and the fourth subframe period SF4, black grayscale data is written to the first subpixel P1 and the second subpixel P2. During the third subframe period SF3 and the fourth subframe period SF4, when the second pixel driving voltage EVDD2 has a first voltage level H, the first pixel driving voltage EVDD1 has a second voltage level L. During the third subframe period SF3 and the fourth subframe period SF4, the first subpixel P1 and the second subpixel P2 are in an OFF state due to the black grayscale data.

[0119] refer to Figure 2 , Figure 9 and Figure 11During the first subframe period SF1, first pixel data is written to the first subpixel P1, and black-grayscale data is written to the second subpixel P2. During the second subframe period SF2, black-grayscale data can be written to both the first subpixel P1 and the second subpixel P2. During both the first and second subframe periods SF1 and SF2, when the first pixel driving voltage EVDD1 has a first voltage level H, the second pixel driving voltage EVDD2 has a second voltage level L. Therefore, the first subpixel P1 can be turned on (ON) in the first viewing mode (S mode) during the first subframe period SF1 and turned off (OFF) during the second subframe period SF2. The second subpixel P2 is turned off (OFF) during both the first and second subframe periods SF1 and SF2.

[0120] During the third subframe period SF3, second pixel data is written to the second subpixel P2, and black grayscale data is written to the first subpixel P1. During the fourth subframe period SF4, black grayscale data can be written to both the first subpixel P1 and the second subpixel P2. During both the third and fourth subframe periods SF3 and SF4, when the second pixel driving voltage EVDD2 has a first voltage level H, the first pixel driving voltage EVDD1 has a second voltage level L. Therefore, the second subpixel P2 can be turned on (ON) in the second view mode (P mode) during the third subframe period SF3 and turned off (OFF) during the fourth subframe period SF4. The first subpixel P1 is turned off (OFF) during both the third and fourth subframe periods SF3 and SF4.

[0121] refer to Figure 2 , Figure 9 and Figure 12 During the first subframe period SF1, first pixel data is written to first subpixel P1 and second subpixel P2. Subsequently, during the second subframe period SF2, black / grayscale data can be written to first subpixel P1 and second subpixel P2. During both the first and second subframe periods SF1 and SF2, when the first pixel driving voltage EVDD1 has a first voltage level H, the second pixel driving voltage EVDD2 has a second voltage level L. Therefore, first subpixel P1 and second subpixel P2 can be turned on (ON) in the first viewing mode (S mode) during the first subframe period SF1 and turned off (OFF) during the second subframe period SF2.

[0122] During the third subframe period SF3, second pixel data is written to the second subpixel P2, and black grayscale data is written to the first subpixel P1. During the fourth subframe period SF4, black grayscale data can be written to both the first subpixel P1 and the second subpixel P2. During both the third and fourth subframe periods SF3 and SF4, when the second pixel driving voltage EVDD2 has a first voltage level H, the first pixel driving voltage EVDD1 has a second voltage level L. Therefore, the second subpixel P2 can be turned on (ON) in the second view mode (P mode) during the third subframe period SF3 and turned off (OFF) during the fourth subframe period SF4. The first subpixel P1 is turned off (OFF) during both the third and fourth subframe periods SF3 and SF4. Figure 12 In the example, the first sub-pixel can be enabled with a 25% duty cycle, and the second sub-pixel can be enabled with a 25% duty cycle.

[0123] Figure 13 , Figure 14 and Figure 15 This diagram illustrates a method for applying a first pixel driving voltage EVDD1 and a second pixel driving voltage EVDD2 to a sub-pixel.

[0124] Figure 13 This is a diagram illustrating the connection structure of the display panel and the circuit board in a display device according to an embodiment of the present disclosure.

[0125] refer to Figure 13 Source printed circuit boards (PCBs) 320 and 330 can be electrically connected to display panel 100. Control PCB 300 can be electrically connected to source PCBs 320 and 330 via a flexible cable (e.g., flexible flat cable (FFC) 310). Timing controller 130 and power supply 140 can be disposed on control PCB 300. Level shifter 150 can be mounted on at least one of control PCB 300 and source PCBs 320 and 330. Non-volatile memory can be disposed on one or more of source PCBs 320 and 330. Initial compensation values ​​for each sub-pixel and accumulated data values ​​written to each sub-pixel can be stored in non-volatile memory. External compensation circuitry can derive compensation values ​​for compensating for sub-pixel degradation based on the initial compensation values ​​and accumulated data values ​​of each sub-pixel read from memory.

[0126] Each driver IC SIC including data driver 110 can be mounted on the flexible film of a chip-on-film (COF) and can be connected between source PCBs 320 and 330 and display panel 100. The COF electrically connects source PCBs 320 and 330 to display panel 100, applies the data voltage Vdata and black / grayscale voltage Vblack output from the data output channel of data driver 110 to the data lines of display panel 100, and applies the sensing voltage received from the reference voltage line in sensing mode to the sensing channel of data driver 110.

[0127] Figure 14 This is a diagram illustrating the paths of the first and second pixel driving voltages according to an embodiment of the present disclosure. In this embodiment, as... Figures 8 to 12 As shown, the power supply 140 can periodically reverse the first pixel driving voltage EVDD1 and the second pixel driving voltage EVDD2 under the control of the timing controller 130. Figure 14 In this context, "BRD" refers to the source PCB.

[0128] refer to Figure 14 The first power line 410 and the second power line 420 can be formed by wires extending across the COF, the non-display area NA, and the display area AA. The first pixel driving voltage EVDD1 output from the power supply 140 can be applied via the first power line 410 to the anode electrode of the first light-emitting element LD1 disposed in sub-pixels P1 and P2. The second pixel driving voltage EVDD2 output from the power supply 140 can be applied via the second power line 420 to the anode electrode of the second light-emitting element LD2 disposed in sub-pixels P1 and P2.

[0129] Figure 15 This is a diagram illustrating the paths of the first and second pixel driving voltages according to another embodiment of the present disclosure. In this embodiment, power supply 140 can output a first pixel driving voltage EVDD1 and a second pixel driving voltage EVDD2, which are constant voltages (or DC voltages) having a first voltage level H (e.g., 9V). Power supply 140 can output a pixel ground voltage EVSS, which is the same voltage as the second voltage level, for example, 0V.

[0130] refer to Figure 15The display device may further include a first switch 510 and a second switch 520 connected to power lines 410, 420, and 430. The first power line 410, the second power line 420, and the third power line 430 may be formed by wires extending across the COF, the non-display area NA, and the display area AA. A first pixel driving voltage EVDD1 output from power supply 140 may be applied via the first power line 410 to the anode electrode of the first light-emitting element LD1 disposed in sub-pixels P1 and P2. A second pixel driving voltage EVDD2 output from power supply 140 may be applied via the second power line 420 to the anode electrode of the second light-emitting element LD2 disposed in sub-pixels P1 and P2. A pixel ground voltage EVSS may be applied via the third power line 430 to the cathode electrodes of the first light-emitting element LD1 and the second light-emitting element LD2 disposed in sub-pixels P1 and P2.

[0131] The first switch 510 and the second switch 520 may be disposed on the non-display area NA of the display panel 100, but this disclosure is not limited thereto. For example, switches 510 and 520 may be disposed on the flexible film of the COF or embedded in the driver IC SIC. Switches 510 and 520 may be implemented by transistors that turn on / off in response to corresponding first and second control signals SWS and SWP. The control signals SWS and SWP may be output from the logic circuitry of the timing controller 130 or the driver IC SIC and may be applied to the control terminals or gate electrodes of switches 510 and 520 via control signal lines 440 and 450. The control signal lines 440 and 450 may extend through the COF and the non-display area NA and may be connected to switches 510 and 520.

[0132] The first switch 510, in response to the first control signal SWS, selects one of the first pixel driving voltage EVDD1 and the pixel ground voltage EVSS, and supplies the selected voltage to the first light-emitting element LD1. For example, the first switch 510 may apply the first pixel driving voltage EVDD1 to the anode electrode of the first light-emitting element LD1 disposed in the first sub-pixel P1 and the second sub-pixel P2 during the first sub-frame period SF1 and the second sub-frame period SF2, and subsequently apply the pixel ground voltage EVSS to the anode electrode of the first light-emitting element LD1 during the third sub-frame period SF3 and the fourth sub-frame period SF4.

[0133] The second switch 520, in response to the second control signal SWP, selects one of the second pixel driving voltage EVDD2 and the pixel ground voltage EVSS, and supplies the selected voltage to the second light-emitting element LD2. For example, the second switch 520 may apply the pixel ground voltage EVSS to the anode electrode of the second light-emitting element LD2 disposed in the first sub-pixel P1 and the second sub-pixel P2 during the first sub-frame period SF1 and the second sub-frame period SF2, and then may apply the second pixel driving voltage EVDD2 to the anode electrode of the second light-emitting element LD2 during the third sub-frame period SF3 and the fourth sub-frame period SF4.

[0134] Figure 16 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure. In the following embodiments, the redundant descriptions of the above embodiments will not be repeated.

[0135] refer to Figure 3 and Figure 16 The pixel circuit includes a first light-emitting element LD1 that emits light in a first viewing mode, a second light-emitting element LD2 that emits light in a second viewing mode, a first transistor M11 that drives the first light-emitting element LD1 and the second light-emitting element LD2, a capacitor Cst connected between a second node n2 and a third node n3, a second transistor M12 that electrically connects a data line 102 to the second node n2 in response to a gate on-state voltage of the gate signal SCAN, and a third transistor M13 that electrically connects a reference voltage line 107 to the third node n3 in response to a gate on-state voltage of the gate signal SCAN. Transistors M11, M12, and M13 can be implemented by n-channel transistors. In this case, the gate on-state voltage is a gate high voltage, and the gate off-state voltage is a gate low voltage.

[0136] The pixel circuit can be connected to wires such as a data line 102 with applied data voltage Vdata and black grayscale voltage Vblack, a gate line 103 with applied gate signal SCAN, a first power supply line 104 with applied pixel drive voltage EVDD, a second power supply line 115 with applied first pixel ground voltage EVSS1, a third power supply line 116 with applied second pixel ground voltage EVSS2, and a reference voltage line 107 with applied reference voltage Vref.

[0137] The first pixel ground voltage EVSS1 may have a second voltage level L for turning on the first light-emitting element LD1 by reducing the cathode voltage of the first light-emitting element LD1 in a first viewing mode, and a first voltage level H for turning off the first light-emitting element LD1 by increasing the cathode voltage of the first light-emitting element LD1 in a second viewing mode. The second pixel ground voltage EVSS2 may have a second voltage level L for turning on the second light-emitting element LD2 by reducing the cathode voltage of the second light-emitting element LD2 in a second viewing mode, and a first voltage level H for turning off the second light-emitting element LD2 by increasing the cathode voltage of the second light-emitting element LD2 in a first viewing mode. The second voltage level L of each of the first pixel ground voltage EVSS1 and the second pixel ground voltage EVSS2 may be 2V, but this disclosure is not limited thereto. The first voltage level H of each of the first pixel ground voltage EVSS1 and the second pixel ground voltage EVSS2 may be 11V, but this disclosure is not limited thereto. The pixel driving voltage EVDD may be the same voltage as the first voltage level H of each of the first pixel ground voltage EVSS1 and the second pixel ground voltage EVSS2, for example, 11V, but this disclosure is not limited thereto.

[0138] The data voltage Vdata can be selectively set to a voltage corresponding to the grayscale value of the pixel data within a dynamic range of 1V to 7V, but this disclosure is not limited thereto. The reference voltage Vref can be 1V, but this disclosure is not limited thereto. The voltage of the gate signal SCAN includes pulses oscillating between a gate high voltage and a gate low voltage. The gate high voltage can be 13V, and the gate low voltage can be -13V, but this disclosure is not limited thereto.

[0139] The first light-emitting element LD1 and the second light-emitting element LD2 can be light-emitting elements such as organic light-emitting diodes (OLEDs) or micro LEDs, but this disclosure is not limited thereto. The anode electrode of each of the first light-emitting element LD1 and the second light-emitting element LD2 is connected to a third node n3. A first pixel ground voltage EVSS1 is applied to the cathode electrode of the first light-emitting element LD1, and a second pixel ground voltage EVSS2 is applied to the cathode electrode of the second light-emitting element LD2.

[0140] Each sub-pixel can include Figure 3 Lenses 32 and 34 are shown. The first lens 32 overlaps with the light-emitting area of ​​the first light-emitting element LD1. The second lens 34 overlaps with the light-emitting area of ​​the second light-emitting element LD2.

[0141] The first transistor M11 includes a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3. The first node n1 is connected to a first power supply line 104. A capacitor Cst is connected between the second node n2 and the third node n3 and is charged with the gate-source voltage of the first transistor M11.

[0142] The second transistor M12 is connected between the data line 102 and the second node n2, and is turned on in response to the gate on-voltage of the gate signal SCAN to electrically connect the data line 102 to the second node n2. The second transistor M12 includes a first electrode connected to the data line 102, a gate electrode connected to the gate line 103 to which the gate signal SCAN is applied, and a second electrode connected to the second node n2.

[0143] The third transistor M13 is connected between the reference voltage line 107 and the third node n3, and is turned on in response to the gate on-state voltage of the gate signal SCAN, so as to electrically connect the third node n3 to the reference voltage line 107. The third transistor M13 includes a first electrode connected to the third node n3, a gate electrode connected to the gate line 103, and a second electrode connected to the reference voltage line 107. The reference voltage line 107 can be connected to an external compensation circuit.

[0144] Figure 16 The duty cycle driving method of the pixel circuit shown is as follows: Figures 6 to 18 As shown. A frame period can be divided into four subframe periods in a time-division manner: a first subframe period (SF1), a second subframe period (SF2), a third subframe period (SF3), and a fourth subframe period (SF4). During the first subframe period (SF1), first pixel data can be written to the first subpixel, and the first subpixel can be enabled in the first view mode (S mode). During the first subframe period (SF1), black grayscale data can be written to the second subpixel. During the second subframe period (SF2), black grayscale data can be written to both the first and second subpixels. During the third subframe period (SF3), second pixel data can be written to the second subpixel, and the second subpixel can be enabled in the second view mode (P mode). During the third subframe period (SF3), black grayscale data can be written to the first subpixel. During the fourth subframe period (SF4), black grayscale data can be written to both the first and second subpixels.

[0145] Figure 18 It shows that it is applied to Figure 16 The waveform diagram shows an example of the first and second pixel ground voltages of the pixel circuit shown.

[0146] refer to Figure 18The first pixel ground voltage EVSS1 can have a second voltage level L during the first subframe period SF1 and the second subframe period SF2, and a first voltage level H during the third subframe period SF3 and the fourth subframe period SF4. The second pixel ground voltage EVSS2 can have a first voltage level H during the first subframe period SF1 and the second subframe period SF2, and a first voltage level H during the third subframe period SF3 and the fourth subframe period SF4. The first pixel ground voltage EVSS1 with the second voltage level L can turn on the first sub-pixel by causing the first light-emitting element LD1 in the first sub-pixel to emit light.

[0147] The first subpixel can be driven and enabled during the first subframe period SF1 of a frame period, and can be disabled during the second subframe periods SF2, SF3, and SF4. Therefore, the first subpixel can be enabled with a 25% duty cycle. The second subpixel can be driven and enabled during the third subframe period SF3 of a frame period, and can be disabled during the first subframe period SF1, the second subframe period SF2, and the fourth subframe period SF4. Therefore, the second subpixel can be enabled with a 25% duty cycle.

[0148] Figures 19 to 21 This shows the application. Figure 16 A diagram showing the viewing angle control method for the first and second sub-pixels of the pixel circuit.

[0149] refer to Figure 9 , Figure 16 and Figure 19 During the first subframe period SF1, first pixel data can be written to first subpixel P1 and second subpixel P2, and then black / grayscale data can be written to first subpixel P1 and second subpixel P2 during the second subframe period SF2. During both the first and second subframe periods SF1 and SF2, when the first pixel ground voltage EVSS1 has a second voltage level L, the second pixel ground voltage EVSS2 has a first voltage level H. Therefore, first subpixel P1 and second subpixel P2 can be turned on (ON) in the first viewing mode (S mode) during the first subframe period SF1 and turned off (OFF) during the second subframe period SF2.

[0150] During the third subframe period SF3 and the fourth subframe period SF4, black grayscale data is written to the first subpixel P1 and the second subpixel P2. During the third subframe period SF3 and the fourth subframe period SF4, when the second pixel ground voltage EVSS2 has a second voltage level L, the first pixel ground voltage EVSS1 has a first voltage level H. The first subpixel P1 and the second subpixel P2 are in an OFF state during the third subframe period SF3 and the fourth subframe period SF4 due to the black grayscale data.

[0151] refer to Figure 9 , Figure 16 and Figure 20 During the first subframe period SF1, first pixel data is written to first subpixel P1, and black grayscale data is written to second subpixel P2. During the second subframe period SF2, black grayscale data can be written to both first subpixel P1 and second subpixel P2. During both subframe periods SF1 and SF2, when the first pixel ground voltage EVSS1 has a second voltage level L, the second pixel ground voltage EVSS2 has a first voltage level H. Therefore, first subpixel P1 can be turned on (ON) in the first viewing mode (S mode) during the first subframe period SF1 and turned off (OFF) during the second subframe period SF2. Second subpixel P2 is turned off (OFF) during both subframe periods SF1 and SF2.

[0152] During the third subframe period SF3, second pixel data is written to second subpixel P2, and black grayscale data is written to first subpixel P1. During the fourth subframe period SF4, black grayscale data can be written to both first subpixel P1 and second subpixel P2. During both the third and fourth subframe periods SF3 and SF4, when the second pixel ground voltage EVSS2 has a second voltage level L, the first pixel ground voltage EVSS1 has a first voltage level H. Therefore, second subpixel P2 can be turned on (ON) in the second view mode (P mode) during the third subframe period SF3 and turned off (OFF) during the fourth subframe period SF4. First subpixel P1 is turned off (OFF) during both the third and fourth subframe periods SF3 and SF4.

[0153] refer to Figure 9 , Figure 16 and Figure 21During the first subframe period SF1, first pixel data is written to first subpixel P1 and second subpixel P2. Subsequently, during the second subframe period SF2, black grayscale data can be written to first subpixel P1 and second subpixel P2. During the first subframe period SF1 and the second subframe period SF2, when the first pixel ground voltage EVSS1 has a second voltage level L, the second pixel ground voltage EVSS2 has a first voltage level H. Therefore, first subpixel P1 and second subpixel P2 can be turned on (ON) in the first viewing mode (S mode) during the first subframe period SF1 and turned off (OFF) during the second subframe period SF2.

[0154] During the third subframe period SF3, second pixel data is written to second subpixel P2, and black grayscale data is written to first subpixel P1. During the fourth subframe period SF4, black grayscale data can be written to both first subpixel P1 and second subpixel P2. During both the third and fourth subframe periods SF3 and SF4, when the second pixel ground voltage EVSS2 has a second voltage level L, the first pixel ground voltage EVSS1 has a first voltage level H. Therefore, second subpixel P2 can be turned on (ON) in the second view mode (P mode) during the third subframe period SF3 and turned off (OFF) during the fourth subframe period SF4. First subpixel P1 is turned off (OFF) during both the third and fourth subframe periods SF3 and SF4. Figure 21 In the example, the first subpixel can be turned on with a 25% duty cycle, and the second subpixel can be turned on with a 25% duty cycle.

[0155] Figure 22 and Figure 23 This diagram illustrates a method for applying a first pixel ground voltage EVSS1 and a second pixel ground voltage EVSS2 to a sub-pixel.

[0156] Figure 22 This is a diagram illustrating the paths of the first and second pixel ground voltages according to an embodiment of the present disclosure. In this embodiment, as... Figures 18 to 21 As shown, the power supply 140 can periodically reverse the first pixel ground voltage EVSS1 and the second pixel ground voltage EVSS2 under the control of the timing controller 130.

[0157] refer to Figure 22Power lines 610 and 620, to which pixel ground voltages EVSS1 and EVSS2 are applied, can be formed by wires extending through the COF, the non-display area NA, and the display area AA. The first pixel ground voltage EVSS1, output from power supply 140, can be applied via the second power line 610 to the cathode electrode of the first light-emitting element LD1 disposed in sub-pixels P1 and P2. The second pixel ground voltage EVSS2, output from power supply 140, can be applied via the third power line 620 to the anode electrode of the second light-emitting element LD2 disposed in sub-pixels P1 and P2.

[0158] Figure 23 This is a diagram illustrating the paths of the first and second pixel ground voltages according to another embodiment of the present disclosure. In this embodiment, power supply 140 can output a first pixel ground voltage EVSS1 and a second pixel ground voltage EVSS2, which are constant voltages (or DC voltages) having a second voltage level L (e.g., 0V). Power supply 140 can output a pixel drive voltage EVDD, which is the same voltage as the first voltage level H, for example, 9V.

[0159] refer to Figure 23 The display device may further include a first switch 710 and a second switch 720 connected to power lines 610, 620, and 630. Power lines 610, 620, and 630 may be formed by wires extending through the COF, the non-display area NA, and the display area AA. A first pixel ground voltage EVSS1 output from power supply 140 may be applied via the second power line 610 to the cathode electrode of the first light-emitting element LD1 disposed in sub-pixels P1 and P2. A second pixel ground voltage EVSS2 output from power supply 140 may be applied via the third power line 620 to the cathode electrode of the second light-emitting element LD2 disposed in sub-pixels P1 and P2. A pixel drive voltage EVDD may be applied via the first power line 630 to the anode electrodes of the first light-emitting element LD1 and the second light-emitting element LD2 disposed in sub-pixels P1 and P2.

[0160] Switches 710 and 720 can be implemented by transistors that turn on / off in response to corresponding control signals SWS and SWP. Control signal lines 640 and 650 can extend through the COF and the non-display area NA and can be connected to switches 710 and 720.

[0161] The first switch 710 responds to the first control signal SWS to select one of the pixel driving voltage EVDD and the first pixel ground voltage EVSS1, and supplies the selected voltage to the first light-emitting element LD1. For example, the first switch 710 may apply the first pixel ground voltage EVSS1 to the cathode electrode of the first light-emitting element LD1 disposed in the first sub-pixel P1 and the second sub-pixel P2 during the first sub-frame period SF1 and the second sub-frame period SF2, and subsequently apply the pixel driving voltage EVDD to the cathode electrode of the first light-emitting element LD1 during the third sub-frame period SF3 and the fourth sub-frame period SF4.

[0162] The second switch 720 responds to the second control signal SWP to select one of the pixel driving voltage EVDD and the second pixel ground voltage EVSS2, and supplies the selected voltage to the second light-emitting element LD2. For example, the second switch 720 may apply the pixel driving voltage EVDD to the cathode electrode of the second light-emitting element LD2 disposed in the first sub-pixel P1 and the second sub-pixel P2 during the first sub-frame period SF1 and the second sub-frame period SF2, and then may apply the second pixel ground voltage EVSS2 to the cathode electrode of the second light-emitting element LD2 during the third sub-frame period SF3 and the fourth sub-frame period SF4.

[0163] According to one or more embodiments of this disclosure, the display device can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic organizers, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, vehicle navigation systems, vehicle display devices, vehicle equipment, theater equipment, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, portable video cameras, and home appliances, etc. Additionally, the display device according to one or more embodiments of this disclosure can be applied to organic light-emitting devices or inorganic light-emitting devices.

[0164] The object to be achieved by this disclosure, the means for achieving the object, and the aforementioned effects of this disclosure do not specify the essential features of the claims, and therefore the scope of the claims is not limited to the disclosure of this disclosure.

[0165] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A display panel, comprising: Multiple data cables; Multiple gate lines; Multiple power cords; as well as Multiple sub-pixels, each sub-pixel being electrically connected to the data line, the gate line, and the power line. Each of the sub-pixels includes: First light-emitting element, The second light-emitting element, and A first transistor connected to the first light-emitting element and the second light-emitting element, and The first AC voltage applied to one of the anode and cathode electrodes of the first light-emitting element changes periodically between a first voltage and a second voltage. The second AC voltage applied to one of the anode and cathode electrodes of the second light-emitting element changes periodically between the first voltage and the second voltage. The second voltage is a voltage lower than the first voltage.

2. The display panel according to claim 1, further comprising: A first lens, the first lens overlapping the light-emitting area of ​​the first light-emitting element; as well as The second lens overlaps with the light-emitting area of ​​the second light-emitting element.

3. The display panel according to claim 1, wherein the first AC voltage applied to the first light-emitting element and the second AC voltage applied to the second light-emitting element have waveforms that are out of phase with each other.

4. The display panel according to claim 1, wherein when the first AC voltage applied to the first light-emitting element is the first voltage, the second AC voltage applied to the second light-emitting element is the second voltage.

5. The display panel according to claim 1, further comprising: A first switching element is configured to select one of the first voltage and the second voltage and supply the selected voltage to the first light-emitting element; as well as A second switching element is configured to select one of the first voltage and the second voltage and supply the selected voltage to the second light-emitting element.

6. The display panel according to claim 1, wherein the sub-pixel further comprises: A capacitor connected between the first node and the second node. The second transistor, which turns on in response to a gate-on voltage applied to the gate line, electrically connects the data line to the second node. A third transistor, which turns on in response to the gate on-voltage of the gate signal to electrically connect the first node to the reference voltage line, and The cathode electrode of the first light-emitting element and the cathode electrode of the second light-emitting element are connected to the first node. A first power supply line, to which the first AC voltage is applied, is connected to the anode electrode of the first light-emitting element. A second power supply line, to which the second AC voltage is applied, is connected to the anode electrode of the second light-emitting element, and A third power line with a pixel ground voltage applied is connected to the third node.

7. The display panel of claim 6, wherein the first transistor includes a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to the third node. The second transistor includes a first electrode connected to the data line, a gate electrode connected to the gate line, and a second electrode connected to the second node. The third transistor includes a first electrode connected to the first node, a gate electrode connected to the gate line, and a second electrode connected to the reference voltage line. The data voltage or black / grayscale voltage of the pixel data is applied to the data line.

8. The display panel according to claim 6, wherein the pixel ground voltage has the same voltage level as the second voltage.

9. The display panel according to claim 1, wherein the sub-pixel further comprises: The capacitor connected between the second node and the third node The second transistor, which turns on in response to a gate-on voltage applied to the gate line, electrically connects the data line to the second node. The third transistor, which is turned on in response to the gate on-voltage of the gate signal to electrically connect the third node to the reference voltage line, and The anode electrode of the first light-emitting element and the anode electrode of the second light-emitting element are connected to the third node. The first power line, to which the pixel driving voltage is applied, is connected to the first node. A second power supply line, to which the first AC voltage is applied, is connected to the cathode electrode of the first light-emitting element, and A third power supply line, to which the second AC voltage is applied, is connected to the cathode electrode of the second light-emitting element.

10. The display panel of claim 9, wherein the first transistor includes a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to the third node. The second transistor includes a first electrode connected to the data line, a gate electrode connected to the gate line, and a second electrode connected to the second node. The third transistor includes a first electrode connected to the third node, a gate electrode connected to the gate line, and a second electrode connected to the reference voltage line. The data voltage or black / grayscale voltage of the pixel data is applied to the data line.

11. The display panel of claim 9, wherein the pixel driving voltage has the same voltage level as the first voltage.

12. The display panel according to any one of claims 1-11, wherein the first light-emitting element emits light in a first viewing angle mode, and The second light-emitting element emits light in a second viewing mode, which has a different viewing angle than the first viewing mode.

13. A display device, comprising: The display panel includes multiple data lines, multiple gate lines, multiple power lines, and multiple sub-pixels, with each sub-pixel electrically connected to the data lines, the gate lines, and the power lines. A data driver electrically connected to the data line; as well as The gate driver is electrically connected to the gate line. Each of the sub-pixels includes: First light-emitting element, The second light-emitting element, and A first transistor connected to the first light-emitting element and the second light-emitting element, and The first AC voltage applied to one of the anode and cathode electrodes of the first light-emitting element changes periodically between a first voltage and a second voltage. The second AC voltage applied to one of the anode and cathode electrodes of the second light-emitting element changes periodically between the first voltage and the second voltage, and The second voltage is a voltage lower than the first voltage.

14. The display device according to claim 13, wherein the sub-pixel further comprises: A capacitor connected between the first node and the second node. The second transistor, which turns on in response to a gate-on voltage applied to the gate line, electrically connects the data line to the second node. A third transistor, which turns on in response to the gate on-voltage of the gate signal to electrically connect the first node to the reference voltage line, and The cathode electrode of the first light-emitting element and the cathode electrode of the second light-emitting element are connected to the first node. A first power supply line, to which the first AC voltage is applied, is connected to the anode electrode of the first light-emitting element. A second power supply line, to which the second AC voltage is applied, is connected to the anode electrode of the second light-emitting element, and A third power line with a pixel ground voltage applied is connected to the third node.

15. The display device of claim 14, wherein the first transistor includes a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to the third node. The second transistor includes a first electrode connected to the data line, a gate electrode connected to the gate line, and a second electrode connected to the second node. The third transistor includes a first electrode connected to the first node, a gate electrode connected to the gate line, and a second electrode connected to the reference voltage line. The data voltage or black / grayscale voltage of the pixel data is applied to the data line. The pixel ground voltage has the same voltage level as the second voltage. The first light-emitting element emits light in the first viewing angle mode, and The second light-emitting element emits light in a second viewing mode, which has a different viewing angle than the first viewing mode.

16. The display device of claim 13, wherein the sub-pixel further comprises: The capacitor connected between the second node and the third node The second transistor, which turns on in response to a gate-on voltage applied to the gate line, electrically connects the data line to the second node. The third transistor, which is turned on in response to the gate on-voltage of the gate signal to electrically connect the third node to the reference voltage line, and The anode electrode of the first light-emitting element and the anode electrode of the second light-emitting element are connected to the third node. The first power line, to which the pixel driving voltage is applied, is connected to the first node. A second power supply line, to which the first AC voltage is applied, is connected to the cathode electrode of the first light-emitting element, and A third power supply line, to which the second AC voltage is applied, is connected to the cathode electrode of the second light-emitting element.

17. The display device of claim 16, wherein the first transistor includes a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to the third node. The second transistor includes a first electrode connected to the data line, a gate electrode connected to the gate line, and a second electrode connected to the second node. The third transistor includes a first electrode connected to the third node, a gate electrode connected to the gate line, and a second electrode connected to the reference voltage line. The data voltage or black / grayscale voltage of the pixel data is applied to the data line. The pixel driving voltage has the same voltage level as the first voltage. The first light-emitting element emits light in the first viewing angle mode, and The second light-emitting element emits light in a second viewing mode, which has a different viewing angle than the first viewing mode.

18. The display device according to claim 13, further comprising: A timing controller configured to send pixel data of the input video to the data driver and control the operating timing of the data driver and the gate driver. The timing controller divides a frame period into at least a first subframe period, a second subframe period, a third subframe period, and a fourth subframe period.

19. The display device of claim 13, wherein a data voltage or black grayscale voltage of the first pixel data is applied to the data line during the first subframe period. During the second subframe period, the black grayscale voltage is applied to the data line. During the third subframe period, the data voltage of the second pixel data or the black grayscale voltage is applied to the data line. The black grayscale voltage is applied to the data line during the fourth subframe period. The first alternating voltage is applied to the anode electrode of the first light-emitting element. The second AC voltage is applied to the anode electrode of the second light-emitting element. The pixel ground voltage, set as the second voltage, is applied to the cathode electrode of the first light-emitting element and the cathode electrode of the second light-emitting element. During the first subframe period and the second subframe period, the first AC voltage is the first voltage, and the second AC voltage is the second voltage, and During the third subframe period and the fourth subframe period, the first AC voltage is the second voltage, and the second AC voltage is the first voltage.

20. The display device of claim 13, wherein during the first subframe period, a data voltage or black grayscale voltage of the first pixel data is applied to the data line. During the second subframe period, the black grayscale voltage is applied to the data line. During the third subframe period, the data voltage or black-grayscale voltage of the second pixel data is applied to the data line. The black grayscale voltage is applied to the data line during the fourth subframe period. A pixel driving voltage, set to the first voltage, is applied to the anode electrode of the first light-emitting element and the anode electrode of the second light-emitting element. The first alternating voltage is applied to the cathode electrode of the first light-emitting element. The second AC voltage is applied to the cathode electrode of the second light-emitting element. During the first subframe period and the second subframe period, the first AC voltage is the second voltage, and the second AC voltage is the first voltage. During the third subframe period and the fourth subframe period, the first AC voltage is the first voltage, and the second AC voltage is the second voltage.

21. The display device according to claim 13, wherein the display panel further comprises: A first switching element is configured to select one of the first voltage and the second voltage and supply the selected voltage to the first light-emitting element; as well as A second switching element is configured to select one of the first voltage and the second voltage and supply the selected voltage to the second light-emitting element.

Images