Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and can avoid short circuit between a cathode and a signal line in a lower frame. The display panel comprises a display area and a first sub-non-display area. A substrate; the first metal layer comprises a first signal line located in the first non-display sub-area; the first film layer is located on the side, away from the substrate, of the first metal layer, and the first film layer is overlapped with the display area and the first sub-non-display area; the cathode is positioned on one side, far away from the substrate, of the first film layer and is overlapped with the display area and the first sub non-display area; the first retaining wall is at least located in the first sub-non-display area; the first sub-non-display area comprises a first area and a second area, and the display area, the first area, the second area and the first retaining wall are arranged in the first direction; the second area comprises a first sub-area, the first sub-area comprises a first signal line, the first film layer is overlapped with the first area and the first sub-area, in the first sub-area, the first film layer is overlapped with the first signal line, and the film thickness of the first film layer in the first sub-area is smaller than that of the first film layer in the first area.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In a display panel, the cathode is a key electrode structure for light-emitting devices, and its structural reliability greatly affects the display effect of the display panel.

[0003] Currently, in order to ensure the uniformity of light emission in the display area, the cathode usually needs to be extended to the outer edge of the display area. However, this can lead to a short circuit risk between the cathode and some signal lines inside the lower edge, which in turn affects the panel performance. Summary of the Invention

[0004] This invention provides a display panel and a display device to prevent short circuits between the cathode and the signal lines within the lower bezel.

[0005] In a first aspect, embodiments of the present invention provide a display panel, comprising: Display area and non-display area, wherein the non-display area includes a first sub-non-display area, the first sub-non-display area being located on one side of the display area in a first direction; Substrate; A first metal layer located on one side of the substrate, the first metal layer including a first signal line, the first signal line being located in the first sub-non-display area and transmitting a first signal; The first film layer located on the side of the first metal layer away from the substrate overlaps with the display area and the first sub-non-display area in a direction perpendicular to the plane of the substrate. A cathode located on the side of the first film layer away from the substrate transmits a second signal, which is different from the first signal. In a direction perpendicular to the plane of the substrate, the cathode overlaps with the display area and the first sub-non-display area. At least the first retaining wall located in the first sub-non-display area; The first sub-non-display area includes a first area and a second area, and the display area, the first area, the second area and the first barrier are arranged sequentially along the first direction; The second region includes a first sub-region, the first sub-region includes the first signal line, and in a direction perpendicular to the plane of the substrate, the first film layer overlaps with the first region and the first sub-region. In the first sub-region, the first film layer overlaps with at least the first signal line, and the film thickness of the first film layer in the first sub-region is less than the film thickness of the first film layer in the first region.

[0006] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the aforementioned display panel.

[0007] The technical solution provided by the embodiments of the present invention has the following beneficial effects: In this embodiment of the invention, the first non-display area includes a first area and a second area, with the second area located on the side closer to the first barrier wall. One side of the first signal line is connected to the display function trace in the display area, and the other side extends from at least the first area and the second area to the side of the first barrier wall away from the display area and is connected to a pin. The second area includes a first sub-area, which is the region within the second area where the first signal line is located. In this embodiment of the invention, the first film layer adjacent to the first signal line is located in the first region and the first sub-region. In the first sub-region, the first film layer overlaps with the first signal line, thereby covering the first signal line within the first sub-region and preventing this portion of the first signal line from being exposed. Thus, even if the distance between the boundary of the cathode film deposition area and the second region is compressed due to the narrowing of the bezel, causing the cathode vapor deposition material to extend and overlap with the first signal line, the first film layer can still be used to prevent a short circuit between the cathode and the first signal line. This effectively improves the performance and yield of the display panel, especially the performance and yield of narrow bezel display panels.

[0008] Furthermore, in this embodiment of the invention, the thickness of the first film layer in the first sub-region is set to be less than the thickness of the first film layer in the first region. That is, this portion of the first film layer in the first sub-region is thinned to have only a small thickness. Consequently, there is still a significant step difference between the film layer structure in the first sub-region and the film layer structure in the first region, as well as between the film layer structure in the first sub-region and the first barrier. This significant step difference allows the pit structure formed in the second region to have sufficient depth, thereby effectively suppressing the flow of organic encapsulation material during the encapsulation layer process. Specifically, the display panel also includes an encapsulation layer located on the side of the cathode away from the substrate. The encapsulation layer includes a stacked first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. During the organic encapsulation layer process, the organic encapsulation material fills the pit structure in the second region to prevent overflow.

[0009] In other words, in this embodiment of the invention, the design based on the first film layer can avoid the short circuit problem between the cathode and the first signal line. Therefore, the boundary of the cathode film-forming area is no longer limited by the risk of a short circuit between the cathode and the first signal line: the distance between the boundary of the cathode film-forming area and the display area can be further increased, allowing the cathode film-forming area to extend further out of the display area, thereby optimizing the film-forming effect of the cathode. Furthermore, the design of the bottom bezel width is also no longer limited by the risk of a short circuit between the cathode and the first signal line: the distance between the cathode film-forming area and the second area can be reduced, for example, to below 90 μm. In fact, there can be overlap between the cathode film-forming area and the second area, thus the bottom bezel can be further narrowed, for example, to below 0.9 mm, which helps to achieve an ultra-narrow bezel. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a display panel in related technologies; Figure 2 for Figure 1 A sectional view along the A1-A2 direction; Figure 3 This is a schematic diagram of a display panel provided in an embodiment of the present invention; Figure 4 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 5 This is another schematic diagram of the display panel provided in an embodiment of the present invention; Figure 6 for Figure 5 A sectional view along the B1-B2 direction; Figure 7 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 8 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 9 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 10 for Figure 9 A sectional view along the C1-C2 direction; Figure 11 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 12 for Figure 11 A sectional view along the D1-D2 direction; Figure 13 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 14 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 15 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 16 for Figure 14 A sectional view along the E1-E2 direction; Figure 17 for Figure 14 A sectional view along the F1-F2 direction; Figure 18 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 19 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 20 This is another schematic diagram of a display panel provided in an embodiment of the present invention; Figure 21 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0012] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0013] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0014] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0015] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0016] Before describing the technical solutions provided by the embodiments of the present invention, the present invention first explains the problems existing in the related technologies.

[0017] Figure 1 This is a schematic diagram of a display panel in related technologies. Figure 2 for Figure 1 A sectional view along the A1-A2 direction, such as Figure 1 and Figure 2 As shown, the display panel includes a display area 101 and a lower border area 102.

[0018] The display panel also includes a substrate 103, a first metal layer 104, a first film layer 105 located on the side of the first metal layer 104 away from the substrate 103, a cathode 106 located on the side of the first film layer 105 away from the substrate 103, and an encapsulation layer 107 located on the side of the cathode 106 away from the substrate 103.

[0019] The first metal layer 104 includes a first bus 108, which is located at least in the lower border area 102. The first bus 108 is electrically connected to the display function traces in the display area 101 and is used to transmit the required signals to these display function traces. The signals transmitted by the first bus 108 are different from the cathode signals.

[0020] The encapsulation layer 107 includes a first inorganic encapsulation layer 109, an organic encapsulation layer 110, and a second inorganic encapsulation layer 111 stacked together.

[0021] The display panel also includes a first barrier 112 and a second barrier 113, the first barrier 112 and the second barrier 113 being located at least in the lower border area 102, and the first barrier 112 being located between the display area 101 and the second barrier 113.

[0022] The lower frame area 102 includes a clearance area 114, which is located between the display area 101 and the first barrier 112. The first film layer 105 is removed within the clearance area 114, thereby utilizing the film layer step difference to form the first barrier 112 and to form a recessed structure within the clearance area 114. This recessed structure is used to suppress the flow of organic encapsulation material during the process of organic encapsulation layer 110, preventing organic encapsulation material overflow.

[0023] In the cathode manufacturing process, considering issues such as the accuracy of incoming materials and shading during the evaporation process, the actual coverage position of the cathode may have a certain deviation. Therefore, the cathode film formation area is generally designed to extend outward from the display area 101 so that the final cathode can cover each pixel area.

[0024] Currently, at the lower frame area 102, the cathode film formation area needs to extend at least 90μm beyond the display area. That is, the distance between the boundary of the cathode film formation area and the display area 101 needs to be designed to be greater than or equal to 90μm. Correspondingly, in the structure, this distance can also be understood as the distance X between the edge of the cathode 106 and the display area 101.

[0025] However, with the development of narrow bezel technology, the width of the bottom bezel of the display panel is gradually decreasing. While ensuring a safe distance between the boundary of the cathode film formation area and the display area 101, the distance between the cathode film formation area and the clearance area 114 will be compressed.

[0026] Table 1 illustrates various dimensions for the seven products A through G. Based on Table 1, it can be seen that in product F, when the width of the lower bezel area 102 is 0.9mm, after ensuring that the distance between the boundary of the cathode film-forming area and the display area 101 is greater than or equal to 90μm, the distance between the cathode film-forming area and the clearance area 114 will be reduced to less than or equal to 70μm. In the structural context, this distance can also be understood as the distance W between the cathode 106 and the clearance area 114. When the distance between the cathode film-forming area and the clearance area is less than or equal to 90μm, the cathode vapor-deposited material is prone to extending into the clearance area, causing a short circuit between the cathode 106 and the exposed first bus 108, leading to burns and abnormal display issues.

[0027] Table 1 In response, embodiments of the present invention provide a technical solution that can effectively improve the above-mentioned problems.

[0028] This invention provides a display panel. Figure 3 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 4 This is another schematic diagram of the display panel provided in an embodiment of the present invention. Figure 5 This is another schematic diagram of the display panel provided in an embodiment of the present invention. Figure 6 for Figure 5 A cross-sectional view along the B1-B2 direction, such as... Figures 3-6 As shown, the display panel can be an organic light-emitting diode (OLED) display panel, such as an active matrix organic light-emitting diode (AMOLED) display panel.

[0029] like Figures 3-6As shown, the display panel includes a display area 1 and a non-display area 2. The non-display area 2 includes a first sub-non-display area 3, which is located on one side of the display area 1 in the first direction x and is the lower border area.

[0030] The display panel also includes a substrate 4 and a first metal layer 5 located on one side of the substrate 4. The first metal layer 5 includes a first signal line 6, which is located in the first sub-non-display area 3 and transmits a first signal. The first signal line 6 can be electrically connected to the display function traces 7 in the display area 1, for example, to the power line, for transmitting the power signal pvdd output by the pin to the power line.

[0031] The display panel also includes a first film layer 8, which is located on the side of the first metal layer 5 away from the substrate 4 and is in contact with the first metal layer 5. In a direction perpendicular to the plane of the substrate 4, the first film layer 8 overlaps with the display area 1 and the first sub-non-display area 3.

[0032] The display panel also includes a cathode 9, which is located on the side of the first film layer 8 away from the substrate 4. The cathode 9 transmits a second signal, which is a cathode signal pvee, and the second signal is different from the first signal. In a direction perpendicular to the plane of the substrate 4, the cathode 9 overlaps with the display area 1 and the first sub-non-display area 3.

[0033] The display panel also includes a first barrier 10, which is located at least in the first sub-non-display area 3.

[0034] The first non-display area 3 includes a first area 11 and a second area 12. Along the first direction x, the display area 1, the first area 11, the second area 12 and the first barrier wall 10 are arranged in sequence.

[0035] The second region 12 includes a first sub-region 13, which includes a first signal line 6. That is, the first sub-region 13 is the area in the second region 12 where the first signal line 6 is located. In a direction perpendicular to the plane of the substrate 4, the first film layer 8 overlaps with the first region 11 and the first sub-region 13. In the first sub-region 13, the first film layer 8 overlaps at least with the first signal line 6; for example, the first film layer 9 covers the first signal line 6. Furthermore, the film thickness d1 of the first film layer 8 in the first sub-region 13 is less than the film thickness d2 of the first film layer 8 in the first region 11. It should be noted that the film thickness described in this embodiment refers to the thickness of the film layer in a direction perpendicular to the plane of the substrate 4.

[0036] In this embodiment of the invention, the first non-display area 3 includes a first area 11 and a second area 12, with the second area 12 located between the first area 11 and the first barrier wall 10. A first signal line 6 is connected to the display function trace 7 in the display area 1 on the side closest to the display area 1, and extends from at least the first area 11 and the second area 12 to the side of the first barrier wall 10 away from the display area 1, where it is connected to a pin. The second area 12 includes a first sub-area 13, and the first signal line 6 extends within the second area 12 of the first sub-area 13. In this embodiment of the invention, the first film layer 8 adjacent to the first signal line 6 is located in the first region 11 and the first sub-region 13. In the first sub-region 13, the first film layer 8 overlaps with the first signal line 6, thereby covering the first signal line 6 within the first sub-region 13 and preventing this part of the first signal line 6 from being exposed. In this way, even if the distance between the boundary of the cathode film-forming area and the second region 12 is compressed due to the narrowing of the bezel, causing the vapor-deposited material of the cathode 9 to extend to overlap with the first signal line 6, the first film layer 8 can still be used to prevent short circuits between the cathode 9 and the first signal line 6, thereby effectively improving the performance and yield of the display panel, especially the performance and yield of narrow bezel display panels.

[0037] Furthermore, in this embodiment of the invention, the thickness of the first film layer 8 in the first sub-region 13 is set to be less than the thickness of the first film layer 8 in the first region 11. That is, this portion of the first film layer 8 in the first sub-region 13 is thinned to have only a small thickness. Furthermore, there is still a significant step difference between the film structure in the first sub-region 13 and the film structure in the first region 11, and between the film structure in the first sub-region 13 and the first barrier 10. This significant step difference allows the pit structure formed in the first sub-region 13 to have sufficient depth, thereby enabling better utilization of the pit structure to effectively suppress the flow of organic encapsulation material during the encapsulation layer process. Specifically, the display panel also includes an encapsulation layer 14, located on the side of the cathode 9 away from the substrate 4. The encapsulation layer 14 includes a stacked first inorganic encapsulation layer 15, an organic encapsulation layer 16, and a second inorganic encapsulation layer 17. During the process of the organic encapsulation layer 16, the organic encapsulation material fills the pit structure in the second region 12 to prevent overflow.

[0038] In other words, in this embodiment of the invention, the design based on the first film layer 8 can avoid the short circuit problem between the cathode 9 and the first signal line 6. Therefore, the boundary of the cathode film-forming area is no longer limited by the short circuit risk between the cathode 9 and the first signal line 6. The distance between the boundary of the cathode film-forming area and the display area 1 can be further increased, allowing the cathode film-forming area to extend further out of the display area 1, thereby optimizing the film-forming effect of the cathode 9. Furthermore, the design of the bottom bezel width is also no longer limited by the short circuit risk between the cathode 9 and the first signal line 6. The distance between the cathode film-forming area and the second area 12 can be reduced, for example, to below 90 μm. In fact, there can be overlap between the cathode film-forming area and the second area 12. Therefore, the bottom bezel can be further narrowed, for example, to below 0.9 mm, thereby helping to achieve an ultra-narrow bezel.

[0039] In one feasible implementation, see Figure 6 The thickness d1 of the first film layer 8 in the first sub-region 13 is greater than or equal to 0.6 μm and less than or equal to 1.1 μm.

[0040] The first film layer 8 in the first sub-region 13 has a minimum thickness of 0.6 μm. This design prevents the first film layer 8 from being too thin, allowing it to provide more reliable insulation. For example, this portion of the first film layer 8 can have sufficient thickness to cover the step at the edge of the first signal line 6, further reducing the risk of short circuit between the cathode 9 and the first signal line 6. The first film layer 8 in the first sub-region 13 has a maximum thickness of 1.1 μm. This design further prevents the first film layer 8 from being too thick, which would increase the film height in the first sub-region 13 excessively. This ensures that the pit structure in the second region 12 has sufficient depth to suppress the flow of organic encapsulation material.

[0041] In one feasible implementation, see Figure 6 The first membrane layer 8 includes at least two sublayers 18, the first subregion 13 includes at least one sublayer 18, and the number of sublayers 18 included in the first subregion 13 is less than the number of sublayers 18 included in the first region 11.

[0042] That is, in the first sub-region 13, some sub-layers 18 in the first film layer 8 are removed. After the removal of some sub-layers 18, the thinning of the first film layer 8 in the first sub-region 13 is relatively large, thus making the first sub-region 13 and the surrounding area form a larger step difference.

[0043] In one feasible implementation, Figure 7 This is another schematic diagram of a display panel provided in an embodiment of the present invention. Figure 8 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 7 and Figure 8As shown, at least two sub-layers 18 in the first film layer 8 include a planarization layer 19 and a pixel definition layer 20 located on the side of the planarization layer 19 away from the substrate 4.

[0044] In a specific panel structure, the display panel includes a buffer layer 21, a semiconductor layer 22, a first insulating layer 23, a gate metal layer 24, a second insulating layer 25, an electrode metal layer 26, a third insulating layer 27, a source / drain metal layer 28, a fourth insulating layer 29, a first metal layer 5, and a planarization layer 19 stacked along a direction away from the substrate 4.

[0045] The semiconductor layer 22 includes the active layer p of the transistor 31, the gate metal layer 24 includes the gate g of the transistor 31 and the first electrode c1 of the capacitor 32, the electrode metal layer 26 includes the second electrode c2 of the capacitor 32, and the first source / drain metal layer 28 includes the connection electrode 33 connected to the active layer of the transistor 31.

[0046] The display panel also includes an anode 34 and a light-emitting layer 35. A pixel definition layer 20 is located on the side of the anode 34 away from the substrate 4. The pixel definition layer includes an opening. The anode 34 is located on the side of the planarization layer 19 away from the substrate 4 and overlaps with the opening at least in a direction perpendicular to the plane of the substrate 4. The light-emitting layer 35 is located within the opening.

[0047] The first region 11 includes a flattening layer 19 and a pixel definition layer 20, and the first sub-region 13 includes either the flattening layer 19 or the pixel definition layer 20. That is, one of the flattening layer 19 and the pixel definition layer 20 is removed in the first sub-region 13.

[0048] Both the planarization layer 19 and the pixel definition layer 20 are organic film layers. Organic film layers are usually quite thick. Removing one of the planarization layer 19 and the pixel definition layer 20 from the first sub-region 13 can ensure that the first sub-region 13 forms a large step difference with the surrounding area, thereby ensuring that the pit structure has sufficient depth.

[0049] In one feasible implementation, see Figure 7 The first sub-region 13 includes a planarization layer 19 but does not include a pixel definition layer 20. The planarization layer 19 is located below the pixel definition layer 20. When the planarization layer 19 is located in both the first region 11 and the first sub-region 13, the film layer flatness in both regions is better.

[0050] Alternatively, in another feasible implementation, see [link to relevant documentation]. Figure 8 The first sub-region 13 includes the pixel definition layer 20 but does not include the flattening layer 19.

[0051] In one structure, the first barrier 10 is formed by stacking the film material of the pixel definition layer 20 and the film material of the support layer. The support layer is used to form a support structure, which is used to support the mask during the fabrication process of the light-emitting layer 35. In one fabrication process, the pixel definition layer 20 and the support layer are simultaneously patterned in the same halftone mask process. That is, after forming the entire pixel definition layer 20 and the entire support layer, the two film layers are patterned simultaneously using the same patterning process. The pixel definition layer 20 in the first sub-region 13 can be implemented based on this fabrication process. After processing based on this process, the support layer in the first sub-region 13 is removed, and only the material of the pixel definition layer 20 is retained.

[0052] In one feasible implementation, see Figure 7 and Figure 8 In at least one sublayer 18, the sublayer 18 is a single-layer film structure and is located in the first region 11 and the first sub-region 13. Furthermore, the film thickness of the at least one sublayer 18 in the first sub-region 13 is less than the film thickness of the sublayer 18 in the first region 11. This difference in film thickness can be specifically achieved by halftone lithography.

[0053] For example, see Figure 7 When the first sub-region 13 includes the planarization layer 19 but does not include the pixel definition layer 20, the film thickness of the planarization layer 19 in the first sub-region 13 is less than the film thickness of the planarization layer 19 in the first region 11. For example, the conventional thickness of the planarization layer 19 can be around 2 μm, and in this embodiment of the invention, the planarization layer 19 in the first sub-region 13 can be further thinned to greater than or equal to 0.6 μm and less than or equal to 1.1 μm.

[0054] See Figure 8 When the first sub-region 13 includes the pixel definition layer 20 but does not include the planarization layer 19, the film thickness of the pixel definition layer 20 in the first sub-region 13 is less than the film thickness of the pixel definition layer 20 in the first region 11. For example, the conventional total thickness of the pixel definition layer 20 and the support layer is about 2.8 μm. After patterning, the first sub-region 13 only includes the pixel definition layer 20, and the thickness of the pixel definition layer 20 in the first sub-region 13 is reduced to greater than or equal to 0.6 μm and less than or equal to 1.1 μm, which is less than the original thickness of the pixel definition layer 20.

[0055] By reducing the number of sublayers in the first sub-region 13, the thickness of the sublayer 18 in the first sub-region 13 can be further reduced, which can further increase the step difference between the first sub-region 13 and the surrounding area, thereby increasing the depth of the pit structure.

[0056] In one feasible implementation, see Figure 7 and Figure 8The fourth insulating layer 29 can also be removed within the first sub-region 13, thereby allowing the first signal line 6 within the first sub-region 13 to have a larger film thickness when forming the first signal line 6, thus reducing the load on the first signal line 6 and optimizing signal transmission.

[0057] In one feasible implementation, Figure 9 This is another schematic diagram of a display panel provided in an embodiment of the present invention. Figure 10 for Figure 9 A sectional view along the C1-C2 direction, such as Figure 9 and Figure 10 As shown, the display panel also includes a second barrier 36, which is located on the side of the first barrier 10 away from the display area 1.

[0058] The first sub-non-display area 3 also includes a third area 37, which is located between the first barrier 10 and the second barrier 36. The third area 37 includes a second sub-area 38, which includes a first signal line 6. That is, the second sub-area 38 is the area in the third area 37 where the first signal line 6 is arranged. In a direction perpendicular to the plane of the substrate 4, the first film layer 8 also overlaps with the first signal line 6 in the second sub-area 38, and the film thickness d3 of the first film layer 8 in the second sub-area 38 is less than the film thickness d2 of the first film layer 8 in the first area 11. For example, the film thickness d3 of the first film layer 8 in the second sub-area 38 is equal to the film thickness d1 of the first film layer 8 in the first sub-area 13.

[0059] In related technologies, see Figure 1 and Figure 2 During the continuous compression of the lower frame area 102, the cathode evaporation material may also short-circuit with the first signal line 6 exposed between the first barrier wall 112 and the second barrier wall 113.

[0060] Therefore, in this embodiment of the invention, the first film layer 8 is further configured to overlap with the second sub-region 38, thereby covering the first signal line 6 at that location using the second sub-region 38 to prevent it from short-circuiting with the cathode 9. Furthermore, the thickness of the first film layer 8 in the second sub-region 38 is less than the thickness of the first film layer 8 in the first region 11, resulting in a significant step difference between the film structure in the second sub-region 38 and the first barrier wall 10, and between the film structure in the second sub-region 38 and the second barrier wall 36. This creates a deeper pit structure in the second sub-region 38, further restricting the flow of the organic encapsulation material and preventing it from flowing outside the second barrier wall 36 and affecting the encapsulation effect.

[0061] Furthermore, see again Figure 9 and Figure 10The first sub-display area 3 also includes a fourth area 39, which is located on the side of the second barrier 36 away from the first barrier 10. In a direction perpendicular to the plane of the substrate 4, the first film layer 8 overlaps with the second barrier 36 but does not overlap with the fourth area 39.

[0062] That is, the first membrane layer 8 extends to the bottom of the second barrier wall 36 and stops, and does not continue to extend outward. This can prevent the sidewall of the first membrane layer 8 from being exposed by the second inorganic encapsulation layer 17 and providing a path for water and oxygen to penetrate, thus ensuring a better encapsulation effect.

[0063] In one feasible implementation, Figure 11 This is another schematic diagram of a display panel provided in an embodiment of the present invention. Figure 12 for Figure 11 A sectional view along the D1-D2 direction, such as Figure 11 and Figure 12 As shown, the first metal layer 5 also includes a second signal line 40, which is located at least in the first sub-display area 3 and is electrically connected to the cathode 9.

[0064] The second region 12 also includes a third sub-region 41, which includes the second signal line 40. It can also be understood as the region in the second region 12 where the second signal line 40 is arranged. In the direction perpendicular to the plane of the substrate 4, the first film layer 8 does not overlap with the third sub-region 41, while the cathode 9 overlaps with the third sub-region 41 and contacts the second signal line 40 in the third sub-region 41.

[0065] In this structure, the cathode 9 is connected to the second region 12. The first sub-region 13 of the second region 12 contains the first signal line 6, but because the first signal line 6 is covered by the first film layer 8, even if the cathode 9 overlaps with the first signal line 6, a short circuit will not occur. The third sub-region 41 of the second region 12 contains the second signal line 40. Therefore, the first film layer 8 in the third sub-region 41 can be removed, allowing the cathode 9 to directly contact and connect with the second signal line 40 in this area, increasing the connection area, reducing contact resistance, and improving connection reliability.

[0066] In one feasible implementation, see Figure 3 The non-display area 2 also includes two second sub-non-display areas 42, which are located on opposite sides of the display area 1 in the second direction y, and the second direction y intersects with the first direction x.

[0067] Figure 13 This is another schematic diagram of a display panel provided in an embodiment of the present invention. Figure 14 This is another schematic diagram of a display panel provided in an embodiment of the present invention. Figure 15 This is another schematic diagram of a display panel provided in an embodiment of the present invention. Figure 16 for Figure 14 A sectional view along the E1-E2 direction. Figure 17 for Figure 14 A sectional view along the F1-F2 direction, combined with Figure 3 , Figures 13-16 The first metal layer 5 also includes a second signal line 40, which is located at least in the first sub-display area 3.

[0068] The display panel also includes a second metal layer 43, which is located between the first film layer 8 and the cathode 9. For example, the second metal layer 43 can be the metal layer where the anode 34 is located.

[0069] The second metal layer 43 includes a lap electrode 44, which is located in the non-display area 2 and is electrically connected to the cathode 9 and the second signal line 40, respectively.

[0070] The overlapping electrode 44 includes a first electrode portion 45 and two second electrode portions 46. The two second electrode portions 46 are respectively located in two second sub-non-display areas 42. The first electrode portion 45 is located in the first sub-non-display area 3 and connected between the two second electrode portions 46. That is, the first electrode portion 45 extends laterally through the first sub-non-display area 3.

[0071] In this embodiment of the invention, as described above, the positions in the second region 12 where the first signal line 6 is arranged are all covered with a first film layer 8. Therefore, the two first electrode portions 45 located in the two second sub-non-display regions 42 can be connected by the first electrode portions 45 that span the first sub-non-display regions 3. Even if the first electrode portion 45 overlaps with the first signal line 6, it will not be short-circuited with the first signal line 6.

[0072] The overlapping electrode 44 extends continuously within the first sub-non-display area 3 and the second sub-non-display area 42, enabling the cathode signal to pass through horizontally. Furthermore, in a direction perpendicular to the plane of the substrate 4, the cathode 9 can overlap with the first electrode portion 45, thereby achieving contact connection between the cathode 9 and the first electrode portion 45, increasing the contact area between the cathode 9 and the overlapping electrode 44, and facilitating the transmission of the cathode signal.

[0073] In one feasible implementation, combined with Figures 14-16 The second region 12 also includes a third sub-region 41, which includes a second signal line 40. In the direction perpendicular to the plane of the substrate 4, the first film layer 8 and the third sub-region 41 do not overlap, and the first electrode portion 45 is in contact with the second signal line 40 in the third sub-region 41.

[0074] The second signal line 40 is arranged in the third sub-region 41 of the second region 12. By removing the first film layer 8 in this region, the second signal line 40 can be exposed, thereby allowing the first electrode part 45 and the second signal line 40 to contact and connect, increasing the connection area between the two, which helps to reduce the contact resistance and improve the connection reliability.

[0075] In one feasible implementation, Figure 18 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 18 As shown, the display panel also includes a second barrier 36, which is located on the side of the first barrier 10 away from the display area 1. In a direction perpendicular to the plane of the substrate 4, the edge of the first electrode portion 45 overlaps with the second barrier 36.

[0076] That is, the boundary of the first electrode portion 45 extends below the second barrier wall 36. At this point, the first electrode portion 45 has a larger width, and the overlap area with the second signal line 40 and the cathode 9 can be larger, which can further optimize display uniformity and reduce power consumption. Moreover, the boundary of the first electrode portion 45 does not exceed the second barrier wall 36, which can also avoid affecting the reliability of the package.

[0077] In one feasible implementation, see again Figure 6 The cathode 9 is located on the side of the second region 12 away from the first barrier 10. That is, the edge of the cathode 9 is located on the side of the second region 12 closer to the display area 1. In the direction perpendicular to the plane of the substrate 4, the cathode 9 does not overlap with the second region 12. In this way, the cathode 9 will not fill the pit structure of the second region 12, which helps the pit structure to have a greater depth to suppress the flow of organic encapsulation material.

[0078] Furthermore, the distance W between the cathode 9 and the second region 12 is less than 90 μm.

[0079] As described above, in related technologies, when the distance between the boundary of the cathode film-forming area and the clearance area is less than or equal to 90 μm, the cathode vapor-deposited material is prone to extend into the clearance area, leading to a short circuit between the cathode and the first bus, causing burns and abnormal display issues. Therefore, to avoid short circuits, the distance between the boundary of the cathode film-forming area and the clearance area must be maintained at 90 μm or more in related technologies. However, this contradicts the narrow bezel design, limiting further narrowing of the bezel.

[0080] In this embodiment of the invention, since the first film layer 8 can be used to avoid the short circuit problem between the cathode 9 and the first signal line 6, the distance between the cathode 9 and the second region 12 can be compressed to within 90μm, which helps to match the narrower bezel design.

[0081] It should be noted that the first film layer 8 includes a first portion located in the first region 11 and a second portion located in the second region 12. The thickness of the first portion is greater than that of the second portion, and there is a virtual boundary between these two portions due to the existence of a step difference. The distance between the cathode 9 and the second region 12 can be regarded as the distance between the cathode 9 and this virtual boundary.

[0082] Under one design, see Figure 6 Along the first direction x, the distance between the cathode 9 and the second region 12 is W, the width of the second region 12 is B, the width of the first barrier wall 10 is C, the width of the third region 37 is D, and the width of the second barrier wall 36 is E. The design of W can satisfy W+B+C+D+E≥90μm. For example, under the conditions of B=20μm, 20μm≤C≤30μm, 20μm≤D≤30μm, and 20μm≤E≤30μm, the design of W satisfies the minimum value of W+B+C+D+E as 100μm. This ensures a safe distance between the edge of the cathode 9 and the fourth region 39, preventing the cathode vapor-deposited material from extending to the area outside the second barrier wall 36 and contacting the first signal line 6.

[0083] In one feasible implementation, Figure 19 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 19 As shown, in a direction perpendicular to the plane of the substrate 4, the cathode 9 overlaps with the second region 12 and further overlaps with the first sub-region 13.

[0084] This design can increase the distance between the edge of the cathode 9 and the display area 1. For example, with a certain bezel width, when the cathode 9 overlaps with the second area 12, the distance between the edge of the cathode 9 and the display area 1 can be greater, which can better eliminate the film formation position caused by the precision of incoming materials and the process, thereby optimizing the film formation effect of the cathode 9. Alternatively, this design can achieve a narrower bezel design. For example, under the condition that the distance between the edge of the cathode 9 and the display area 1 is constant, when the cathode 9 overlaps with the second area 12, the width of the bottom bezel can be designed to be smaller.

[0085] In an embodiment of the present invention, Figure 20 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 20 As shown, in order to reduce the load on the first signal line 6 and the second signal line 40, the first signal line 6 can also be electrically connected to the first trace 50, which is located on the side of the first signal line 6 near the substrate 4. The second signal line 40 can also be electrically connected to the second trace 51, which is located on the side of the second signal line 40 near the substrate 4.

[0086] Based on the same inventive concept, embodiments of the present invention also provide a display device, such as... Figure 21 As shown, Figure 21 This is a schematic diagram of a display device provided in an embodiment of the present invention, the display device including the aforementioned display panel 100. Of course, Figure 21 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0087] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Display area and non-display area, wherein the non-display area includes a first sub-non-display area, the first sub-non-display area being located on one side of the display area in a first direction; Substrate; A first metal layer located on one side of the substrate, the first metal layer including a first signal line, the first signal line being located in the first sub-non-display area and transmitting a first signal; The first film layer located on the side of the first metal layer away from the substrate overlaps with the display area and the first sub-non-display area in a direction perpendicular to the plane of the substrate. A cathode located on the side of the first film layer away from the substrate transmits a second signal, which is different from the first signal. In a direction perpendicular to the plane of the substrate, the cathode overlaps with the display area and the first sub-non-display area. At least the first retaining wall located in the first sub-non-display area; The first sub-non-display area includes a first area and a second area, and the display area, the first area, the second area and the first barrier are arranged sequentially along the first direction; The second region includes a first sub-region, the first sub-region includes the first signal line, and in a direction perpendicular to the plane of the substrate, the first film layer overlaps with the first region and the first sub-region. In the first sub-region, the first film layer overlaps with at least the first signal line, and the film thickness of the first film layer in the first sub-region is less than the film thickness of the first film layer in the first region.

2. The display panel according to claim 1, characterized in that, The thickness of the first film layer in the first sub-region is greater than or equal to 0.6 μm and less than or equal to 1.1 μm.

3. The display panel according to claim 1, characterized in that, The first film layer includes at least two sublayers, and the number of sublayers included in the first subregion is less than the number of sublayers included in the first region.

4. The display panel according to claim 3, characterized in that, At least two of the sub-layers include a planarization layer and a pixel definition layer located on the side of the planarization layer away from the substrate; The first region includes the flattening layer and the pixel definition layer, and the first sub-region includes either the flattening layer or the pixel definition layer.

5. The display panel according to claim 3, characterized in that, In at least one of the sublayers, the sublayer is a single-layer membrane structure, and the membrane thickness of the sublayer in the first sub-region is less than the membrane thickness of the sublayer in the first region.

6. The display panel according to claim 1, characterized in that, The display panel further includes a second barrier wall, which is located on the side of the first barrier wall away from the display area. The first sub-non-display area further includes a third area, which is located between the first barrier and the second barrier. The third area includes a second sub-area, which includes the first signal line. In a direction perpendicular to the plane of the substrate, the first film layer also overlaps with the first signal line in the second sub-area. Furthermore, the film thickness of the first film layer in the second sub-area is less than the film thickness of the first film layer in the first area.

7. The display panel according to claim 6, characterized in that, The first sub-non-display area also includes a fourth area, which is located on the side of the second retaining wall away from the first retaining wall; In a direction perpendicular to the plane of the substrate, the first film layer overlaps with the second barrier but does not overlap with the fourth region.

8. The display panel according to claim 1, characterized in that, The first metal layer further includes a second signal line, which is located at least in the first sub-non-display area and is electrically connected to the cathode. The second region further includes a third sub-region, which includes the second signal line. In a direction perpendicular to the plane of the substrate, the first film layer does not overlap with the third sub-region, and the cathode overlaps with the third sub-region and contacts the second signal line in the third sub-region.

9. The display panel according to claim 1, characterized in that, The non-display area further includes two second sub-non-display areas, which are located on opposite sides of the display area in a second direction, and the second direction intersects with the first direction. The first metal layer further includes a second signal line, which is located at least in the first sub-display area; The display panel further includes a second metal layer, which is located between the first film layer and the cathode. The second metal layer includes a lap electrode, which is located in the non-display area and is electrically connected to the cathode and the second signal line, respectively. The overlapping electrode includes a first electrode portion and two second electrode portions. The two second electrode portions are respectively located in two second sub-display areas, and the first electrode portion is located in the first sub-display area and connected between the two second electrode portions.

10. The display panel according to claim 9, characterized in that, The second region further includes a third sub-region, which includes the second signal line. In a direction perpendicular to the plane of the substrate, the first film layer does not overlap with the third sub-region, and the first electrode portion contacts the second signal line in the third sub-region.

11. The display panel according to claim 10, characterized in that, The display panel further includes a second barrier wall, which is located on the side of the first barrier wall away from the display area. In a direction perpendicular to the plane of the substrate, the edge of the first electrode overlaps with the second barrier.

12. The display panel according to claim 1, characterized in that, The cathode is located on the side of the second zone away from the first retaining wall.

13. The display panel according to claim 12, characterized in that, The distance between the cathode and the second region is less than 90 μm.

14. The display panel according to claim 1, characterized in that, In a direction perpendicular to the plane of the substrate, the cathode overlaps with the second region.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 14.

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