Pin-exposed sensing chip packaging structure and method

Abstract

The invention discloses a pin-exposed sensing chip packaging structure and method, and the method comprises the following steps: electroplating a first line at an electrical port of a bare chip, and rearranging the electrical port; electroplating a second circuit on a part of the first circuit, rearranging the electrical property of the first circuit, extending the second circuit into the two cutting channels which are perpendicular to each other, and integrally encapsulating; drilling holes on the back surface of the bare chip and filling an electroplated connecting column to electrically lead the other part of the circuit I to the area of the back surface of the bare chip, electroplating a circuit IV to be electrically connected with the connecting column, extending the circuit IV and the circuit II to the same cutting channel, and integrally encapsulating; according to the invention, filtering in the parallel direction is realized, the signal to noise ratio of an output signal is improved, the detection precision and stability are ensured, and the process is simplified and efficient.

Description

Technical Field

[0001] This invention belongs to the field of sensor chip packaging technology, and particularly relates to a sensor chip packaging structure and method with exposed pins. Background Technology

[0002] A sensing chip is a type of semiconductor device based on the principle of magnetic sensing. It detects physical quantities such as angle, position, and displacement by sensing changes in magnetic fields. The sensing chip has a sensing surface on which Hall elements are arranged. It is a key area specifically used to sense changes in external magnetic fields. In practical applications, the sensing surface of the sensing chip must face the magnetic field source such as a magnet or magnetic encoder. The sensing surface is the surface closest to the magnetic medium being detected. After the sensing chip is mounted, there must be no magnetic metal interference between the sensing surface and the magnetic medium being detected.

[0003] The sensor chip needs to be encapsulated and then mounted on the soldering board in the working area using solder paste and other soldering materials. Solder paste and other soldering materials are magnetic metals. For sensor chips where the sensing surface and the chip's electrical ports are located on the same surface, the sensing surface and the mounting surface need to be distributed on different surfaces of the encapsulation, which increases the difficulty of the process and makes it difficult to guarantee detection accuracy and stability. Summary of the Invention

[0004] To address the problems in the prior art, the present invention provides a pin-exposed sensing chip packaging structure and method.

[0005] To achieve the above objectives, the present invention proposes a method for packaging an exposed pin sensing chip, comprising the following steps: Electrical layout: The electroplating line 1 at the electrical port of the bare die is removed, and the electrical port is rearranged. Front wiring: Electroplating of line 2 on part of line 1, re-layout of the electrical properties of line 1, and extension of line 2 into two mutually perpendicular cut channels, and overall encapsulation. Backside wiring: Drill holes in the backside encapsulant of the bare die and electroplate the connecting posts to fill them. Another part of the line is electrically led to the backside encapsulant area of ​​the bare die, and line four is electroplated and electrically connected to the connecting posts. Line four extends to the same cutting track as line two, and the whole is encapsulated. Cutting and Separation: The package is cut along the cutting track to separate it into package units. Lines 2 and 4 are flush with the package and exposed. The right-angled sides of the package are connected after being cut by two mutually perpendicular cutting tracks to serve as chip mounting pins.

[0006] Furthermore, in the back-side wiring step, the orthographic projections of line two and line four from the front of the die may be the same or different.

[0007] Furthermore, in the front wiring step, line three is electroplated on line two, and line three extends into the same cutting area as lines two and four.

[0008] Furthermore, in the back-side wiring step, line five is electroplated on line four, and line five extends into the same cutting area as lines two, three, and four.

[0009] Furthermore, in the back-side wiring step, the orthographic projections of lines three and five from the front of the die may be the same or different.

[0010] A pin-exposed sensor chip packaging structure includes a package body, wherein the package body encapsulates: The die has electrical ports distributed on its front side. Line 1: Electroplating is applied to the electrical terminals of the bare die to rearrange the electrical properties of the terminals; Line 2: Line 2 is installed on a portion of Line 1, and the electrical properties of Line 1 are rearranged. Line 4 involves electrically connecting another portion of the lines to the back cover area of ​​the bare die and rearranging them. Lines 2 and 4 are flush with and exposed on the same surface of the package, and are connected at right angles on the same package side to serve as chip mounting pins.

[0011] Furthermore, the orthographic projections of line two and line four from the front of the die may be the same or different.

[0012] Furthermore, line three is electroplated on line two. Line three is flush with line two and exposed on the surface of the package. The exposed parts of line three are connected at right angles on the same package.

[0013] Furthermore, line five is electroplated on line four. Line five is flush with and exposed on the surface of the package, just like lines two, three, and four. The exposed parts of line five are connected at right angles on the same package.

[0014] Furthermore, the orthographic projections of lines three and five from the front of the die may be the same or different.

[0015] Beneficial effects of this invention: 1. The wiring is flush with the two adjacent sides of the package and is connected by a right angle. The exposed part becomes the path for mounting pins and solder crawling. Solder will not overflow the surface of the package corresponding to the die sensing surface, avoiding magnetic metal interference. The wiring extends to the dicing channel to be cut into pins, simplifying and improving the efficiency of the process.

[0016] 2. During mounting, the sensing surface of the bare die inside the package is perpendicular to the soldering board, and the chip sensing direction is perpendicular to the plane of the mounting substrate. It is almost impossible to sense interference magnetic fields in the parallel direction, thus achieving parallel direction filtering, improving the signal-to-noise ratio of the output signal, and ensuring detection accuracy and stability. Attached Figure Description

[0017] Figures 1-2This is a cross-sectional view of the electrical layout steps of an embodiment of a pin-exposed sensor chip packaging method of the present invention; Figures 3-6 This is a cross-sectional view of the front wiring steps in an embodiment of a pin-exposed sensor chip packaging method of the present invention. Figures 7-12 This is a cross-sectional view of the back-side wiring steps in an embodiment of a pin-exposed sensor chip packaging method of the present invention; Figure 13 This is a cross-sectional view of the cutting and separating step in an embodiment of a pin-exposed sensor chip packaging method of the present invention; Figure 14 This is a cross-sectional view of a first embodiment of the exposed pin sensor chip packaging structure of the present invention; Figure 15 This is a top perspective view of a first embodiment of a pin-exposed sensor chip packaging structure according to the present invention; Figure 16 This is a cross-sectional view of a second embodiment of the exposed pin sensor chip packaging structure of the present invention.

[0018] In the diagram: 1. Bare die; 2. Circuit 1; 3. Metal pillar; 4. Circuit 2; 5. Connecting pillar; 6. Circuit 4; 7. Circuit 3; 8. Circuit 5; 9. Package. Detailed Implementation

[0019] The present invention will now be described in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout.

[0020] The directional terms used in this invention, such as up, down, left, right, front, back, inside, outside, front, back, side, etc., are merely for reference to the accompanying drawings. The embodiments and directional terms used in the following description with reference to the accompanying drawings are exemplary and are only used to explain this invention, and should not be construed as limiting this invention. Furthermore, the various specific processes and materials provided in this invention are examples that those skilled in the art will recognize for the application of other processes and / or the use of other materials. Example 1

[0021] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an explanation of the pin-exposed sensor chip packaging structure and method proposed in this invention.

[0022] The process specifically includes the following steps: Electrical layout: First, multiple bare dies 1 are mounted on a substrate. Based on the area of ​​the substrate and the product unit layout design, multiple bare dies 1 are evenly placed on the substrate with the front side of the bare die 1 facing up and the back side facing the substrate. Electrical ports are distributed on the front side of the bare die 1.

[0023] The die 1 can be a magnetic induction chip. A magnetic induction chip is a semiconductor device that detects physical quantities such as angle, position, and displacement by sensing changes in the magnetic field based on the principle of magnetic sensing. In this invention, the sensing surface of the die 1 is the front side of the die 1. The core magnetic induction element is integrated on the front side of the die 1. It is a key area specifically used to sense changes in the external magnetic field. The sensing surface is arranged with components such as Hall array, giant magnetoresistive film, and anisotropic magnetoresistive film, which can convert the magnetic field into an electrical signal. In this invention, the sensing surface of the die 1 is also simultaneously provided with an electrical port that is electrically connected to the magnetic induction film. After the front side of the die 1 is mounted, both the electrical port and the sensing surface of the die 1 face upwards.

[0024] After the bare die 1 is mounted using adhesives commonly used in the art, an encapsulation material is used to encapsulate the bare die 1 on the substrate into a single unit (e.g., Figure 1 As shown in the figure, this is the first encapsulation in the entire process. After the encapsulating material is cured, the bare die 1 is completely encapsulated. The encapsulating material is horizontally ground on the top surface of the encapsulation using mechanical grinding until the electrical ports on the front of the bare die 1 are exposed. The electrical ports are flush with and exposed on the top surface of the encapsulation. The ground encapsulating material becomes the first encapsulation layer.

[0025] Then, electroplating of line 2 (e.g., on the exposed electrical ports of the encapsulation layer 1) is performed. Figure 2 As shown), a line 2 is electroplated at each electrical port for electrical traction layout. The line 2 extends on the surface of the encapsulation layer 1 and is electrically connected to the electrical port, thus rearranging the electrical port. The layout of the line 2 electroplated on the electrical port can be different depending on the product structure and the function of the bare die 1. The electroplating settings can be flexible. In this invention, four electrical ports are set on the front side of the bare die 1 as an example. The electrical ports are grouped in pairs. The layout of the line 2 in each group is the same, while the layout of the line 2 between the two groups is different. One group has a small extension range, and the other group has a large extension range.

[0026] Front wiring: The height of the electroplated lines 1 and 2 may be the same or different. After the metal pillars 3 are electroplated on some of the lines 1 and 2, the lines 2 and 4 are electroplated to prevent the lines 2 and 4 from connecting with other lines 1 and 2. In this invention, metal pillars 3 are electroplated on a group of lines 1 and 2 with a small extension range. The metal pillars 3 locally increase the height of the corresponding lines 1 and 2. The total height of the metal pillars 3 and the corresponding lines 1 and 2 is higher than the height of other lines 1 and 2 without metal pillars 3, thus preventing the lines 2 and 4 from connecting with other lines 1 and 2.

[0027] Using encapsulating material, continue encapsulation on top of encapsulation layer one, completely encapsulating metal pillar 3 and line 2. After the encapsulating material cures, mechanically grind the top surface of the encapsulation horizontally until the top surface of metal pillar 3 is exposed (e.g., Figure 3 As shown), the encapsulating material after grinding is the second encapsulation layer. The second encapsulation layer is fused with the first encapsulation layer at the contact point. A second circuit 4 is electroplated on the surface of the second encapsulation layer. The second circuit 4 is electrically connected to the metal pillar 3, and is electrically connected to the first circuit 2 through the metal pillar 3. The electrical properties of the first circuit 2 are then re-extended and re-laid out on the second encapsulation layer (as shown). Figure 4 and Figure 5 As shown, Figure 5 for Figure 4 (A top view, where the shaded area represents the cutting channel region).

[0028] Line 2 4 extends flatly on the surface of the encapsulation layer 2. At least one bare die 1 is mounted on the substrate. Each bare die 1 can undergo the same process flow to obtain the same or different structures. In this invention, the final product units with the same structure are obtained. The bare dies 1 are uniformly mounted and have cutting channels between each other. That is, there are cutting channels on all four sides of the bare die 1, separated by encapsulation material. Only encapsulation material is in the cutting channels. Line 1 2, bare die 1, etc. do not extend into the cutting channels, but one end of line 2 4 is extended into two mutually perpendicular cutting channels to ensure that when the product units are subsequently cut and separated along the cutting channels, the surface of line 2 4 is flush with and exposed on two adjacent sides of the package 9, and connected at the right angle edge common to these two adjacent sides of the package 9. Line 2 4 is electroplated and extends into the cutting channels, and the extension size in the cutting channels is controlled according to the cutting channel size to avoid the line 2 4 in adjacent product units being electroplated and connected to the same cutting channel as a whole, which would increase the difficulty of cutting and separation.

[0029] After the electroplating of line 24 is completed, encapsulating material is used to continue encapsulating on the basis of encapsulation layer 2, completely encapsulating line 24 to obtain encapsulation layer 3 (e.g., Figure 6 As shown in the figure, at this point, the entire structure is encapsulated, and the area where the third encapsulation layer and the second encapsulation layer meet is integrated into one whole.

[0030] Backside Wiring: After the front-side process of die 1 is completed, the entire encapsulation is removed from the substrate, flipped over, and remounted onto the substrate. At this point, the backside of die 1 is flush with and exposed to the surface of encapsulation layer 1 (e.g., Figure 7 As shown), encapsulating material is used to encapsulate the back side of the bare wafer 1 on top of encapsulation layer one, completely encapsulating the back side of the wafer 1 to form encapsulation layer four (as shown). Figure 8 As shown in the figure, the area where the fourth encapsulation layer and the third encapsulation layer meet is fused together.

[0031] The top surface of the encapsulation layer four is level and flat. Vertical holes are drilled into the encapsulation material on this top surface until one end of each line with a large layout extension is exposed (e.g., Figure 9As shown), during the product design phase, the extension layout dimensions of line 12 are set, and the drilling positions are set to prevent drilling deviation from damaging other components. The drilling can be formed using laser drilling methods commonly used in this field.

[0032] Electroplated metal is used to fill the drilled hole, forming a connecting post 5. One end of the connecting post 5 is electroplated and connected to line 2. The other end of the connecting post 5 is electroplated and exposed flush with the top surface of the encapsulation layer (e.g., ...). Figure 10 As shown), the connecting post 5 leads the corresponding line 12 to the encapsulation material area of ​​the encapsulation layer 4 on the back of the bare die 1.

[0033] Electroplated circuit 6 is applied to encapsulation layer 4. Circuit 6 is electroplated and connected to connecting post 5 as a single unit, and extends outwards from the surface of encapsulation layer 4 (e.g., ...). Figure 11 As shown), one end of line 46 extends into two perpendicular cutting channels, just like line 24, and extends into the same cutting channel as line 24. This ensures that when the product units are subsequently cut and separated along the cutting channels, the surface of line 24 is flush with the two adjacent sides of the package 9 and connected at the right-angled edge common to these two adjacent sides of the package 9. Line 46 is electroplated and extends into the cutting channels, and the extension size in the cutting channels is controlled according to the size of the cutting channels to avoid the electroplating connection of line 46 to the same cutting channel in adjacent product units, which would increase the difficulty of cutting and separating.

[0034] After the electroplating of circuit 46 is completed, encapsulating material is used to continue encapsulating on the basis of encapsulation layer 4, completely encapsulating circuit 46 to obtain encapsulation layer 5 (e.g., Figure 12 As shown), at this point, the entire structure is encapsulated, and the area where the encapsulation layer five contacts the encapsulation layer four is fused together as a whole. The surface of the encapsulation layer five is horizontal and flat, resulting in a complete encapsulation.

[0035] Furthermore, the orthographic projections of line 2 4 and line 4 6 from the front of the bare die 1 may be the same or different. In this invention, the orthographic projections of line 2 4 and line 4 6 from the front of the bare die 1 are set to be the same, and the heights of the electroplated line 4 6 and line 2 4 are the same, so as to ensure that the circuit structure on the front and back of the bare die 1 is symmetrical, the stress is uniform, and the structure is more stable. This invention does not impose any restrictions on the height, size, etc. of line 2 4 and line 4.

[0036] Cutting and Separation: Finally, the entire package needs to be cut along the cutting lines to separate it into product units. Each product unit is a complete package 9 (e.g., Figure 13As shown), each package 9 includes a bare die 1, and corresponding line 1 2, metal pillar 3, line 2 4, connecting pillar 5 and line 4 6. Since one end of line 2 4 and line 4 6 extends into the dicing channel, after being cut and separated into product units along the dicing channel, the two surfaces of line 2 4 and line 4 6 in each package 9 are flush with each other and exposed on two adjacent sides of the package 9. They are connected by a right angle on two adjacent sides of the package 9. The exposed surfaces of line 2 4 and line 4 6 can be used as chip mounting pins.

[0037] Furthermore, the exposed lines 2 and 4 serve as the medium for the chip to be mounted onto the working area and are electrically connected to the outside. They are exposed to the outside and are not protected by the package 9, making them susceptible to oxidation and corrosion. Therefore, gold and other protective materials are electroplated on the surface of the exposed lines 2 and 4 to prevent oxidation and corrosion of the lines 2 and 4.

[0038] Line 2 4 and Line 4 6 are located on the front and back sides of the die 1, and one end of each extends into the same dicing channel. The exposed surfaces after dicing serve as mounting pins. Line 2 4 electrically pulls part of the electrical ports of the die 1 to the outside of the package 9, and Line 4 6 electrically pulls the other part of the electrical ports of the die 1 to the outside of the same surface of the package 9. The package 9 exposes the surfaces of Line 2 4 and Line 4 6 at the same time as the mounting surface of the package 9.

[0039] Furthermore, the portions of lines 2 (4) and 4 (6) that are flush with the outer surface of the package 9 after cutting are continuous structures. The portions encapsulated within the package 9 can be electroplated to form a curved structure, increasing the contact area between the encapsulating material and the encapsulating layer, ensuring structural stability after cutting, and reducing the risk of electroplating peeling off.

[0040] When mounting the package 9 (such as in SMT reflow soldering), solder paste is used for mounting. Since the mounting pins are flush with and exposed to the encapsulant, it is difficult to observe and judge the solder joint shape, wetting state, and whether there are defects such as cold solder joints or false solder joints during soldering. In this case, it is necessary to judge the soldering quality by observing the solder creep during soldering. If the solder paste evenly covers the edge of the pins and climbs up the side of the package 9, it indicates that the mounting and soldering are sufficient and the soldering quality is qualified. If the mounting surface is the bottom surface and the surrounding exposed sides are all encapsulant, the solder paste is different from the encapsulant, and it is difficult for the solder paste to climb up the side encapsulant, which also affects the observation of solder creep and causes misjudgment of the soldering quality.

[0041] In this invention, the surfaces of Line 2 (4) and Line 4 (6) are flush with each other and exposed on two adjacent sides of the package 9. These adjacent sides of the package 9 are connected by a right-angled edge. After mounting, the exposed Line 2 (4) and Line 4 (6) become the path for solder crawling, facilitating observation during soldering. Solder crawling occurs along the exposed Line 2 (4) and Line 4 (6), preventing solder from overflowing from the surface of the package 9 corresponding to the sensing surface of the die 1. Within the space facing the sensing surface of the sensing chip, there are no magnetic metal components (while the plated Line 1 (2) and metal pillars (3) within the space facing the sensing surface are made of copper, which is non-magnetic and causes no magnetic interference). Magnetic metals can attract and distort the target magnetic field, leading to magnetic field distortion. This results in the magnetic field signal received by the sensing chip being inconsistent with the actual magnetic field, causing detection errors (such as excessive or insufficient travel measurement, angle detection jumps, etc.). Furthermore, magnetic metal particles can become localized small magnets, interfering with the magnetic field sensing of the Hall element on the sensing surface, leading to increased output noise and decreased stability of the sensing chip. In this invention, the sensing surface is free of magnetic interference, ensuring the chip's detection accuracy and stability.

[0042] The sensing surface of the bare die 1 inside the mounted package 9 is perpendicular to the soldering plate, and the chip sensing direction is perpendicular to the plane of the mounting substrate. For scenarios that require detection of magnetic fields in the vertical direction (such as proximity switches and position sensors), this structure allows the target magnetic field to pass directly perpendicularly through the sensing surface. The angle between the magnetic field lines and the wiring layer is close to 90°. According to the law of electromagnetic induction E=n·Δt / ΔΦ (Φ=B·S·cosθ), cosθ=1 at this time, the magnetic flux Φ reaches its maximum value, the induced electromotive force is strongest, and the chip's sensitivity to the vertical magnetic field is significantly improved. The current on the soldering plate or the electromagnetic radiation from other mounted electronic components generates stray magnetic fields parallel to the mounting substrate. When the stray magnetic field is parallel to the sensing surface and the magnetic field lines pass parallel to the sensing surface, cosθ=0, the magnetic flux approaches zero, and it is almost impossible to sense the parallel interference magnetic field, thus achieving parallel direction filtering and improving the signal-to-noise ratio of the output signal.

[0043] In this invention, the orthographic projections of line 4 and line 6 from the front of the bare die 1 may be the same or different. Since line 4 and line 6 are both made of non-magnetic metals such as copper, the lines with different orthographic projections are electrically pulled and cut into pins, and the heat of the sensing chip can be dissipated through line 4 and line 6. The lines with the same orthographic projection are symmetrical vertically. In addition to the above functions, they also reduce parasitic magnetic fields. The current directions of line 4 and line 6 are opposite and the magnetic field magnitudes are equal. The parasitic magnetic fields generated by them cancel each other out, significantly reducing the electromagnetic interference (EMI) of the package itself, ensuring that the sensing signal only reflects the changes in the external target magnetic field, and suppressing the influence of the package parasitic magnetic field. After mounting, the sensing surface faces other sensing devices, realizing the interactive confirmation of physical parameters, such as the travel test of equipment components, track spacing, and machine tools. By extending the layout of the lines and cutting them into exposed pins, the process is simplified and the cost is reduced.

[0044] The above-described pin-exposed sensor chip packaging method yields a pin-exposed sensor chip packaging structure (such as...). Figure 14 and Figure 15 As shown, Figure 15 (The dashed line in the middle indicates the cross-sectional direction in the cross-sectional view in the attached figure). The structure includes a package 9, which encapsulates: a bare die 1 with electrical ports distributed on the front side; a circuit 1 2 electroplated on the electrical ports of the bare die 1, which rearranges the electrical properties of the electrical ports; a circuit 2 4 disposed on part of the circuit 1 2, which rearranges the electrical properties of the circuit 1 2; and a circuit 4 6 that leads another part of the circuit 1 2 to the back encapsulation area of ​​the bare die 1 and rearranges it. The circuits 2 4 and 4 are flush with the same surface of the package 9 and connected at the right angle of the same package 9 as chip mounting pins. The orthographic projections of the circuits 2 4 and 4 6 from the front side of the bare die 1 are the same or different. Example 2

[0045] In the front wiring step of the above embodiment, after electroplating line 2 4, line 3 7 is electroplated on line 2 4. Line 3 7 extends to the same cutting area as lines 2 4 and 4. Line 3 7 is electroplated on each line 2 4. Then, encapsulating material is used to encapsulate line 2 4 and line 3 7 on the basis of encapsulation layer 2 to obtain encapsulation layer 3. At this time, the whole is encapsulated, and the place where encapsulation layer 3 and encapsulation layer 2 meet is fused into a whole.

[0046] In the back-side wiring step of the above embodiment, after electroplating line 4 6, line 5 8 is electroplated on line 4 6. Line 5 8 extends to the same cutting area as lines 2 4, 3, and 4. Line 5 8 is electroplated on each line 4 6. Then, encapsulating material is used to encapsulate line 5 8 and line 4 6 on the basis of encapsulation layer 4 to obtain encapsulation layer 5. At this time, the whole is encapsulated, and the place where encapsulation layer 5 and encapsulation layer 4 come into contact is fused into a whole.

[0047] Furthermore, the orthographic projections of lines 3.7 and 5.8 from the front of the die 1 may be the same or different. In this invention, the orthographic projections of lines 5.8 and 3.7 from the front of the die 1 are set to be the same, and the heights of the electroplated lines 3.7 and 5.8 are the same to ensure that the circuit structure on the front and back of the die 1 is symmetrical, the stress is uniform, and the structure is more stable. This invention does not limit the height, size, etc. of lines 3.7 and 5. The orthographic projections of lines 3.7 and 5.8 from the front of the die 1 may be the same or different. Since lines 3.7 and 5.8 are both made of non-magnetic metal materials such as copper, lines 3.7 and 5.8 with different orthographic projections will be electrically drawn and cut into pins, and the heat of the sensing chip can be dissipated through lines 2.4, 3.4 and 5. Lines 3.7 and 5.8 with the same orthographic projections are symmetrical from top to bottom. In addition to the above functions, they also have the effect of reducing parasitic magnetic fields and suppressing the influence of parasitic magnetic fields in the packaging.

[0048] Lines 3 (7) and 5 (8) extend into the dicing area in the same way as lines 2 (4) and 4 (6). After dicing, they are exposed on the adjacent sides of the package 9 and connected by the right-angled edge shared by the adjacent sides. The exposed portions of lines 3 (7) and 5 (8) on the mounting surface of the package 9 have the same area as the exposed portions of lines 2 (4) and 4 (6), which increases the mounting pin area, increases mounting stability, reduces the plating height of lines 2 (4) and 4 (6), and avoids the risk of detachment.

[0049] Meanwhile, the dimensions and areas of lines 3 (7) and 5 (8) extending into the cutting channel are the same as those of lines 2 (4) and 4 (6), respectively, to ensure that the exposed areas after cutting are the same. However, the areas of lines 3 (7) and 5 (8) encapsulated in the package 9 are not the same as those of lines 2 (4) and 4 (6). That is, the orthogonal projection areas of lines 3 (7) and 5 (8) from the front of the bare die 1 are smaller than those of the corresponding lines 2 (4) and 4 (6). Lines 3 (7) and 5 (8) can even be set as meandering structures to increase their contact area with the encapsulating material of the encapsulation layer, ensure the stability of the structure after cutting, and reduce the risk of electroplating peeling.

[0050] The above-described pin-exposed sensor chip packaging method yields a pin-exposed sensor chip packaging structure (such as...). Figure 16 As shown), the structure includes a package 9, which encapsulates: a bare die 1 with electrical ports distributed on the front side; a line 2 electroplated on the electrical ports of the bare die 1, which rearranges the electrical connections of the electrical ports; a line 4 disposed on part of the line 2, which rearranges the electrical connections of the line 2; and a line 6 that leads another part of the line 2 to the back encapsulation area of ​​the bare die 1 and rearranges the electrical connections thereto. The lines 2 and 4 are flush with the same surface of the package 9 and connected at the right angle of the same package 9 as chip mounting pins. The projections of the lines 2 and 4 from the front side of the bare die 1 are the same or different.

[0051] Line 3 7 is electroplated on Line 2 4. Line 3 7 is flush with Line 2 4 and exposed on the surface of the package 9. The exposed part of Line 3 7 is connected at the right angle of the same package 9. Line 5 8 is electroplated on Line 4 6. Line 5 8 is flush with Line 2 4, Line 3 4 and Line 4 and exposed on the surface of the package 9. The exposed part of Line 5 8 is connected at the right angle of the same package 9. The orthographic projections of Line 3 7 and Line 5 8 from the front of the die 1 are the same or different.

[0052] All encapsulation steps involved in the process of this invention use molding compounds, specifically epoxy resin, cyanate ester, polyimide, etc., which are low in cost, have good curing performance, and are commonly used encapsulation methods in the field. Encapsulation technology plays an important role in the semiconductor manufacturing field, mainly in protecting the bare die, connecting the whole, supporting the structure, improving reliability, and promoting technological progress. The encapsulation method in this invention is the commonly used molding injection method in the field, but other suitable encapsulation methods are also acceptable. After the encapsulation material is cured, the outer surface of the entire encapsulation structure is flat and smooth.

[0053] Furthermore, the post-encapsulation drilling process involved in all process steps of this invention can be categorized into three main types based on the encapsulation material, hole size, and precision requirements: laser drilling, mechanical drilling, and plasma etching drilling. This invention primarily uses laser drilling, which utilizes a high-energy laser beam (ultraviolet, green, or infrared bands) focused on the surface of the encapsulation layer. Through thermal ablation (infrared laser) or cold peeling (ultraviolet laser) effects, the encapsulation material is removed layer by layer to form through-holes or micro-holes.

[0054] In all process steps of this invention involving electroplating, a photoresist film is first adhered, followed by photolithography techniques such as exposure and development to form a protective electroplating layer on the surface of the area to be electroplated. Areas not requiring electroplating are protected by the photoresist film, exposing the areas to be electroplated. Then, a metal seed layer is formed on the exposed areas to be electroplated using suitable methods such as sputtering or copper deposition. The metal seed layer is made of copper or other metals. The metal seed layer ensures the bonding strength between subsequent metal-to-metal and metal-to-encapsulating materials, while also providing a surface for conductive ion adhesion, thus ensuring the electroplating effect. The entire electroplating process and the materials used are common knowledge in the field. While all electroplating processes in this invention use copper, this invention does not limit this.

[0055] It is understood that this invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this invention are within the protection scope of this invention.

Claims

1. A method for packaging an exposed pin sensing chip, characterized in that, Includes the following steps: Electrical layout: The electroplating line 1 at the electrical port of the bare die is removed, and the electrical port is rearranged. Front wiring: Electroplating of line 2 on part of line 1, re-layout of the electrical properties of line 1, and extension of line 2 into two mutually perpendicular cut channels, and overall encapsulation. Backside wiring: Drill holes in the backside encapsulant of the bare die and electroplate the connecting posts to fill them. Another part of the line is electrically led to the backside encapsulant area of ​​the bare die, and line four is electroplated and electrically connected to the connecting posts. Line four extends to the same cutting track as line two, and the whole is encapsulated. Cutting and separating: Cut along the cutting line to separate into package units. Lines 2 and 4 are flush with each other and exposed on adjacent sides of the package. They are connected by a right angle on two adjacent sides of the package, which serve as chip mounting pins.

2. The pin-exposed sensor chip packaging method according to claim 1, characterized in that, In the back-side wiring step, the orthographic projections of line two and line four from the front of the die may be the same or different.

3. The method for packaging an exposed pin sensor chip according to claim 1, characterized in that, In the front wiring step, line three is electroplated on line two, and line three extends into the same cutting area as lines two and four.

4. The pin-exposed sensor chip packaging method according to claim 3, characterized in that, In the back-side wiring step, line five is electroplated on line four, and line five extends into the same cutting area as lines two, three, and four.

5. The pin-exposed sensor chip packaging method according to claim 4, characterized in that, In the back-side wiring step, the orthographic projections of lines three and five from the front of the die may be the same or different.

6. A package structure for an exposed pin sensing chip, comprising a package body, characterized in that, The package body encapsulates: The die has electrical ports distributed on its front side. Line 1: Electroplating is applied to the electrical terminals of the bare die to rearrange the electrical properties of the terminals; Line 2: Line 2 is installed on a portion of Line 1, and the electrical properties of Line 1 are rearranged. Line 4 involves electrically connecting another portion of the lines to the back cover area of ​​the bare die and rearranging them. Lines 2 and 4 are flush with and exposed on the same surface of the package, and are connected at right angles on the same package side to serve as chip mounting pins.

7. The exposed pin sensor chip packaging structure according to claim 6, characterized in that, The projections of line two and line four from the front of the die may be the same or different.

8. The exposed pin sensor chip packaging structure according to claim 6, characterized in that, Line 3 is electroplated on Line 2. Line 3 is flush with Line 2 and exposed on the surface of the package. The exposed parts of Line 3 are connected at right angles on the same side of the package.

9. The exposed pin sensor chip packaging structure according to claim 8, characterized in that, Line 5 is electroplated on Line 4. Line 5 is flush with Lines 2, 3, and 4 and exposed on the surface of the package. The exposed part of Line 5 is connected to the right-angled side of the same package.

10. The exposed pin sensor chip packaging structure according to claim 9, characterized in that, The orthographic projections of lines three and five from the front of the die may be the same or different.

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