Radio frequency chip integrated packaging structure and technology

Abstract

The invention discloses a radio frequency chip integrated packaging structure and technology, and the structure comprises the following steps: carrying out the primary packaging of a first line which is parallel and is uniformly arranged at intervals, and forming a first packaging layer; holes are drilled in the surface of the first encapsulation layer to expose all end points of the first lines, metal is electroplated on the exposed end points to fill the drilled holes, wiring connecting columns are electroplated on a set of diagonal end points arranged on the two edge first lines, and first stand columns are electroplated on the other exposed end points; electroplating a wiring layer on one surface of the encapsulation layer, and electrically rearranging the wiring connecting columns; the electrical end of the bare chip is electrically connected and mounted with the corresponding wiring layer, and the bare chip and the wiring layer are encapsulated again to form an encapsulation layer II; drilling holes in the surface of the encapsulation layer II to expose the end points of the upright posts I, and electroplating upright posts II on the exposed end points to fill the drilled holes; the bare chip is located in the geometric center of the three-dimensional coil, the induction current and the signal intensity are optimal, the three-dimensional coil has the more omnidirectional induction characteristic, and stable coupling can be kept.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, and particularly relates to an integrated packaging structure and process for radio frequency chips. Background Technology

[0002] Radio frequency identification (RFID) chips are the core components of RFID systems, integrating functions such as radio frequency transceiver, modulation and demodulation, encoding and decoding, storage and control. They enable contactless data transmission and identification through wireless radio frequency signals, allowing information exchange without physical contact. They are widely used in scenarios such as logistics tracking, identification, and IoT sensing. RFID chips need to be bonded and electrically connected to a coil, and connected to an external antenna with a coil structure to form a complete RFID tag. The chip is responsible for signal processing and data storage, while the antenna coil is responsible for transmitting and receiving radio frequency signals and harvesting energy.

[0003] Most existing RFID chip packaging structures only protect and interconnect the chip itself; the coil, as the antenna component of the RFID tag, is separate from the chip package. The packaged chip is then electrically connected to the coil via bonding and other processes. However, this connection structure results in a large overall size, a significant distance between the coil and the chip separated by packaging material, inefficient signal transmission and reception, uneven magnetic field strength, low coupling efficiency, and significant parasitic interference from the bonding connection, affecting stable signal transmission from the coil, resulting in strong signal reflection loss and weak coil radiation performance. Summary of the Invention

[0004] To address the problems in the prior art, the present invention provides an integrated packaging structure and process for radio frequency chips.

[0005] To achieve the above objectives, the present invention proposes an integrated packaging process for radio frequency chips, comprising the following steps: First encapsulation: Parallel and evenly spaced lines, encapsulated by an encapsulation layer; One-time drilling: Drill holes on the surface of the encapsulation layer to expose each endpoint of the line one, and electroplate metal to fill them. Electroplate wiring connection posts on a set of diagonally opposite endpoints of the line one on both edges, and electroplate posts one on the other endpoints. Electrical wiring: A wiring layer is electroplated on one surface of the encapsulation layer, and the electrical properties of the wiring connection posts are rearranged. Bare die mounting: The electrical terminals of the bare die are electrically connected to the corresponding wiring layer and mounted. The bare die and the wiring layer are encapsulated as encapsulation layer two. Secondary drilling: Drill holes on the surface of the second encapsulation layer to expose the end point of the first column, and electroplate the exposed end point with the second column to fill it; Circuit connection: Parallel and evenly spaced circuits are electroplated on the surface of the second encapsulation layer. The circuits are electrically connected to the second post. The encapsulation is the third encapsulation layer. The three encapsulations constitute the encapsulation body. Lines 1 and 2 form a three-dimensional winding coil with one end input and one end output through columns 1 and 2. The coil wraps the bare chip in the middle and is electrically connected to the chip port through wiring connection columns and wiring layers.

[0006] Furthermore, in the wiring and electrical connection step, one of the wiring connection posts is an electrical end, which is laid out through the wiring layer of an electrical connection, and the other wiring connection post is an electrical end, which is laid out through the wiring layer of another electrical connection.

[0007] Furthermore, in the die mounting step, the die is an RF chip, and the die is flipped and the electrical ports are aligned with the corresponding wiring layers to achieve electrical connection.

[0008] Furthermore, in the secondary drilling step, the electroplated column two is coaxial with the column but has a different diameter.

[0009] Furthermore, in the circuit connection step, the horizontal distance from the center point of the bare die to circuit one and circuit two is the same.

[0010] Furthermore, the process also includes three drilling operations: drilling vertically into the surface of encapsulation layer one away from encapsulation layer two until one end of the wiring layer is exposed, and then electroplating the leads to fill the drill holes.

[0011] A radio frequency chip integrated packaging structure includes a package body, which is formed by stacking encapsulation layer one, encapsulation layer two, and encapsulation layer three from bottom to top, and further includes: Line 1, parallel and evenly spaced lines 1, is encapsulated in encapsulation layer 1, and wire connection posts are electroplated on a set of diagonal endpoints of lines 1 arranged on the two edges, and posts 1 are electroplated on the other endpoints. The bare die is electroplated on the surface of the first encapsulation layer to lay out the wiring connection pillars electrically. The electrical ends of the bare die are electrically connected and mounted to the corresponding wiring layer. After drilling in the second encapsulation layer, the second pillar is electroplated and connected to the first pillar. The bare die, the wiring layer and the second pillar are encapsulated in the second encapsulation layer. Line 2, parallel and evenly spaced lines are electroplated on the surface of encapsulation layer 2, and lines 2 are electrically connected to pillar 2 respectively. Line 2 is encapsulated in encapsulation layer 3. Lines 1 and 2 form a three-dimensional winding coil with one end input and one end output through columns 1 and 2. The coil wraps the bare chip in the middle and is electrically connected to the chip port through wiring connection columns and wiring layers.

[0012] Furthermore, one of the wiring connection posts is electrically connected at one end and is laid out through a wiring layer with electrical connection, while the other wiring connection post is electrically connected at the other end and is laid out through a wiring layer with electrical connection.

[0013] Furthermore, the bare die is an RF chip, which is flip-chip mounted and its electrical ports are aligned with the corresponding wiring layers to achieve electrical connection.

[0014] Furthermore, the second column is coaxial with the first column but has a different diameter.

[0015] Furthermore, the horizontal distance from the center point of the bare die to line one and line two is the same.

[0016] Furthermore, a vertical hole is drilled on the surface of encapsulation layer one away from encapsulation layer two to expose one end of the wiring layer, and the drilled hole is filled with electroplated pins.

[0017] Beneficial effects of this invention: 1. Line 1 and Line 2 of different layers form a three-dimensional winding coil that wraps the bare chip in the middle through Post 1 and Post 2. The bare chip is located at the geometric center of the three-dimensional coil, so the induced current and signal strength are optimized. The three-dimensional coil has more omnidirectional induction characteristics and can maintain stable coupling. 2. The bare die is electrically connected to the coil through the wiring layer, which optimizes the package space, reduces the package size, and avoids parasitic parameter interference caused by additional connection structures; 3. Optimal encapsulation layer thickness and a compact package structure reduce signal transmission loss in the medium and lower signal reflection loss. 4. Line 1 and Line 2 are located in different encapsulation layers and are connected by drilled electroplated posts to reduce conductor loss and further improve the radiation performance of the coil. Attached Figure Description

[0018] Figures 1-2 This is a cross-sectional view of a primary encapsulation step in an integrated radio frequency chip packaging process according to the present invention. Figures 3-4 This is a cross-sectional view of the wiring and electrical connection steps in an integrated packaging process for an RF chip according to the present invention. Figure 5 This is a cross-sectional view of the die mounting steps in an RF chip integrated packaging process according to the present invention. Figures 6-8 This is a cross-sectional view of the circuit connection steps in an integrated packaging process for an RF chip according to the present invention. Figures 9-11 This is a cross-sectional view of the three drilling steps in an integrated packaging process for an RF chip according to the present invention. Figure 12 This is a cross-sectional view of an integrated packaging structure for a radio frequency chip according to the present invention; Figure 13 This is a top perspective view of an integrated packaging structure for a radio frequency chip according to the present invention.

[0019] In the diagram: 1. Encapsulation layer 1; 2. Circuit 1; 3. Wiring connection post; 4. Post 1; 5. Bare die; 6. Wiring layer; 7. Encapsulation layer 2; 8. Post 2; 9. Circuit 2; 10. Encapsulation layer 3; 11. Package. Detailed Implementation

[0020] The present invention will now be described in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout.

[0021] The directional terms used in this invention, such as up, down, left, right, front, back, inside, outside, front, back, side, etc., are merely for reference to the accompanying drawings. The embodiments and directional terms used in the following description with reference to the accompanying drawings are exemplary and are only used to explain this invention, and should not be construed as limiting this invention. Furthermore, the various specific processes and materials provided in this invention are examples that those skilled in the art will recognize for the application of other processes and / or the use of other materials.

[0022] Radio frequency (RFID) chips are miniaturized, low-power application-specific integrated circuits (ASICs) that are widely used in logistics tracking, identification, and IoT sensing. RFID chips are encapsulated in packaging materials and then electrically connected via stacked antenna coils to achieve energy coupling and signal transmission. By forming an LC resonant circuit with the chip, the RFID chip receives electromagnetic signals from the reader and converts them into electrical energy to power the chip, while also transmitting the chip's feedback signals.

[0023] Most existing RFID chip packaging structures only protect and interconnect the chip itself; the coil, as the antenna component of the RFID tag, is separate from the overall chip package. The packaged chip is then connected to an external antenna containing a coil structure through bonding and other processes to form a complete RFID tag. The chip is responsible for signal processing and data storage, while the antenna coil is responsible for transmitting and receiving radio frequency signals and harvesting energy. However, this connection structure results in a large overall size, inefficient signal transmission and reception between the coil and the chip, uneven magnetic field strength, low coupling efficiency, and significant parasitic parameter interference from the bonding connection, affecting the stable signal transmission of the coil, resulting in strong signal reflection loss and weak coil radiation performance.

[0024] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an integrated packaging structure and process for an RF chip proposed in this invention.

[0025] The process specifically includes the following steps: Primary encapsulation: Parallel and evenly spaced lines 2, the initial encapsulation is encapsulation layer 1; One-time drilling: Drill holes on the surface of the encapsulation layer 1 to expose each end of the line 2, electroplate metal to fill the holes on the exposed ends, electroplate wiring connection posts 3 on a set of diagonally opposite ends of the two edge lines 2, and electroplate posts 4 on the other exposed ends. Electrical wiring connection: Electroplating wiring layer 6 on the surface of encapsulation layer 1, and electrically rearranging wiring connection posts 3; Bare die 5 mounting: Electrically connect the electrical terminals of bare die 5 to the corresponding wiring layer 6 and mount them. Then encapsulate bare die 5 and wiring layer 6 again as encapsulation layer 7. Secondary drilling: Drill holes on the surface of the second encapsulation layer 7 to expose the end point of the first post 4, and electroplate the second post 8 on the exposed end point to fill the drill hole; Circuit connection: Parallel and evenly spaced matrix-arranged circuits 9 are electroplated on the surface of encapsulation layer 2 7. Circuits 2 9 are electrically connected to pillars 2 8 respectively. Encapsulation is then performed again to form encapsulation layer 3 10. The three encapsulations constitute the package 11. Lines 1 and 2 form a three-dimensional winding coil with one end input and one end output through columns 1 and 2. The coil wraps the bare chip 5 in the middle and is electrically connected to the port of the bare chip 5 through wiring connection column 3 and wiring layer 6.

[0026] Three drilling operations were performed, with vertical holes drilled on the surface of encapsulation layer 1 away from encapsulation layer 2 7 until one end of wiring layer 6 was exposed, and the drilled holes were filled with electroplated leads.

[0027] In one encapsulation step, line 2 is formed on a substrate coated with an encapsulating material of a certain thickness through an electroplating process. Line 2 consists of multiple electroplated metal strips, which are parallel to each other and evenly spaced along their width (e.g., ...). Figure 1 As shown), the endpoints of each line 2 are on the same straight line. The length and number of lines 2 are set according to the specific product, and this invention does not limit this. An encapsulation layer 1 is initially encapsulated on the substrate using an encapsulating material, completely encapsulating the lines 2 within the encapsulation layer 1 (e.g., ...). Figure 2 As shown), the encapsulation layer 1 is integrated with the encapsulation material attached to the substrate.

[0028] In one drilling step, holes are drilled vertically at corresponding positions on the surface of the encapsulation layer 1 after the line 1 is encapsulated. Each hole exposes each end of the line 1. The drilling is performed by laser drilling. This drilling is the first drilling in this process. After the endpoints are exposed, the posts 4 and wiring connection posts 3 are formed by electroplating metal into the drilled holes. The wiring connection posts 3 are electroplated metals arranged on a set of diagonally opposite endpoints of the two edge lines 2. The other endpoints are electroplated with posts 4. Posts 4 and wiring connection posts 3 can be made of the same metal material. One end of post 4 and wiring connection post 3 is connected to the corresponding endpoint of line 2 as a whole, and the other end is flush with the drilled surface of the encapsulation layer 1 and exposed. Posts 4 and wiring connection posts 3 are electroplated at the same time. In order to ensure that the electroplated metal can be completely filled after drilling, the thickness of the encapsulation layer 1 needs to be controlled. If it is too thick, the endpoints will not be exposed in the drilled holes, and the electroplating solution will have difficulty entering the holes, affecting the electroplating. However, the encapsulation layer 1 needs to completely encapsulate line 2. The specific thickness is flexibly controlled according to the actual product situation to reduce costs.

[0029] In the wiring and electrical connection step, the drilled surface of the encapsulation layer 1 is flush with the exposed post 4 and wiring connection post 3. A wiring layer 6 (e.g., ...) is electroplated on this surface. Figure 3 As shown), wiring layer 6 does not contact the post 4 to form an electrical connection. The number of wiring layers 6 is the same as the number of electrical ports of the bare die 5. The accompanying drawings of this invention only show some of the electrical ports of the bare die 5, so wiring layers 6 are only shown accordingly, not all of them. The number of wiring layers 6 is independent of each other. Some wiring layers 6 are electrically connected to wiring connection posts 3. Each wiring connection post 3 is electrically connected to only one wiring layer 6. The electrical layout of the wiring connection posts 3 is rearranged (e.g., Figure 4 As shown, Figure 4 for Figure 3 (Top view), the layout of wiring layer 6 is set according to the actual product situation and the bare die 5 situation, which facilitates the subsequent bare die 5 mounting and electrical connection.

[0030] In the die 5 mounting step, the electrical ports of die 5 (which is an RF chip) are aligned with the ports of wiring layer 6 for flip-chip mounting (e.g., Figure 5 As shown in the diagram, the components are firmly soldered to achieve structural stability and electrical interconnection. The electrical ports of the bare die 5 are rearranged and connected by wiring layer 6. The RF antenna ports are electrically connected to the wiring connection posts 3 via wiring layer 6. Other ports, such as grounding ports and detection ports, are rearranged and connected by other wiring layers 6. After mounting, the die 5 is further encapsulated by encapsulating material to form encapsulation layer 7, which completely encapsulates the bare die 5. Encapsulation layer 7 is integrated with encapsulation layer 1, and the top surface of the cured encapsulation layer 7 is horizontal and flat. The mounted bare die 5 does not contact the posts 4 to establish an electrical connection. After mounting, the bare die 5 is located between the two rows of posts 4.

[0031] In the secondary drilling step, vertical holes are drilled at corresponding positions on the surface of the second encapsulation layer 7 until the endpoint of the first post 4 is exposed. Each drilled hole exposes the endpoint of the first post 4 at the corresponding position, and metal is electroplated into the drilled hole to form the second post 8. The first post 4 and the second post 8 are vertically connected as one unit. The electroplated second post 8 is coaxial with the first post 4 but has a different diameter. The difference in diameter between the two posts results in a different contact area with the encapsulation material, which increases the connection stability between the posts and the encapsulation material and reduces the likelihood of delamination and failure. The top of the second post 8 is flush with and exposed on the surface of the drilled hole in the second encapsulation layer 7.

[0032] In the circuit connection step, circuit 9 is electroplated on the surface of the hole drilled in the second encapsulation layer 7 (e.g., ...). Figure 6 As shown), line 29 electrically connects a set of posts 28 at the diagonal ends of each pair of adjacent lines 12 together. Lines 29 are arranged in parallel and evenly spaced order, with their endpoints on the same straight line. The electrical connections of each line 12 are vertically pulled by posts 14 and 28, and their endpoints are connected in series to form a complete three-dimensional coil (as shown). Figure 7 As shown, Figure 7 for Figure 6 (Top view). Continue encapsulating with encapsulating material to completely encapsulate line 29, forming encapsulation layer 310 (as shown). Figure 8 As shown), encapsulation layer 3 10 is carried out on the basis of encapsulation layer 2 7, and the encapsulation is integrated into one.

[0033] The bare die outputs electrical signals through a wiring layer 6 and the corresponding wiring connection post 3 of the wiring layer 6. The signal passes through line 1 2 to the endpoint of the corresponding post 1 4, and is transmitted from post 1 4 and post 2 8 at the endpoint to line 2 9. This process is repeated to form a complete loop of a three-dimensional coil around the bare die.

[0034] Lines 1 and 2 form a three-dimensional wound coil with one end input and one end output through pillars 1 and 2, creating a regular loop structure that helps generate a stable magnetic field and efficiently transmit and receive radio frequency signals. The coil and the bare die 5 are electrically connected by wiring layer 6, avoiding parasitic parameter interference caused by additional connection structures, making the coil's signal transmission more stable and ensuring its core functions of energy acquisition and data interaction. Lines 1 and 2 are located in different encapsulation layers and are connected by drilled electroplated pillars, reducing conductor loss and further improving the coil's radiation performance.

[0035] The coil wraps around the bare die 5 in the middle and is electrically connected to the port of the bare die 5 through wiring connection post 3 and wiring layer 6. The horizontal distance from the center point of the bare die 5 to line 2 and line 9 is the same. The bare die 5 is located at the geometric center of the three-dimensional coil. The magnetic field strength of the coil is the most uniform and the coupling efficiency is the highest. The radio frequency magnetic field can cut the coil with maximum flux, and the induced current and signal strength are optimal.

[0036] Furthermore, the die 5 is electrically connected to the coil through the wiring layer 6. The die 5 is located in the middle of the three-dimensional coil, which allows for a reasonable layout of the package space and reduces the package size.

[0037] The more omnidirectional induction characteristics of the three-dimensional coil eliminate the directional limitations of the planar coil. It can maintain stable coupling regardless of the angle at which the package faces the reader, avoiding signal interruption caused by attitude deviation.

[0038] From bottom to top, a complete package 11 is formed by stacking encapsulation layer 1, encapsulation layer 7, and encapsulation layer 3. The three-dimensional wound coil is encapsulated by encapsulating material, resulting in extremely low dielectric loss at high frequencies and preventing significant absorption or shielding of electromagnetic signals generated by the coil. The encapsulation layer thickness is optimally designed according to product requirements. The compact structure of the entire package 11 reduces signal transmission loss in the medium, ensures efficient RF coupling between the coil and the external reader, matches the coil impedance, and further reduces signal reflection loss.

[0039] In the three drilling steps, the encapsulation assembly is peeled off from the substrate and then flipped over and reattached to the substrate (e.g., Figure 9 As shown), at this time, the surface of encapsulation layer 1 away from encapsulation layer 2 7 is exposed above the substrate. A vertical hole is drilled at the corresponding position on this surface of encapsulation layer 1 until one end of each wiring layer 6 is exposed (e.g., ...). Figure 10 As shown in Figure 11), after drilling, the leads are filled with electroplated metal. The leads completely fill the drilled hole and are flush with the surface of the encapsulation layer 1. The leads electrically pull the bare die 5 from the wiring layer 6 to the outside of the package 11, serving as a medium for electrical connection between the external working environment and the internal bare die 5 (as shown in Figure 11). Figure 11 for Figure 10 (Perspective view).

[0040] For a package 11 that forms multiple sets of bare dies and three-dimensional coils on a substrate, after the process is completed, multiple sets of structural units are finally encapsulated in the entire encapsulation material. Finally, a cutting process is required to vertically cut and separate the structural units in the cutting channel area between them to obtain each package 11 product unit.

[0041] In all the encapsulation steps involved in this invention, the encapsulating material used is a molding compound, specifically epoxy resin, cyanate ester, polyimide, etc. These materials are low in cost, have good curing performance, and are commonly used encapsulation methods in the field. Encapsulation technology plays an important role in semiconductor manufacturing, mainly in protecting the die, connecting the whole structure, supporting the structure, improving reliability, and promoting technological progress. The encapsulation method in this invention is the commonly used molding injection molding method, but other suitable encapsulation methods are also acceptable. After the encapsulating material cures, the outer surface of the entire encapsulation structure is smooth and flat.

[0042] Furthermore, the post-encapsulation drilling process involved in all process steps of this invention can be categorized into three main types based on the encapsulation material, hole size, and precision requirements: laser drilling, mechanical drilling, and plasma etching drilling. This invention primarily uses laser drilling, which utilizes a high-energy laser beam (ultraviolet, green, or infrared bands) focused on the surface of the encapsulation layer. Through thermal ablation (infrared laser) or cold peeling (ultraviolet laser) effects, the encapsulation material is removed layer by layer to form through-holes or micro-holes.

[0043] In all process steps of this invention involving electroplating, a photoresist film is first adhered, followed by photolithography techniques such as exposure and development to form a protective electroplating layer on the surface of the area to be electroplated. Areas not requiring electroplating are protected by the photoresist film, exposing the areas to be electroplated. Then, a metal seed layer is formed on the exposed areas to be electroplated using suitable methods such as sputtering or copper deposition. The metal seed layer is made of copper or other metals. The metal seed layer ensures the bonding strength between subsequent metal-to-metal and metal-to-encapsulating materials, while also providing a surface for conductive ion adhesion, thus ensuring the electroplating effect. The entire electroplating process and the materials used are common knowledge in the field. While all electroplating processes in this invention use copper, this invention does not limit this.

[0044] In this invention, lines 1 (2) and 2 (9) of different layers form a three-dimensional winding coil that encloses the bare die 5 in the middle through pillars 1 (4) and 2 (8). The bare die 5 is located at the geometric center of the three-dimensional coil, achieving optimal induced current and signal strength. The more omnidirectional induction characteristics of the three-dimensional coil can maintain stable coupling. The bare die 5 is electrically connected to the coil through wiring layer 6, with reasonable layout of the packaging space, reducing the packaging size and avoiding parasitic parameter interference caused by additional connection structures. The encapsulation layer thickness is optimal, and the compact structure of the entire package 11 can reduce signal transmission loss in the medium and reduce signal reflection loss. Lines 1 (2) and 2 (9) are located in different encapsulation layers and are connected by drilled electroplated pillars, reducing conductor loss and further improving the radiation performance of the coil.

[0045] Based on the above-mentioned RF chip integrated packaging process, an RF chip integrated packaging structure (such as...) is obtained. Figures 12-13 As shown, Figure 13 The middle horizontal line is Figure 12 (Cross-sectional view, cross-sectional direction), including a package 11, which is composed of encapsulation layer 1, encapsulation layer 7 and encapsulation layer 10 stacked from bottom to top, and also includes: Line 12, parallel and evenly spaced lines 12, encapsulated in encapsulation layer 1, and wire connection posts 3 are electroplated on a set of diagonal endpoints of lines 12 arranged on the two edges, and posts 4 are electroplated on the other endpoints. The bare die 5 has a wiring layer 6 on the surface of the encapsulation layer 1, which is used to electrically rearrange the wiring connection posts 3. The electrical ends of the bare die 5 are electrically connected to the corresponding wiring layer 6 and mounted. The bare die 5 is an RF chip. The bare die 5 is flip-chip and the electrical ports are aligned with the corresponding wiring layers 6 to achieve electrical connection. After drilling in the encapsulation layer 2, the second post 8 is electroplated and connected to the first post 4. The bare die 5, the wiring layer 6 and the second post 8 are encapsulated in the encapsulation layer 2. The electrical ports of the bare die 5 are pulled by the rearrangement of the wiring layer 6. The RF antenna port is electrically connected to the wiring connection post 3 through the wiring layer 6. Other ports are pulled by the rearrangement of other wiring layers 6, such as the ground port, the detection port, etc.

[0046] Column 28 is coaxial with Column 14 but has a different diameter. The difference in diameter between the two columns results in a different contact area with the encapsulating material, which increases the connection stability between the column and the encapsulating material and makes it less likely to fail due to delamination or circuit breakage.

[0047] Line 2 9 is electroplated on the surface of encapsulation layer 2 7, with parallel and evenly spaced lines 2 9. Line 2 9 is electrically connected to post 2 8. Line 2 9 is encapsulated in encapsulation layer 3 10. The endpoints of line 2 9 are located on the same straight line. The electrical properties of each line 1 2 are vertically pulled by post 1 4 and post 2 8 and then electrically connected in series to form a complete three-dimensional coil. The coil and the bare die 2 are electrically connected by wiring layer 6, avoiding parasitic parameter interference caused by additional connection structures and making the signal transmission of the coil more stable.

[0048] Lines 1 and 2 form a three-dimensional winding coil with one end input and one end output through columns 1 and 2. The coil wraps the bare chip 5 in the middle and is electrically connected to the port of the bare chip 5 through wiring connection column 3 and wiring layer 6.

[0049] The horizontal distance from the center point of die 5 to line 2 and line 9 is the same. Die 5 outputs electrical signals through a wiring layer 6 and the corresponding wiring connection post 3 of the wiring layer 6. The signal passes through line 2 to the endpoint of the corresponding post 4, and is transmitted from post 4 and post 8 at the endpoint to line 9. This cycle repeats to form a complete loop of three-dimensional coil around die 5, forming a regular loop structure that helps generate a stable magnetic field and efficiently transmit and receive radio frequency signals. Line 2 and line 9 are located in different encapsulation layers and are connected by drilled electroplated posts to reduce conductor loss and further improve the radiation performance of the coil. Die 5 is located at the geometric center of the three-dimensional coil, where the magnetic field strength of the coil is most uniform and the coupling efficiency is highest.

[0050] A vertical hole is drilled on the surface of encapsulation layer 1 away from encapsulation layer 2 7 to expose one end of wiring layer 6, and the drilled hole is filled with electroplated pins. The pins completely fill the inside of the drilled hole and are flush with the surface of encapsulation layer 1. The pins electrically pull the die 5 from wiring layer 6 to the outside of package 11, serving as a medium for electrical connection between the external working environment and the internal die 5.

[0051] In this invention, the encapsulation structure consists of circuits 2 and 9, which form a three-dimensional wound coil that encloses a bare die 5 in the middle via pillars 4 and 8. The bare die 5 is located at the geometric center of the three-dimensional coil, achieving optimal induced current and signal strength. The more omnidirectional induction characteristics of the three-dimensional coil ensure stable coupling. The bare die 5 is electrically connected to the coil via wiring layer 6, reducing the package size and avoiding parasitic parameter interference caused by additional connection structures. The encapsulation layer thickness is optimal, and the compact structure of the entire package 11 reduces signal transmission loss in the medium and lowers signal reflection loss. Circuits 2 and 9 are located within different encapsulation layers and are connected by drilled electroplated pillars, reducing conductor loss and further improving the radiation performance of the coil.

[0052] It is understood that this invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this invention are within the protection scope of this invention.

Claims

1. A radio frequency chip integrated packaging process, characterized in that, Includes the following steps: First encapsulation: Encapsulating parallel and evenly spaced lines as encapsulation layer one; One-time drilling: Drill a hole in the encapsulation layer to expose the endpoint of line one, fill it with electroplated metal, electroplat wiring connection posts are arranged on a set of diagonally opposite endpoints of line one on both edges, and electroplat the other endpoints with posts one. Electrical wiring: A wiring layer is electroplated on one surface of the encapsulation layer, and the electrical properties of the wiring connection posts are rearranged. Bare die mounting: The electrical terminals of the bare die are electrically connected to the corresponding wiring layer and mounted. The bare die and the wiring layer are encapsulated as encapsulation layer two. Secondary drilling: Drill a hole in the second encapsulation layer to expose one end of the column, and then fill the hole with electroplated column two; Line connection: Parallel and evenly spaced lines are electroplated on the second encapsulation layer. Lines are electrically connected to the second pillar. The encapsulation is the third encapsulation layer. The three encapsulations constitute the encapsulation body. Lines 1 and 2 form a three-dimensional winding coil with one end input and one end output through columns 1 and 2. The bare die is wrapped in the middle and electrically connected to the die port through wiring connection columns and wiring layers.

2. The RF chip integrated packaging process according to claim 1, characterized in that, In the wiring and electrical connection step, one of the wiring connection posts is the electrical end, which is laid out through the wiring layer of one electrical connection, and the other wiring connection post is the electrical end, which is laid out through the wiring layer of another electrical connection.

3. The RF chip integrated packaging process according to claim 1, characterized in that, In the die mounting step, the die is an RF chip. The die is flipped and the electrical ports are aligned with the corresponding wiring layers to achieve electrical connection.

4. The RF chip integrated packaging process according to claim 3, characterized in that, In the secondary drilling step, the electroplated column two is coaxial with the column but has a different diameter.

5. The RF chip integrated packaging process according to claim 4, characterized in that, In the circuit connection step, the horizontal distance from the center point of the bare die to circuit one and circuit two is the same.

6. The RF chip integrated packaging process according to claim 1, characterized in that, The process also includes three drilling operations: drilling vertically into the surface of encapsulation layer one away from encapsulation layer two until one end of the wiring layer is exposed, and then electroplating the leads to fill the drill holes.

7. A radio frequency chip integrated packaging structure, comprising a package body, wherein the package body is formed by stacking encapsulation layer one, encapsulation layer two, and encapsulation layer three sequentially from bottom to top, characterized in that, It also includes: Line 1, parallel and evenly spaced lines 1, is encapsulated in encapsulation layer 1, and wire connection posts are electroplated on a set of diagonal endpoints of lines 1 arranged on the two edges, and posts 1 are electroplated on the other endpoints. The bare die is electroplated on the surface of the first encapsulation layer to lay out the wiring connection pillars electrically. The electrical ends of the bare die are electrically connected and mounted to the corresponding wiring layer. After drilling in the second encapsulation layer, the second pillar is electroplated and connected to the first pillar. The bare die, the wiring layer and the second pillar are encapsulated in the second encapsulation layer. Line 2, parallel and evenly spaced lines are electroplated on the surface of encapsulation layer 2, and lines 2 are electrically connected to pillar 2 respectively. Line 2 is encapsulated in encapsulation layer 3. Lines 1 and 2 form a three-dimensional winding coil with one end input and one end output through columns 1 and 2. The coil wraps the bare chip in the middle and is electrically connected to the chip port through wiring connection columns and wiring layers.

8. The radio frequency chip integrated packaging structure according to claim 7, characterized in that, One of the wiring connection posts is electrically connected at one end and is laid out through a wiring layer with electrical connection, while the other wiring connection post is electrically connected at the other end and is laid out through a wiring layer with electrical connection.

9. The radio frequency chip integrated packaging structure according to claim 7, characterized in that, The die is an RF chip. The die is flip-chip and the electrical ports are aligned with the corresponding wiring layers to achieve electrical connection.

10. The radio frequency chip integrated packaging structure according to claim 9, characterized in that, The second column is coaxial with the first column but has a different diameter.

11. The radio frequency chip integrated packaging structure according to claim 10, characterized in that, The horizontal distance from the center point of the bare die to line one and line two is the same.

12. The radio frequency chip integrated packaging structure according to claim 7, characterized in that, A vertical hole is drilled on the surface of encapsulation layer one away from encapsulation layer two to expose one end of the wiring layer, and the drilled hole is filled with electroplated pins.

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