Multi-amplifier circuit

Abstract

The invention provides a multi-amplifier circuit. The first amplifier (1) amplifies and outputs two input differential voltages. The second amplifier (2) amplifies and outputs the differential voltages of the two inputs. Each of the first amplifier (1) and the second amplifier (2) includes a first differential input circuit (D1), a second differential input circuit (D2), and a current adjustment unit (30). The first differential input circuit (D1) includes a transistor pair that amplifies and outputs a differential voltage of two inputs. The second differential input circuit (D2) includes a transistor pair that amplifies and outputs a differential voltage input to the two differential input circuits (D1). The differential input circuits (D1, D2) have asymmetric structures that each generate input offset voltages that are positively and negatively opposite to each other. A monitor amplifier (51) amplifies and outputs a differential voltage between an input to the first amplifier (1) and an input to the second amplifier (2). The current adjustment unit (30) adjusts the current ratio of the currents flowing into the differential input circuits (D1, D2) in response to the output of the monitor amplifier (51).

Description

Technical Field

[0001] This invention relates to reducing the fluctuation of input offset voltage in multiple amplifiers. Background Technology

[0002] Patent Document 1 discloses an op-amp with an offset voltage cancellation circuit. This op-amp includes a first differential input circuit and a second differential input circuit. Because the transistors forming pairs in the first and second differential input circuits are of different sizes, each differential input circuit has an asymmetrical structure. By controlling the tail current flowing into each differential input circuit, it is possible to adjust which of the first and second differential input circuits is dominant. As a result, the offset of the op-amp can be continuously adjusted.

[0003] Patent Document 2 also discloses an imbalance adjustment circuit similar to that in Patent Document 1.

[0004] Patent Document 1: U.S. Patent No. 7,167,049

[0005] Patent Document 2: Japanese Patent Application Publication No. 2003-318670 Summary of the Invention When multiple OP amplifiers from Patent Document 1 are used instead of a single one, there is a need to eliminate the difference in input offset voltage between the multiple amplifiers. However, Patent Documents 1 and 2 only disclose individual circuits and do not disclose a structure for adjusting input offset between multiple circuits.

[0006] In view of the above, the object of the present invention is to reduce offset error when there are multiple amplifiers capable of adjusting the input offset voltage.

[0007] The problem to be solved by the present invention is as described above. Next, the method for solving the problem and its effects will be explained.

[0008] According to a first aspect of the present invention, a multi-amplifier circuit with the following structure is provided. That is, the multi-amplifier circuit includes a first amplifier, a second amplifier, and a monitoring amplifier. The first amplifier amplifies and outputs a differential voltage from two inputs. The second amplifier amplifies and outputs a differential voltage from two inputs. At least one of the first amplifier and the second amplifier includes a first differential input circuit, a second differential input circuit, and a current adjustment unit. The first differential input circuit includes a pair of transistors that amplifies and outputs a differential voltage from two inputs, having an asymmetric structure that generates an input offset voltage. The second differential input circuit includes a pair of transistors that amplifies and outputs a differential voltage from the two inputs of the first differential input circuit, having an asymmetric structure that generates an input offset voltage opposite in sign to the input offset voltage of the first differential input circuit. The current adjustment unit adjusts the current ratio of the currents flowing into the first differential input circuit and the second differential input circuit. The monitoring amplifier amplifies and outputs a differential voltage from one of the two inputs of the first amplifier and one of the two inputs of the second amplifier. The current adjustment unit adjusts the current ratio in response to the voltage output by the monitoring amplifier.

[0009] This allows for adjustments to reduce the difference in input offset voltage between the two amplifiers based on the output of the monitoring amplifier. The result is improved signal amplification accuracy.

[0010] According to a second aspect of the present invention, a multi-amplifier circuit with the following structure is provided. The multi-amplifier circuit includes a first amplifier, a second amplifier, and a monitoring amplifier. The first amplifier amplifies and outputs a differential voltage from two inputs. The second amplifier amplifies and outputs a differential voltage from two inputs. At least one of the first amplifier and the second amplifier includes a first differential input circuit, a second differential input circuit, and a current adjustment unit. The first differential input circuit includes a pair of transistors that amplifies and outputs the differential voltage from the two inputs, having an asymmetric structure that generates an input offset voltage. The second differential input circuit includes a pair of transistors that amplifies and outputs the differential voltage from the two inputs to the first differential input circuit, having an asymmetric structure that generates an input offset voltage opposite in sign to the input offset voltage of the first differential input circuit. The current adjustment unit adjusts the current ratio of the currents flowing into the first differential input circuit and the second differential input circuit. The monitoring amplifier amplifies and outputs the differential voltage from the outputs of the first amplifier and the second amplifier. The current adjustment unit adjusts the current ratio in response to the voltage output by the monitoring amplifier.

[0011] (The effect of the invention) This allows for adjustments to reduce the input offset voltage difference between the two amplifiers based on the output of the monitoring amplifier. The result is improved signal amplification accuracy. Attached Figure Description

[0012] Figure 1 This is a circuit diagram illustrating the multi-amplifier circuit according to the first embodiment of the present invention.

[0013] Figure 2 The circuit diagrams show several examples of asymmetric structures for implementing differential input circuits.

[0014] Figure 3 This is a circuit diagram illustrating the multi-amplifier circuit of the second embodiment.

[0015] Figure 4 This is a circuit diagram illustrating the multi-amplifier circuit of the third embodiment.

[0016] Figure 5 This is a circuit diagram illustrating the multi-amplifier circuit of the fourth embodiment. Detailed Implementation

[0017] Next, embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a circuit diagram showing the multi-amplifier circuit 101 according to the first embodiment of the present invention. In the description of this embodiment, components that are the same or similar to those in the comparative example described above are labeled with the same symbols in the drawings, and sometimes the description is omitted.

[0018] Figure 1 The multi-amplifier circuit 101 shown in this embodiment includes a first amplifier 1, a second amplifier 2, and a monitoring amplifier 51.

[0019] The signal output by the first sensor 11 is input to the first amplifier 1. The signal output by the second sensor 12 is input to the second amplifier 2. Sensors 11 and 12 can be, for example, photodiodes that detect light and output current, and the first amplifier 1 and the second amplifier 2 can be, for example, transimpedance amplifiers that convert the current output by the input sensors 11 and 12 into voltage signals. However, they are not limited to these.

[0020] The first amplifier 1 includes a first input terminal IN1, a second input terminal IN2, an output terminal OUT, a first current adjustment terminal TAIL1, and a second current adjustment terminal TAIL2. The output terminal of the first sensor 11 is electrically connected to the first input terminal IN1. The first input terminal IN1 and the output terminal OUT are electrically connected via a first feedback resistor 21.

[0021] The second amplifier 2 includes a first input terminal IN1, a second input terminal IN2, an output terminal OUT, a first current adjustment terminal TAIL1, and a second current adjustment terminal TAIL2. The output terminal of the second sensor 12 is electrically connected to the first input terminal IN1. The first input terminal IN1 and the output terminal OUT are electrically connected via a second feedback resistor 22.

[0022] A common reference potential is input to the second input terminal IN2 of the first amplifier 1 and the second input terminal IN2 of the second amplifier 2.

[0023] Consider the case where the current output by both the first sensor 11 and the second sensor 12 is zero. Ideally, since the potential of the first input terminal IN1 in the first amplifier 1 is equal to the potential of the second input terminal IN2 (in other words, the reference potential), the potential of the output terminal OUT is the reference potential. However, in reality, due to reasons such as the strictly inconsistent characteristics of the differential transistor pair included in the first amplifier 1, the potential of the output terminal OUT is not consistent with the reference potential. Instead, in order for the potential of the output terminal OUT to be consistent with the reference potential, a potential difference with inconsistent cancellation characteristics must be generated between the potentials of the first input terminal IN1 and the second input terminal IN2. This potential difference is called the input offset voltage. The same applies in the second amplifier 2.

[0024] Due to individual differences between the first amplifier 1 and the second amplifier 2, the input offset voltages are typically different. The potential difference between the first input terminal IN1 of the first amplifier 1 and the first input terminal IN1 of the second amplifier 2 affects the measurement accuracy using sensors 11 and 12. When σ represents the fluctuation (standard deviation) of the potential difference between the first input terminal IN1 and the second input terminal IN2 of each of the first amplifier 1 and the second amplifier 2, the fluctuation of the potential difference between the first input terminals IN1 of the two amplifiers 1 and 2 is (√2) × σ.

[0025] In the multi-amplifier circuit 101 of this embodiment, an amplifier with adjustable input offset voltage is used in each of the first amplifier 1 and the second amplifier 2. The amplifier with adjustable input offset voltage can be, for example, the amplifier disclosed in Patent Documents 1 and 2, but is not limited thereto.

[0026] exist Figure 2 In the text, several examples are shown regarding the two differential input circuits D1 and D2 in the first amplifier 1.

[0027] In the first example, the differential input circuit D1 includes a differential transistor pair consisting of two transistors, M1 and M2. Transistors M1 and M2 are each configured as known MOSFETs. The gate of transistor M1 is connected to the first input terminal IN1, and the gate of transistor M2 is connected to the second input terminal IN2. The sources of transistors M1 and M2 are connected to a common first current source I1.

[0028] The first example corresponds to the structure disclosed in Patent Document 1, achieving asymmetry by making the transistors M1 and M2 have different dimensions. In the first example, the difference in size is achieved by making the channel width W of the MOS transistors different, which can be either different in channel length L or different in both channel width W and channel length L.

[0029] Differential input circuit D2 is the same as differential input circuit D1, including a differential transistor pair consisting of two transistors M1 and M2. The gate of transistor M1 is connected to the first input terminal IN1, and the gate of transistor M2 is connected to the second input terminal IN2. The sources of transistors M1 and M2 are connected to a common second current source I2.

[0030] In differential input circuit D2, similar to differential input circuit D1, the transistors M1 and M2 that form the pair have different sizes. Here, the size relationship of transistors M1 and M2 is opposite to that in differential input circuit D1. In other words, the asymmetry assigned to the structure of each differential input circuit D1 and D2 is complementary. Therefore, when considering each differential input circuit D1 and D2 individually, the input offset voltages are complementary with opposite signs. This is also true in the second example onwards.

[0031] The drains of transistor M1 in differential input circuit D1 and transistor M1 in differential input circuit D2 are connected to the terminals on one side of load 60. The drains of transistor M2 in differential input circuit D1 and transistor M2 in differential input circuit D2 are connected to the terminals on the other side of load 60. The voltage between the two terminals of load 60 is led out to the output stage (not shown).

[0032] Which of the two differential input circuits, D1 and D2, exhibits a stronger characteristic depends on the magnitude relationship between the first current source I1 and the second current source I2. For example, when the current magnitudes of the first current source I1 and the second current source I2 are equal, the size imbalance of transistors M1 and M2 between the two differential input circuits D1 and D2 is canceled out, thus no adjustment of the input offset voltage is substantially performed. When the current of the first current source I1 is greater than the current of the second current source I2, the input offset voltage can be adjusted to one side (e.g., the positive side) because the characteristic of differential input circuit D1 is stronger. When the current of the second current source I2 is greater than the current of the first current source I1, the input offset voltage can be adjusted to the opposite side (e.g., the negative side) because the characteristic of differential input circuit D2 is stronger.

[0033] In the second example, asymmetry is achieved by changing the back-gate potentials of the transistors M1 and M2 that constitute the pair in the differential input circuit D1. Specifically, in the differential input circuit D1, the back-gate of transistor M1 is connected to the source, and the back-gate of transistor M2 is grounded. The description of the differential input circuit D2 is omitted.

[0034] The third example, like the second, also achieves asymmetry by changing the back-gate potentials of the transistors M1 and M2 that constitute the pair in the differential input circuit D1. Specifically, in the differential input circuit D1, the back-gate of transistor M1 is set to a predetermined potential, while the back-gate of transistor M2 is grounded. The back-gate of transistor M2 can also be set to a different predetermined potential than that of transistor M1. The description of the differential input circuit D2 is omitted.

[0035] In the fourth example, asymmetry is achieved by adding a source resistor to only one of the transistors M1 and M2 that form a pair in the differential input circuit D1. Asymmetry can also be achieved by adding source resistors with different values ​​to both transistors M1 and M2. The description of the differential input circuit D2 is omitted.

[0036] exist Figure 2 In the four examples shown, the transistors are all NMOS transistors, but PMOS transistors can also be used to construct the differential input circuits D1 and D2.

[0037] In addition to the above, as shown in Patent Document 2, the transistors M1 and M2 that form a pair in the differential input circuit D1 can also be configured as known bipolar transistors. As exemplified in Patent Document 2, asymmetry in emitter size can be achieved by configuring the number of transistors in the pair M1 and M2 as n:m (n>m) and connecting them together to each emitter.

[0038] like Figure 1As shown, the first amplifier 1 includes a current adjustment unit 30. The current adjustment unit 30 adjusts the current flowing into the amplifier. Figure 2 The magnitudes of the currents in the first current source I1 and the second current source I2 are controlled. In this embodiment, as an example, when a voltage higher than the second current adjustment terminal TAIL2 is applied to the first current adjustment terminal TAIL1 of the first amplifier 1, the current flowing into the first current source I1 is made greater than the current flowing into the second current source I2 by the control of the current adjustment unit 30. As a result, the function of the differential input circuit D1 becomes dominant. The difference between the currents flowing into the two current sources I1 and I2 becomes a value corresponding to the potential difference between the first current adjustment terminal TAIL1 and the second current adjustment terminal TAIL2. On the other hand, when a voltage higher than the first current adjustment terminal TAIL1 is applied to the second current adjustment terminal TAIL2, the current flowing into the second current source I2 is made greater than the current flowing into the first current source I1 by the control of the current adjustment unit 30. As a result, the function of the differential input circuit D2 becomes dominant.

[0039] The monitoring amplifier 51 is configured as a known differential amplifier. The monitoring amplifier 51 includes a first monitoring terminal MON1, a second monitoring terminal MON2, a first output terminal MOD1, and a second output terminal MOD2.

[0040] The first monitoring terminal MON1 of the monitoring amplifier 51 is electrically connected to the first input terminal IN1 of the second amplifier 2. The second monitoring terminal MON2 is electrically connected to the first input terminal IN1 of the first amplifier 1.

[0041] The first output terminal MOD1 of the monitoring amplifier 51 is electrically connected to the first current adjustment terminal TALI1 of the first amplifier 1 and the second current adjustment terminal TAIL2 of the second amplifier 2. The second output terminal MOD2 is electrically connected to the second current adjustment terminal TAIL2 of the first amplifier 1 and the first current adjustment terminal TAIL1 of the second amplifier 2.

[0042] Consider the case where, under this structure, the potential of the output terminal OUT of the first amplifier 1 and the potential of the output terminal OUT of the second amplifier 2 are both reference voltages.

[0043] Since both the first amplifier 1 and the second amplifier 2 are differential amplifiers, ideally, the first input terminal IN1 of the first amplifier 1 and the first input terminal IN1 of the second amplifier 2 should be equal to the reference potential, which is the potential of the second input terminal IN2. However, in reality, due to the input offset voltages present in the first amplifier 1 and the second amplifier 2 respectively, the first input terminal IN1 of the first amplifier 1 and the first input terminal IN1 of the second amplifier 2 are not equal to the reference voltage. In this explanation, we consider the case where the potentials of both first input terminals IN1 are greater than the reference voltage, and the potential of the first input terminal IN1 of the first amplifier 1 is higher than the potential of the first input terminal IN1 of the second amplifier 2.

[0044] As described above, the second monitoring terminal MON2 of the monitoring amplifier 51 is connected to the first input terminal IN1 of the first amplifier 1, and the first monitoring terminal MON1 is connected to the first input terminal IN1 of the second amplifier 2. Therefore, the potential of the second monitoring terminal MON2 of the monitoring amplifier 51 is higher than the potential of the first monitoring terminal MON1. The monitoring amplifier 51 amplifies this potential difference and outputs it to the first output terminal MOD1 and the second output terminal MOD2. As a result, the potential of the second output terminal MOD2 of the monitoring amplifier 51 is higher than the potential of the first output terminal MOD1.

[0045] Focusing on the first amplifier 1, as described above, the first output terminal MOD1 of the monitoring amplifier 51 is connected to the first current adjustment terminal TAIL1 of the first amplifier 1, and the second output terminal MOD2 is connected to the second current adjustment terminal TAIL2 of the first amplifier 1. Therefore, in the first amplifier 1, the potential of the second current adjustment terminal TAIL2 is higher than the potential of the first current adjustment terminal TAIL1. As a result, in the first amplifier 1, the current flowing into the second current source I2 is controlled to be greater than the current flowing into the first current source I1. Consequently, in the first amplifier 1, since the function of the differential input circuit D2 is dominant, the input offset voltage of the first amplifier 1 decreases. Since the potential of the second input terminal IN2 in the first amplifier 1 is constant at the reference potential, the reduction in the input offset voltage means that the potential of the first input terminal IN1 of the first amplifier 1 decreases.

[0046] Focusing on the second amplifier 2, as described above, the first output terminal MOD1 of the monitoring amplifier 51 is connected to the second current adjustment terminal TAIL2 of the second amplifier 2, and the second output terminal MOD2 is connected to the first current adjustment terminal TAIL1 of the second amplifier 2. Therefore, in the second amplifier 2, the potential of the first current adjustment terminal TAIL1 is higher than the potential of the second current adjustment terminal TAIL2. Consequently, in the second amplifier 2, the current flowing into the first current source I1 is controlled to be greater than the current flowing into the second current source I2. As a result, in the second amplifier 2, since the function of the differential input circuit D1 is dominant, the input offset of the second amplifier 2 increases. Since the potential of the second input terminal IN2 in the second amplifier 2 is constant at the reference potential, the increase in the input offset voltage means that the potential of the first input terminal IN1 of the second amplifier 2 rises.

[0047] In this way, the potential difference between the first input terminal IN1 of the first amplifier 1 and the first input terminal IN1 of the second amplifier 2 decreases. Therefore, the potential difference between the second output terminal MOD2 and the first output terminal MOD1 of the monitoring amplifier 51 also approaches zero. Thus, as the potential difference between the first input terminals IN1 of the first amplifier 1 and the second input terminal IN1 of the second amplifier 2 decreases, the degree of current change in each of the first amplifier 1 and the second amplifier 2 weakens. Finally, when the potentials at the first input terminals IN1 of the first amplifier 1 and the first input terminals IN1 of the second amplifier 2 become equal, the multi-amplifier circuit 101 stabilizes in a balanced state.

[0048] The above description applies when the potential of the first input terminal IN1 of the first amplifier 1 is higher than the potential of the first input terminal IN1 of the second amplifier 2. Since the opposite potential only results in opposite operations, this description is omitted.

[0049] The above describes a balanced state where the multi-amplifier circuit 101 is in equilibrium when the potential of the first input terminal IN1 of the first amplifier 1 and the first input terminal IN1 of the second amplifier 2 are equal. However, in reality, an input offset voltage also exists in the monitoring amplifier 51. Therefore, the potential difference between the first monitoring terminal MON1 and the second monitoring terminal MON2 of the monitoring amplifier 51 is actually in equilibrium at a time when it is almost exactly the same as the input offset voltage. In other words, the potential difference between the first input terminal IN1 of the first amplifier 1 and the first input terminal IN1 of the second amplifier 2 in the equilibrium state is almost determined by the input offset voltage of the monitoring amplifier 51.

[0050] Secondly, the effects of the aforementioned features will be explained.

[0051] Consider a conventional structure where no input offset voltage adjustment is performed between the first amplifier 1 and the second amplifier 2. When σ represents the fluctuation (standard deviation) of the potential difference between the first input terminal IN1 and the second input terminal IN2 of each of the first amplifier 1 and the second amplifier 2, as described above, the fluctuation of the potential difference between the first input terminals IN1 of the two amplifiers 1 and 2 is (√2) × σ. On the other hand, in the structure of this embodiment, the potential difference between the first input terminal IN1 of the first amplifier 1 and the first input terminal IN1 of the second amplifier 2 is almost determined by the input offset voltage of the monitoring amplifier 51. Therefore, assuming that the fluctuation (standard deviation) between the first monitoring terminal MON1 and the second monitoring terminal MON2 of the monitoring amplifier 51 is equal to the aforementioned σ, the fluctuation of the potential difference between the first input terminal IN1 of the first amplifier 1 and the first input terminal IN1 of the second amplifier 2 is substantially σ. Therefore, the fluctuation that adversely affects measurement accuracy can be suppressed to approximately 1 / √2 = 70%.

[0052] Secondly, consider the situation where the input offset voltage of the amplifier is reduced by increasing the area of ​​the input transistors, and these transistors are much larger than other components, so only the layout area needs to be considered using these transistors. Since there are two transistors in the OP amplifier that require increased area, there are four in a typical P-amp. On the other hand, in the above embodiment, two are sufficient for the monitoring amplifier 51. Therefore, when the same layout area is given, in this embodiment, the input transistors can be formed with a multiple of the area. If the area is doubled, the fluctuation can be suppressed to about 1 / √2 = approximately 70%.

[0053] Therefore, although several conditions must be met, since (1 / √2) × (1 / √2) = 1 / 2, the fluctuation can be reduced to 50% in the same layout area through the combination of the above effects. Thus, the measurement accuracy can be effectively improved.

[0054] As described above, the multi-amplifier circuit 101 of this embodiment includes a first amplifier 1, a second amplifier 2, and a monitoring amplifier 51. The first amplifier 1 amplifies and outputs the differential voltages of the two inputs. The second amplifier 2 amplifies and outputs the differential voltages of the two inputs. Each of the first amplifier 1 and the second amplifier 2 includes a first differential input circuit D1, a second differential input circuit D2, and a current adjustment unit 30. The first differential input circuit D1 includes a pair of transistors that amplify and output the differential voltages of the two inputs. The first differential input circuit D1 has an asymmetric structure that generates an input offset voltage. The second differential input circuit D2 includes a pair of transistors that amplify and output the differential voltages of the two inputs to the first differential input circuit D1. The second differential input circuit D2 has an asymmetric structure that generates an input offset voltage that is opposite in sign to the input offset voltage of the first differential input circuit D1. The current adjustment unit 30 adjusts the current ratio of the currents flowing into the first differential input circuit D1 and the second differential input circuit D2. The monitoring amplifier 51 amplifies and outputs the differential voltage between one of the two inputs to the first amplifier 1 and one of the two inputs to the second amplifier 2. The current adjustment unit 30 adjusts the current ratio of the current flowing into the first differential input circuit D1 and the second differential input circuit D2 in response to the voltage output by the monitoring amplifier 51.

[0055] In this way, the difference in input offset voltage can be reduced between the first amplifier 1 and the second amplifier 2 based on the output of the monitoring amplifier 51. As a result, the accuracy of signal amplification can be improved.

[0056] In the multi-amplifier circuit 101 of this embodiment, both the first amplifier 1 and the second amplifier 2 include a first differential input circuit D1, a second differential input circuit D2, and a current adjustment unit 30.

[0057] This allows for effective adjustment of the input offset voltage difference.

[0058] In the multi-amplifier circuit 101 of this embodiment, as in Figure 2 As shown in the first example, the asymmetric structure in the first differential input circuit D1 and the second differential input circuit D2 can be achieved by making the device dimensions different between the transistors constituting the transistor pair. The difference in device dimensions can be achieved, for example, by making at least one of the channel width W and the channel length L in the transistor pair different.

[0059] At this point, a simple and miniaturized structure can be achieved for the multi-amplifier circuit 101.

[0060] However, as Figure 2As shown in the second and third examples, an asymmetric structure can be achieved by making the back gate potential in the transistor pair asymmetric. Furthermore, as shown in the fourth example, an asymmetric structure can be achieved by making the source resistance of the transistor pair asymmetric. Moreover, as mentioned above, an asymmetric structure can also be achieved by making the number of transistors in the transistor pair different from each other.

[0061] In the multi-amplifier circuit 101 of this embodiment, each of the first sensor 11 and the second sensor 12 is a photodiode that outputs current. Each of the first amplifier 1 and the second amplifier 2 is a transimpedance amplifier that converts the current output of the photodiode into a voltage signal.

[0062] This allows for the measurement of the current output by the photodiode with high accuracy.

[0063] Next, the second implementation method will be described. Figure 3 This is a circuit diagram showing the multi-amplifier circuit 102 according to the second embodiment. In the description following this embodiment, components that are the same or similar to those in the above embodiment are labeled with the same symbols in the drawings, and sometimes the description is omitted.

[0064] Figure 3 In the multi-amplifier circuit 102 of the second embodiment shown, the second amplifier 2 does not have the function of adjusting the input offset voltage.

[0065] The first amplifier 1 has only one current adjustment terminal TAIL. The monitoring amplifier 51 has only one output terminal MOD. The monitoring amplifier 51 amplifies and outputs the potential difference between the second monitoring terminal MON2 and the first monitoring terminal MON1. The output terminal MOD of the monitoring amplifier 51 is electrically connected to the current adjustment terminal TAIL.

[0066] In the first amplifier 1, if the potential of the current adjustment terminal TAIL is higher than the specified potential, the current adjustment unit 30 controls the current flowing into the second current source I2 to be greater than the current flowing into the first current source I1. Conversely, if the potential of the current adjustment terminal TAIL is lower than the specified potential, the current adjustment unit 30 controls the current flowing into the first current source I1 to be greater than the current flowing into the second current source I2.

[0067] Thus, the number of feedback paths from the monitoring amplifier 51 can be either one, or only one of the first amplifier 1 and the second amplifier 2 can have the function of adjusting the input offset voltage.

[0068] As described above, in the multi-amplifier circuit 102 of this embodiment, only the first amplifier 1 includes a first differential input circuit D1, a second differential input circuit D2, and a current adjustment unit 30.

[0069] This allows for the creation of a simple structure.

[0070] In the multi-amplifier circuit 102 of this embodiment, the first amplifier 1, including the current adjustment unit 30, includes a current adjustment terminal TAIL for inputting the voltage output by the monitoring amplifier 51. When the voltage input to the current adjustment terminal TAIL exceeds or falls below a predetermined value, the current adjustment unit 30 adjusts the current ratio of the currents flowing into the first differential input circuit D1 and the second differential input circuit D2, so that the magnitudes of the currents flowing into the first differential input circuit D1 and the second differential input circuit D2 are reversed.

[0071] This allows for the creation of a simple structure.

[0072] The multi-amplifier circuit 102 of this embodiment includes a second amplifier 2 that does not have an input offset voltage adjustment function, or the second amplifier 2 can be omitted and the input can be changed to any potential that is input to the first monitoring terminal MON1 of the monitoring amplifier 51.

[0073] Next, the third implementation method will be described. Figure 4 This is a circuit diagram showing the multi-amplifier circuit 103 of the third embodiment.

[0074] Figure 4 The multi-amplifier circuit 103 of the third embodiment shown includes a third amplifier 3. The first amplifier 1 does not have the function of adjusting the input offset voltage. Since the structure of the first amplifier 1 is the same as that of the second amplifier 2 in the second embodiment described above, its description is omitted.

[0075] The second amplifier 2 and the third amplifier 3 have the function of adjusting the input offset voltage. Since the structure of the second amplifier 2 and the third amplifier 3 is the same as that of the first amplifier 1 in the second embodiment described above, the description is omitted.

[0076] The third amplifier 3 includes a first input terminal IN1, a second input terminal IN2, an output terminal OUT, and a current adjustment terminal TAIL. The output terminal of the third sensor 13 is electrically connected to the first input terminal IN1. The first input terminal IN1 and the output terminal OUT are electrically connected via a third feedback resistor 23.

[0077] The multi-amplifier circuit 103 includes a first monitoring amplifier 51 and a second monitoring amplifier 52. Since the structures of the first monitoring amplifier 51 and the second monitoring amplifier 52 are the same as those of the monitoring amplifier 51 in the second embodiment described above, their descriptions are omitted.

[0078] The first monitoring terminal MON1 of the first monitoring amplifier 51 is electrically connected to the first input terminal IN1 of the second amplifier 2. The second monitoring terminal MON2 is electrically connected to the first input terminal IN1 of the first amplifier 1.

[0079] The first monitoring amplifier 51 amplifies the potential difference between the second monitoring terminal MON2 and the first monitoring terminal MON1, and outputs it as the potential of the output terminal MOD. The output terminal MOD of the first monitoring amplifier 51 is connected to the current adjustment terminal TAIL of the second amplifier 2.

[0080] The first monitoring terminal MON1 of the second monitoring amplifier 52 is electrically connected to the first input terminal IN1 of the third amplifier 3. The second monitoring terminal MON2 is electrically connected to the first input terminal IN1 of the first amplifier 1.

[0081] The second monitoring amplifier 52 amplifies the potential difference between the second monitoring terminal MON2 and the first monitoring terminal MON1, and outputs it as the potential of the output terminal MOD. The output terminal MOD of the second monitoring amplifier 52 is connected to the current adjustment terminal TAIL of the third amplifier 3.

[0082] The multi-amplifier circuit 103 of the third embodiment can reduce the difference in input offset voltage between the three amplifiers.

[0083] Next, the fourth implementation method will be described. Figure 5 This is a circuit diagram showing the multi-amplifier circuit 104 according to the fourth embodiment.

[0084] Compared to the second embodiment, Figure 5 The multi-amplifier circuit 104 of the fourth embodiment shown is modified to monitor the outputs of the first amplifier 1 and the second amplifier 2 by monitoring amplifier 51.

[0085] The output terminal OUT of the first amplifier 1 is electrically connected to the second monitoring terminal MON2 of the monitoring amplifier 51 via resistor 41. The output terminal OUT of the second amplifier 2 is electrically connected to the first monitoring terminal MON1 of the monitoring amplifier 51 via resistor 42. The first monitoring terminal MON1 and the second monitoring terminal MON2 are connected via capacitor 43.

[0086] The monitoring amplifier 51 amplifies the potential difference between the second monitoring terminal MON2 and the first monitoring terminal MON1, and outputs it as the potential of the output terminal MOD. The output terminal MOD of the first monitoring amplifier 51 is connected to the current adjustment terminal TAIL of the first amplifier 1.

[0087] The multi-amplifier circuit 104 of this embodiment can remove not only the difference in input offset voltage, but also the difference in DC noise generated by sensors 11 and 12. This embodiment is applicable to situations where the signals of the first amplifier 1 and the second amplifier 2 have frequency components and the signal, noise, and offset can be distinguished by frequency.

[0088] The preferred embodiments of the present invention have been described above, and the above structure can be modified, for example, as described below. These modifications can be made individually or in any combination.

[0089] exist Figure 2 Each example of the asymmetric structure described herein can be applied individually or in appropriate combinations.

[0090] In the second embodiment, instead of the first amplifier 1, only the second amplifier 2 has the function of adjusting the input offset voltage.

[0091] In the second embodiment, the monitoring amplifier 51 may also be configured to have two output terminals MOD1 and MOD2. The same applies in the third and fourth embodiments.

[0092] (Explanation of symbols) 1-First amplifier; 2-Second amplifier; 51-Monitoring amplifier; 101-104-Multi-amplifier circuit; D1-First differential input circuit; D2-Second differential input circuit; M1, M2-Transistors.

Claims

1. A multi-amplifier circuit, characterized in that: The multi-amplifier circuit includes a first amplifier, a second amplifier, and a monitoring amplifier. The first amplifier amplifies the differential voltages of the two inputs and outputs them, and the second amplifier amplifies the differential voltages of the two inputs and outputs them. At least one of the first amplifier and the second amplifier includes a first differential input circuit, a second differential input circuit, and a current adjustment unit. The first differential input circuit includes a pair of transistors that amplify the differential voltages of the two inputs and output them, and has an asymmetric structure that generates an input offset voltage. The second differential input circuit includes a pair of transistors that amplify the differential voltages of the two inputs to the first differential input circuit and output them, and has an asymmetric structure that generates an input offset voltage with the opposite sign to the input offset voltage of the first differential input circuit. The current adjustment unit adjusts the current ratio of the currents flowing into the first differential input circuit and the second differential input circuit. The monitoring amplifier amplifies the differential voltage between one of the two inputs of the first amplifier and one of the two inputs of the second amplifier and outputs it. The current adjustment unit adjusts the current ratio in response to the voltage output by the monitoring amplifier.

2. A multi-amplifier circuit, characterized in that: The multi-amplifier circuit includes a first amplifier, a second amplifier, and a monitoring amplifier. The first amplifier amplifies the differential voltages of the two inputs and outputs them, and the second amplifier amplifies the differential voltages of the two inputs and outputs them. At least one of the first amplifier and the second amplifier includes a first differential input circuit, a second differential input circuit, and a current adjustment unit. The first differential input circuit includes a pair of transistors that amplify the differential voltages of the two inputs and output them, and has an asymmetric structure that generates an input offset voltage. The second differential input circuit includes a pair of transistors that amplify the differential voltages of the two inputs to the first differential input circuit and output them, and has an asymmetric structure that generates an input offset voltage with the opposite sign to the input offset voltage of the first differential input circuit. The current adjustment unit adjusts the current ratio of the currents flowing into the first differential input circuit and the second differential input circuit. The monitoring amplifier amplifies and outputs the differential voltage between the outputs of the first amplifier and the second amplifier. The current adjustment unit adjusts the current ratio in response to the voltage output by the monitoring amplifier.

3. The multi-amplifier circuit according to claim 1 or 2, characterized in that: Both the first amplifier and the second amplifier include the first differential input circuit, the second differential input circuit, and the current adjustment unit.

4. The multi-amplifier circuit according to claim 1 or 2, characterized in that: Only one of the first amplifier and the second amplifier includes the first differential input circuit, the second differential input circuit, and the current adjustment unit.

5. The multi-amplifier circuit according to claim 1 or 2, characterized in that: The first amplifier or the second amplifier, including the current adjustment section, includes a current adjustment terminal for inputting the voltage output by the monitoring amplifier. When the voltage input to the current adjustment terminal exceeds or falls below a predetermined value, the current adjustment unit adjusts the current ratio so that the magnitudes of the currents flowing into the first differential input circuit and the second differential input circuit are reversed.

6. The multi-amplifier circuit according to claim 1 or 2, characterized in that: In each of the first differential input circuit and the second differential input circuit, the device sizes differ between the transistors constituting the transistor pair.

7. The multi-amplifier circuit according to claim 6, characterized in that: In each of the first differential input circuit and the second differential input circuit, at least one of the channel width W and the channel length L is different between the transistors constituting the transistor pair.

8. The multi-amplifier circuit according to claim 1 or 2, characterized in that: In each of the first differential input circuit and the second differential input circuit, the back gate potential in the transistor pair is asymmetrical.

9. The multi-amplifier circuit according to claim 1 or 2, characterized in that: In each of the first differential input circuit and the second differential input circuit, the source resistance of the transistor pair is asymmetrical.

10. The multi-amplifier circuit according to claim 1 or 2, characterized in that: In each of the first differential input circuit and the second differential input circuit, the number of transistors in the transistor pair is different.

11. The multi-amplifier circuit according to claim 1 or 2, characterized in that: Each of the first amplifier and the second amplifier is a transimpedance amplifier that converts the current output of a photodiode into a voltage signal.

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