Light detection device and electronic apparatus

Abstract

Provided is a light detection device capable of suppressing a decrease in quantum efficiency Qe while suppressing the generation of dark current. Specifically, the light detection device includes: a semiconductor substrate; a plurality of photoelectric conversion units formed in a two-dimensional array in the semiconductor substrate; a trench part which is formed in a region between the photoelectric conversion parts in the semiconductor substrate and has an opening at least on the back surface side; and a conductive film which is disposed inside the trench portion and to which a negative bias voltage is applied. Furthermore, a first portion of the conductive film, which is a portion located on the back surface side, includes: a first conductive film covering one of a pair of inner wall surfaces of the trench portion facing each other; and a second conductive film separated from the first conductive film and covering the other inner wall surface of the pair of inner wall surfaces. A second portion of the conductive film, which is a portion located on the front surface side, includes a blocking portion that blocks the inside of the trench portion.

Description

Technical Field

[0001] This technology (based on the technology disclosed herein) relates to optical detection devices and electronic devices. Background Technology

[0002] For example, a photodetector has been proposed in the past, comprising: a semiconductor substrate having a plurality of photoelectric conversion sections; a trench formed in the semiconductor substrate in a region between the photoelectric conversion sections; and a conductor embedded in the trench and subjected to a negative bias voltage (see, for example, Patent Document 1). In the photodetector disclosed in Patent Document 1, a negative bias voltage is applied to the conductor to make the periphery of the trench a high hole concentration state and suppress the generation of dark current. Citation List Patent documents

[0003] Patent Document 1: Japanese Patent No. 7279014 Summary of the Invention The technical problem to be solved by the present invention

[0004] However, in the light detection device disclosed in Patent Document 1, the conductor in the trench absorbs light. Therefore, the amount of incident light that is converted by the photoelectric conversion unit will be reduced, and there is a possibility that the quantum efficiency will decrease.

[0005] This disclosure aims to provide a light detection device and electronic device that can suppress the generation of dark current while also suppressing the reduction of quantum efficiency Qe. Technical solutions to the problem

[0006] The light detection device disclosed herein includes: (a) a semiconductor substrate having a first surface as a light receiving surface and a second surface on a side opposite to the first surface; (b) a plurality of photoelectric conversion portions formed in a two-dimensional array in the semiconductor substrate; (c) a trench portion formed in the semiconductor substrate in a region between the photoelectric conversion portions and having an opening at least on the first surface side; and (d) a conductor film disposed inside the trench portion and subjected to a negative bias voltage, characterized in that: (e) a first portion of the conductor film located on the first surface side includes: a first conductor film covering one of a pair of inner wall surfaces of the trench portion facing each other; and a second conductor film separated from the first conductor film and covering the other inner wall surface of the pair of inner wall surfaces, and a second portion of the conductor film located on the second surface side includes a blocking portion that blocks the interior of the trench portion.

[0007] The electronic device disclosed herein includes a photodetector comprising: (a) a semiconductor substrate having a first surface as a light-receiving surface and a second surface on a side opposite to the first surface; (b) a plurality of photoelectric conversion portions formed in a two-dimensional array in the semiconductor substrate; (c) a trench portion formed in the semiconductor substrate in a region between the photoelectric conversion portions and having an opening at least on the first surface side; and (d) a conductor film disposed inside the trench portion and subjected to a negative bias voltage, characterized in that: (e) a first portion of the conductor film located on the first surface side comprises: a first conductor film covering one of a pair of inner wall surfaces of the trench portion facing each other; and a second conductor film separated from the first conductor film and covering the other inner wall surface of the pair of inner wall surfaces, and a second portion of the conductor film located on the second surface side comprises a blocking portion that blocks the interior of the trench portion. Attached Figure Description

[0008] Figure 1 This is a diagram showing the overall structure of the solid-state camera device according to the first embodiment. Figure 2 This indicates the interception along the row direction. Figure 1 A diagram showing the cross-sectional structure of a solid-state camera device in the case of a semiconductor substrate. Figure 3 This is a diagram showing the overall structure of a solid-state camera device according to a modified example. Figure 4 This is a diagram showing the overall structure of a solid-state camera device according to a modified example. Figure 5 This is a diagram illustrating the method for forming the trench separation structure. Figure 6 This is a diagram illustrating the method for forming the trench separation structure. Figure 7 This is a diagram illustrating the method for forming the trench separation structure. Figure 8 This is a diagram illustrating the method for forming the trench separation structure. Figure 9 This is a diagram illustrating the method for forming the trench separation structure. Figure 10 This is a diagram showing the overall structure of a solid-state camera device according to a modified example. Figure 11 This is a diagram showing the cross-sectional structure of the voltage-applied structure. Figure 12 This is a magnified view of the negative bias region. Figure 13 This is an enlarged view showing the negative bias region according to the modified example. Figure 14 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a modified example. Figure 15 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a modified example. Figure 16 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a modified example. Figure 17 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a modified example. Figure 18 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a modified example. Figure 19 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a modified example. Figure 20 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a modified example. Figure 21 It shows along Figure 20 The diagram shows the cross-sectional structure of the solid-state camera device, taken from line AA. Figure 22 This is a diagram showing the cross-sectional construction of the voltage-applied structure according to a modified example. Figure 23 This is a diagram illustrating a schematic construction of an electronic device according to the second embodiment. Detailed Implementation

[0009] The following is for reference Figures 1 to 23 Examples of optical detection devices and electronic devices according to embodiments of this disclosure will be described. Embodiments of this disclosure will be described in the following order. Note that this disclosure is not limited to the examples below. Furthermore, the effects described in this specification are merely illustrative and not restrictive, and other additional effects may exist. 1. First Implementation Scheme: Solid State Camera Device 1-1 Overall Structure of Solid State Camera Device Structure of 1-2 key parts Methods for forming 1-3 trench separation structures 1-4 Voltage Application Structure 1-5 Variations 2. Second Implementation Plan: Application Examples of Electronic Devices

[0010] <1. First Implementation Plan> [1-1 Overall Structure of Solid State Camera Device] A description will be given of a solid-state camera device 1 (which may be broadly referred to as a "light detection device") according to a first embodiment of this disclosure. Figure 1 This is a diagram showing the overall structure of the solid-state camera device 1 according to the first embodiment. Figure 1 The solid-state camera device 1 in the image is a back-illuminated CMOS (complementary metal oxide semiconductor) image sensor. For example... Figure 23 As shown, the solid-state camera device 1 (1002) takes in imaging light (incident light) from the subject through the lens group 1001, converts the amount of incident light imaging on the imaging surface into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal. like Figure 1 As shown, the solid-state camera device 1 includes a pixel area 2, a vertical driving circuit 3, a column signal processing circuit 4, a horizontal driving circuit 5, an output circuit 6, and a control circuit 7.

[0011] Pixel region 2 includes a plurality of pixels 8 arranged in a two-dimensional array. Pixel 8 includes a plurality of photoelectric conversion units PD (see...). Figure 2 ) and multiple pixel transistors Tr (e.g., transfer transistors, reset transistors, amplification transistors, and selection transistors). For example, the vertical drive circuit 3 includes a shift register that sequentially selects each pixel 8 in the pixel region 2 row by row by sequentially outputting selection pulses to the pixel drive line 9, and outputs the pixel signal of the selected pixel 8 to the column signal processing circuit 4 via the vertical signal line 10. The pixel signal is a signal obtained based on the charge (e.g., electrons) generated by the photoelectric conversion unit PD.

[0012] For example, the column signal processing circuit 4 is configured for each column of pixels 8, and the column signal processing circuit 4 performs signal processing such as noise removal on a pixel-by-pixel column basis for the signal output from a row of pixels 8. As signal processing, for example, correlated double sampling processing for removing fixed-pattern noise inherent in the pixels, and analog-to-digital (AD) conversion processing can be employed. For example, the horizontal drive circuit 5 includes a shift register that sequentially selects the column signal processing circuit 4 by outputting horizontal scan pulses to the column signal processing circuit 4, and causes the selected column signal processing circuit 4 to output the processed pixel signal to the horizontal signal line 11.

[0013] The output circuit 6 performs various signal processing operations on the pixel signals sequentially output by the column signal processing circuit 4 via the horizontal signal line 11. For example, various digital signal processing techniques such as buffering, black level adjustment, and column difference correction can be employed for signal processing. Based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal (not shown), the control circuit 7 generates clock signals and control signals that serve as the operating references for the vertical drive circuit 3, the column signal processing circuit 4, the horizontal drive circuit 5, etc. Then, the control circuit 7 outputs the generated clock signals and control signals to the vertical drive circuit 3, the column signal processing circuit 4, the horizontal drive circuit 5, etc.

[0014] [Structure of the essential parts 1-2] Next, the structure of the solid-state camera device 1 will be described in detail. Figure 2 This indicates the interception along the row direction. Figure 1 A diagram showing the cross-sectional structure of the solid-state imaging device 1 in the case of the semiconductor substrate 12. like Figure 2 As shown, the solid-state imaging device 1 includes a semiconductor substrate 12, and a fixed charge film 13, an insulating film 14, a color filter 15, and an on-chip lens 16 are sequentially stacked on the light-receiving surface of the semiconductor substrate 12 (hereinafter also referred to as the "back side S1", and broadly as the "first surface"). Furthermore, a wiring layer 17 is arranged on the surface of the semiconductor substrate 12 opposite to the back side S1 (hereinafter also referred to as the "front side S2", and broadly as the "second surface").

[0015] For example, the semiconductor substrate 12 is a substrate formed of silicon (Si) or the like. In the semiconductor substrate 12, photoelectric conversion units (PDs) are formed in regions corresponding to each pixel 8. That is, multiple photoelectric conversion units (PDs) are arranged in a two-dimensional array in the semiconductor substrate 12. Each photoelectric conversion unit (PD) includes a p-type semiconductor region and an n-type semiconductor region. The photoelectric conversion unit (PD) uses a pn junction of these two semiconductor regions to form a photodiode, and the photoelectric conversion unit (PD) generates a charge corresponding to the amount of light received. Furthermore, the photoelectric conversion unit (PD) accumulates the charge (e.g., electrons) generated through photoelectric conversion into an electrostatic capacitance generated in the pn junction. Furthermore, a p-type well region (pwell) is formed in the region on the front side (S2) of the semiconductor substrate 12. A pixel transistor (Tr) is formed in the pwell region. The gate electrode 18 of the pixel transistor (Tr) is disposed on the front side (S2) through an insulating film 22.

[0016] Furthermore, in the semiconductor substrate 12, trench separation structures 20 are formed in the entire region between adjacent photoelectric conversion units (PDs). That is, the trench separation structures 20 are formed in a lattice pattern around each of the plurality of photoelectric conversion units (PDs). The trench separation structures 20 are formed to penetrate the semiconductor substrate 12 from the back side S1 to the front side S2. The trench separation structure 20 includes a trench portion 21 and an insulating film 22 and a conductive film 23 disposed in the trench portion 21. The trench portion 21 penetrates the semiconductor substrate 12 from the back side S1 to the front side S2, and the inner wall surface of the trench portion 21 forms the outline of the trench separation structure 20. That is, the trench portion 21 is formed in the region between the photoelectric conversion units (PDs) in the semiconductor substrate 12 and has an opening at least on the back side S1 side. Furthermore, an insulating film 24 is disposed within the end of the trench portion 21 on the front side S2 side to seal the interior of the trench portion 21.

[0017] Furthermore, the insulating film 22 is formed by a laminate of a fixed charge film 13 and an insulating film 25 other than the fixed charge film 13. That is, the fixed charge film 13 and the insulating film 25 are arranged sequentially from the inner wall side between the inner wall surface of the trench portion 21 and the conductive film 23. The fixed charge film 13 continuously covers the inner wall surface of the trench portion 21, the surface of the insulating film 24 located on the back side S1 (hereinafter also referred to as "back side S3"), and the back side S1 of the semiconductor substrate 12. Using the fixed charge film 13, holes (positive holes) can be induced on the trench separation structure 20 side of the semiconductor substrate 12, thus forming a portion with a high hole concentration state. Therefore, pinning of the inner wall surface of the trench portion 21 can be achieved, and the generation of dark current can be suppressed. As the material of the fixed charge film 13, for example, a high refractive index material film or a high dielectric film with a negative charge can be used. For example, the material can be an oxide or nitride containing at least one element selected from hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti). Furthermore, the insulating film 25 continuously covers the inner wall surface of the trench portion 21, which is covered by the fixed charge film 13, and the back surface S3 of the insulating film 24. Using the insulating film 25, the trench separation structure 20 can suppress charge migration from one side to the other between adjacent photoelectric conversion portions PD, and can suppress color mixing. For example, silicon oxide (SiO) can be used as the material of the insulating film 25.

[0018] Furthermore, the conductor film 23 is disposed within the internal space of the trench portion 21, which is already covered by the insulating film 22. The conductor film 23 also covers the inner wall surface of the trench portion 21 through the insulating film 22 (fixed charge film 13 and insulating film 25) inserted between the conductor film 23 and the inner wall surface of the trench portion 21. Specifically, the portion of the conductor film 23 located on the back side S1 (hereinafter also referred to as "first portion 26") includes a first conductor film 27 and a second conductor film 28. The first conductor film 27 covers one of the pair of inner wall surfaces S4 and S5 facing each other in the trench portion 21, and the second conductor film 28 covers the other inner wall surface S5. The first conductor film 27 and the second conductor film 28 are in the width direction of the trench portion 21 ( Figure 2 The conductor film 23 is separated from each other in the transverse direction (in the middle). With this arrangement, in the inner region of the trench portion 21, the conductor film 23 is not present at the center in the width direction of the region located on the back side S1 (hereinafter also referred to as "first region 29"), and a slit-like gap 30 extending along the thickness direction of the semiconductor substrate 12 and having a constant width is formed. The thickness t1 of the first conductor film 27 in the width direction of the trench portion 21 and the thickness t2 of the second conductor film 28 in the width direction of the trench portion 21 are designed to be the same. Furthermore, the ends of the insulating film 25, the first conductor film 27, and the second conductor film 28 located on the back side S1 ( Figure 2 The upper end of the fixed charge film 13 is formed closer to the front side S2 than the surface of the fixed charge film 13 located on the insulating film 14 side (hereinafter also referred to as "back side S6"). Figure 2 (Lower side of the middle). Through this arrangement, a slit-like gap 31 extending along the width direction of the groove portion 21 is formed on the insulating film 14 side of the first region 29.

[0019] Furthermore, the portion of the conductor film 23 located on the front side S2 (hereinafter also referred to as "second portion 32") has a blocking portion 33 for sealing off the interior of the trench portion 21. This blocking portion 33 is a space located in the region on the front side S2 of the interior region of the trench portion 21 (hereinafter also referred to as "second region 34"), and is arranged without gaps in the space enclosed by the inner wall surfaces S4 and S5 of the trench portion 21 and the back side S3 of the insulating film 24, separated by the insulating film 22. That is, the fixed charge film 13 and the insulating film 25 cover the end of the blocking portion 33 located on the front side S2. For example, the thickness t3 of the blocking portion 33 in the thickness direction of the semiconductor substrate 12 is 10 nm or more, preferably 20 nm or more, and more preferably 30 nm or more. Alternatively, for example, the thickness t3 is set to be greater than the thickness t1 (=t2) of the first conductor film 27. Furthermore, for example, the upper limit of the thickness t1 is 1 μm or less, preferably 900 nm or less, and more preferably 800 nm or less. Alternatively, for example, the upper limit of the thickness t1 is set to 1 / 4 or less of the thickness of the semiconductor substrate 12. As the material of the conductor film 23, for example, boron (B) doped amorphous silicon BDAS or boron (B) doped polycrystalline silicon B-poly can be used.

[0020] Furthermore, the portion of the conductor film 23 located on the outer periphery of the pixel region 2 is via a voltage application structure described below (see Figure 11 The portion is electrically connected to a negative bias voltage supply source and is subjected to a negative bias voltage. This negative bias voltage is transmitted from the outside of the pixel region 2 through the second portion 32 of the conductor film 23 to the center of the pixel region 2 and is applied to the conductor film 23 located at various points in the pixel region 2. Furthermore, the conductor film 23 to which the negative bias voltage is applied can cause the periphery of the trench separation structure 20 (i.e., the area in contact with the sidewall of the trench separation structure 20) to become a high hole concentration state via the first conductor film 27 and the second conductor film 28, and can suppress the generation of dark current.

[0021] The insulating film 14 continuously covers the back side S6 of the fixed charge film 13. As a material for the insulating film 14, silicon oxide (SiO2) or silicon nitride (SiN) can be used, for example. The color filters 15 are arranged in a two-dimensional array, such that one color filter 15 is provided for each photoelectric conversion unit PD. Each type of color filter 15 allows light of a specific wavelength to pass through, and the transmitted light is incident on the photoelectric conversion unit PD. For example, a Bayer array can be used as the array pattern of the color filters 15. Furthermore, waveguide walls 47 and inter-pixel light-shielding films 48 can be arranged between the color filters 15. The on-chip lenses 16 are arranged in a two-dimensional array, such that one on-chip lens 16 is provided for each photoelectric conversion unit PD. The on-chip lenses 16 converge the light from the object being photographed, and the converged light is incident on the photoelectric conversion unit PD through the color filter 15. The wiring layer 17 includes an interlayer insulating film (not shown) and a multilayer wiring (not shown) stacked with the interlayer insulating film in between, and drives the pixel transistors of each pixel 8 via the multilayer wiring.

[0022] In the solid-state imaging device 1 with the above-described structure, when light is incident from the back side S1 of the semiconductor substrate 12, the incident light passes through the on-chip lens 16, and the transmitted light is photoelectrically converted by the photoelectric conversion unit PD to generate charge (e.g., electrons). Subsequently, the generated charge is transmitted as a pixel signal from the vertical signal line 10 formed by the wiring of the wiring layer 17 (see... Figure 1 Output. Here, as Figure 3 As shown, for example, when the conductor film 23 is arranged without gaps inside the trench portion 21, the conductor film 23 inside the trench portion 21 will absorb light, and therefore, there is a possibility that the amount of incident light converted by the photoelectric conversion unit PD will decrease and the quantum efficiency Qe will decrease. In addition, such as Figure 4 As shown, for example, consider the following configuration: to reduce light absorption of the conductor film 23, the thickness of the conductor film 23 is reduced to decrease its volume. In this case, due to the reduction in the volume of the conductor film 23, the resistance of the negative bias voltage transmission path from the outside of the pixel region 2 to the center of the pixel region 2 increases, and there is a possibility that IR drop or RC delay will occur in the negative bias voltage due to the increase in resistance. Therefore, the negative bias voltage applied to the center of the pixel region 2 will decrease, and the dark current at the center of the pixel region 2 may increase.

[0023] In contrast, in the solid-state camera device 1 according to the first embodiment, such as Figure 2As shown, the portion of the conductor film 23 located on the back side S1 (first portion 26) includes a first conductor film 27 and a second conductor film 28. The first conductor film 27 covers one of the inner wall surfaces S4 and S5 of the trench portion 21 that face each other. The second conductor film 28 is separate from the first conductor film and covers the other inner wall surface S5 of the pair of inner wall surfaces. Furthermore, the portion of the conductor film 23 located on the front side S2 (second portion 32) has a blocking portion 33 that closes the interior of the trench portion 21. With this arrangement, the volume of the conductor film 23 on the back side S1 can be reduced, and the absorption of incident light by the conductor film 23 in the trench portion 21 can be reduced. Therefore, the amount of incident light that is photoelectrically converted by the photoelectric conversion unit PD can be increased, and the decrease in quantum efficiency Qe can be suppressed. Furthermore, the volume of the conductor film 23 located on the front side S2, where the photoelectric conversion unit PD absorbs the incident light and the incident light has difficulty reaching, can be increased, and the increase in resistance value of the negative bias voltage transmission path from the outside of the pixel region 2 to the center of the pixel region 2 can be suppressed. Based on this, the IR drop and RC delay of the negative bias voltage caused by the resistive component of the transmission path can be avoided, and the generation of dark current at the center of the pixel region 2 can be suppressed.

[0024] [Methods for forming 1-3 trench separation structures] Next, for Figure 2 The method for forming the groove separation structure 20 shown will be explained. First, such as Figure 5 As shown, a trench 21 is formed on the front side S2 of the semiconductor substrate 12. Then, polysilicon 35 and an insulating film 24 are buried within the trench 21. Subsequently, as... Figure 6 As shown, a wiring layer 17 is formed on the front side S2 of the semiconductor substrate 12. Subsequently, a polishing process such as chemical mechanical polishing (CMP) is performed on the back side S1 of the semiconductor substrate 12 to expose the polysilicon 35 and the trench portion 21 from the back side S1. Then, as... Figure 7 As shown, after removing the polysilicon 35, a fixed charge film 13 is formed, which continuously covers the inner wall surface of the trench portion 21, the back surface S3 of the insulating film 24, and the back surface S1 of the semiconductor substrate 12.

[0025] Subsequently, as Figure 8 As shown, an insulating film 25 is formed, which continuously covers the inner wall surface of the trench portion 21, which is covered by the fixed charge film 13, and the back surface S3 of the insulating film 24. For example, the insulating film 25 is formed using a low-temperature process such as atomic layer deposition (ALD). Subsequently, as... Figure 9As shown, a conductor film 23 is formed within the interior space of the trench portion 21, which is already covered by the insulating film 25. The conductor film 23 is formed to fill the second region 34 of the trench portion 21 in a void-free manner, while covering each of the pair of inner wall surfaces of the trench portion 21 facing each other in the first region 29 of the trench portion 21, and leaving a gap 30 at the center of the first region 29 in the width direction. For example, chemical vapor deposition (CVD) is used to form the conductor film 23. As a material for the conductor film 23, BDAS can be used, for example. Here, the film formation temperature of BDAS is 400°C. Through the above steps, the trench portion 21, the fixed charge film 13, the insulating film 25, and the conductive film 23 are formed in sequence, thus forming... Figure 2 The groove separation structure 20 shown.

[0026] Here, for example, if in such Figure 5 When the polysilicon 35 is buried as shown, and the conductor film 23 is formed and buried in a manner that replaces the polysilicon 35, boron (B) may diffuse from the material of the conductor film 23 (e.g., BDAS or B-poly) into the photoelectric conversion section PD due to the heat treatment required before forming the wiring layer 17. Therefore, there is a possibility that the volume of the n-type semiconductor region containing the photoelectric conversion section PD will decrease, and the saturation charge Qs of the photoelectric conversion section PD will decrease. Furthermore, if the above process is adopted, then there is a possibility, for example, that the material of the conductor film 23 (e.g., BDAS or B-poly) may migrate due to heat, and thus... Figure 10 As shown, the shape of the gap 30 changes from a slit to an elliptical shape (void structure), and a portion without the conductor film 23 appears on the inner wall surface of the trench 21. Therefore, it is possible that in the portion without the conductor film 23, the negative bias voltage cannot be applied to the inner wall surface of the trench 21, and the dark current will increase. Furthermore, for example, if BDAS is used as the material for conductor film 23 in the case of the above process, BDAS may be converted into polycrystalline silicon due to the heat of the heat treatment. Therefore, there is a possibility that the volume of BDAS (conductor film 23) will increase and the warping of the wafer will be exacerbated.

[0027] In contrast, according to the trench separation structure 20 formation method of the first embodiment, the conductor film 23 is formed into the trench portion 21 from the back side S1 side of the semiconductor substrate 12 after the wiring layer 17 is formed. Based on this, heat generated by heat treatment performed before the formation of the wiring layer 17 (e.g., heat treatment for repairing formation damage of the trench portion 21) can be avoided from acting on the conductor film 23, and boron (B) can be prevented from diffusing from the material of the conductor film 23 (e.g., BDAS or B-poly) into the photoelectric conversion portion PD. Therefore, a decrease in the saturation charge Qs of the photoelectric conversion portion PD can be avoided. Furthermore, since the heat generated by the aforementioned heat treatment does not act on the conductor film 23, material migration of the conductor film 23 can be prevented, and changes in the shape of the conductor film 23 can be suppressed. Therefore, a negative bias voltage can be appropriately applied to the inner wall surface of the trench portion 21, and the generation of dark current can be appropriately suppressed. Furthermore, since the heat generated by the aforementioned heat treatment does not act on the conductor film 23, it is possible to prevent the material of the conductor film 23 (BDAS) from transforming into polycrystalline silicon due to the heat of the heat treatment. Therefore, it is possible to avoid an increase in the volume of the BDAS (conductor film 23) and to prevent the aggravation of wafer warpage.

[0028] [1-4 Voltage Application Structure] Next, the structure for applying a negative bias voltage to the conductor film 23 (hereinafter also referred to as the "voltage application structure") will be described. Figure 11 This is a diagram showing the cross-sectional construction of the voltage-applied structure. Note that in... Figure 11 In, with Figure 2 Compared to the structure shown, the solid-state camera device 1 has some modifications, but a similar voltage application structure can also be applied. Figure 2 The solid-state camera device 1 shown is illustrated. Furthermore, a similar voltage application structure can also be applied to the solid-state camera device 1 according to the various modifications described below.

[0029] Figure 11An example of a solid-state imaging device 1 is shown, which is formed by sequentially stacking a first substrate 100, a second substrate 200, and a third substrate 300 from the light incident surface side of the solid-state imaging device 1. The first substrate 100 includes a semiconductor substrate 12, which includes a transfer transistor 36 and a floating diffusion section FD (generally referred to as a "charge storage section"). The transfer transistor 36 is used to transfer the charge obtained by photoelectric conversion by the photoelectric conversion section PD, and the floating diffusion section FD is used to store the charge transferred by the transfer transistor 36. The second substrate 200 includes a pixel transistor 37, which is used to read out the charge stored in the floating diffusion section FD. Examples of pixel transistors 37 for reading out the charge include a reset transistor, an amplification transistor, and a selection transistor. The third substrate 300 includes logic circuitry for processing pixel signals obtained based on the charge read out from the second substrate 200. Examples of logic circuitry include a vertical drive circuit 3, a column signal processing circuit 4, a horizontal drive circuit 5, an output circuit 6, and a control circuit 7 (see Figure 1 ).

[0030] In addition, Figure 11 In this semiconductor substrate 12, a p-type semiconductor region 38 is formed between the trench portion 21 and the photoelectric conversion portion PD, covering the sidewall surface of the trench separation structure 20. The p-type semiconductor region 38 is continuously formed from the back side S1 to the front side S2 of the semiconductor substrate 12. This arrangement increases the hole concentration around the trench separation structure 20 and further suppresses the generation of dark current. For example, the p-type semiconductor region 38 is formed by doping the inner wall surface of the trench portion 21 with boron (B) or the like after the trench portion 21 is formed. In addition, Figure 11 In this process, the insulating film 25 and the gap 31 inside the trench portion 21 are omitted, and in addition, the conductor film 23 is formed on the back side S1 of the semiconductor substrate 12.

[0031] like Figure 11 As shown, pixel region 2 includes: an effective pixel region 39; a light-shielding pixel region 40 surrounding the effective pixel region 39; and a negative bias region 41 surrounding the light-shielding pixel region 40. In the light-shielding pixel region 40, the on-chip lens 16 and color filter 15 are omitted. Furthermore, as... Figure 12 As shown, in the negative bias region 41, in addition to omitting the on-chip lens 16 and the color filter 15, various structures for acquiring pixel signals (such as on-chip lens 16, color filter 15, insulating film 14, fixed charge film 13, photoelectric conversion unit PD, transmission transistor 36, floating diffusion unit FD, pixel transistor Tr and pixel transistor 37, etc.) are also omitted. Figure 12 This is an enlarged view of the negative bias region 41. Furthermore, in the negative bias region 41, a side contact 42 is formed at the end of the trench portion 21 located on the front side S2. That is, the interior of the trench portion 21 has the following structure: the side contact 42, the insulating film 24, the insulating film 22, and the conductive film 23 are sequentially stacked from the front side S2 of the semiconductor substrate 12. The side contact 42 is formed without gaps inside the trench portion 21 and is electrically connected to each p-type semiconductor region 38 located on each inner wall surface of the trench portion 21. For example, doped polysilicon doped with boron (B) or the like can be used as the side contact 42. Furthermore, the side contact 42 protrudes from the interior of the trench portion 21 toward the second substrate 200. The end of the side contact 42 located on the second substrate 200 side is electrically connected to a contact via 43. The contact via 43 is a via extending from the second substrate 200 toward the first substrate 100 side and is electrically connected to a negative bias voltage supply source (not shown). With this arrangement, the side contact 42 enables the negative bias voltage to be transmitted from the contact via 43 to the side contact 42 and then to the p-type semiconductor region 38.

[0032] Furthermore, a light-shielding metal film 44 is disposed on the back side S1 of the semiconductor substrate 12 in both the light-shielding pixel region 40 and the negative bias region 41. The light-shielding metal film 44 blocks light from entering the photoelectric conversion unit PD in the light-shielding pixel region 40, and the pixel 8 in the light-shielding pixel region 40 can function as an OPB pixel (a pixel used for black level adjustment). Here, in the negative bias region 41 on the back side S1 of the semiconductor substrate 12, the insulating film 14 is omitted, and the back side S1 is further excavated by etching or the like, exposing the p-type semiconductor region 38 and the conductor film 23 from the back side S1 of the semiconductor substrate 12. Thus, in the negative bias region 41, the light-shielding metal film 44 is disposed on the back side S1 of the semiconductor substrate 12 and electrically connected to the p-type semiconductor region 38 and the conductor film 23 exposed from the back side S1 of the semiconductor substrate 12. Therefore, the light-shielding metal film 44 transmits the negative bias voltage from the p-type semiconductor region 38 to the conductor film 23. The material used for the light-shielding metal film 44 can be, for example, tungsten (W), aluminum (Al) or copper (Cu). With the above configuration, a voltage application structure for applying a negative bias voltage to the conductor film 23 is formed, and the negative bias voltage is transmitted from the negative bias voltage supply source to the contact via 43, then to the side contact 42, then to the p-type semiconductor region 38, then to the light-shielding metal film 44, and then to the conductor film 23.

[0033] Here, in adopting Figures 5 to 9 When the method shown in the diagram, which forms the conductor film 23 from the back side S1 of the semiconductor substrate 12 into the trench portion 21, is used as the method for forming the trench separation structure 20, it is impossible to attach the contact member 45 (see...). Figure 13It is arranged directly below the conductor film 23. For example, if a contact 45 is formed directly below the conductor film 23, then... Figure 6 In the step of removing polysilicon 35 shown, contact 45 (e.g., doped polysilicon) is also removed. Therefore, contact 45 cannot be used as a voltage application structure for applying a negative bias voltage. In contrast, according to the voltage application structure of the first embodiment, a negative bias voltage is applied to the conductor film 23 via the side contact 42, the p-type semiconductor region 38, and the light-shielding metal film 44. Furthermore, the side contact 42 is provided with an insulating film 24 between itself and the insulating film 22 inside the trench portion 21 and the conductor film 23. Therefore, the side contact 42 is protected by the insulating film 24, and... Figure 6 In the step of removing polysilicon 35 shown, the side contact 42 is not removed at the same time.

[0034] [1-5 Variations] (1) Note that although the first embodiment has described an example in which a BDAS film or a B-poly film is used as the conductor film 23, other constructions may also be used. For example, such as Figure 14 As shown, a transparent electrode film can be used as the conductor film 23. For example, an indium tin oxide (ITO) film can be used as the transparent electrode film. Here, the light absorption rate of the ITO film is lower than that of the BDAS film and the B-poly film. Therefore, for example, compared to the case where a BDAS film is used, the absorption of incident light by the conductor film 23 can be reduced, and the decrease in quantum efficiency Qe can be suppressed. Or, for example, such as Figure 15 As shown, a metal film can be used as the conductor film 23. For example, tungsten (W), aluminum (Al), or copper (Cu) can be used as the material for the metal film. Here, the resistivity of the metal film is lower than that of BDAS film, B-poly film, and ITO film. Therefore, compared to the case using BDAS film, IR drop and RC delay due to negative bias voltage can be avoided, and the generation of dark current at the center of pixel region 2 can be suppressed.

[0035] (2) Furthermore, although an example in which a single-layer film is used as the conductor film 23 has been described in the first embodiment, other constructions may also be employed. For example, such as Figure 16 As shown, a multilayer film can be obtained by stacking a transparent conductor film 50 and a conductor film other than the transparent conductor film 50 (hereinafter also referred to as "second conductor film 51"). Figure 16An example is shown where a second conductive film 51 and a transparent conductive film 50 are sequentially stacked from the inner wall side of the trench portion 21. For example, a BDAS film or a B-poly film can be used as the second conductive film 51. With this arrangement, the second conductive film 51 (BDAS film or B-poly film) can be thinned by an amount comparable to the thickness of the transparent conductive film 50. Therefore, for example, compared to using a single layer of BDAS film or a single layer of B-poly film as the conductive film 23, the absorption of incident light by the second conductive film 51 (BDAS film or B-poly film) can be suppressed, and the decrease in quantum efficiency Qe can be suppressed. Furthermore, for example, by increasing the thickness of the transparent conductive film 50, IR drop and RC delay of the negative bias voltage can be avoided, and the generation of dark current at the center of the pixel region 2 can be suppressed.

[0036] (3) Furthermore, although the first embodiment has described an example in which the insulating film 22 has a structure obtained by stacking the fixed charge film 13 and the insulating film 25, other structures may also be used. For example, such as Figure 17 As shown, the insulating film 22 can be formed solely of the fixed charge film 13. In other words, only the fixed charge film 13 is arranged between the inner wall surface of the trench portion 21 and the conductor film 23. With this arrangement, the insulating film 22 can be thinned, and the distance between the conductor film 23 and the portion of the trench separation structure 20 with a high hole concentration (hereinafter also referred to as the "peripheral portion") can be shortened. Therefore, the hole concentration in the peripheral portion can be increased, and the generation of dark current can be further suppressed.

[0037] (4) Furthermore, although an example in which the insulating film 25 has a uniform thickness has been described in the first embodiment, other configurations may also be used. For example, such as Figure 18 As shown, the thickness t4 of the portion of the insulating film 25 covering the end 46 on the front side S2 of the closure portion 33 can be greater than the thickness t5 of the portion of the insulating film 25 covering the inner wall surface of the trench portion 21. With this arrangement, the distance between the conductor film 23 and the floating diffuser FD in the p-type well region can be increased, and the effect of the negative bias voltage applied to the conductor film 23 on the floating diffuser FD can be reduced.

[0038] (5) Furthermore, although the first embodiment has described an example in which an on-chip lens 16 is formed for each photoelectric conversion unit PD, other configurations may also be used. For example, such as Figure 19 As shown, multiple shared on-chip lenses 16 can be provided, each shared on-chip lens 16 being formed for each block containing m×n photoelectric conversion units PD arranged in an m×n array (here, one of m and n is an integer greater than 2, and the other of m and n is an integer greater than 1). Figure 19 An example of a block formed by four photoelectric conversion units (PDs) arranged in a 2×2 array is shown. In this case, the color filter 15 is also formed as a shared type for each block. Because the on-chip lens 16 and the color filter 15 are both shared type, the phase difference signal can be obtained from the pixel signals of the four photoelectric conversion units (PDs). Note that in this configuration, each of the trench separation structures 20 arranged around the block and each of the trench separation structures 20 located between the photoelectric conversion units (PDs) within the block have a structure similar to the trench separation structure 20 of the first embodiment (i.e., a structure having a fixed charge film 13, an insulating film 25, and a conductive film 23).

[0039] (6) Furthermore, although an example in which each pixel 8 has a photoelectric conversion unit PD has been described in the first embodiment, other configurations may also be adopted. For example, such as Figure 20 and Figure 21 As shown, each pixel 8 may include two photoelectric conversion units PD1 and PD2. This arrangement, along with... Figure 19 The configuration shown is similar, comprising multiple shared on-chip lenses 16, each formed for each block containing two photoelectric conversion units PD1 and PD2 arranged in a 1×2 array. Therefore, a phase difference signal can be obtained from the pixel signals of the two photoelectric conversion units PD1 and PD2. Figure 21 It shows along Figure 20 The diagram shows the cross-sectional structure of the solid-state camera device 1, taken from line AA. In addition, after adopting Figure 19 and Figure 20 In the case shown, including the on-chip lens 16 shared by m×n photoelectric conversion units (PDs), as Figure 21 As shown, the groove portion 21 may include a first groove portion 52 and a second groove portion 53, the first groove portion 52 surrounding m×n ( Figure 21 The second trench portion 53 is located between the photoelectric conversion portions PD1 and PD2 in the region surrounded by the first trench portion 52, and the second trench portion 53 may be a protrusion 54 protruding from the first trench portion 52 toward the region between the two adjacent photoelectric conversion portions PD1 and PD2. In this configuration, the trench separation structure 20 (including the first trench portion 52) provided around the pixel 8 and the trench separation structure 20 (including the second trench portion 53) located between the photoelectric conversion portions PD1 and PD2 in the pixel 8 each have a structure similar to the trench separation structure 20 of the first embodiment.

[0040] (7) Furthermore, although the first embodiment has described an example in which the space between the first conductor film 27 and the second conductor film 28 is a gap 30 (air), other configurations may also be used. For example, a film other than conductor film 23 may be arranged in the space between the first conductor film 27 and the second conductor film 28. The film other than conductor film 23 may be a film having a lower light absorption rate than conductor film 23.

[0041] (8) Furthermore, although the first embodiment has described an example of implementing an electrical connection between the conductor film 23 and the light-shielding metal film 44 only at the end of the conductor film 23 located on the side of the light-shielding metal film 44 in the negative bias region 41, other configurations may also be employed. For example, such as Figure 22 As shown, a back electrode 55 can be disposed in the negative bias region 41. This back electrode 55 protrudes from the light-shielding metal film 44 into the space between the first conductor film 27 and the second conductor film 28, filling the interior of that space. The back electrode 55 is arranged without gaps in the space between the first conductor film 27 and the second conductor film 28. This arrangement allows the conductor film 23 and the light-shielding metal film 44 to be electrically connected in a more suitable manner, and enhances contact performance. The back electrode 55 is formed of the same material as the light-shielding metal film 44 and is integrated with it.

[0042] (9) Furthermore, this technology is applicable to any light detection device, including not only the solid-state camera device 1 described above as an image sensor, but also a range sensor, also known as a time-of-flight (ToF) sensor, capable of measuring distance. The range sensor emits illumination light towards an object, detects the reflected light after the illumination light is reflected from the surface of the object, and calculates the distance to the object based on the time of flight from the emission of the illumination light to the reception of the reflected light. The light-receiving pixel structure of the range sensor can adopt the structure of pixel 8 described above.

[0043] <2. Second Implementation Plan> The technology disclosed herein (the technology) can be applied to various electronic devices. Figure 23 This is a diagram illustrating an example of the schematic construction of a camera device (digital camera, camcorder, etc.) that is an electronic device to which this technology is applied. like Figure 23 As shown, the camera device 1000 includes a lens group 1001, a solid-state camera device 1002 (solid-state camera device 1 according to the first embodiment), a signal processing circuit 1003, a memory 1004, and a monitor 1005. The signal processing circuit 1003, the memory 1004, and the monitor 1005 are interconnected via a bus 1006.

[0044] The lens group 1001 guides the incident light (imaging light) from the subject to the solid-state imaging device 1002 so that it forms an image on the light receiving surface (pixel area) of the solid-state imaging device 1002. The solid-state imaging device 1002 is formed from the CMOS image sensor according to the first embodiment described above. The solid-state imaging device 1002 converts the amount of incident light imaged on the light receiving surface by the lens group 1001 into an electrical signal in units of pixels, and provides the electrical signal as a pixel signal to the signal processing circuit 1003. The signal processing circuit 1003 performs predetermined image processing on the pixel signals provided from the solid-state imaging device 1002. Then, the signal processing circuit 1003 stores the image signal after image processing in the memory 1004, and also causes the monitor 1005 to display the image of the subject based on the image signal. The memory 1004 is formed of flash memory or the like. In addition, the monitor 1005 is formed of a display device such as a liquid crystal panel or an organic electroluminescence (EL) panel.

[0045] Note that the electronic devices to which the solid-state camera device 1 is applicable are not limited to the camera device 1000, and the solid-state camera device 1 can also be applied to other electronic devices. Furthermore, as the solid-state camera device 1002, although the solid-state camera device 1 according to the first embodiment can be used, other configurations can also be adopted. For example, other light detection devices that apply this technology, such as the solid-state camera device 1 according to any one of the modifications (1) to (8) of the first embodiment, can be used.

[0046] Note that this technology can also have the following configurations. (1) A light detection device, comprising: A semiconductor substrate having a first surface as a light-receiving surface and a second surface on the side opposite to the first surface; Multiple photoelectric conversion units formed in a two-dimensional array in the semiconductor substrate; A trench formed in the semiconductor substrate between the photoelectric conversion portions, and having an opening at least on the first surface side; and A conductive film, disposed inside the trench, is subjected to a negative bias voltage. The first portion of the conductor film, located on the first surface side, includes: a first conductor film covering one of a pair of opposing inner wall surfaces of the trench; and a second conductor film separate from the first conductor film and covering the other of the pair of inner wall surfaces. The second part of the conductor film, which is located on the second surface side, includes a blocking portion that closes the interior of the trench portion. (2) The optical detection device according to (1), wherein, The conductor film is a transparent electrode film. (3) The optical detection device according to (1) or (2), wherein, The conductor film is a metal film. (4) The optical detection device according to (1), wherein, The conductor film is a multilayer film, in which a transparent conductor film and conductor films other than the transparent conductor film are stacked. (5) The light detection apparatus according to any one of (1) to (4), wherein, Between the inner wall surface of the groove and the conductor film, a fixed charge film and an insulating film with negative charge are arranged sequentially from the inner wall surface side. (6) The optical detection device according to (5), wherein, The fixed charge film and the insulating film cover the end of the second surface side of the occluded portion, and The thickness of the portion of the insulating film covering the second surface side of the occluded portion is greater than the thickness of the portion of the insulating film covering the inner wall surface of the groove portion. (7) The light detection apparatus according to any one of (1) to (4), wherein, Between the inner wall surface of the groove and the conductor film, only a fixed charge film with a negative charge is arranged. (8) The light detection apparatus according to any one of (1) to (7) further comprises: Multiple shared on-chip lenses are formed for each block containing m×n photoelectric conversion units arranged in an m×n array, where one of m and n is an integer greater than 2, and the other of m and n is an integer greater than 1. (9) The optical detection device according to (8), wherein, The trench portion includes: a first trench portion surrounding the m×n photoelectric conversion units; and a second trench portion located between the photoelectric conversion units within the region surrounded by the first trench portion. Furthermore, the second groove portion includes a protrusion that protrudes from the first groove portion into the region between two adjacent photoelectric conversion portions among the plurality of photoelectric conversion portions. (10) The light detection apparatus according to any one of (1) to (9), wherein, The semiconductor substrate includes a transfer transistor and a charge storage section. The transfer transistor transfers the charge obtained by photoelectric conversion by the photoelectric conversion section, and the charge storage section stores the charge transferred by the transfer transistor. The optical detection device further includes: A first substrate, comprising the semiconductor substrate; and A second substrate includes a pixel transistor for reading the charge stored in the charge storage portion of the semiconductor substrate, the second substrate being stacked on the first substrate. (11) The light detection apparatus according to any one of (1) to (10) further comprises: A p-type semiconductor region is formed between the trench and the photoelectric conversion section; and A light-shielding metal film is disposed on the first surface side of the semiconductor substrate in the region surrounding the effective pixel region, and electrically connects the p-type semiconductor region to the conductor film. (12) The optical detection device according to (11) further includes: A side contact is formed at the end of the second surface side of the trench in the region surrounding the effective pixel region and is electrically connected to the p-type semiconductor region. (13) The light detection device according to (11) or (12) further includes: A back electrode protrudes from the light-shielding metal film into the space between the first conductor film and the second conductor film in the region surrounding the effective pixel area to fill the interior of the space. (14) An electronic device comprising a light detection device, the light detection device comprising: A semiconductor substrate having a first surface as a light-receiving surface and a second surface on the side opposite to the first surface; Multiple photoelectric conversion units formed in a two-dimensional array in the semiconductor substrate; A trench formed in the semiconductor substrate between the photoelectric conversion portions, and having an opening at least on the first surface side; and A conductive film, disposed inside the trench, is subjected to a negative bias voltage. The first portion of the conductor film, located on the first surface side, includes: a first conductor film covering one of a pair of opposing inner wall surfaces of the trench; and a second conductor film separate from the first conductor film and covering the other of the pair of inner wall surfaces. The second part of the conductor film, which is located on the second surface side, includes a blocking portion that closes the interior of the trench portion. Explanation of reference numerals in the attached figures

[0047] 1. Solid-state imaging device; 2. Pixel area; 3. Vertical driving circuit; 4. Column signal processing circuit; 5. Horizontal driving circuit; 6. Output circuit; 7. Control circuit; 8. Pixel; 9. Pixel driving line; 10. Vertical signal line; 11. Horizontal signal line; 12. Semiconductor substrate; 13. Fixed charge film; 14. Insulating film; 15. Color filter; 16. On-chip lens; 17. Wiring layer; 18. Gate electrode; 20. Trench separation structure; 21. Trench portion; 22. Insulating film; 23. Conductive film; 24. Insulating film; 25. Insulating film; 26. First part; 27. First conductive film; 28. Second conductive film. 29 First region, 30 Gap, 31 Gap, 32 Second part, 33 Blocking part, 34 Second region, 34, 35 Polysilicon, 36 Transmission transistor, 37 Pixel transistor, 38 Semiconductor region, 39 Effective pixel region, 40 Light-shielding pixel region, 41 Negative bias region, 42 Side contact, 43 Contact via, 44 Light-shielding metal film, 45 Contact, 50 Transparent conductor film, 51 Second conductor film, 52 First trench, 53 Second trench, 54 Protrusion, 55 Back electrode, 100 First substrate, 200 Second substrate, 300 Third substrate.

Claims

1. A light detection device, comprising: A semiconductor substrate having a first surface as a light-receiving surface and a second surface on the side opposite to the first surface; Multiple photoelectric conversion units formed in a two-dimensional array in the semiconductor substrate; A trench portion is formed in the semiconductor substrate in the region between the photoelectric conversion portions, and has an opening at least on the first surface side; as well as A conductive film, disposed inside the trench, is subjected to a negative bias voltage. The first portion of the conductor film, located on the first surface side, includes: a first conductor film covering one of a pair of inner wall surfaces facing each other in the trench; and a second conductor film separated from the first conductor film and covering the other inner wall surface of the pair of inner wall surfaces. The second part of the conductor film, which is located on the second surface side, includes a blocking portion that closes the interior of the trench portion.

2. The optical detection device according to claim 1, wherein, The conductor film is a transparent electrode film.

3. The optical detection device according to claim 1, wherein, The conductor film is a metal film.

4. The optical detection device according to claim 1, wherein, The conductor film is a multilayer film, in which a transparent conductor film and conductor films other than the transparent conductor film are stacked.

5. The optical detection device according to claim 1, wherein, Between the inner wall surface of the groove and the conductor film, a fixed charge film and an insulating film with negative charge are arranged sequentially from the inner wall surface side.

6. The optical detection device according to claim 5, wherein, The fixed charge film and the insulating film cover the end of the second surface side of the occluded portion, and The thickness of the portion of the insulating film covering the second surface side of the occluded portion is greater than the thickness of the portion of the insulating film covering the inner wall surface of the groove portion.

7. The optical detection device according to claim 1, wherein, Between the inner wall surface of the groove and the conductor film, only a fixed charge film with a negative charge is arranged.

8. The optical detection device according to claim 1, further comprising: Multiple shared on-chip lenses are formed for each block containing m×n photoelectric conversion units arranged in an m×n array, where one of m and n is an integer greater than 2, and the other of m and n is an integer greater than 1.

9. The optical detection device according to claim 8, wherein, The trench portion includes: a first trench portion surrounding the m×n photoelectric conversion units; and a second trench portion located between the photoelectric conversion units within the region surrounded by the first trench portion. Furthermore, the second groove portion includes a protrusion that protrudes from the first groove portion into the region between two adjacent photoelectric conversion portions among the plurality of photoelectric conversion portions.

10. The optical detection device according to claim 1, wherein, The semiconductor substrate includes a transfer transistor and a charge storage section. The transfer transistor transfers the charge obtained by photoelectric conversion by the photoelectric conversion section, and the charge storage section stores the charge transferred by the transfer transistor. The optical detection device further includes: A first substrate, comprising the semiconductor substrate; and A second substrate includes a pixel transistor for reading the charge stored in the charge storage portion of the semiconductor substrate, the second substrate being stacked on the first substrate.

11. The optical detection device according to claim 1, further comprising: A p-type semiconductor region is formed between the trench and the photoelectric conversion section; and A light-shielding metal film is disposed on the first surface side of the semiconductor substrate in the region surrounding the effective pixel region, and electrically connects the p-type semiconductor region to the conductor film.

12. The optical detection device according to claim 11, further comprising: A side contact is formed at the end of the second surface side of the trench in the region surrounding the effective pixel region and is electrically connected to the p-type semiconductor region.

13. The optical detection device according to claim 11, further comprising: A back electrode protrudes from the light-shielding metal film into the space between the first conductor film and the second conductor film in the region surrounding the effective pixel area to fill the interior of the space.

14. An electronic device comprising a light detection device, the light detection device comprising: A semiconductor substrate having a first surface as a light-receiving surface and a second surface on the side opposite to the first surface; Multiple photoelectric conversion units formed in a two-dimensional array in the semiconductor substrate; A trench portion is formed in the semiconductor substrate in the region between the photoelectric conversion portions, and has an opening at least on the first surface side; as well as A conductive film, disposed inside the trench, is subjected to a negative bias voltage. The first portion of the conductor film, located on the first surface side, includes: a first conductor film covering one of a pair of inner wall surfaces facing each other in the trench; and a second conductor film separated from the first conductor film and covering the other inner wall surface of the pair of inner wall surfaces. The second part of the conductor film, which is located on the second surface side, includes a blocking portion that closes the interior of the trench portion.

Images