Method for detecting stacking fault defect of heavily doped silicon wafer
By employing steps such as cleaning, chemical etching, CuSO4·5H2O solution coating, and heat treatment, the contrast of stacking fault defects in silicon wafers is exposed and enhanced. This solves the problems of high detection cost and low efficiency in existing technologies, achieving low-cost and high-precision detection results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-22
- Publication Date
- 2026-04-10
AI Technical Summary
Existing detection methods are difficult to accurately identify tiny stacking fault defects in heavily doped silicon wafers, and are costly and inefficient, failing to meet the automated and high-precision production requirements of semiconductor manufacturing.
Through steps such as cleaning, chemical etching, CuSO4·5H2O solution coating and heat treatment, and selective etching, the contrast of stacking fault defects in silicon wafers is revealed and enhanced, and finally macroscopic inspection is carried out in a darkroom.
It achieves low-cost and accurate detection of stacking fault defects, improving detection efficiency and accuracy.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of silicon wafer detection, and particularly relates to a detection method for stacking fault defects of heavily doped silicon wafer. BACKGROUND
[0002] Heavily doped silicon wafers are widely used in the manufacture of power semiconductors, integrated circuits and other devices due to their low resistivity, high conductivity and other characteristics. Stacking fault defects (ESF) are common crystal defects in the preparation process of heavily doped silicon wafers, which are mainly caused by crystal growth, slicing, grinding, polishing and other process links. The existence of ESF defects can seriously affect the electrical performance, reliability and service life of the device. Therefore, accurate detection of ESF defects in heavily doped silicon wafers is a key link to ensure the quality of semiconductor devices.
[0003] Currently, after the crystal bar is cut into silicon wafers after the crystal pulling is completed, the ESF defects are preliminarily detected at the front end. The detection methods of ESF defects mainly include chemical etching method, transmission electron microscope (TEM) method, infrared microscope method and the like. Among them, the chemical etching method is widely used in industrial detection due to its simple operation and low cost, but when it comes to heavily doped silicon wafers, the reaction rate of the etching solution and the surface of the silicon wafer is uneven due to the high carrier concentration, which leads to insufficient defect exposure and low contrast, making it difficult to accurately identify small SF defects; the TEM method has high detection accuracy, but the detection cost is high and the efficiency is low, which cannot meet the batch detection demand; the detection sensitivity of the infrared microscope method for heavily doped silicon wafers is significantly reduced due to the influence of the doping concentration of the silicon wafer.
[0004] Therefore, due to the problems such as high detection cost and large error of the existing detection methods, it is difficult to adapt to the automatic and high-precision production demand of semiconductor manufacturing. Therefore, it is of important industrial application value to develop a detection method for heavily doped silicon wafers with small detection error and low cost. SUMMARY
[0005] Therefore, in view of the above problems, it is necessary to provide a detection method for heavily doped silicon wafers with small detection error and low cost.
[0006] The technical scheme adopted by the present application to solve its technical problems is:
[0007] A detection method for stacking fault defects of heavily doped silicon wafer, comprising the following steps:
[0008] Step 1: cleaning the heavily doped silicon wafer to obtain a cleaned silicon wafer;
[0009] Step 2: chemically etching the cleaned silicon wafer to make the damage layer of the silicon wafer 200-300um to obtain an etched silicon wafer;
[0010] Step three: uniformly apply CuSO4·5H2O solution on the surface of the etched silicon wafer, and heat treat the etched silicon wafer uniformly applied with CuSO4·5H2O solution to obtain a decorated silicon wafer;
[0011] The heat treatment is that the etched silicon wafer uniformly applied with CuSO4·5H2O solution is heat treated at 35-45°C for 35-45 min, and then cleaned and dried to obtain the decorated silicon wafer.
[0012] Step four: preferentially etch the decorated silicon wafer to obtain a detection silicon wafer.
[0013] Step five: place the detection silicon wafer in a darkroom for macroscopic detection.
[0014] Preferably, in step three, the concentration of CuSO4·5H2O is 0.02-0.04 mol / L.
[0015] Preferably, in step two, the etching solution for chemical etching is composed of HF and HNO3, and the volume ratio of HF to HNO3 is 1:2-5.
[0016] Preferably, the chemical etching process needs to be continuously stirred, and the etching temperature is 20-35°C.
[0017] Preferably, the chemical etching process needs to etch the cleaned silicon wafer twice, and the second etching time is 1.5-3 times the first etching time.
[0018] Preferably, when the thickness of the cleaned silicon wafer is 0.5-1.0 mm, the first etching time is 10-120 s, and when the thickness of the cleaned silicon wafer is greater than 1 mm and less than or equal to 2.0 mm, the first etching time is 30-180 s.
[0019] Preferably, when the thickness of the cleaned silicon wafer is 0.5-1.0 mm, the second etching time is 2-3 times the first etching time, and when the thickness of the cleaned silicon wafer is greater than 1 mm and less than or equal to 2.0 mm, the second etching time is 1.5-2 times the first etching time.
[0020] Preferably, the first etching temperature is 20-30°C, and the second etching temperature is 25-35°C.
[0021] Preferably, the etching solution for preferential etching is secco solution or wright solution.
[0022] Preferably, the heavily doped silicon wafer is N-type or P-type.
[0023] Compared with the prior art, the present application has the following advantages:
[0024] The application provides a method for detecting stacking fault defects of a heavily doped silicon wafer, which comprises the following steps: cleaning a heavily doped silicon wafer to obtain a cleaned silicon wafer; performing chemical etching on the cleaned silicon wafer to make a damage layer of the silicon wafer be 200-300 um, and obtaining an etched silicon wafer; uniformly applying CuSO4·5H2O solution on the surface of the etched silicon wafer, and performing heat treatment on the etched silicon wafer with the uniformly applied CuSO4·5H2O solution at 35-45 DEG C for 35-45 min, and then cleaning and drying the etched silicon wafer to obtain a decorated silicon wafer; performing preferential etching on the decorated silicon wafer to obtain a detected silicon wafer; and performing macroscopic detection on the detected silicon wafer in a darkroom. Dirt and impurities on the surface of the silicon wafer are removed in advance by the above method, so that interference factors on the surface of the silicon wafer are removed, then chemical etching is performed to gradually expose stacking fault defects of the silicon wafer, then CuSO4·5H2O is applied and heat treatment is performed to perform copper decoration, so that the contrast between defects and the substrate is enhanced, then preferential etching is performed to expose the defects after enhancement, and then macroscopic detection of stacking fault defects can be performed in a darkroom, so that the detection cost is low, the result is accurate, and the detection efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1 The detection result of Example 1. DETAILED DESCRIPTION
[0026] In order to further understand the present application, the preferred embodiments of the present application are described below in conjunction with examples, but it should be understood that the description is only for further illustrating the features and advantages of the present application, and is not a limitation on the claims of the present application.
[0027] A method for detecting stacking fault defects of a heavily doped silicon wafer, characterized in that the method comprises the following steps:
[0028] Step one: cleaning a heavily doped silicon wafer to obtain a cleaned silicon wafer;
[0029] Step two: performing chemical etching on the cleaned silicon wafer to make a damage layer of the silicon wafer be 200-300 um, and obtaining an etched silicon wafer;
[0030] Step three: uniformly applying CuSO4·5H2O solution on the surface of the etched silicon wafer, and performing heat treatment on the etched silicon wafer with the uniformly applied CuSO4·5H2O solution to obtain a decorated silicon wafer;
[0031] The heat treatment is that the etched silicon wafer with the uniformly applied CuSO4·5H2O solution is heat treated at 35-45 DEG C for 35-45 min, and then the etched silicon wafer is cleaned and dried to obtain the decorated silicon wafer;
[0032] Step four: performing preferential etching on the decorated silicon wafer to obtain a detected silicon wafer;
[0033] Step five: place the detection silicon wafer in a dark room for macroscopic detection.
[0034] Compared with the prior art, the present application has the beneficial effects that:
[0035] The present application provides a method for detecting stacking fault defects of a heavily doped silicon wafer. The heavily doped silicon wafer is cleaned to obtain a cleaned silicon wafer. The cleaned silicon wafer is chemically etched so that the damage layer of the silicon wafer is 200-300 um, and an etched silicon wafer is obtained. The surface of the etched silicon wafer is uniformly coated with a CuSO4·5H2O solution. The etched silicon wafer with a uniformly coated CuSO4·5H2O solution is heat treated at 35-45℃ for 35-45 min. After the heat treatment, the etched silicon wafer is cleaned and dried to obtain a decorated silicon wafer. The decorated silicon wafer is preferentially etched to obtain a detection silicon wafer. Finally, the detection silicon wafer is placed in a dark room for macroscopic detection. The above method is used to pre-clean the dirt and impurities on the surface of the silicon wafer to remove the interference factors on the surface of the silicon wafer. Then, the silicon wafer is chemically etched to gradually expose the stacking fault defects of the silicon wafer. Then, CuSO4·5H2O is coated and heat treated to decorate the copper, thereby enhancing the contrast between the defects and the substrate. Finally, the preferential etching is performed to expose the enhanced defects, and the macroscopic detection of the stacking fault defects in the dark room is performed, thereby reducing the detection cost, improving the detection efficiency, and obtaining accurate results.
[0036] Further, in step three, the concentration of CuSO4·5H2O is 0.02-0.04 mol / L.
[0037] Further, in step two, the etching solution for chemical etching is composed of HF and HNO3, and the volume ratio of HF to HNO3 is 1:2-5. Preferably, the volume ratio of HF to HNO3 is 1:3.
[0038] Further, the chemical etching process needs to be continuously stirred, and the etching temperature is 20-35℃.
[0039] Further, the chemical etching process needs to be performed twice on the cleaned silicon wafer, and the second etching time is 1.5-3 times the first etching time.
[0040] In an embodiment, the chemical etching is performed by a full-automatic acid etching machine. The first etching is performed to remove the stains on the surface of the sample and other impurities attached to the surface of the cleaned silicon wafer. The second etching is performed to remove the damage layer and polish. If the one-time etching is directly performed, the polishing effect cannot be achieved.
[0041] Further, when the thickness of the silicon wafer is 0.5mm-1.0mm, the first etching time is 10s-120s, when the thickness of the silicon wafer is greater than 1mm and less than or equal to 2.0mm, the first etching time is 30s-180s.
[0042] Further, when the thickness of the silicon wafer is 0.5mm-1.0mm, the second etching time is 2-3 times of the first etching time, when the thickness of the silicon wafer is greater than 1mm and less than or equal to 2.0mm, the second etching time is 1.5-2 times of the first etching time.
[0043] Further, the first etching temperature is 20℃-30℃, the second etching temperature is 25℃-35℃, and the second etching temperature is greater than the first etching temperature, so as to improve the etching efficiency.
[0044] In an embodiment, when the volume ratio of HF and HNO3 is 1:3, the thickness of the silicon wafer, the etching number, the etching time and the etching temperature are shown in Table 1.
[0045] Table 1
[0046] By twice etching, the detection accuracy is improved.
[0047] In an embodiment, the etching liquid for the selective etching is secco liquid or wright liquid, the development effect of using secco liquid is good, the etching removal is more significant, and no shaking is needed, the temperature for the selective etching is 23-27℃, and the development effect of using wright liquid is not as good as that of secco liquid.
[0048] Specifically, the secco liquid is composed of 5-15g K2Cr2O7, 150-250ml H2O and 300-500ml HF, the mass concentration of the HF is 49%, the wright liquid is composed of CrO3 solution, Cu(NO3)2·3H2O solution, HNO3 solution, CH3COOH solution and HF solution with a mass concentration of 49%, wherein 45g CrO3, 90ml H2O are configured into CrO3 solution, 6g Cu(NO3)2·3H2O, 180ml H2O are configured into Cu(NO3)2·3H2O solution, 90ml HNO3 solution, 180ml CH3COOH solution and 180ml HF solution.
[0049] Further, the heavily doped silicon wafer is N-type or P-type.
[0050] In order to further understand the present application, the technical solutions of the present application are demonstrated by the following embodiments of the method of the present application.
[0051] Embodiment 1:
[0052] Step one: select P-type heavily doped silicon wafer with a doping concentration of 5*10 18 atoms / cm³, rinse with deionized water for 3 times, 3 min each time, and finally dry at 90°C in nitrogen atmosphere for 8 min to remove surface moisture, to obtain a cleaned silicon wafer.
[0053] Step two: configure a chemical etching solution, the volume ratio of the chemical etching solution is HF:HNO3=1:3; put the cleaned silicon wafer into the etching reaction tank of the full-automatic acid etching machine, and perform the first etching at 30°C for 20 s to remove the surface metamorphic layer; then continue to etch for 60 s while keeping the composition of the etching solution unchanged, so that the SF defects are preliminarily exposed; mechanical stirring is adopted during the etching process, and the stirring rate is 100 r / min, to obtain an etched silicon wafer.
[0054] Step three: configure a decoration solution, the composition is 0.03 mol / L CuSO4·5H2O; evenly smear the surface of the etched silicon wafer, and keep it at 40°C for 40 min to selectively deposit Cu atoms on the SF defects; after taking out, rinse with deionized water, and dry with an air gun, to obtain a decorated silicon wafer;
[0055] Step four: at room temperature, the decorated silicon wafer is subjected to preferential etching by secco solution to obtain a detection silicon wafer, the secco solution is composed of 5-15 g K2Cr2O7, 150-250 ml H2O, and 300-500 mL HF, and the mass concentration of the HF is 49%;
[0056] Step five: place the detection silicon wafer in a dark room to observe the surface state of the silicon wafer and determine (the copper precipitate with stacking fault defects is white, and the area without stacking fault defects is black, as shown in Figure 1 ).
[0057] As Figure 1 can be seen, the detection method of the present application can accurately detect stacking fault defects, improve detection efficiency, and reduce detection cost.
[0058] The above disclosure is only the preferred embodiments of the present application, and of course cannot limit the scope of the rights of the present application, and those skilled in the art can understand that the above-mentioned embodiments can be implemented in whole or in part, and equivalent changes made according to the claims of the present application still belong to the scope covered by the present application.
Claims
1. A method for detecting stacking fault defects in a heavily doped silicon wafer stack, characterized by, It comprises the following steps: Step one: cleaning the heavily doped silicon wafer to obtain a cleaned silicon wafer; Step two: chemically etching the cleaned silicon wafer to make the damage layer of the silicon wafer 200-300 um, and obtain an etched silicon wafer; Step three: uniformly applying CuSO4·5H2O solution on the surface of the etched silicon wafer, and heat treating the etched silicon wafer with the uniformly applied CuSO4·5H2O solution to obtain a decorated silicon wafer; The heat treatment is: heat treating the etched silicon wafer with the uniformly applied CuSO4·5H2O solution at 35-45℃ for 35-45 min, and cleaning and drying after the heat treatment to obtain the decorated silicon wafer; Step four: preferentially etching the decorated silicon wafer to obtain a test silicon wafer; Step five: placing the test silicon wafer in a darkroom for macroscopic detection.
2. The method of detecting stacking fault defects in a heavily doped silicon wafer of claim 1 wherein, In step three, the concentration of CuSO4·5H2O is 0.02-0.04 mol / L.
3. The method of claim 1, wherein the heavily doped silicon wafer is a silicon wafer having a stacking fault defect density of less than 5 x 105 cm"2. In step two, the etching solution for chemical etching is composed of HF and HNO3, and the volume ratio of HF to HNO3 is 1:2-5.
4. The method for detecting stacking fault defects in heavily doped silicon wafers as described in claim 3, characterized in that, The chemical etching process needs to be continuously stirred, and the etching temperature is 20-35℃.
5. The method for detecting stacking fault defects in heavily doped silicon wafers as described in claim 4, characterized in that, The chemical etching process needs to etch the cleaned silicon wafer twice, and the second etching time is 1.5-3 times the first etching time.
6. The method of detecting stacking fault defects in a heavily doped silicon wafer of claim 5, wherein the step of measuring the intensity of the light reflected from the heavily doped silicon wafer is performed by a spectrometer. When the thickness of the cleaned silicon wafer is 0.5-1.0 mm, the first etching time is 10-120 s, and when the thickness of the cleaned silicon wafer is greater than 1 mm and less than or equal to 2.0 mm, the first etching time is 30-180 s.
7. The method of detecting stacking fault defects in a heavily doped silicon wafer of claim 6 wherein, When the thickness of the cleaned silicon wafer is 0.5-1.0 mm, the second etching time is 2-3 times the first etching time, and when the thickness of the cleaned silicon wafer is greater than 1 mm and less than or equal to 2.0 mm, the second etching time is 1.5-2 times the first etching time.
8. The method of detecting stacking fault defects in a heavily doped silicon wafer of claim 5, wherein, The first etching temperature is 20-30℃, and the second etching temperature is 25-35℃.
9. The method of claim 1, wherein the heavily doped silicon wafer is a silicon wafer having a stacking fault defect density of less than 5 x 105 cm"2. The etching solution for preferential etching is secco solution or wright solution.
10. The method of claim 1 wherein the heavily doped silicon wafer is a silicon wafer having a stacking fault defect. The heavily doped silicon wafer is N-type or P-type.