Low-power-consumption method and device for achieving NVMeSSD entering and exiting L1.2 based on server mainboard and server

Abstract

The invention belongs to the technical field of SSD power consumption management, and particularly relates to a method and device for achieving low power consumption of an NVMeSSD entering and exiting L1.2 based on a server mainboard and a server. The method for achieving low power consumption of the NVMeSSD entering and exiting L1.2 based on the server mainboard is achieved by connecting one end of a PCIe adapter card with an NVME M.2 SSD and connecting the other end of the PCIe adapter card with the server mainboard. According to the method, related pins of a PCIe interface on the NVME M.2 SSD are controlled at a proper time, the NVME M.2 SSD can be controlled to enter an ASPM L1.2 low-power-consumption state, meanwhile, the PCIe adapter card can monitor the real-time voltage and current of the NVME M.2 SSD and confirm the ASPM L1.2 low-power-consumption state, and therefore low-power-consumption operation of the NVME M.2 SSD used by a server can be achieved, energy saving of the server can be achieved, the temperature of the NVME M.2 SSD is reduced, and the service life of the server is prolonged. Therefore, the hard disk can fully rest and the failure rate of the hard disk is reduced.

Description

Technical Field

[0001] This invention belongs to the field of SSD power management technology, specifically relating to a method, device, and server for implementing NVMeSSD entry and exit from L1.2 low power based on a server motherboard. Background Technology

[0002] With the widespread adoption of NVMe SSDs in the storage field, low-power SSD technology is becoming increasingly valuable in the consumer market. Low power consumption in SSDs can increase the standby time of mobile devices and significantly reduce platter temperature. The NVMe protocol defines several Power States (PS), commonly PS0, PS1, PS2, PS3, and PS4, with PS4 having the lowest power consumption, typically around 3mW. The PCIe protocol also defines an energy-saving mode, ASPM (Active State Power Management), which is divided into three states: L0, L0s, and L1. L1 has two sub-states: L1.1 and L1.2, with L1.2 having the lowest power consumption. However, currently only consumer-grade CPUs that support PCIe L1 sub-states can allow NVMe SSDs to reach the lowest power consumption of L1.2. Due to factors such as hardware configuration and power management strategies, server CPUs do not support PCIe L1.2, therefore NVMe SSDs cannot reach the lowest power consumption of L1.2 in server environments. Summary of the Invention

[0003] The present invention aims to provide a method, apparatus and server for enabling NVMeSSD to enter and exit L1.2 low power state based on a server motherboard, so as to enable NVMeSSD to enter and exit L1.2 low power state, thereby reducing the functionality and heat generation of NVMeSSD.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: This paper provides a method for implementing L1.2 low-power mode entry and exit of an NVMe SSD based on a server motherboard. The method uses a PCIe adapter card, with one end connected to the NVMe M.2 SSD and the other end connected to the server motherboard. Both the PCIe adapter card and the NVMe M.2 SSD support L1.2 low-power mode. The method includes two aspects: enabling the NVMe SSD to enter L1.2 low-power mode and enabling the NVMe SSD to exit L1.2 low-power mode. The process of enabling NVMe SSDs to enter L1.2 low power consumption includes: Disable the ASPM option on the server motherboard used for active state power management of NVMe M.2 SSDs; Send commands to the PCIe adapter card and the NVMe M.2 SSD to put them into ASPM L1.2 state; Set the power state of the NVMe M.2 SSD to PS4 and confirm. Confirm whether the NVMe M.2 SSD has entered the ASPM L1 state; Disable the clock request signal of the NVMe M.2 SSD and disable the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD; Confirm whether the NVME M.2 SSD has entered the ASPM L1.2 low-power state; The implementation of NVMe SSD exiting L1.2 low power consumption includes: Enable the clock request signal of the NVMe M.2 SSD, and enable the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD; Confirm whether the NVMe M.2 SSD has entered the ASPM L1 state; Wake up the NVMe M.2 SSD to ASPM L0 state; Confirm whether the NVME M.2 SSD has entered the ASPM L0 state.

[0005] Preferably, sending commands to the PCIe adapter card and the NVMe M.2 SSD to enter the ASPM L1.2 state includes: first sending a command to the PCIe adapter card and the NVMe M.2 SSD to enter the ASPM L1 state, and then sending a command to the PCIe adapter card and the NVMe M.2 SSD to enter the ASPM L1.2 state.

[0006] Preferably, the confirmation of whether the NVMe M.2 SSD has entered the ASPM L1 state includes: monitoring the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculating the power consumption value = voltage x current, and confirming whether the NVMe M.2 SSD has entered the ASPM L1 state through the power consumption value.

[0007] Preferably, the confirmation of whether the NVMe M.2 SSD has entered the ASPM L1.2 low-power state includes: reading the clock request signal of the NVMe M.2 SSD through the PCIe adapter card to confirm whether the NVMe M.2 SSD has entered the ASPM L1.2 low-power state; or, monitoring the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculating the power consumption value = voltage x current, and confirming whether the NVMe M.2 SSD has entered the ASPM L1.2 low-power state through the power consumption value. The process of confirming whether the NVMe M.2 SSD has entered the ASPM L0 state includes: monitoring the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculating the power consumption value = voltage x current, and confirming whether the NVMe M.2 SSD has entered the ASPM L0 state through the power consumption value.

[0008] Preferably, the PCIe adapter card is equipped with an FPGA controller.

[0009] This invention also provides a device for enabling NVMe SSDs to enter and exit L1.2 low-power mode based on a server motherboard. This device is used in a device consisting of a PCIe adapter card connected to an NVMe M.2 SSD at one end and a server motherboard at the other end. Both the PCIe adapter card and the NVMe M.2 SSD support L1.2 low-power mode. The device includes a module for enabling the NVMe SSD to enter L1.2 low-power mode and a module for enabling the NVMe SSD to exit L1.2 low-power mode, wherein: The implementation of NVMe SSD entering the L1.2 low-power module includes: The server ASPM option disable unit is used to disable the ASPM option used by the server motherboard for power management of NVMe M.2 SSD active state. The ASPM L1.2 state entry command unit is used to send commands to the PCIe adapter card and the NVME M.2 SSD to enter the ASPM L1.2 state. The PS4 status setting unit is used to control the power state of the NVMe M.2 SSD to be set to PS4 and confirm it. The first ASPM L1 status confirmation unit is used to confirm whether the NVME M.2 SSD has entered the ASPM L1 status. A clock request and clock signal shutdown unit is provided, which is used to shut down the clock request signal of the NVMe M.2 SSD and shut down the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD. The ASPM L1.2 low-power state verification unit is used to verify whether the NVME M.2 SSD has entered the ASPM L1.2 low-power state. The method for enabling NVMe SSDs to exit the L1.2 low-power module includes: A clock request and clock signal enable unit is provided, which is used to enable the clock request signal of the NVMe M.2 SSD and enable the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD. The second ASPM L1 status confirmation unit is used to confirm whether the NVME M.2 SSD has entered the ASPM L1 status. ASPM L0 wake-up unit, which is used to wake up the NVME M.2 SSD to ASPM L0 state; The ASPM L0 status confirmation unit is used to confirm whether the NVME M.2 SSD has entered the ASPM L0 status.

[0010] Preferably, the command unit for entering ASPM L1.2 state includes a command to enter ASPM L1 state subunit and a command to enter ASPM L1.2 state subunit, wherein the command to enter ASPM L1 state subunit is used to send a command to the PCIe adapter card and the NVME M.2 SSD to enter ASPM L1 state, and the command to enter ASPM L1.2 state subunit is used to send a command to the PCIe adapter card and the NVME M.2 SSD to enter ASPM L1.2 state.

[0011] Preferably, the first ASPM L1 status confirmation unit and the second ASPM L1 status confirmation unit monitor the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculate the power consumption value = voltage x current, and confirm whether the NVMe M.2 SSD has entered the ASPM L1 state through the power consumption value.

[0012] Preferably, the ASPM L1.2 low-power state confirmation unit reads the clock request signal of the NVME M.2 SSD through the PCIe adapter card to confirm whether the NVME M.2 SSD has entered the ASPM L1.2 low-power state; or, it monitors the voltage and current of the NVME M.2 SSD through the PCIe adapter card, calculates the power consumption value = voltage x current, and confirms whether the NVME M.2 SSD has entered the ASPM L1.2 low-power state through the power consumption value. The ASPM L0 status confirmation unit monitors the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculates the power consumption value = voltage x current, and confirms whether the NVMe M.2 SSD has entered the ASPM L0 state through the power consumption value.

[0013] The present invention also provides a server, wherein the server motherboard is connected to an NVMe SSD via a PCIe adapter card, and the server is capable of implementing the method described in any of the preceding claims for NVMe SSD to enter and exit L1.2 low power based on the server motherboard.

[0014] Compared with existing technologies, the beneficial effects of this invention are as follows: This method for enabling NVMe SSDs to enter and exit the ASPM L1.2 low-power state based on a server motherboard is achieved by connecting one end of a PCIe adapter card to the NVMe M.2 SSD and the other end to the server motherboard. By adding a PCIe adapter card, the relevant pins of the PCIe interface on the NVMe M.2 SSD can be controlled at appropriate times to control the NVMe M.2 SSD to enter the ASPM L1.2 low-power state. At the same time, the PCIe adapter card can monitor the real-time voltage and current of the NVMe M.2 SSD and confirm the ASPM L1.2 low-power state, thereby enabling the low-power operation of the NVMe M.2 SSD used in the server. This achieves server energy saving and reduces the temperature of the NVMe M.2 SSD platter, allowing the hard drive to rest fully and reducing the hard drive failure rate. Attached Figure Description

[0015] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart illustrating how an NVMeSSD enters and exits L1.2 low power mode based on a server motherboard, according to one embodiment of the present invention.

[0016] Figure 2This is a flowchart illustrating how an NVMeSSD exits L1.2 low power mode based on a server motherboard is implemented in one embodiment of the present invention.

[0017] Figure 3 This is a general architecture diagram of an embodiment of the device for implementing NVMeSSD entry and exit from L1.2 low power based on a server motherboard according to the present invention.

[0018] Figure 4 This is an architecture diagram of the NVMeSSD entering / exiting L1.2 low power module in one embodiment of the device for implementing NVMeSSD entry / exiting L1.2 low power based on a server motherboard according to the present invention.

[0019] Figure 5 This is an architecture diagram illustrating how an NVMeSSD exits the L1.2 low-power module in one embodiment of the device for implementing NVMeSSD entry and exit from L1.2 low-power mode based on a server motherboard according to the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] In one embodiment, a method for implementing L1.2 low-power state entry and exit of an NVMe SSD based on a server motherboard is provided. This method utilizes a PCIe adapter card, with one end connected to the NVMe M.2 SSD and the other end connected to the server motherboard. Both the PCIe adapter card and the NVMe M.2 SSD support L1.2 low-power state. The method includes two aspects: implementing L1.2 low-power state entry and exiting L1.2 low-power state entry for the NVMe SSD. like Figure 1 As shown, the method for implementing NVMeSSD entry and exit from L1.2 low power based on a server motherboard includes the following steps to achieve NVMeSSD entry into L1.2 low power: Step S101: Disable the ASPM option on the server motherboard used for NVMe M.2 SSD active state power management.

[0022] Step S102: Send commands to the PCIe adapter card and NVMe M.2 SSD to put them into ASPM L1.2 state.

[0023] Step S103: Set the power state of the NVMe M.2 SSD to PS4 and confirm.

[0024] Step S104: Confirm whether the NVME M.2 SSD has entered the ASPM L1 state.

[0025] Step S105: Turn off the clock request signal of the NVMe M.2 SSD and turn off the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD.

[0026] Step S106: Confirm whether the NVME M.2 SSD has entered the ASPM L1.2 low-power state.

[0027] In this embodiment, the PCIe adapter card used in the method for implementing NVMe SSD entry and exit from L1.2 low power based on a server motherboard is an adapter card capable of PCIe communication. Figure 3 As shown, the PCIe adapter card uses the PXDM2_230802001 board developed by Luanqi Technology. The NVMe M.2 SSD is a solid-state drive that uses the PCIe bus, M.2 interface, and transmits data via the NVMe protocol.

[0028] The ASPM option, which disables the server motherboard's power management for NVMe M.2 SSD activity, can be controlled by entering the server motherboard BIOS and executed by the server or PCIe adapter card.

[0029] After the PCIe adapter card and the NVMe M.2 SSD receive the command to enter ASPM L1.2 state, they can control most of the modules of the NVMe M.2 SSD to be in a power-down state, thus reducing power consumption. Setting the power state of the NVMe M.2 SSD to PS4 (Power State 4) puts the NVMe M.2 SSD into standby mode, but still retains some functions, such as the ability to be woken up by external signals. Entering ASPM L1.2 state requires the power supply of the NVMe M.2 SSD to be in PS4 state. After the clock signal is turned off, it will fully enter ASPM L1.2 state.

[0030] The ASPM L1.2 state is a sub-state of the ASPM L1 state and represents the lowest power consumption state. An NVMe M.2 SSD entering the ASPM L1.2 state will necessarily enter the ASPM L1 state. Monitoring the power consumption of the NVMe M.2 SSD can confirm whether it has entered the ASPM L1 state. After disabling the clock request signal and the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD, the NVMe M.2 SSD will fully enter the ASPM L1.2 state. The clock request signal is used by the NVMe M.2 SSD to request an external clock, and the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD is used for PCIe communication.

[0031] To confirm whether an NVMe M.2 SSD has entered the ASPM L1.2 low-power state, you can calculate the power consumption or read the clock request signal. If the NVMe M.2 SSD's power consumption is within the ASPM L1.2 low-power state range, or if the signal used by the NVMe M.2 SSD to request an external clock is in an unrequested state, then the NVMe M.2 SSD has entered the ASPM L1.2 low-power state.

[0032] like Figure 2 As shown, the method for implementing NVMeSSD entry and exit from L1.2 low power based on server motherboard includes the following steps for implementing NVMeSSD exit from L1.2 low power: Step S201: Enable the clock request signal of the NVMe M.2 SSD and enable the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD.

[0033] Step S202: Confirm whether the NVME M.2 SSD has entered the ASPM L1 state.

[0034] Step S203: Wake up the NVME M.2 SSD to ASPM L0 state.

[0035] Step S204: Confirm whether the NVME M.2 SSD has entered the ASPM L0 state.

[0036] After an NVMe SSD enters the L1.2 low-power state, it must have the ability to exit L1.2 low-power mode to ensure normal operation. In this embodiment, the steps for the NVMe SSD to exit L1.2 low-power mode are also implemented step by step. First, the clock signal of the PCIe link is enabled through a clock request signal. Then, power consumption is monitored to confirm whether the NVMe M.2 SSD has entered the ASPM L1 state, that is, to determine whether the NVMe M.2 SSD has entered the ASPM L1 state from the L1.2 low-power state. Compared to the L1.2 low-power state, although the NVMe M.2 SSD disables most functions in the L1 state, it still maintains the ability to quickly respond to commands. Therefore, when transitioning to the L1 state, a wake-up command is sent to the NVMe M.2 SSD to transition to the ASPM L0 state. Finally, power consumption is monitored to confirm whether the NVMe M.2 SSD has indeed entered the ASPM L0 state.

[0037] Optionally, in this method for implementing NVMe SSD entry and exit from ASPM L1.2 low-power mode based on a server motherboard, the preceding steps of sending commands to the PCIe adapter card and NVMe M.2 SSD to enter ASPM L1.2 state include: first sending a command to the PCIe adapter card and NVMe M.2 SSD to enter ASPM L1 state, and then sending a command to the PCIe adapter card and NVMe M.2 SSD to enter ASPM L1.2 state. That is, entering ASPM L1.2 state is also implemented step by step.

[0038] Optionally, in this method for implementing NVMe SSD entry and exit from L1.2 low power mode based on a server motherboard, the preceding confirmation of whether the NVMe M.2 SSD has entered the ASPM L1 state includes: monitoring the voltage and current of the NVMe M.2 SSD through a PCIe adapter card, calculating the power consumption value = voltage x current, and confirming whether the NVMe M.2 SSD has entered the ASPM L1 state based on the power consumption value. The PCIe adapter card is equipped with measurement circuitry for collecting the operating voltage and current of the NVMe M.2 SSD, thereby enabling the measurement of voltage and current data.

[0039] Optionally, in this method for implementing NVMe SSD entry and exit from ASPM L1.2 low power mode based on a server motherboard, the confirmation of whether the NVMe M.2 SSD has entered the ASPM L1.2 low power state includes: confirming whether the NVMe M.2 SSD has entered the ASPM L1.2 low power state by reading the clock request signal of the NVMe M.2 SSD through a PCIe adapter card; or, monitoring the voltage and current of the NVMe M.2 SSD through a PCIe adapter card, calculating the power consumption value = voltage x current, and confirming whether the NVMe M.2 SSD has entered the ASPM L1.2 low power state through the power consumption value. One of these two methods can be used, or both can be used simultaneously.

[0040] Confirming whether an NVMe M.2 SSD has entered the ASPM L0 state involves: monitoring the voltage and current of the NVMe M.2 SSD using a PCIe adapter card, calculating the power consumption value (voltage x current), and then using this power consumption value to confirm whether the NVMe M.2 SSD has entered the ASPM L0 state. The power consumption of the ASPM L0 state differs from that of the ASPM L1 state, so the ASPM L0 state can be identified through power consumption.

[0041] Optionally, in this method of implementing NVMeSSD entry and exit L1.2 low power based on server motherboard, the front PCIe adapter card is equipped with an FPGA controller. The FPGA controller is low in cost and flexible in configuration, making it suitable as a controller for intermediate boards.

[0042] As can be seen from the above embodiments, this method for implementing NVMe SSD entry and exit from L1.2 low power mode based on a server motherboard involves adding an FPGA PCIe adapter card. This adapter card, through the FPGA and external circuitry, controls the relevant pins of the PCIe interface on the NVMe M.2 SSD at appropriate times, thereby controlling the NVMe M.2 SSD to enter the ASPM L1.2 low power state. Simultaneously, the FPGA PCIe adapter card can monitor the real-time voltage and current of the NVMe M.2 SSD to confirm the ASPM L1.2 low power state.

[0043] In another embodiment, a device is provided for enabling NVMe SSDs to enter and exit L1.2 low-power mode based on a server motherboard. This device is used in a device consisting of a PCIe adapter card connected to an NVMe M.2 SSD at one end and a server motherboard at the other end. Both the PCIe adapter card and the NVMe M.2 SSD support L1.2 low-power mode. Figure 3As shown, the device includes 310 for enabling the NVMe SSD to enter the L1.2 low-power module and 320 for enabling the NVMe SSD to exit the L1.2 low-power module, wherein: like Figure 4 As shown, the NVMe SSD entering L1.2 low-power module 310 includes a server ASPM option disabling unit 311, an ASPM L1.2 state entry command unit 312, a PS4 state setting unit 313, a first ASPM L1 state confirmation unit 314, a clock request and clock signal disabling unit 315, and an ASPM L1.2 low-power state confirmation unit 316. The functions of each unit are as follows: The server ASPM option disabling unit 311 disables the ASPM option used by the server motherboard for power management of the NVMe M.2 SSD's active state; the command to enter ASPM L1.2 state unit 312 sends commands to the PCIe adapter card and the NVMe M.2 SSD to enter the ASPM L1.2 state; the PS4 state setting unit 313 controls the power state of the NVMe M.2 SSD to PS4 and confirms this; the ASPM L1 state confirmation unit 314 confirms whether the NVMe M.2 SSD has entered the ASPM L1 state; and the clock request and clock signal disabling unit 315 disables the NVMe M.2... The SSD clock request signal is turned off, and the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD is turned off; the ASPM L1.2 low power state confirmation unit 316 is used to confirm whether the NVMe M.2 SSD has entered the ASPM L1.2 low power state.

[0044] In this embodiment, the PCIe adapter card used in the device for implementing NVMe SSD entry and exit from L1.2 low power based on the server motherboard is an adapter card capable of PCIe communication. The PCIe adapter card adopts the PXDM2_230802001 board developed by Luanqi Technology. NVMe M.2 SSD is a solid-state drive that uses PCIe bus, M.2 interface and transmits data through NVMe protocol.

[0045] The ASPM option, which disables the server motherboard's power management for NVMe M.2 SSD activity, can be controlled via the server motherboard BIOS, executed by the server or PCIe adapter card. After receiving the command to enter ASPM L1.2 state, the PCIe adapter card and the NVMe M.2 SSD can control most modules of the NVMe M.2 SSD to be in a power-down state, thus reducing power consumption. Setting the NVMe M.2 SSD's power state to PS4 (Power State 4) puts it in standby mode, while still maintaining some functionality, such as the ability to be woken up by external signals. Entering ASPM L1.2 state requires the NVMe M.2 SSD's power supply to be in PS4 state. After disabling the clock signal, it fully enters ASPM L1.2 state. ASPM L1.2 state is a sub-state of ASPM L1 state and represents the lowest power consumption state. An NVMe M.2 SSD entering ASPM L1.2 state necessarily enters ASPM L1 state. Monitoring the NVMe M.2 SSD's power consumption can determine whether it has entered ASPM L1 state. After disabling the clock request signal and the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD, the NVMe M.2 SSD fully enters the ASPM L1.2 state. The clock request signal is used by the NVMe M.2 SSD to request an external clock signal, and the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD is used for PCIe communication. To confirm whether the NVMe M.2 SSD has entered the ASPM L1.2 low-power state, you can calculate the power consumption or read the clock request signal. If the NVMe M.2 SSD's power consumption is within the ASPM L1.2 low-power state range, or if the signal used by the NVMe M.2 SSD to request an external clock signal is in an unrequested state, then the NVMe M.2 SSD has entered the ASPM L1.2 low-power state.

[0046] like Figure 5As shown, the NVMe SSD exiting the L1.2 low-power module 320 includes a clock request and clock signal activation unit 321, a second ASPM L1 state confirmation unit 322, an ASPM L0 state wake-up unit 323, and an ASPM L0 state confirmation unit 324. The functions of each unit are as follows: the clock request and clock signal activation unit 321 is used to activate the clock request signal of the NVMe M.2 SSD and activate the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD; the second ASPM L1 state confirmation unit 322 is used to confirm whether the NVMe M.2 SSD has entered the ASPM L1 state; the ASPM L0 state wake-up unit 323 is used to wake up the NVMe M.2 SSD to the ASPM L0 state; and the ASPM L0 state confirmation unit 324 is used to confirm whether the NVMe M.2 SSD has entered the ASPM L0 state.

[0047] After an NVMe SSD enters the L1.2 low-power state, it must have the ability to exit L1.2 low-power mode to ensure normal operation. In this embodiment, the steps for the NVMe SSD to exit L1.2 low-power mode are also implemented step by step. First, the clock signal of the PCIe link is enabled through a clock request signal. Then, power consumption is monitored to confirm whether the NVMe M.2 SSD has entered the ASPM L1 state, that is, to determine whether the NVMe M.2 SSD has entered the ASPM L1 state from the L1.2 low-power state. Compared to the L1.2 low-power state, although the NVMe M.2 SSD disables most functions in the L1 state, it still maintains the ability to quickly respond to commands. Therefore, when transitioning to the L1 state, a wake-up command is sent to the NVMe M.2 SSD to transition to the ASPM L0 state. Finally, power consumption is monitored to confirm whether the NVMe M.2 SSD has indeed entered the ASPM L0 state.

[0048] Optionally, in this device for implementing NVMe SSD entry and exit from L1.2 low-power mode based on a server motherboard, the preceding ASPM L1.2 state entry command unit 312 includes an ASPM L1 state entry command subunit and an ASPM L1.2 state entry command subunit. The ASPM L1 state entry command subunit sends commands to the PCIe adapter card and the NVMe M.2 SSD to enter ASPM L1 state, while the ASPM L1.2 state entry command subunit sends commands to the PCIe adapter card and the NVMe M.2 SSD to enter ASPM L1.2 state. The ASPM L1 state entry command subunit and the ASPM L1.2 state entry command subunit can be deployed on the server or the PCIe adapter card, and the ASPM L1.2 state of the NVMe M.2 SSD can be achieved through gradual adjustments.

[0049] Optionally, the first ASPM L1 state confirmation unit 314 and the second ASPM L1 state confirmation unit 322 in the server motherboard-based device for implementing NVMe SSD entry and exit from L1.2 low power mode monitor the voltage and current of the NVMe M.2 SSD via a PCIe adapter card, calculate the power consumption value (voltage x current), and confirm whether the NVMe M.2 SSD has entered the ASPM L1 state based on the power consumption value. The PCIe adapter card is equipped with measurement circuitry for collecting the operating voltage and current of the NVMe M.2 SSD, thereby enabling the measurement of voltage and current data.

[0050] Optionally, the ASPM L1.2 low-power state confirmation unit 316 in this server motherboard-based device for implementing NVMe SSD entry and exit from L1.2 low-power states can confirm whether the NVMe M.2 SSD has entered the ASPM L1.2 low-power state by reading the clock request signal of the NVMe M.2 SSD through a PCIe adapter card; or, it can monitor the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculate the power consumption value = voltage x current, and confirm whether the NVMe M.2 SSD has entered the ASPM L1.2 low-power state based on the power consumption value. Either method or both can be used simultaneously.

[0051] The ASPM L0 status verification unit 324 monitors the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculates the power consumption value (voltage x current), and uses the power consumption value to confirm whether the NVMe M.2 SSD has entered the ASPM L0 state. The power consumption of the ASPM L0 state is different from that of the ASPM L1 state, so the ASPM L0 state can be identified by the power consumption.

[0052] Based on the above embodiments, it can be seen that the device for implementing NVMe SSD entry and exit from L1.2 low power mode based on a server motherboard is a functional module that can be executed jointly by the server and / or an added FPGA PCIe adapter card. During the execution of this device, the adapter card, through the FPGA and external circuitry, controls the relevant pins of the PCIe interface on the NVMe M.2 SSD at appropriate times, thereby controlling the NVMe M.2 SSD to enter the ASPM L1.2 low power state. Simultaneously, the FPGA PCIe adapter card can monitor the real-time voltage and current of the NVMe M.2 SSD to confirm the ASPM L1.2 low power state.

[0053] In another embodiment, a server is provided, wherein the server motherboard is connected to an NVMe M.2 SSD via a PCIe adapter card, and the server or / and the PCIe adapter card are provided with the device for implementing NVMe SSD entry and exit from L1.2 low power based on the server motherboard in the previous embodiment, thereby enabling the method for implementing NVMe SSD entry and exit from L1.2 low power based on the server motherboard in the previous embodiment.

[0054] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0055] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for implementing NVMe SSD entry and exit from L1.2 low power based on a server motherboard, characterized in that, This method is implemented by connecting an NVMe M.2 SSD to a PCIe adapter card at one end and the server motherboard at the other end. Both the PCIe adapter card and the NVMe M.2 SSD support L1.2 low-power state. The method includes two aspects: enabling the NVMe SSD to enter L1.2 low-power state and enabling the NVMe SSD to exit L1.2 low-power state. The process of enabling NVMe SSDs to enter L1.2 low power consumption includes: Disable the ASPM option on the server motherboard used for active state power management of NVMe M.2 SSDs; Send commands to the PCIe adapter card and the NVMe M.2 SSD to put them into ASPM L1.2 state; Set the power state of the NVMe M.2 SSD to PS4 and confirm. Confirm whether the NVMe M.2 SSD has entered the ASPM L1 state; Disable the clock request signal of the NVMe M.2 SSD and disable the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD; Confirm whether the NVME M.2 SSD has entered the ASPM L1.2 low-power state; The implementation of NVMe SSD exiting L1.2 low power consumption includes: Enable the clock request signal for the NVMe M.2 SSD, and enable the clock signal for the PCIe link between the PCIe adapter card and the NVMe M.2 SSD; Confirm whether the NVMe M.2 SSD has entered the ASPM L1 state; Wake up the NVMe M.2 SSD to ASPM L0 state; Confirm whether the NVME M.2 SSD has entered the ASPM L0 state.

2. The method for implementing NVMe SSD entry and exit from L1.2 low power mode based on a server motherboard according to claim 1, characterized in that, Sending commands to the PCIe adapter card and the NVMe M.2 SSD to enter ASPM L1.2 state includes: first sending a command to the PCIe adapter card and the NVMe M.2 SSD to enter ASPM L1 state, and then sending a command to the PCIe adapter card and the NVMe M.2 SSD to enter ASPM L1.2 state.

3. The method for implementing NVMe SSD entry and exit from L1.2 low power based on a server motherboard according to claim 1, characterized in that, The process of confirming whether the NVMe M.2 SSD has entered the ASPM L1 state includes: monitoring the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculating the power consumption value = voltage x current, and confirming whether the NVMe M.2 SSD has entered the ASPM L1 state through the power consumption value.

4. The method for implementing NVMe SSD entry and exit from L1.2 low power based on a server motherboard according to claim 1, characterized in that, The confirmation of whether the NVMe M.2 SSD has entered the ASPM L1.2 low-power state includes: reading the clock request signal of the NVMe M.2 SSD through the PCIe adapter card to confirm whether the NVMe M.2 SSD has entered the ASPM L1.2 low-power state; or, monitoring the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculating the power consumption value = voltage x current, and confirming whether the NVMe M.2 SSD has entered the ASPM L1.2 low-power state through the power consumption value. The process of confirming whether the NVMe M.2 SSD has entered the ASPM L0 state includes: monitoring the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculating the power consumption value = voltage x current, and confirming whether the NVMe M.2 SSD has entered the ASPM L0 state through the power consumption value.

5. The method for implementing NVMe SSD entry and exit from L1.2 low power based on a server motherboard according to claim 1, characterized in that, The PCIe adapter card is equipped with an FPGA controller.

6. A device for implementing NVMe SSD entry and exit from L1.2 low power based on a server motherboard, characterized in that, This device is designed for deployment on a system that uses a PCIe adapter card to connect an NVMe M.2 SSD at one end and a server motherboard at the other. Both the PCIe adapter card and the NVMe M.2 SSD support L1.2 low-power mode. The device includes features for enabling the NVMe SSD to enter and exit the L1.2 low-power mode, wherein: The implementation of NVMe SSD entering the L1.2 low-power module includes: The server ASPM option disable unit is used to disable the ASPM option used by the server motherboard for power management of NVMe M.2 SSD active state. The ASPM L1.2 state entry command unit is used to send commands to the PCIe adapter card and the NVME M.2 SSD to enter the ASPM L1.2 state. The PS4 status setting unit is used to control the power state of the NVMe M.2 SSD to be set to PS4 and confirm it. The first ASPM L1 status confirmation unit is used to confirm whether the NVME M.2 SSD has entered the ASPM L1 status. A clock request and clock signal shutdown unit is provided, which is used to shut down the clock request signal of the NVMe M.2 SSD and shut down the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD. ASPM L1.2 Low Power State Confirmation Unit: This ASPM L1.2 Low Power State Confirmation Unit is used to confirm whether the NVMEM.2 SSD has entered the ASPM L1.2 Low Power State. The method for enabling NVMe SSDs to exit the L1.2 low-power module includes: A clock request and clock signal enable unit is provided, which is used to enable the clock request signal of the NVMe M.2 SSD and enable the clock signal of the PCIe link between the PCIe adapter card and the NVMe M.2 SSD. The second ASPM L1 status confirmation unit is used to confirm whether the NVME M.2 SSD has entered the ASPM L1 status. ASPM L0 state wake-up unit, which is used to wake up the NVME M.2 SSD to ASPM L0 state; The ASPM L0 status confirmation unit is used to confirm whether the NVME M.2 SSD has entered the ASPM L0 status.

7. The apparatus for implementing NVMe SSD entry and exit from L1.2 low power based on a server motherboard according to claim 6, characterized in that, The command unit for entering ASPM L1.2 state includes a command to enter ASPM L1 state subunit and a command to enter ASPM L1.2 state subunit. The command to enter ASPM L1 state subunit is used to send commands to the PCIe adapter card and the NVME M.2 SSD to enter ASPM L1 state, and the command to enter ASPM L1.2 state subunit is used to send commands to the PCIe adapter card and the NVME M.2 SSD to enter ASPM L1.2 state.

8. The apparatus for implementing NVMe SSD entry and exit from L1.2 low power based on a server motherboard according to claim 6, characterized in that, The first ASPM L1 status confirmation unit and the second ASPM L1 status confirmation unit monitor the voltage and current of the NVME M.2 SSD through the PCIe adapter card, calculate the power consumption value = voltage x current, and confirm whether the NVME M.2 SSD has entered the ASPM L1 state through the power consumption value.

9. The apparatus for implementing NVMe SSD entry and exit from L1.2 low power based on a server motherboard according to claim 6, characterized in that, The ASPM L1.2 low-power state confirmation unit reads the clock request signal of the NVME M.2 SSD through the PCIe adapter card to confirm whether the NVME M.2 SSD has entered the ASPM L1.2 low-power state; or, it monitors the voltage and current of the NVME M.2 SSD through the PCIe adapter card, calculates the power consumption value = voltage x current, and confirms whether the NVME M.2 SSD has entered the ASPM L1.2 low-power state through the power consumption value. The ASPM L0 status confirmation unit monitors the voltage and current of the NVMe M.2 SSD through the PCIe adapter card, calculates the power consumption value = voltage x current, and confirms whether the NVMe M.2 SSD has entered the ASPM L0 state through the power consumption value.

10. A server, characterized in that, The server's motherboard is connected to an NVMe SSD via a PCIe adapter card, and the server is capable of implementing the method for entering and exiting L1.2 low power based on the server motherboard as described in any one of claims 1-5.

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