SATA disk array access method and system, electronic equipment and storage medium

Abstract

The invention provides an SATA (Serial Advanced Technology Attachment) disk array access method, which comprises the following steps of: acquiring write-in data of FIFO (First In First Out), carrying out circular detection on the data volume written in the FIFO based on a timestamp, initiating a file write-in application, and carrying out file distribution on the written-in data volume so as to correspondingly write the write-in data into an SATA write queue, the file distribution is based on disk information of each SATA disk, and the disk information at least comprises disk capacity and a relative wear factor; arbitrating each path of SATA write queue through an arbitration strategy, performing data caching on the arbitrated SATA write queue, and sending a write completion message; and reading the cached data according to the received write completion message, forming a cache queue, and transmitting the data in the cache queue to a rear-end SATA disk. According to the method, a multi-level storage strategy is adopted, so that the high-speed reliability and anti-risk capability of the multi-level cache can be improved, and the power consumption cost of the system is greatly saved.

Description

Technical Field

[0001] This application belongs to the field of satellite communication technology, and in particular relates to a SATA disk array access method, system, electronic device and storage medium. Background Technology

[0002] With the massive growth of network data streams, the demands on data caching capacity and throughput are increasing, posing unprecedented challenges to data storage. Therefore, flexible, efficient, and reliable high-capacity storage systems have become a key component of terrestrial communication systems, satellite communication systems, and data acquisition and storage systems.

[0003] Currently, in the field of satellite communication, considering the single-event effect caused by high-energy particles in storage systems, the mainstream storage system still adopts the storage mode of FPGA + NAND Flash. However, due to the limited single-chip capacity of NAND Flash and the lack of autonomous management capabilities, its system transmission rate is only a few Gbps, which cannot meet the requirements of tens of Gbps throughput. Furthermore, because NAND Flash occupies a large amount of space, it further limits its application in space-constrained scenarios.

[0004] The currently available satellite high-performance storage and data transmission integrated system based on a single SATA chip has improved the system capacity and has been verified in real-world scenarios. However, the storage system based on a single SATA chip limits the system's memory access throughput, and the storage of single or multi-SATA arrays does not take into account the management of the system's file system. Furthermore, the implementation scenarios are relatively limited and the scalability is poor.

[0005] The paper "Design and Implementation of Array Storage Strategy Based on Load Balancing" proposes a multi-disk storage scheme based on SATA disk health status monitoring. However, this scheme only provides test results and lacks specific implementation strategies. Patent number CN202411776147.X discloses a performance-balanced spaceborne dynamic array storage method, proposing a high-throughput storage scheme for payload systems. This scheme implements a high-throughput, high-data-volume merged storage scheme for 2711 / LVDS and Cameralink using a data merging storage approach. However, this scheme is highly dependent on interface design, and data storage between different payloads is strongly correlated, resulting in poor system scalability. Summary of the Invention

[0006] In view of this, this application aims to provide a SATA disk array access method, system, electronic device, and storage medium to solve at least one of the above-mentioned problems.

[0007] To achieve the above objectives, the technical solution of this application is implemented as follows: Firstly, this application provides a method for accessing a SATA disk array, including: The system acquires the data written to the FIFO and performs cyclic detection on the amount of data written to the FIFO based on the timestamp. Based on the detection results, it initiates a file write request and allocates files for the amount of data to be written to the corresponding SATA write queue. The file allocation is based on the disk information of each SATA disk, and the disk information includes at least the disk capacity and relative wear factor. Arbitration is performed on each SATA write queue using a preset arbitration strategy, and the arbitrated SATA write queue is buffered for data and a write completion message is sent. Based on the received write complete message, the cached data is read and a cache queue is formed. The data in the cache queue is then transferred to the backend SATA disk.

[0008] Secondly, based on the same inventive concept, this application also provides a SATA disk array access system for implementing the method described in the first aspect, including a write data parsing module, a file management system, a magnetoresistive random access memory, a write management module, a read management module, and a SATA controller. The write data parsing module is configured to cyclically detect the amount of data written to the FIFO based on the timestamp, initiate a file write request to the file management system based on the detection result, and write the write data to the SATA write queue according to the file allocation information issued by the file management system. The file management system is configured to determine whether the amount of data currently written to the FIFO can be stored in each SATA disk based on the relative wear factor and disk capacity. The magnetoresistive random access memory is configured to store a file information structure written to a SATA disk, wherein the file information structure includes disk information, file header information, and file content information. The write management module is configured to arbitrate each SATA write queue through a preset arbitration strategy, and cache the arbitrated SATA write queue to external memory. After the SATA write queue is cached to external memory, a write completion message is sent to the read management module. The read management module is configured to receive the write completion message sent by the write management module and read the cached data, and then transmit the cache queue formed by the cached data to the SATA disk through the SATA controller.

[0009] Thirdly, based on the same inventive concept, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described in the first aspect.

[0010] Fourthly, based on the same inventive concept, this application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions for causing the computer to perform the method as described in the first aspect.

[0011] Compared with existing technologies, the SATA disk array access method, system, electronic device, and storage medium described in this application have the following advantages: The SATA disk array access method described in this application shares a multi-level 6.0Gbps interface cache, is compatible with non-volatile cache, and detects the impact of spatial radiation. It can flexibly adjust the multi-level storage strategy in real time, which not only increases the reliability and risk resistance of the high speed of the multi-level cache, but also reduces the layout of the multi-level cache, greatly saving the system's size and power consumption costs. Attached Figure Description

[0012] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart of a SATA disk array access method according to an embodiment of this application; Figure 2 This is a schematic diagram of a SATA disk array access system structure according to an embodiment of this application; Figure 3 This is a diagram of the file system information structure described in the embodiments of this application; Figure 4 This is a schematic diagram of the operation flow of the write management module described in an embodiment of this application; Figure 5 This is a schematic diagram of the hardware structure of the electronic device described in an embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0014] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0015] The SATA disk array access method described in this embodiment is based on a high-performance multi-level shared storage architecture. This architecture can guarantee the sharing of multi-level storage and the reliability of stored data. It can provide signal storage for satellite communication practitioners, repair particle flips caused by space radiation, and facilitate testers to accurately respond to system communication data, thereby adjusting and improving the satellite status and promoting the progress of the entire satellite communication industry.

[0016] Furthermore, the application of high-performance multi-level shared storage architecture is not limited to multi-level storage sharing. In other cases, there are other types of spaceborne storage architectures that can store high-speed payload data signals or repair particle flips. However, at present, most spaceborne storage is limited by size and can only achieve single-level storage. The storage function is affected when the storage unit speed fluctuates, and the storage repair work for particle flip damage will completely lose data, resulting in poor risk resistance.

[0017] This embodiment provides a SATA disk array access method that, by sharing a multi-level 6.0Gbps interface cache, is compatible with non-volatile caches, detects the impact of spatial radiation, and flexibly adjusts the multi-level storage strategy in real time. This not only increases the reliability and resilience of the multi-level cache at high speeds, but also reduces the layout of the multi-level cache, greatly saving system size and power consumption costs.

[0018] The embodiments of this application are described in detail below with reference to the accompanying drawings.

[0019] Please see Figure 1 As shown in the figure, the SATA disk array access method described in this embodiment specifically includes the following steps: Step S101: Obtain the write data of the FIFO, and perform cyclic detection on the amount of data written to the FIFO based on the timestamp. Initiate a file write request based on the detection result, and allocate the write data to the corresponding SATA write queue. The file allocation is based on the disk information of each SATA disk, and the disk information includes at least the disk capacity and relative wear factor.

[0020] Specifically, in this embodiment, the data to be written is temporarily stored in a FIFO (First-In-First-Out) queue. The crucial "circular detection" mechanism monitors the data volume of the FIFO based on timestamps, checking whether the data volume within the window reaches a preset threshold. Once reached, a "file write request" is triggered, preparing to send a batch of data to the SATA write queue. This time-based triggering mechanism helps smooth I / O traffic and avoids sudden data surges impacting the backend disk.

[0021] In this step, file allocation based on disk information is the core of achieving "compatible multi-level data storage" and "real-time adjustment of multi-level storage strategies." Disk information includes: disk capacity, which ensures data is evenly distributed across all disks, preventing some disks from filling up prematurely; and wear factor, which can be derived from SSD wear leveling algorithms or estimated using SMART information. The system will prioritize writing data to SSDs with lower wear levels, thereby achieving wear leveling and extending the lifespan of the entire array.

[0022] Step S102: Arbitrate each SATA write queue using a preset arbitration strategy, cache the data of the arbitrated SATA write queue, and send a write completion message.

[0023] Specifically, in this embodiment, when multiple SATA write queues have data to be written at the same time, an arbitrator is needed to decide which queue to process first. After the arbitrator selects a SATA write queue, it will not immediately write the data to the physical disk, but will first cache the data in a cache (such as RAM). Once the data is successfully stored in the cache, the system will immediately send a write complete message.

[0024] This step allows the host or upstream system to quickly release resources and continue subsequent tasks, thereby greatly improving the system's response speed and high concurrency capabilities.

[0025] Step S103: Read the cached data according to the received write complete message, form a cache queue, and transfer the data in the cache queue to the backend SATA disk.

[0026] Specifically, in this embodiment, a background process or thread continuously listens for "write complete message". Once the message is received, the corresponding data block is read from the cache and added to another cache queue. The system then writes the data in the cache queue to the corresponding backend SATA disk in sequence.

[0027] This embodiment provides a high-performance SATA disk array access method that is compatible with multi-level data storage and can adjust multi-level storage strategies in real time to flexibly respond to storage unit speed fluctuations and correct errors caused by particle flipping.

[0028] In some implementations, the current timestamp of the data to be written is recorded as the write start time, and the amount of data written to the FIFO is detected to be ≥ n×2048 bytes or less than n×2048 bytes and the current timestamp minus the write start time is greater than a set threshold, in order to determine whether to initiate a file write request.

[0029] Specifically, in this embodiment, if it is possible to store FIFO data and the data capacity is ≥ n×2048, and if the current file size is 0, then the current file start time is set to the current timestamp, the file size corresponding to the MRAM is increased by n×2048 bytes, and the MRAM end time is updated to the current timestamp, where n represents the number of disks; If storage is possible and the FIFO data capacity is less than n×2048, and if the current file size is 0, then set the current file start time to the current timestamp, increase the FIFO data capacity by the file size corresponding to the MRAM, update the MRAM end time to the current timestamp, increment the current file write index number by 1, and set the new current file start time and file end time to the current timestamp, and set the file size to 0 bytes.

[0030] If the current write operation cannot be stored, the write operation is abandoned, and a file write error status is returned through the file allocation interface.

[0031] In some implementations, in response to initiating a file write request and the relative wear factor meeting a preset condition, it is determined whether the current disk array can accommodate the write data based on the disk capacity of the disk array. If the current disk array can accommodate new write data, the current write data is written to each SATA write queue in the order of disk access.

[0032] Specifically, in this embodiment, in response to initiating a file write request to the file management system, the relative wear factor of the current file management is obtained from the file management system, and it is determined whether the relative wear factor is equal to 1; if the relative wear factor = 1, the write operation is determined to have failed. If the relative wear factor ≠ 1, the capacity of the current disk array is obtained from the file management system, and it is determined whether the current disk array can accommodate the write data. If it can accommodate the write data, and if the current access times out, the current file write time and write capacity are updated, and the current data volume is written to the SATA1 / SATA2 / SATA3 / SATA4 write queues according to the disk access order; if it cannot accommodate the write data, the write operation is determined to have failed.

[0033] The relative wear factor is determined based on the SATA disk's SMART information, write throughput, and total written data volume. The SMART information includes single-disk temperature and single-disk CRC error rate. The relative wear factor α is expressed as: .

[0034] In some implementations, the arbitration strategy uses a polling priority approach, which polls each SATA write queue to check whether data has been written to the SATA write queue.

[0035] Specifically, in this embodiment, the n-way SATA write queues are arbitrated using a round-robin priority method. The arbitrated write queues are then written to the external DDR3 / DDR4 memory using a circular buffer method. To improve system throughput, the capacity of the circular buffer needs to be greater than 1Mbyte. The starting address of the circular buffer after power-on is set to the lowest address of each memory. After the corresponding queue is written to the external DDR3 / DDR4 memory, a write completion message (including which disk is being written to, the write start address, and the amount of data written) is sent to the backend.

[0036] This embodiment provides a SATA disk array access method that, by sharing a multi-level 6.0Gbps interface cache, is compatible with non-volatile caches, and detects the impact of spatial radiation, can flexibly adjust the multi-level storage strategy in real time. This not only increases the reliability and resilience of the multi-level cache at high speeds, but also reduces the layout of the multi-level cache, greatly saving system size and power consumption costs.

[0037] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0038] Based on the same inventive concept, and corresponding to the methods of any of the above embodiments, the embodiments of this application also provide a SATA disk array access system.

[0039] like Figure 2 As shown, the SATA disk array access system includes: It includes a write data parsing module, a file management system, a magnetoresistive random access memory, a write management module, a read management module, and a SATA controller; The write data parsing module is configured to cyclically detect the amount of data written to the FIFO based on the timestamp, and send a file write request to the file management system based on the detection result. Based on the file allocation information issued by the file management system, the write data is written to the corresponding SATA write queue. The file management system is configured to determine whether the amount of data currently being written to the FIFO can be stored on each SATA disk based on the relative wear factor and disk capacity. The magnetoresistive random access memory is configured to store the file information structure written to the SATA disk, wherein the file information structure includes disk information, file header information, and file content information; The write management module is configured to arbitrate each SATA write queue through a preset arbitration strategy, and cache the arbitrated SATA write queue to external memory. After the SATA write queue is cached to external memory, a write completion message is sent to the read management module. The read management module is configured to receive write completion messages sent by the write management module and read the cached data, then transfer the cached data to the SATA disk via the SATA controller to form a cache queue.

[0040] The SATA disk array access system described in this embodiment uses an MRAM-based file management system as its core. External data access first accesses the file system, and determines whether the current data can be written to the disk array based on the file system's wear factor and disk capacity. If it can be written, the write address of the currently accessed disk is obtained, improving the system's fault tolerance performance. The following explanation, in conjunction with the accompanying drawings, describes the various parts of this system: The system is configured with n SATA disks (i.e., SATA SSDs) to store high-throughput write data. It implements pure logical access to the SATA disks according to the SATA3.0 protocol, obtains the SMART information (including single disk temperature and single disk CRC check error rate), write throughput and total write data of each SATA disk, and calculates the relative wear factor of each SATA disk based on relevant parameters. If the wear factor of a certain SATA disk is 1, an alarm message is provided to the system and the operation is abandoned. One MRAM (Magnetic Reluctance Random Access Memory) is configured as the system's file management storage medium to store file status information written to the SATA disks and key parameters such as disk wear factors. The MRAM supports both parallel MRAM and serial MRAM. The information stored in the MRAM includes: status information of n SATA disks (SMART information, write throughput, total amount of data written, and wear factors of n SATA SSDs); capacity information of n SATA disks (write start sector index, write end sector index); and file status information (file name index number, file write start time, file write end time, file size, and file checksum). Configure DDR3 / DDR4 external storage as a SATA disk data write buffer; The system uses a FIFO interface for data storage. The minimum capacity of the FIFO can be n×2048 bytes. This FIFO interface is input to the data parsing module.

[0041] To elaborate further, after the write data parsing module detects the information from the file allocation interface, if the current data can be written to the subsequent n SATA drives, it writes the first 2048 bytes to the SATA1 write queue of the first SATA SSD, the second 2048 bytes to the SATA2 write queue of the second SATA SSD, and the nth 2048 bytes to the SATAn write queue of the nth SATA SSD. The aforementioned n SATA SSD write queues are connected to the DDR-based multi-disk FIFO write management. The write management module arbitrates the n SATA write queues coming from the front end using a round-robin priority method. Then, the arbitrated write queues are written to the external DDR3 / DDR4 memory using a circular buffer method. To improve system throughput, the capacity of the circular buffer needs to be greater than 1Mbyte. The starting address of the circular buffer after power-on is set to the lowest address of each circular memory. After the corresponding queue is written to the external DDR3 / DDR4 memory, a write completion message (including which disk is being written to, the write start address, and the amount of data written) is sent to the read management module.

[0042] After receiving the write completion message from the front end, the read management module records the message for each disk. Then, it waits for the storage queue of the subsequent SATA controller (i.e., SATAControl IP) to be able to accommodate the new content, and then reads the corresponding data from the DDR3 / DDR4 external memory into each storage queue. This cache queue is connected to the subsequent SATA Control IP, and the SATA Control IP transmits the data from the cache queue to the back-end SATA disk.

[0043] Implementation Case 1, using n=4 as an example, introduces the implementation case of the system.

[0044] The FIFO write operation was 4096 bytes, and this was the first write operation. The total disk capacity is 8,589,934,592 bytes, and the capacity of a single disk is 2,147,483,648 bytes. The file information structure diagram in this embodiment is as follows: Figure 3 As shown, the file information structure is stored in external MRAM. This structure mainly consists of three parts: disk information, file header information, and file content information. The disk information includes disk capacity, minimum write unit per disk, and wear factor (obtained from total written data volume, write throughput, single disk temperature, and single disk CRC error rate). Since this is the initial operation, the total written data volume is set to 0, the write throughput to 300 Mbps, the disk temperature is initialized to 50°C, and the disk wear factor is set to 0.

[0045] The file header information contains information about the currently stored files on the disk. The file header pointer points to the index of the first file written to the disk, and the file tail pointer points to the index of the next file written to the disk. In this embodiment, since there are no files to write to initially, both pointers are set to 0. The disk capacity occupied by the file in the file header information refers to the total disk capacity occupied by the written files, and the total amount of data in the current file in the file header information refers to the total amount of data written to the disk array. In this embodiment, the disk capacity occupied by the current file and the total amount of data in the current file are initially set to 0 because the system is empty.

[0046] The file content information stores the status information of each file. The status information of each file has a fixed length. In this embodiment, the file status information mainly includes the file write start time, file write end time, the initial write position of the file on the disk, and the size of the file. Since the file head pointer and file tail pointer are both 0 when the system is initially powered on, that is, the file to be operated on by the system next is file 0, all the status information of file 0 is set to 0 when the system is initially powered on.

[0047] In this embodiment, the write data parsing module detects that 4096 bytes of data have been written to the FIFO, records the current timestamp (assumed to be 0) as Y, and then performs cyclic detection on the amount of data written to the FIFO. Since only 4096 bytes of data need to be written in this embodiment, once the difference between the current timestamp and Y is detected to be greater than 1 second (the timeout time is set to 1 second in this embodiment), it indicates that 4096 bytes of the current file need to be written, and the write tail pointer needs to be updated after the current file is written. The write data parsing module, detecting a write data timeout and that the written data is not 0, initiates a query to the MRAM-based file management system. Since the wear and tear of all disk arrays in the current file management module is 0, and the file occupies 0 disk space, it indicates that the currently written data can be stored in the backend disk array.

[0048] In this embodiment, the written data can be automatically allocated to the written file according to the timeout policy, and the write start time, write start time and file size of the corresponding file are recorded, which simplifies the complexity of file management.

[0049] Next, the data parsing module sets the start time of file 0 to the current timestamp. Since the current write operation is less than 4 × 2048 = 8,192 bytes, the end time of file 0 is also set to the current timestamp, the start position of file 0 is set to 0, and the file size is set to 4096 bytes. Similarly, since the current write operation is less than 8192 bytes, this data is marked as the last write operation for the current file, so the file header's tail pointer is incremented by 1, i.e., the file header's tail pointer is set to 1. Again, since the current 4096 bytes need to be written to the disk, the total disk space occupied by the updated file header information is 8192 bytes (the smallest operation unit is 8192 bytes), and the total file data is set to 4096 bytes. The above operations complete the relevant content update of the MRAM-based file management system.

[0050] Next, the data parsing module reads 2048 bytes from the FIFO, then writes the read content and the address to be written (0 in this operation) to the SATA1 write queue. Then, it writes the remaining 2048 bytes and the address to be written (0 in this operation) to the SATA2 write queue. Since the above two operations have already read all 4096 bytes to be written to the FIFO, the SATA3 and SATA4 write queues are not updated. This indicates that data is only written to SATA1 and SATA2 in this operation.

[0051] In this real-time example, the write management module uses a polling pattern to write the four SATA data streams from the front end of the module to the external DDR3 / DDR4 memory. In this example, the external DDR3 / DDR4 memory has a capacity of 8 Mbytes. The SATA1 write queue is stored in location 0-1 Mbytes of the external DDR3 / DDR4 memory, the SATA2 write queue is stored in location 2-3 Mbytes, the SATA3 write queue is stored in location 4-5 Mbytes, and the SATA4 write queue is stored in location 6-7 Mbytes.

[0052] Upon power-up, the SATA1 write queue has a write position of 0 in external memory, while the SATA2 write queue has a write position of 2 Mbytes in external memory. A flowchart of the write management module's operation is shown below. Figure 4 As shown. The polling module first detects that the SATA1 write queue data is valid, then writes 2048 bytes of data from SATA1 to the memory starting at address 0 through the write data interface between this module and the external DDR3 / DDR4 memory. Once the SATA1 write queue has moved the data to the external DDR3 / DDR4 memory, a write completion message is generated. In this operation, the subsequent module generates a "SATA1 address 0 write 2048 bytes" message.

[0053] Next, the write management module queries the SATA2 write queue and finds 2048 bytes to be written to the external DDR3 / DDR4 buffer. It then reads these 2048 bytes from the SATA2 write queue and writes them to the DDR3 / DDR4 buffer at a start / end address of 2Mbytes via the write data interface. It then generates a "SATA2 2MByte address write 2048 bytes" message to the subsequent module. Next, the write management module continues to poll the SATA3 and SATA4 write queues for data. Since there is no data to write to these two queues, the module then polls the SATA1 through SATA4 write queues again.

[0054] After the read management module detects that the preceding write completion message queue is not empty, it reads the first message (i.e., "SATA1 0 address write 2048 bytes"), then reads 2048 bytes from address 0 of the DDR3 / DDR4 memory, writes this content to the SATA1 Control IP, and the SATA1 Control IP transfers this data to the external cache SATA1 disk. Similarly, since there are two write completion messages, it then retrieves the second message ("SATA2 2MByte address write 2048 bytes"), reads 2048 bytes from address 2Mbytes of the DDR3 / DDR4 memory, writes this content to the SATA2 Control IP, and the SATA2 Control IP transfers this data to the external cache SATA2 disk.

[0055] In this embodiment, the write operation of the multi-level disk array adopts an independent memory access queue, which can greatly improve the write performance of each disk, simplify the complexity of system memory access, and improve the reliability of pure logical access to multi-level disks.

[0056] For ease of description, the above system is described by dividing it into various modules based on their functions. Of course, in implementing the embodiments of this application, the functions of each module can be implemented in one or more software and / or hardware.

[0057] The system described in the above embodiments is used to implement the corresponding method in any of the foregoing embodiments and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0058] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, embodiments of this application also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the methods described in any of the above embodiments.

[0059] Figure 5 This embodiment illustrates a more specific hardware structure of an electronic device, which may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0060] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0061] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0062] The input / output interface 1030 is used to connect input / output modules to realize information input and output. The input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0063] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0064] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0065] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0066] The electronic devices described above are used to implement the corresponding methods in any of the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0067] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium that stores computer instructions for causing the computer to perform the methods described in any of the above embodiments.

[0068] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0069] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to perform the methods described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0070] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0071] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0072] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0073] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A method for accessing a SATA disk array, characterized in that, include: The system acquires the data written to the FIFO and performs cyclic detection on the amount of data written to the FIFO based on the timestamp. Based on the detection results, it initiates a file write request and allocates files for the amount of data to be written to the corresponding SATA write queue. The file allocation is based on the disk information of each SATA disk, and the disk information includes at least the disk capacity and relative wear factor. Arbitration is performed on each SATA write queue using a preset arbitration strategy, and the arbitrated SATA write queue is buffered for data and a write completion message is sent. Based on the received write complete message, the cached data is read and a cache queue is formed. The data in the cache queue is then transferred to the backend SATA disk.

2. The method according to claim 1, characterized in that: Record the current timestamp of the data to be written as the write start time, and check whether the amount of data written to the FIFO is greater than or equal to n×2048 bytes or less than n×2048 bytes and the current timestamp minus the write start time is greater than the set threshold, in order to determine whether to initiate a file write request.

3. The method according to claim 1, characterized in that: The relative wear factor is determined based on the SMART information, write throughput, and total amount of data written to the SATA disk. The SMART information includes the single disk temperature and the single disk CRC check error rate.

4. The method according to claim 3, characterized in that, The relative wear factor α is expressed as: 。 5. The method according to claim 1, characterized in that: In response to an initiated file write request, and provided that the relative wear factor meets a preset condition, determine whether the current disk array can accommodate the write data based on the disk capacity of the disk array. If the current disk array can accommodate new write data, the current write data is written to each of the SATA write queues in the order of disk access.

6. The method according to claim 1, characterized in that: The arbitration strategy adopts a polling priority method, which polls each SATA write queue according to the polling priority to check whether data has been written to the SATA write queue.

7. The method according to claim 6, characterized in that: The retrieved SATA write queues are written to external memory using a circular buffer pool method, and the starting address of the circular buffer pool after power-on is set to the lowest address of each memory.

8. A SATA disk array access system for implementing the method as described in any one of claims 1 to 7, characterized in that: It includes a write data parsing module, a file management system, a magnetoresistive random access memory, a write management module, a read management module, and a SATA controller; The write data parsing module is configured to cyclically detect the amount of data written to the FIFO based on the timestamp, initiate a file write request to the file management system based on the detection result, and write the write data to the SATA write queue according to the file allocation information issued by the file management system. The file management system is configured to determine whether the amount of data currently written to the FIFO can be stored in each SATA disk based on the relative wear factor and disk capacity. The magnetoresistive random access memory is configured to store a file information structure written to a SATA disk, wherein the file information structure includes disk information, file header information, and file content information. The write management module is configured to arbitrate each SATA write queue through a preset arbitration strategy, and cache the arbitrated SATA write queue to external memory. After the SATA write queue is cached to external memory, a write completion message is sent to the read management module. The read management module is configured to receive the write completion message sent by the write management module and read the cached data, and then transmit the cache queue formed by the cached data to the SATA disk through the SATA controller.

9. The system according to claim 8, characterized in that: The write data parsing module is also configured to record the current timestamp of the data to be written as the write start time, and to detect whether the amount of data written to the FIFO is ≥ n×2048 bytes or the amount of data written to the FIFO is less than n×2048 bytes and the current timestamp minus the write start time is greater than a set threshold, so as to determine whether to initiate a file write request.

10. The system according to claim 8, characterized in that: The disk information includes disk capacity, minimum write unit for a single disk, and status information for each disk. The file header information includes a file header pointer, a file tail pointer, the total disk space occupied by the current file, and the total amount of data in the current file; The file content information includes the file write start time, file write end time, the file's initial write position on the disk, and the file size.

11. The system according to claim 10, characterized in that: The relative wear factor is determined by the disk's status information, which includes the total amount of data written, write throughput, single disk temperature, and single disk CRC check error rate.

12. The system according to claim 8, characterized in that: The minimum storage capacity of the write FIFO is n×2048 bytes, and the write FIFO is connected to the write data parsing module through the FIFO interface.

13. The system according to claim 8, characterized in that: The magnetoresistive random access memory supports both parallel MRAM and serial MRAM.

14. The system according to claim 13, characterized in that: The information stored in the magnetoresistive random access memory includes: status information, capacity information, and file status information of the SATA disk.

15. The system according to claim 8, characterized in that: The write management arbitrates the n-way SATA write queues input from the front end. The arbitration strategy adopts a round-robin priority method, and the arbitrated write queues are written to the external memory according to the circular buffer pool method.

16. The system according to claim 15, characterized in that: The ring buffer pool has a capacity greater than 1 Mbyte, and its starting address after power-on is set to the lowest address of each external memory.

17. The system according to claim 8, characterized in that: After receiving the write completion message from the front end, the read management module records the message for each disk. Once the cache queue of the SATA controller can accommodate new content, it reads the corresponding data from the external storage into each cache queue, which is connected to the SATA controller.

18. The system according to claim 8, characterized in that, Also includes: If the current data cannot be stored, the write operation is abandoned, and a file write error status is returned through the file allocation interface.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method as claimed in any one of claims 1-7.

20. A non-transitory computer-readable storage medium, characterized in that, in, The non-transitory computer-readable storage medium stores computer instructions for causing a computer to perform the method described in any one of claims 1-7.

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