Data transmission method of printer, printer and storage medium thereof

Abstract

The invention provides a data transmission method of a printer, the printer and a storage medium thereof, and the method comprises the steps: reading a first occupation time length of a printing processor for processing a current task, and configuring a temporarily storable byte quantity of a data buffer area according to the first occupation time length; whenever the slave control interface receives a first signal sent by the host, bytes sent by the host are determined from the data interface, and the bytes are temporarily stored in the data buffer area; when the byte quantity of the data buffer area reaches the byte quantity capable of being temporarily stored, a second signal is sent to the printing processor, so that the printing processor suspends the current task in a resource channel for processing the current task according to the second signal, and the resource channel is called to read bytes of the byte quantity capable of being temporarily stored from the data buffer area; and when the third signal sent by the printing processor is received, the second occupation duration of the printing processor for processing the current task is read, and the temporarily storable byte quantity is reconfigured according to the second occupation duration, so that the interrupt frequency of the processor is reduced, and processor resources are saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of printer communication, and in particular to a data transmission method of a printer, the printer and a storage medium thereof. BACKGROUND

[0002] Traditional printer data transmission usually relies on the micro controller unit (MCU) of the printer to directly interact with the data of the host. Specifically, the MCU will interrupt the current processing task every time it receives a byte of data from the host. This "single-byte-single-interrupt" mode causes the MCU to need to respond to interrupts frequently to perform a series of operations such as reading a single byte, processing status verification, and storage. Since the host must wait for the previous byte to be completely processed and the interrupt service program to be executed before sending the next byte, the overall data transmission rate is severely limited by the interrupt response speed and processing capacity of the processor. When processing a large number of printing tasks, a large number of interrupt requests will continuously occupy the valuable computing resources of the processor, making it difficult for it to efficiently perform core tasks such as print rendering and motor control, forming a system performance bottleneck. This not only reduces the efficiency of sending data from the host, but also prolongs the total task time, making the entire system inefficient and uneconomical in terms of resource utilization, and making it difficult to meet the stringent requirements of modern high-performance printing equipment for data transmission real-time performance and overall efficiency. SUMMARY

[0003] The present application aims to at least solve one of the technical problems existing in the prior art, and provides a data transmission method of a printer, the printer and a storage medium thereof, which significantly reduces the interrupt frequency, saves processor resources, and improves the data transmission efficiency through a buffering and batch interrupt mechanism.

[0004] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application provides a data transmission method of a printer, applied to a parallel port controller of the printer, the parallel port controller comprising a control interface for receiving signals sent by a host, a data interface for receiving data sent by the host, and a data buffer area, the parallel port controller being in communication connection with a print processor of the printer, and the method comprising: reading a first occupation duration of the print processor processing a current task, and configuring a storable byte amount of the data buffer area according to the first occupation duration, wherein the storable byte amount is not more than a maximum byte amount in the data buffer area; determining a byte sent by the host from the data interface every time a first signal representing the start of data delivery sent by the host is received from the control interface, and storing the byte in the data buffer area; when the byte amount of the data buffer reaches the storable byte amount, a second signal representing an interrupt resource is sent to the print processor, so that the print processor suspends the current task in the resource channel processing the current task according to the second signal, and calls the resource channel to read the storable byte amount of bytes from the data buffer; when the third signal representing the completion of byte reading sent by the print processor is received, the second occupation time length of the print processor processing the current task is read, and the storable byte amount is reconfigured according to the second occupation time length.

[0005] Further, in some embodiments, the parallel port controller further comprises a timing module, and after the bytes are stored in the data buffer, the method further comprises: resetting the count value of the timing module to zero, and controlling the timing module to time the time interval during which the control interface receives the first signal again; if the time interval exceeds the preset receiving time length, the second signal is sent to the print processor, so that the print processor suspends the current task in the resource channel processing the current task according to the second signal, and calls the resource channel to read all bytes from the data buffer.

[0006] Further, in some embodiments, the parallel port controller further comprises a status interface for sending signals to the host, and the control interface further comprises a gating port for electrically connecting the host, and the first signal is a first pulse sent by the host to the gating port; wherein, each time the first signal representing the start of data transmission sent by the host is received from the control interface, the bytes sent by the host are determined from the data interface, and the bytes are stored in the data buffer, comprising: each time the level setting is detected to jump from the first level to the second level and then jump back to the first level on the gating port, it is determined that the first pulse is received, the bytes are determined from the data interface after the first level jumps to the second level, and the bytes are written into the data buffer, and a fourth signal for answering the completion of data buffering is sent to the host through the status interface to inform the host that the single data transmission based on the first signal is completed.

[0007] Further, in some embodiments, the first level is higher than the second level, or the first level is lower than the first level.

[0008] Further, in some embodiments, the data interface comprises a plurality of bit ports for receiving data streams sent by the host, and determining the bytes from the data interface comprises: respectively latching the first bit corresponding to each of the plurality of bit ports, and combining the plurality of bits into at least one byte.

[0009] Further, in some embodiments, the control interface further comprises a busy line port for electrically connecting the host; wherein, before the step of locking the plurality of bytes sent by the host from the data interface and temporarily storing the plurality of bytes into the data buffer, the method further comprises: setting the level of the busy port to a third level to inform the host that the data interface is in an idle state in which the data interface is capable of receiving data.

[0010] Further, in some embodiments, during the process of the first level jumping to the second level, the method further comprises: setting the level of the busy port to a fourth level to inform the host that the data interface is in a latching state in which the data interface is incapable of receiving data. After the step of sending the fourth signal to the host through the status interface to reply that the data buffer is full, the method further comprises: setting the level of the busy port to the third level again to inform the host that the data interface is in the idle state in which the data interface is capable of receiving data.

[0011] Further, in some embodiments, the third level is higher than the fourth level, or the third level is lower than the fourth level.

[0012] To achieve the above object, a second aspect of the embodiments of the present application provides a printer, comprising: a print processor; a parallel port controller, the parallel port controller being in communication connection with the print processor, and the parallel port controller comprising a control interface for receiving a signal sent by a host, a data interface for receiving data sent by the host, and a data buffer; the parallel port controller is configured to read a first occupation time length of the print processor in processing a current task, and configure a temporarily storable byte amount of the data buffer according to the first occupation time length, wherein the temporarily storable byte amount is not more than a maximum byte amount in the data buffer; the parallel port controller is further configured to, whenever receiving a first signal sent by the host and representing data start delivery from the control interface, determine bytes sent by the host from the data interface and temporarily store the bytes into the data buffer; the parallel port controller is further configured to, when the byte amount of the data buffer reaches the temporarily storable byte amount, send a second signal representing interrupt resource to the print processor, so that the print processor suspends the current task in a resource channel in processing the current task according to the second signal, and calls the resource channel to read the temporarily storable byte amount of bytes from the data buffer; the parallel port controller is further configured to, when receiving a third signal sent by the print processor and representing byte reading completion, read a second occupation time length of the print processor in processing the current task, and reconfigure the temporarily storable byte amount according to the second occupation time length.

[0013] To achieve the above object, a third aspect of the embodiment of the present application provides a storage medium, which is a computer readable storage medium, and stores a computer program, which is executed by a processor to implement the data transmission method of the printer according to the first aspect.

[0014] According to the data transmission method of the printer, the printer and the storage medium, at least the following beneficial effects are achieved: through the hardware-level data buffering and intelligent interrupt management mechanism, the processing efficiency of the system is improved, specifically, a data buffer with a dynamically configurable depth is integrated in the parallel port controller, and a batch interrupt triggering mechanism based on data accumulation is innovatively adopted. This design overturns the traditional working mode of "one byte received, one interrupt sent", so that the system only sends an interrupt signal to the print processor when the data amount in the buffer reaches a preset threshold (i.e. the temporarily stored byte amount). This reduces the interrupt frequency by several orders of magnitude, greatly liberates the computing resources of the print processor, and enables the print processor to focus more on and perform more efficiently the core computing tasks such as print task scheduling, graphic rasterization and motor precision control, thereby significantly improving the processing capacity and stability of the entire print system. At the same time, since the host does not need to wait for the response of the processor for each byte when sending data, the host can continuously perform high-speed data transmission while buffering data in the parallel port controller, which greatly improves the bus utilization rate and the effective data throughput rate from the host to the printer, and shortens the overall preparation time of large-capacity print jobs. In addition, the temporarily stored byte amount can be dynamically configured according to the real-time occupation time of the print processor in processing the current task. This adaptive feature enables the system to intelligently balance the relationship between interrupt response timeliness and system overhead under different workloads, for example, increasing the buffer amount to further reduce the interrupt frequency under high load, and appropriately reducing the buffer amount to shorten the data transfer delay under low load, so that the system performance can be optimized in various application scenarios, and the flexibility of the system performance is exhibited.

[0015] Other features and advantages of the present application will be set forth in the following description, and in part will be apparent from the description. The objects and other advantages of the present application will be realized and attained by the structure particularly pointed out in the description. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the technical scheme of the present application, and constitute a part of the specification, and are used to explain the technical scheme of the present application together with the embodiments of the present application, and do not constitute a limitation to the technical scheme of the present application.

[0017] The present application will be further described below in combination with the drawings and embodiments; Figure 1is an optional schematic diagram of the data transmission method of the printer provided by the embodiment of the present application; Figure 2 is another optional schematic diagram of the data transmission method of the printer provided by the embodiment of the present application; Figure 3 is an optional schematic diagram of the data transmission method of the printer provided by the embodiment of the present application; Figure 1 is an optional schematic diagram of step S102 in the method; Figure 4 is an optional waveform diagram of the communication signal in the parallel port controller provided by the embodiment of the present application; Figure 5 is another optional schematic diagram of the data transmission method of the printer provided by the embodiment of the present application; Figure 6 is an optional schematic diagram of the printer provided by the embodiment of the present application; Figure 7 is an optional hardware structure schematic diagram of the electronic device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0018] This part will describe the specific embodiments of the present application in detail, the preferred embodiments of the present application are shown in the drawings, the role of the drawings is to supplement the description of the text part with graphics, so that people can intuitively and visually understand each technical feature and the overall technical scheme of the present application, but it cannot be understood as a limitation on the protection scope of the present application.

[0019] In the description of the present application, if the first, second is used to distinguish technical features for the purpose, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the sequence of indicated technical features, it should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0020] In the description of the present application, unless otherwise explicitly limited, the words such as setting, installing, connecting, etc. should be understood broadly, and those skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical scheme.

[0021] Traditional printer data transmission typically relies on direct data interaction between the printer's microcontroller unit (MCU) and the host computer. Specifically, the MCU interrupts its current processing task every time it receives a single byte of data from the host. This "single-byte, single-interrupt" mode requires the MCU to frequently respond to interrupts to perform a series of operations such as reading individual bytes, processing status checks, and storage. Since the host computer must wait for the previous byte to be fully processed and the interrupt service routine to complete before sending the next byte, the overall data transmission rate is severely limited by the processor's interrupt response speed and processing capabilities. When handling large-volume print jobs, the massive number of interrupt requests continuously consumes the processor's valuable computing resources, making it difficult to efficiently execute core tasks such as print rendering and motor control, thus creating a system performance bottleneck. This not only reduces the host's data transmission efficiency and prolongs the total task execution time but also makes the entire system inefficient and uneconomical in terms of resource utilization, failing to meet the stringent requirements of modern high-performance printing equipment for real-time data transmission and overall performance.

[0022] Based on this, embodiments of this application provide a data transmission method for a printer, a printer and its storage medium, which significantly reduces the interrupt frequency, saves processor resources and improves data transmission efficiency through buffering and batch interrupt mechanisms.

[0023] Therefore, the embodiments of this application will be further described below with reference to the accompanying drawings.

[0024] Reference Figure 1 As shown, Figure 1 This is an optional schematic diagram of a printer data transmission method provided in an embodiment of this application. The data transmission method is applied to the printer's parallel port controller. The parallel port controller includes a control interface for receiving signals sent by the host, a data interface for receiving data sent by the host, and a data buffer. The parallel port controller is communicatively connected to the printer's print processor. The method may include, but is not limited to, steps S101 to S104.

[0025] Step S101: Read the first duration of the print processor processing the current task, and configure the amount of temporary bytes in the data buffer according to the first duration.

[0026] The temporary storage size FIFO_DEEP cannot exceed the maximum size of the data buffer.

[0027] In one possible embodiment, the maximum number of bytes in the data buffer is 16 bytes, and the temporary storage size of the data buffer is configured to be 16 bytes according to the first occupied duration.

[0028] In another possible embodiment, the maximum byte amount in the data buffer is 16 bytes, and the storable byte amount of the data buffer is configured as 8 bytes according to the first occupation time length.

[0029] Step S102: whenever a first signal representing the start of data delivery sent by the host is received from the control interface, the bytes sent by the host are determined from the data interface, and the bytes are stored in the data buffer.

[0030] Step S103: when the byte amount of the data buffer reaches the storable byte amount, a second signal representing an interrupt resource is sent to the print processor, so that the print processor suspends the current task in the resource channel processing the current task according to the second signal, and calls the resource channel to read the storable byte amount of bytes from the data buffer.

[0031] In the embodiments of the present application, the flexible configuration mechanism of the storable byte amount realizes fine optimization of system performance. Specifically, when the system detects that the print processor is relatively lightly processing the current task (i.e., the occupation time length is relatively short), the storable byte amount can be set to a value smaller than the maximum byte amount (such as 16 bytes), for example, 8 bytes. Under this configuration, the parallel port controller will send a second signal representing an interrupt resource to the print processor after receiving and buffering 8 bytes of data. This signal triggers the print processor to suspend the task being processed in the currently executed resource channel, and instead calls the resource channel to read the 8 bytes (i.e., the storable byte amount of bytes) from the data buffer in bulk. The cleverness of this process lies in the "double buffering" idea it adopts: when the print processor is reading the first 8 bytes, the other half of the space (also 8 bytes) remaining in the data buffer can continue to seamlessly receive subsequent data from the host, and the host does not need to wait for the kernel to complete the data reading operation at all. With this design, by achieving the best balance between reducing the frequency of kernel interrupts and maintaining the continuity of data transmission, the occupation of kernel resources by interrupt processing is significantly reduced, releasing its core computing performance, and at the same time, the data flow from the host to the printer is ensured not to be stalled due to the reading operation of the kernel, thereby improving the working efficiency of the print processor and the data transmission throughput from the host to the printer as a whole.

[0032] Step S104: when a third signal representing the completion of byte reading sent by the print processor is received, the second occupation time length of the print processor processing the current task is read, and the storable byte amount is reconfigured according to the second occupation time length.

[0033] Further, in the embodiment of steps S101-S104, a data buffer with a dynamically configurable depth is integrated inside the parallel port controller, and a batch interrupt triggering mechanism based on the accumulated data volume is innovatively adopted. This design overturns the traditional working mode of "one byte received, one interrupt sent", so that the system only sends an interrupt signal to the print processor when the data volume in the buffer reaches a preset threshold (i.e. the temporarily stored byte volume). This reduces the interrupt frequency by several orders of magnitude, greatly liberating the computing resources of the print processor, enabling it to focus more on and perform core computing tasks such as print task scheduling, graphics rasterization, and motor precision control, thereby significantly improving the processing capacity and stability of the entire printing system. At the same time, since the host does not need to wait for the processor's response for each byte when sending data, it can continue to perform high-speed data transmission while the parallel port controller is buffering data, which greatly improves the bus utilization and the effective data throughput from the host to the printer, shortening the overall preparation time for large-capacity printing jobs. In addition, the temporarily stored byte volume can be dynamically configured according to the real-time occupation time of the print processor in processing the current task. This adaptive feature enables the system to intelligently balance the relationship between interrupt response timeliness and system overhead under different workloads, such as increasing the buffer volume to further reduce the interrupt frequency under high load, and appropriately reducing the buffer volume to shorten the data transfer delay under low load, thereby optimizing system performance in various application scenarios and demonstrating the flexibility of system performance.

[0034] Further, the parallel port controller further comprises a timing module, as shown in Figure 2 Figure 2 is another optional schematic diagram of the data transmission method of the printer provided by the embodiment of the present application. The method can include but is not limited to steps S201-S202.

[0035] Step S201: resetting the count value of the timing module to zero and controlling the timing module to time the time interval of the control interface receiving the first signal again.

[0036] Step S202: if the time interval exceeds the preset reception time, sending a second signal to the print processor to make the print processor suspend the current task in the resource channel processing the current task according to the second signal, and call the resource channel to read all bytes from the data buffer.

[0037] ​It is to be noted that, in the step S201 to the step S202, after the parallel port controller successfully receives and temporarily stores a data byte, it immediately resets the count value DATA_CNT of its internal timing module to zero, and then starts the timing module to accurately time the time interval between the first signal representing the start of the data delivery of the next host transmission detected again from the control interface and the second signal representing the end of the data delivery of the current host transmission. This timing operation continuously monitors the continuity of the host data stream. Then, the parallel port controller continuously compares the time interval with a preset receiving duration threshold. If the time interval exceeds the receiving duration, it determines that the current host data packet transmission has ended or is interrupted unexpectedly. At this time, the parallel port controller no longer waits for the data buffer to reach the preset storable byte amount, but immediately actively sends the second signal representing the interrupt resource to the print processor. This signal triggers the print processor to suspend the current task in the resource channel of the task execution, and then calls the resource channel to read all the bytes currently stored in the data buffer, regardless of whether the number of the bytes has reached the previously configured upper limit. This mechanism ensures that when the data transmission is unexpectedly interrupted or a smaller data packet is transmitted, the received data will not be left in the buffer for a long time and can be processed in time, thereby effectively avoiding the delay of data processing, ensuring the real-time response of the system, and improving the robustness of various abnormal communication scenarios. The receiving duration threshold can be flexibly configured according to the actual communication protocol and the characteristics of the host, thereby optimizing the performance of the system in different application environments.

[0038] Further, the parallel port controller further comprises a status interface for sending a signal to the host, and the control interface further comprises a gating port for electrically connecting the host. The first signal is a first pulse sent by the host to the gating port, as shown in Figure 3 Figure 3 is an optional schematic diagram of the step S102 in the method provided by the embodiments of the present application. The method can include but is not limited to the steps S301 to S303. Figure 1

[0039] The step S301: whenever the level setting on the gating port jumps from the first level to the second level and then jumps back to the first level, it is determined that the first pulse is received.

[0040] The step S302: after the first level jumps to the second level, the byte is determined from the data interface, and the byte is written into the data buffer.

[0041] In one possible embodiment, the first level is higher than the second level, i.e., the first level is a high level and the second level is a low level.

[0042] In another possible embodiment, the first level is lower than the first level, i.e., the first level is a low level and the second level is a high level. ​​

[0043] Step S303: sending a fourth signal for answering the completion of data buffering to the host through the status interface, to inform the host that the single data transmission based on the first signal is completed.

[0044] It should be noted that in steps S301 to S303, the parallel port controller continuously detects the gating port of the control interface (for example, the port corresponding to the nStrobe signal line pair connected to the host), referring to Figure 4 , as shown in Figure 4 , is an optional waveform diagram of the communication signal in the parallel port controller provided by the embodiment of the present application. Through the internal edge detection circuit, whenever the level of the gating port jumps from the first level (such as high level) to the second level (such as low level) and then jumps back to the first level, a complete pulse waveform is captured, which indicates that a valid first signal (gating pulse) is received, which indicates that the host is ready to send a byte of data. Subsequently, after detecting the falling edge of the level jumping from the first level to the second level, the parallel port controller will immediately latch the stable data presented on the data interface at this time and write the byte into the data buffer for temporary storage. This design ensures the accuracy and timeliness of data sampling. Subsequently, in order to complete the handshake process and inform the host that the next data can be sent, the controller will send a specific fourth signal (PtrClk response signal) to the host through its status interface (for example, the port corresponding to the nAck signal line connected to the host), which is usually represented as a short low-level pulse. This active feedback mechanism constitutes a complete data transmission closed loop, which not only timely eliminates the waiting state on the host side, ensuring the efficiency and continuity of data flow, but also completely transparentizes the data buffering operation to the host, so that the host does not need to perceive the depth and management strategy of the back-end buffer, and only needs to follow the standard single-byte handshake protocol, thereby realizing the perfect combination of seamless compatibility with the existing host system and performance improvement.

[0045] In one possible embodiment, the data interface includes a plurality of bit ports for receiving the data stream sent by the host, and the step of determining the byte from the data interface in step S302 specifically includes the following steps: respectively latching the first bit corresponding to each of the plurality of bit ports, and combining the plurality of bits into at least one byte.

[0046] In one possible embodiment, the data interface comprises 8 independent bit ports (e.g. D0 to D7, 8 bits in total) for receiving data stream sent by the host in parallel. When performing byte latching operation, after the parallel port controller detects a level transition from a first level to a second level (i.e. a valid falling edge) on the strobe port, the falling edge serves as a global trigger signal and simultaneously acts on the corresponding latches of all bit ports. Each latch will capture and hold the level state (i.e. logic '0' or logic '1') on its connected bit port at exactly the same time. This synchronous latching mechanism ensures that all bit positions constituting the same byte are acquired within the same sampling window, thereby avoiding bit errors caused by timing deviation of data signal due to micro-time. Subsequently, the parallel port controller combines the multiple independent bit positions latched respectively in a predetermined order (e.g. D0 as the least significant bit and D7 as the most significant bit) to form a complete byte (e.g. a byte in 8-bit system). This parallel latching and combination based on hardware trigger is the key to high-speed parallel communication, which maximizes the speed and reliability of data reception and lays a foundation for subsequent writing of bytes into data buffer.

[0047] In one possible embodiment, referring to Figure 5 , the data transmission method provided by the printer can comprise but is not limited to the following steps. Figure 5 is another optional schematic diagram of the data transmission method of the printer provided by the embodiment of the present application, which can comprise but is not limited to step S401.

[0048] Step S401: setting the level of the busy port to a third level to inform the host that the data interface is in an idle state of receiving data.

[0049] Further, referring again to Figure 5 , the process of the first level transitioning to the second level can further comprise but is not limited to step S402. Step S402: setting the level of the busy port to a fourth level to inform the host that the data interface is in a latching state of not receiving data during the process of the first level transitioning to the second level.

[0050] Further, referring again to Figure 5 , after sending the fourth signal to the host through the status interface, the method can further comprise but is not limited to step S403.

[0051] Step S403: setting the level of the busy port to the third level again to inform the host that the data interface is in the idle state of receiving data.

[0052] It should be noted that the parallel port controller achieves reliable data flow control with the host based on the hardware handshake protocol by precisely managing the level state of the busy port (for example, the port corresponding to the Busy signal line connected to the host). The working process is as follows: after system initialization, the controller first sets the level of the busy port to the third level (for example, the low-level PtrBusy signal), which explicitly announces to the host that the data interface is in an "idle" state of receiving data, and indicates that the host can initiate data transmission. When the controller detects the valid falling edge of the first level switching to the second level at the gating port, confirming the first signal sent by the host, instead of immediately latching the data, the controller first switches the level of the busy port from the third level to the fourth level (for example, the high-level PtrBusy signal). This key operation is crucial, which immediately feeds back to the host that the "busy" state, indicating that the slave device has entered the data latching and processing stage, and the host should pause sending new data, thereby effectively preventing data overwrite or loss. After completing data latching and sending the fourth signal of the response to the host through the status interface, the controller does not permanently keep the busy state, but resets the level of the busy port to the third level. This state recovery operation restores the interface to the "idle" state again, inviting the host to perform the next round of data transmission. Through the periodic state switching of "idle-busy-idle" and close cooperation with the gating signal and the response signal, a complete and robust hardware flow control closed loop is constructed, which ensures that the host and the slave device can keep accurate synchronization even in a high-speed data transmission scenario, greatly improving the reliability and efficiency of the entire communication system.

[0053] In a possible embodiment, the third level is higher than the fourth level, that is, the third level is a high level and the fourth level is a low level.

[0054] In a possible embodiment, the third level is lower than the fourth level, that is, the third level is a low level and the fourth level is a high level.

[0055] Referring to Figure 6 as shown, Figure 6 is an optional schematic diagram of a printer provided by the embodiments of the present application. The printer 600 includes a print processor 610 and a parallel port controller 620. The parallel port controller 620 is in communication connection with the print processor 610. The parallel port controller 620 includes a control interface 621 for receiving signals sent by the host, a status interface 622 for sending signals to the host, and a data interface 623 and a data buffer 624 for receiving data sent by the host.

[0056] The parallel port controller 620 is configured to read a first occupation time length of the print processor in processing a current task, and configure a storable byte amount of the data buffer 624 according to the first occupation time length, where the storable byte amount is not more than a maximum byte amount in the data buffer.

[0057] The parallel port controller 620 is further configured to determine the bytes sent by the host from the data interface 623 and store the bytes in the data buffer 624 whenever receiving the first signal representing the start of data transmission sent by the host from the control interface 621.

[0058] The parallel port controller 620 is further configured to send the second signal representing the interrupt resource to the print processor when the amount of bytes in the data buffer 624 reaches the storable byte amount, so that the print processor suspends the current task in the resource channel processing the current task according to the second signal and calls the resource channel to read the storable byte amount of bytes from the data buffer.

[0059] The parallel port controller 620 is further configured to receive the third signal representing the completion of byte reading sent by the print processor, read the second occupation time length of the print processor processing the current task, and reconfigure the storable byte amount according to the second occupation time length.

[0060] The printer 600 and the data transmission method of the printer described above are based on the same inventive concept. Through the hardware-level data buffering and intelligent interrupt management mechanism, the processing efficiency of the system is improved. Specifically, a data buffer with a dynamically configurable depth is integrated in the parallel port controller, and a batch interrupt triggering mechanism based on data accumulation amount is innovatively adopted. This design overturns the traditional working mode of "one byte received, one interrupt sent", so that the system only sends one interrupt signal to the print processor when the data amount in the buffer reaches the preset threshold (i.e. the storable byte amount). This reduces the interrupt frequency by several orders of magnitude, greatly liberates the computing resources of the print processor, and enables the print processor to focus more on and perform core computing tasks such as print task scheduling, graphic rasterization, and motor precision control, thereby significantly improving the processing capacity and stability of the entire printing system. At the same time, since the host does not need to wait for the processor's response for each byte when sending data, it can continuously perform high-speed data transmission while buffering data in the parallel port controller, which greatly improves the bus utilization and the effective data throughput rate from the host to the printer, and shortens the overall preparation time of large-capacity printing jobs. In addition, the storable byte amount can be dynamically configured according to the real-time occupation time length of the print processor processing the current task. This adaptive feature enables the system to intelligently balance the relationship between interrupt response timeliness and system overhead under different workloads, such as increasing the buffer amount to further reduce the interrupt frequency under high load, and appropriately reducing the buffer amount to shorten the data transmission delay under low load, so that the system performance can be optimized in various application scenarios, and the flexibility of system performance is exhibited.

[0061] Please refer to Figure 7 ,Figure 7 is a hardware structure schematic diagram of an electronic device provided by an embodiment of the present application, and the electronic device comprises: The processor 701 can be implemented in a general-purpose CPU (Central Processing Unit), a microprocessor, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits, and is used to execute related programs to implement the blood pressure regulation method based on stimulating the carotid sinus provided by the embodiments of the present application. The memory 702 can be implemented in the form of a ROM (ReadOnly Memory), a static storage device, a dynamic storage device, or a RAM (Random Access Memory). The memory 702 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present application are implemented by software or firmware, the related program codes are stored in the memory 702 and are called and executed by the processor 701 to implement the blood pressure regulation method based on stimulating the carotid sinus provided by the embodiments of the present application. The input / output interface 703 is used to realize information input and output. The communication interface 704 is used to realize the communication interaction between the device and other devices, and can realize communication through a wired manner (for example, a USB, a network cable, etc.) or a wireless manner (for example, a mobile network, WIFI, Bluetooth, etc.). The bus 707 is used to transmit information between various components (for example, the processor 701, the memory 702, the input / output interface 703, and the communication interface 704) of the device. The processor 701, the memory 702, the input / output interface 703, and the communication interface 704 are connected to each other through the bus 707 to realize communication connection between them in the device.

[0062] The embodiments of the present application further provide a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, the blood pressure regulation method based on stimulating the carotid sinus provided by the embodiments of the present application is implemented.

[0063] The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory disposed remotely with respect to the processor, and these remote memories can be connected to the processor through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0064] The embodiments described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0065] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and can include more or fewer steps than shown in the figures, or combine certain steps, or different steps.

[0066] The device embodiments described above are only schematic, and the units described as separate components can or can not be physically separate, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0067] Those skilled in the art can understand that all or some of the steps in the above disclosed method, the functional modules / units in the system and the device can be implemented as software, firmware, hardware and their appropriate combinations.

[0068] The terms "first", "second", "third", "fourth" and the like used in the specification of the present application and the above-described drawings (if any) are used to distinguish similar objects, and do not necessarily have to describe a particular order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0069] It should be understood that, in the application, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can represent three cases of only A, only B and A and B existing at the same time, wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" or the like means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b and c can be single or multiple.

[0070] In several embodiments provided in the application, it should be understood that the disclosed system and method can be implemented in other ways. For example, the system embodiments described above are only illustrative, for example, the division of the above units is only a logical function division, and actual implementation can have another division mode, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed units can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0071] The units described above as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or they can be distributed on multiple network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment.

[0072] In addition, each functional unit in each embodiment of the application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0073] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer accessible storage medium. Based on such understanding, the technical solutions of the present application, essentially or in other words, the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes multiple instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program storage media.

[0074] The preferred embodiments of the embodiments of the present application are described above with reference to the accompanying drawings, and are not limited to the scope of the embodiments of the present application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the embodiments of the present application.

Claims

1. A data transmission method for a printer, characterized in that, A parallel port controller applied to the printer, the parallel port controller including a control interface for receiving signals sent by a host, a data interface for receiving data sent by the host, and a data buffer, the parallel port controller being communicatively connected to the printer's print processor, the method comprising: The first duration of the printing processor processing the current task is read, and the amount of temporary bytes that can be stored in the data buffer is configured according to the first duration, wherein the amount of temporary bytes does not exceed the maximum amount of bytes in the data buffer; Whenever a first signal indicating the start of data transmission from the host is received from the control interface, the byte sent by the host is determined from the data interface, and the byte is temporarily stored in the data buffer; When the number of bytes in the data buffer reaches the number of bytes that can be temporarily stored, a second signal representing an interruption resource is sent to the print processor, so that the print processor suspends the current task in the resource channel processing the current task according to the second signal, and calls the resource channel to read the number of bytes that can be temporarily stored from the data buffer. When a third signal indicating that the reading of bytes has been completed is received from the print processor, the second time duration for the print processor to process the current task is read, and the amount of temporary bytes is reconfigured according to the second time duration.

2. The data transmission method according to claim 1, characterized in that, The parallel port controller further includes a timing module, and after the byte is temporarily stored in the data buffer, the method further includes; The counter value of the timing module is reset to zero, and the timing module is controlled to time the time interval between when the control interface receives the first signal again. If the time interval exceeds the preset reception duration, the second signal is sent to the print processor so that the print processor suspends the current task in the resource channel processing the current task according to the second signal, and calls the resource channel to read all bytes from the data buffer.

3. The data transmission method according to claim 1, characterized in that, The parallel port controller further includes a status interface for sending signals to the host, and the control interface further includes a strobe port for electrically connecting the host, wherein the first signal is a first pulse sent by the host to the strobe port; The step of determining the byte sent by the host from the data interface and temporarily storing the byte in the data buffer whenever a first signal indicating the start of transmission of representation data sent by the host is received from the control interface includes: Whenever the level setting is detected to jump from the first level to the second level and then back to the first level on the strobe port, it is determined that the first pulse has been received. After the first level jumps to the second level, the byte is determined from the data interface and written to the data buffer. A fourth signal is sent to the host through the status interface to acknowledge that the data buffer is complete, so as to inform the host that a single data transmission based on the first signal has been completed.

4. The data transmission method according to claim 3, characterized in that, The first level is higher than the second level, or the first level is lower than the first level.

5. The data transmission method according to claim 3, characterized in that, The data interface includes multiple bit ports for receiving data streams sent by the host, and determining the byte from the data interface includes: The first bit corresponding to each of the plurality of bit ports is latched respectively, and the plurality of bit bits are combined into at least one byte.

6. The data transmission method according to claim 3, characterized in that, The control interface also includes a busy-line port for electrically connecting the host computer; The method further includes, before the step of receiving a data transmission start signal from the host via the control interface, locking multiple bytes sent by the host from the data interface, and temporarily storing the multiple bytes in the data buffer: Set the level of the busy port to the third level to inform the host that the data interface is in an idle state where it can receive data.

7. The data transmission method according to claim 6, characterized in that, During the transition from the first level to the second level, the method further includes: setting the level of the busy line port to a fourth level to inform the host that the data interface is in a latched state where data cannot be received; After sending a fourth signal to the host via the status interface to acknowledge that the data buffer is complete, the method further includes: setting the level of the busy port back to the third level to inform the host that the data interface is in an idle state where it can receive data.

8. The data transmission method according to claim 5, characterized in that, The third level is higher than the fourth level, or the third level is lower than the fourth level.

9. A printer, characterized in that, include: Printer processor; A parallel port controller, which is communicatively connected to the print processor, includes a control interface for receiving signals sent by the host, a data interface for receiving data sent by the host, and a data buffer. The parallel port controller is used to read the first time the print processor takes to process the current task, and configure the number of bytes that can be temporarily stored in the data buffer according to the first time, wherein the number of bytes that can be temporarily stored does not exceed the maximum number of bytes in the data buffer; The parallel port controller is further configured to, whenever a first signal indicating the start of transmission of characterizing data sent by the host is received from the control interface, determine the byte sent by the host from the data interface and temporarily store the byte in the data buffer; The parallel port controller is further configured to, when the number of bytes in the data buffer reaches the number of bytes that can be temporarily stored, send a second signal representing an interrupt resource to the print processor, so that the print processor suspends the current task in the resource channel processing the current task according to the second signal, and calls the resource channel to read the number of bytes that can be temporarily stored from the data buffer. The parallel port controller is also configured to, upon receiving a third signal from the print processor indicating that the byte reading is complete, read the second occupancy time of the print processor processing the current task, and reconfigure the amount of temporarily storable bytes according to the second occupancy time.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a processor-executable program, which, when executed by a processor, is used to implement the printer data transmission method as described in any one of claims 1 to 8.

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