High-order matrix multiplication calculation system and method based on FPGA platform

This high-order matrix multiplication computation system, utilizing a superscalar pipeline architecture and BRAM storage, solves the challenge of efficient matrix multiplication under limited FPGA resources. It achieves efficient computation and resource optimization and is suitable for ADBF adaptive digital shaping covariance matrix operations in the field of radar digital beamforming.

CN121832882APending Publication Date: 2026-04-10BEIJING INST OF REMOTE SENSING EQUIP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-12-29
Publication Date
2026-04-10

AI Technical Summary

Technical Problem

With limited FPGA resources, high-order matrix multiplication operations are difficult to perform efficiently. Existing technologies usually require selecting higher-level FPGA models to increase hardware resources, but this is limited in practical applications, resulting in low computing speed and low resource utilization.

Method used

Employing a superscalar pipelined architecture, this system utilizes BRAM to store matrix data through serial input and parallel computation. Combined with superscalar pipelined multiplication and accumulation modules, it achieves efficient matrix multiplication operations, reducing the demand on FPGA resources.

Benefits of technology

This approach enables efficient high-order matrix multiplication on limited FPGA resources, avoiding explosive growth in resource consumption, improving computation speed and resource utilization, and reducing the consumption of logic resources by data transmission.

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Abstract

The invention provides a high-order matrix multiplication calculation system and method based on an FPGA platform, and belongs to the technical field of computers.The system comprises a superscalar pipeline multiplication calculation module used for obtaining row data and column data of matrixes which are input in a serial mode and stored through a BRAM, the matrixes comprise the first matrix and the second matrix, and the first matrix and the second matrix are used for obtaining the row data and the column data of the matrixes; one BRAM stores a row of data in the first matrix; the superscale streamline multiplication calculation module is also used for carrying out multiplication calculation on each element in rows and columns of the matrix through a multiplier in a superscale serial streamline mode, and outputting each multiplication calculation result in parallel; and the superscale assembly line accumulation calculation module is used for performing assembly line processing on the superscale multiplication calculation result after receiving the superscale multiplication calculation result, performing accumulation calculation, and outputting a matrix multiplication result in parallel. According to the high-order matrix multiplication calculation system and method based on the FPGA platform, a matrix multiplication calculation structure capable of reducing the hardware resource consumption and guaranteeing the calculation speed can be provided.
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