Program data upgrading processing method of chip, chip and vehicle

Abstract

The invention discloses a chip program data upgrading processing method, a chip and a vehicle. The method comprises the steps that a first storage area is configured to be in a read-only mode, a second storage area is configured to be in a writable mode, a forward differential data packet and a reverse differential data packet are obtained, the forward differential data packet is stored in a forward differential packet temporary storage area, and the reverse differential data packet is stored in a reverse differential packet temporary storage area; storing the reverse differential data packet into a reverse differential data packet temporary storage area; after the chip is restarted, the first storage area is configured to be in a writable mode, and when it is detected that the preset flag bit of the chip meets a first preset condition, the forward differential data packet stored in the forward differential packet temporary storage area is read; and updating the program data in the first storage area based on the forward differential data packet. According to the method, the production cost of the chip is reduced, and the performance of the chip is improved.

Description

Technical Field

[0001] This application relates to the field of chip data updates, and in particular to a method for processing chip program data upgrades, a chip, and a vehicle. Background Technology

[0002] As the core control component of automotive electronic systems, automotive-grade microcontroller units (MCUs) must simultaneously meet the triple requirements of high performance, high reliability, and cost control. On the one hand, automotive-grade MCUs need to support the stable operation of large amounts of program data, such as the chip's operating system, drivers, and applications. On the other hand, to optimize chip design costs and system complexity, the size of on-chip random access memory (RAM) needs to be minimized. To address these requirements, existing technologies integrate non-volatile memory (NVM) within the MCU chip, such as magnetoresistive random access memory (MRAM), embedded flash memory (eFlash), and resistive random access memory (RRAM).

[0003] Furthermore, automotive-grade MCUs must meet the functional requirements of over-the-air (OTA) software upgrades, and the upgrade process must comply with automotive-grade high safety standards. Existing technologies typically employ a symmetrical AB partitioning scheme: dividing the on-chip NVM into two partitions, A and B, of equal capacity. In a typical operating mode, one partition (e.g., partition A) is used to hold program data, while the other partition (e.g., partition B) serves as the upgrade partition. After partition B completes the program upgrade, the system switches to partition B for operation, and the original partition A becomes a backup partition for the next upgrade, while also providing system rollback functionality in case of upgrade failure, thus ensuring the safety and reliability of the upgrade process.

[0004] However, the aforementioned symmetrical AB partitioning scheme has significant drawbacks: since program data execution and upgrades require two independent partitions, the maximum capacity of a single version of program data is strictly limited to half of the total NVM capacity. Under the stringent requirements of automotive-grade MCUs for high performance, high reliability, and low cost, the utilization rate of NVM storage space is greatly reduced, resulting in a serious waste of hardware resources and limiting the MCU's ability to support larger volumes of program data.

[0005] In summary, improving NVM resource utilization and expanding the support capacity of single-version program data under automotive-grade chip architecture has become a pressing technical problem to be solved in this field. Summary of the Invention

[0006] This application provides a method for upgrading program data of a chip, applied to a chip with a computing unit. The chip has a non-volatile memory, which is communicatively connected to the computing unit and configured to have a first storage area and a second storage area. The first storage area is used to store program data based on the operation of the chip, and the second storage area has a forward differential packet buffer area and a reverse differential packet buffer area, wherein the first storage area is larger than the second storage area. The method includes: Configure the first storage area as read-only mode and the second storage area as writable mode. Obtain forward differential data packets and reverse differential data packets. Store the forward differential data packets in the forward differential packet temporary storage area and store the reverse differential data packets in the reverse differential data packet temporary storage area. The forward differential data packets are used to upgrade the program data from the first version to the second version, and the reverse differential data packets are used to roll back the program data from the second version to the first version. After the chip restarts, the first storage area is configured to be writable. If the preset flag bit of the chip is detected to meet the first preset condition, the forward differential data packet stored in the forward differential packet temporary storage area is read. The preset flag bit meeting the first preset condition indicates that the program data of the chip is in an upgrade-ready state. Based on the positive differential data packet, the program data in the first storage area is updated so that after the chip restarts, the chip's computing unit reads and executes the second version of the program data from the first storage area.

[0007] Optionally, after configuring the first storage area to read-only mode and the second storage area to write mode, the method further includes: The computing unit directly reads and executes the program data from the first storage area to obtain forward differential data packets and reverse differential data packets.

[0008] Optionally, before reading the forward differential data packets stored in the forward differential packet buffer, the method further includes: Change the flag to be upgraded to the flag in progress.

[0009] Optionally, the update operation on the program data in the first storage area based on the forward differential data packet includes: Based on the forward differential data packets, corresponding update data blocks are generated; Determine the update region within the first storage region; The updated data block is written into the corresponding update area to update part or all of the program data.

[0010] Optionally, after the chip restarts, the method further includes: If the preset flag is detected as an upgrade flag, it indicates that the last update operation of the chip was interrupted. Identify the portion of the first storage area to be updated; Based on the portion to be updated, the update operation on the first storage area is resumed.

[0011] Optionally, determining the portion to be updated in the first storage area includes: During the last update operation of the chip, the data stored in the data buffer area of ​​the non-volatile memory is obtained, wherein the data buffer area is used to temporarily store data to be written into the first memory area; Based on the data in the data temporary storage area, the portion of the first storage area to be updated is determined.

[0012] Optionally, determining the portion to be updated in the first storage area includes: During the last update operation of the chip, the data stored in the data buffer area of ​​the non-volatile memory is obtained, wherein the data buffer area is used to temporarily store the data in the first memory area that is to be overwritten; Based on the data in the data temporary storage area, the portion of the first storage area to be updated is determined.

[0013] Optionally, the method further includes: After the chip restarts, if the preset flag is detected as a rollback flag, the rollback flag is changed to a rollback in progress flag. The reverse differential data packet is obtained from the reverse differential packet buffer area; Based on the reverse differential data packet, the program data is rolled back. After the rollback operation is completed, the rollback flag is cleared.

[0014] Optionally, the rollback operation on the program data based on the reverse differential data packet includes: Based on the reverse differential data packet, a corresponding rollback data block is generated; Determine the rollback region in the first storage region; The rollback data block is written into the corresponding rollback area to restore all or part of the program data to the corresponding first version.

[0015] Optionally, the method further includes: After the chip restarts, if the preset flag is detected as a rollback flag, it is determined that the previous rollback operation of the chip was interrupted. Identify the portion to be rolled back in the first storage area; Based on the portion to be rolled back, the rollback operation on the first storage area is resumed.

[0016] Optionally, after performing a rollback operation on the program data, the method further includes: Perform a verification operation on the program data in the first storage area; After the verification operation is successful, the chip is restarted, the first version of the program data is read and executed.

[0017] This application embodiment also provides a chip, including a computing unit and a non-volatile memory. The non-volatile memory is communicatively connected to the computing unit and configured to have a first storage area and a second storage area. The first storage area is used to store program data based on the operation of the chip. The second storage area has a forward differential packet buffer area and a reverse differential packet buffer area. The first storage area is larger than the second storage area. The computing unit is configured as follows: Configure the first storage area as read-only mode and the second storage area as writable mode. Obtain forward differential data packets and reverse differential data packets. Store the forward differential data packets in the forward differential packet temporary storage area and store the reverse differential data packets in the reverse differential data packet temporary storage area. The forward differential data packets are used to upgrade the program data from the first version to the second version, and the reverse differential data packets are used to roll back the program data from the second version to the first version. After the chip restarts, the first storage area is configured to be writable. If the preset flag bit of the chip is detected to meet the first preset condition, the forward differential data packet stored in the forward differential packet temporary storage area is read. The preset flag bit meeting the preset condition indicates that the program data of the chip is in an upgrade-ready state. Based on the positive differential data packet, the program data in the first storage area is updated so that after the chip restarts, the chip's computing unit reads and executes the second version of the program data from the first storage area.

[0018] This application also provides a chip including a memory and a processor, wherein the memory stores an executable program and the processor processes the executable program to perform the steps of the method described above.

[0019] This application also provides a vehicle that includes the chip described above.

[0020] The program data upgrade processing method of the chip in this application embodiment can still use the stored positive differential data packets to upgrade the program data in the non-volatile memory without expanding the storage space of the chip's non-volatile memory, thus avoiding an increase in chip cost. At the same time, since the first storage area of ​​the non-volatile memory can be set relatively large, the chip can use program data with a larger data volume, improving chip performance while ensuring data security. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of the non-volatile memory of the chip in an embodiment of this application; Figure 2 A flowchart illustrating a chip program data upgrade processing method according to an embodiment of this application; Figure 3 Examples of embodiments of this application Figure 2 A flowchart of one embodiment of step S300; Figure 4 This is a flowchart of the first embodiment of the program data upgrade processing method according to this application; Figure 5 Examples of embodiments of this application Figure 4 A flowchart of one embodiment of step S500; Figure 6 Examples of embodiments of this application Figure 4 A flowchart of another embodiment of step S500; Figure 7 A flowchart illustrating a second embodiment of the program data upgrade processing method according to this application; Figure 8 Examples of embodiments of this application Figure 7 A flowchart of one embodiment of step S30; Figure 9 A flowchart illustrating a third embodiment of the program data upgrade processing method according to this application; Figure 10 This is a flowchart of the fourth embodiment of the program data upgrade processing method according to the present application; Figure 11 This is a flowchart of the fifth specific embodiment of the program data upgrade processing method according to the present application; Figure 12 This is a structural block diagram of the chip according to an embodiment of this application. Detailed Implementation

[0022] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0023] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0024] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0025] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0026] It should also be understood that although this application has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this application.

[0027] The above and other aspects, features and advantages of this application will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0028] Specific embodiments of this application are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this application, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the application. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as the basis and representative basis for the claims to teach those skilled in the art to use this application in a variety of substantially any suitable detailed structures.

[0029] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in other embodiments,” all of which may refer to one or more of the same or different embodiments according to this application.

[0030] This application provides a method for upgrading program data in a chip. This method is applied to a chip with a computing unit, wherein the chip has non-volatile memory, such as... Figure 1 As shown, the non-volatile memory is communicatively connected to the computing unit and configured to have a first storage area and a second storage area. The first storage area is used to store program data based on the operation of the chip, and the second storage area has a forward differential packet buffer area and a reverse differential packet buffer area, wherein the first storage area is larger than the second storage area.

[0031] Specifically, the chip can be of various types, such as automotive-grade MCU (Microcontroller Unit) chips, industrial-grade chips, or SOC chips. The chip has non-volatile memory, which is a semiconductor memory that retains data even after power is lost. For example, this non-volatile memory could be MRAM (Magnetoresistive Random Access Memory), which features data retention even when power is off and fast read speeds. Non-volatile memory can also be embedded flash memory (eFlash), resistive random access memory (RRAM), etc. The chip of this application has one or more computing units, such as a CPU, for processing relevant data of the chip. The computing units are connected to non-volatile memory, enabling them to process data stored in the non-volatile memory. The non-volatile memory is configured with a first storage area and a second storage area. The first storage area stores program data based on chip operation. For example, the program data may include the chip's operating system, drivers, applications, etc., without limitation. The second storage area has a forward differential packet buffer area and a reverse differential packet buffer area. The forward differential packet buffer area stores forward differential data packets, which are used to upgrade program data from a first version to a second version, thus utilizing the forward differential data, and the corresponding program data can also be upgraded from an older version to a newer version. The reverse differential packet buffer area stores reverse differential data packets, which are used to roll back program data from a second version to a first version, thus utilizing the reverse differential data, and the corresponding program data can be rolled back from a newer version to an older version. Because the first storage area stores a large amount of program data, while the difference between the first and second versions of the program data is small, and the second storage area stores a small amount of forward and reverse differential data packets, this allows for flexible configuration of the first storage area (larger) and the second storage area (smaller) according to actual needs. This satisfies functional safety requirements during program data upgrades while also supporting the execution of larger amounts of program data, efficiently utilizing the space of non-volatile memory.

[0032] For example, different types of differential algorithms can be used to identify and record the differences between the first and second versions of program data. For instance, if some data in the second version is a segment of data from the first version, a copy instruction will be generated in the differential data packet, indicating how much data to copy from a certain position in the first version to the second version. Forward and reverse differential data packets cannot be directly derived from each other. That is, without the current version of the program data, the reverse differential data packet cannot be obtained from the forward differential data packet through simple calculation, and vice versa.

[0033] The method of this application will be described in detail below with reference to specific embodiments. Figure 2 This is a flowchart of the chip program data upgrade processing method according to an embodiment of this application, as shown below. Figure 2 As shown, the method includes the following steps: S100, configure the first storage area as read-only mode and the second storage area as writable mode, obtain forward differential data packets and reverse differential data packets, store the forward differential data packets in the forward differential packet temporary storage area, and store the reverse differential data packets in the reverse differential data packet temporary storage area. The forward differential data packets are used to upgrade the program data from the first version to the second version, and the reverse differential data packets are used to roll back the program data from the second version to the first version.

[0034] For example, after the chip restarts, the first storage area can be configured as read-only mode, and the second storage area as writable mode. Read-only mode allows only reading of data from the first storage area, preventing data writing. This ensures that the first storage area cannot be written to by other data during the acquisition of forward and reverse differential data packets, protecting the data security of the first storage area. The second storage area being writable prepares the necessary conditions for forward and reverse differential data packets to be written to the second storage area.

[0035] In one embodiment of this application, after configuring the first storage area as read-only mode and the second storage area as writable mode, the method further includes: directly reading the program data from the first storage area through the computing unit and executing it to obtain forward differential data packets and reverse differential data packets.

[0036] In this embodiment, the non-volatile memory supports fast data reading by the computing unit, allowing program data to be executed directly in the non-volatile memory. This means that computing units such as the CPU can directly read one or more program instructions from the non-volatile memory and execute them, without needing to transfer all or part of the corresponding program data to the chip's RAM for retrieval and execution. Furthermore, during program execution, only a small amount of data, such as variables, can be loaded into memory, significantly saving chip memory space.

[0037] For example, one or more computing units in the chip can directly read program data from the first storage area and execute it, and obtain corresponding forward differential data packets and reverse differential data packets from other devices according to data instructions.

[0038] Forward differential data packets are used to upgrade program data from version 1 to version 2. Version 1 can be the currently used version, such as an older version, while version 2 can be the new version to which the upgrade is desired. The forward differential data packet itself can be the difference between version 1 and version 2 of the program data. Because the difference between version 1 and version 2 is small, the size of the forward differential data packet is relatively small, yet it can still be used to upgrade the current program data.

[0039] Similarly, reverse differential packets are used to roll back program data from version 2 to version 1. Version 2 can be the upgraded new version, while version 1 can be the old version. The reverse differential packet itself can be the difference between version 2 and version 1 of the program data. Because the difference between version 2 and version 1 of the program data is small, the reverse differential packet is still small in size and can still be used to roll back the current program data, restoring it to the original version 1 (the old version).

[0040] In this embodiment, on the one hand, the computing unit can obtain forward differential data packets and reverse differential data packets from other devices in various ways, such as through a network or a host computer. The forward differential data packets are stored in the forward differential packet temporary storage area of ​​the second storage area, and the reverse differential data packets are stored in the reverse differential data packet temporary storage area of ​​the second storage area. Simultaneous acquisition and storage of both forward and reverse differential data packets eliminates the need to re-download the reverse differential data packets via networking or other means to complete the rollback operation. This avoids the second version of the program data from malfunctioning, preventing the system from being unable to download or obtain the reverse differential data packets, thus avoiding system crashes and potential functional safety hazards.

[0041] Furthermore, the timing of the steps to obtain forward differential data packets and reverse differential data packets can be flexible and is not limited here.

[0042] S200, after the chip restarts, the first storage area is configured to be writable. If the preset flag bit of the chip is detected to meet the first preset condition, the forward differential data packet stored in the forward differential packet temporary storage area is read. The preset flag bit meeting the first preset condition indicates that the program data of the chip is in an upgrade-ready state.

[0043] For example, if an update operation is required for the program data, the chip needs to be restarted. After the chip restarts, the first storage area is configured to writable mode, allowing the first storage area to subsequently write the data that needs to be updated. The bootloader is retrieved from the first storage area by the chip's computing unit. This computing unit can be the same as or different from the computing unit used to retrieve the forward differential data packets and the reverse differential data packets. For example, the first computing unit can retrieve the forward differential data packets and the reverse differential data packets and store them in the second storage area, while the second computing unit can then retrieve the bootloader from the first storage area. The first computing unit and the second computing unit can be the same or different.

[0044] For example, the bootloader can be stored in the first storage area of ​​non-volatile memory. When needed, it can be loaded into the chip's volatile memory from the first storage area via a computing unit and then run. Alternatively, the bootloader can be obtained via a network, such as by directly downloading it to the chip's volatile memory. The chip's volatile memory has the characteristics of data loss upon power failure, fast read speed, and the ability to be shared. For example, the volatile memory can be the chip's main memory, i.e., RAM.

[0045] For example, the preset flag bit can be multiple data bits in a non-volatile memory cell. Different data stored in the data bits represent different types of flags. For example, the specific content of the preset flag bit and its representation meaning are as follows: the data content of the preset flag bit is 0 normal, which indicates that the chip's program data is in normal operating state. The preset flag bit has a data content of 1 update, indicating that the chip's program data is in a state of waiting to be upgraded; The preset flag bit contains the value 2 updating, indicating that the chip's program data is in an upgrade state. The preset flag bit contains the value 3 rollback, indicating that the chip's program data is in a state of waiting to be rolled back. The default flag contains the value 4 (rollbacking), indicating that the chip's program data is in a rollback state.

[0046] When the data content of the preset flag bit is 1 update, it indicates that the preset flag bit meets the first preset condition, meaning that the chip's program data is in a state awaiting upgrade, and a complete update operation can then be performed on the chip's program data version. In this embodiment, the bootloader detects whether the chip's preset flag bit meets the first preset condition. If it does, it determines that the chip's software (such as the operating system, firmware, etc.) is in a state awaiting upgrade. The bootloader then obtains the forward differential data packet stored in the forward differential packet temporary storage area for subsequent update operations. If the preset flag bit does not meet the first preset condition, the chip can perform corresponding actions based on the current content of the preset flag bit, such as completing the remaining update operations or performing a rollback operation.

[0047] S300, based on the positive differential data packet, update the program data in the first storage area so that after the chip restarts again, the chip's computing unit reads the second version of the program data from the first storage area and executes it.

[0048] It should be noted that after the chip restarts again, it can be either the first restart or the Nth (N>1) restart; there is no restriction here.

[0049] For example, reading the second version of program data can be done directly from the first storage area or indirectly from the first storage area, such as first transferring the program data to volatile memory RAM, and then the computing unit reading it from volatile memory RAM.

[0050] For example, if the chip's program data is in a state awaiting upgrade, the computing unit can update the program data in the first storage area based on forward differential data packets. For instance, it can use data from the forward differential data packets to overwrite the differences between the second and first versions of the program data. After the chip restarts, the computing unit can directly read the second version of the program data from the first storage area and execute it, allowing the program data to be executed in the first storage area with the new version. This enables rapid upgrades of the corresponding program data. For example, the chip's operating system, drivers, and firmware can run in the first storage area with the new version. This also simultaneously enables the chip's program data to run in XIP (eXecute In Place, where the CPU directly reads and executes code from non-volatile storage media without copying the code to RAM, essentially "running in place") mode on the chip's non-volatile memory (such as PFlash).

[0051] In addition, after the update operation is completed, the preset flag bit in the chip can be cleared to prevent the chip from performing the update operation again after the next restart.

[0052] Since the first storage area, capable of storing program data, can be set relatively large, while the second storage area, capable of storing forward and reverse differential data packets, can be set relatively small, the use and upgrade of program data with large amounts of data can be satisfied without expanding the space of non-volatile memory. At the same time, a larger amount of program data can be stored in the first storage area, thereby improving the chip's responsiveness.

[0053] The data upgrade processing method of the chip in this application embodiment can still use the stored positive differential data packets without losing them, while ensuring that the non-volatile memory of the chip does not expand its storage space. This upgrades the program data in the non-volatile memory, avoiding an increase in chip cost. At the same time, since the first storage area of ​​the non-volatile memory can be set relatively large, the chip can use program data with a larger amount of data, improving chip performance while ensuring data security.

[0054] In one embodiment of this application, before obtaining the forward differential data packets stored in the forward differential packet buffer, the method further includes the following steps: Change the flag to be upgraded to the flag in progress.

[0055] For example, if the preset flag is a pending upgrade flag, it is determined that the preset flag meets the first preset condition, thus indicating that the chip's program data is in a pending upgrade state. Here, the pending upgrade flag can be modified to an upgrade-in-progress flag, where the upgrade-in-progress flag indicates that the chip's program data is being upgraded. Then, the forward differential data packet stored in the forward differential packet temporary storage area is obtained, and the program data in the first storage area is updated using this forward differential data packet.

[0056] In one embodiment of this application, the update operation on the program data in the first storage area based on the forward differential data packet is as follows: Figure 3 As shown, it includes the following steps: S310, Based on the forward differential data packet, generate the corresponding update data block.

[0057] For example, after reading forward differential data packets from the second storage area and program data from the first storage area, a corresponding update data block can be generated based on the forward differential data packets and the current program data. This generated update data block is adapted to the program data and can be used to completely or partially replace the program data.

[0058] For example, update data blocks can be generated according to a fixed data size. The update data blocks to be written to the first storage area are cached in RAM. Once the cache reaches a certain size, such as 1KB, it is ready to be written to the corresponding address in the first storage area. Before writing, the data in this area is backed up to a data buffer. The data buffer can be set in a writable area of ​​a non-volatile storage medium, such as within or near the forward differential packet buffer, and records the location information and upgrade status of the program data segment to be upgraded in the first storage area. Then, the data cached in RAM is written to the corresponding address in the first storage area. If the write process fails, such as due to a power outage, the program data upgrade mode will still be entered upon the next startup. The data in the data buffer will be copied to the corresponding location in the first storage area, or first copied to RAM and then to the corresponding location in the first storage area. From that location, the forward differential data packet will be called again to calculate the update data block and continue the upgrade process. This achieves the effect of continuing the upgrade process even after a power outage and restart.

[0059] S320, determine the update region in the first storage region.

[0060] For example, determining the updated regions in the first storage region includes identifying and recording the regions in the first storage region that have already been updated, as well as the regions that have not yet been updated. Specifically, this includes determining the address and range of the updated regions.

[0061] S330, the updated data block is written into the corresponding update area to update part or all of the program data.

[0062] For example, updated data blocks are written to areas that have not yet been updated, and the attributes of those areas are set to updated. This allows it to determine which program data in the first storage area has been updated and which has not. This will allow some or all of the program data to be updated, for example, the program data is updated to version two, so that the corresponding program data can run with the new version.

[0063] For example, step S320 of this application can be executed after step S310 or before step S310, and there is no limitation on this.

[0064] In one embodiment of this application, such as Figure 4 As shown and combined Figure 10After the chip restarts, the method further includes the following steps: S400, the preset flag bit is detected as an upgrade flag bit, indicating that the last update operation of the chip was interrupted.

[0065] For example, the preset flag can be of various types. After the chip restarts, the computing unit loads the bootloader from the first storage area into the chip's volatile memory, such as the chip's RAM. The bootloader runs in memory and detects the preset flag in the chip.

[0066] The preset flag bit is detected as being in the process of upgrading, indicating that the chip's previous update operation was interrupted and not completed. In the current situation, the remaining part of the program data needs to be updated.

[0067] S500, determine the portion to be updated in the first storage area.

[0068] For example, the updated portion and the portion to be updated in the first storage area can be determined by the bootloader, wherein the updated portion may be the portion of the first storage area that was updated in the previous update operation, and the portion to be updated may be the portion of the first storage area that was not updated in the previous update operation.

[0069] Determining the portion to be updated in the first storage area includes identifying its location, address range, and other information. For example, the updated portions in the first storage area can be determined based on write information recorded during historical updates, and then the portion to be updated in the first storage area can be determined based on these updated portions. Alternatively, the updated portions in the first storage area can be determined based on the time information of the data written to it. Another example is determining the updated portions based on the next segment of data to be updated, and then determining the portion to be updated in the first storage area based on these updated portions.

[0070] S600, based on the portion to be updated, resume the update operation on the first storage area.

[0071] For example, based on the information of the updated portion in the first storage area, the information of the portion to be updated in the first storage area can be determined, thereby resuming the update operation on the portion to be updated in the first storage area. There is no need to update the already updated portion again, saving update time and improving update efficiency. Furthermore, since there are no duplicate update operations or omissions, the accuracy of the program data after the update operation is guaranteed. In addition, after the update operation is completed, a preset flag bit in the chip can be cleared to prevent the chip from performing the update operation again upon the next restart.

[0072] In one embodiment of this application, determining the portion to be updated in the first storage area, such as... Figure 5 As shown, it includes the following steps: S510, acquire the data stored in the data buffer area of ​​the non-volatile memory during the last update operation of the chip, wherein the data buffer area is used to temporarily store data to be written to the first memory area; S520, based on the data in the data temporary storage area, determine the portion in the first storage area to be updated.

[0073] For example, during the update of the first storage area based on forward differential data packets, the data in the forward differential data packets can be temporarily stored in a data buffer in non-volatile memory, and then the data in the data buffer is written into the first storage area. Alternatively, the data in the data buffer can be written into memory first, and then written into the first storage area via memory. During this process, if an interruption occurs, even if the data in memory is lost or the data being written to the first storage area is corrupted, the data in the data buffer will not be lost. The data in the data buffer can still be written back into the first storage area after the chip restarts. Furthermore, during the writing process to the first storage area, relevant information about the data stored in the data buffer, such as the location information of the data being written to the first storage area, can be recorded. This recorded information can then be used to determine the updated portion of the first storage area, and subsequently, the portion to be updated can be determined based on the updated portion. This further ensures the accuracy of the data update.

[0074] In one embodiment of this application, determining the portion to be updated in the first storage area, such as... Figure 6 As shown, it includes the following steps: S530, acquire the data stored in the data buffer area of ​​the non-volatile memory during the last update operation of the chip, wherein the data buffer area is used to temporarily store the data in the first memory area that is to be overwritten; S540, based on the data in the data temporary storage area, determine the portion in the first storage area to be updated.

[0075] For example, the data buffer is used to temporarily store data in the first storage area to be overwritten. For instance, the temporarily stored data could be a portion of the program data from the first version in the first storage area, which was to be overwritten but was not due to an interruption. Because the data buffer can temporarily store this data, even if an interruption occurs during the overwriting process, such as a power outage, the data stored in the data buffer in the non-volatile memory during the chip's previous update operation can still be accurately and completely obtained after the chip restarts. Based on the obtained data, the location of the first storage area being overwritten when the previous update operation was interrupted can be determined, thus identifying the portion of the first storage area to be updated during the previous update operation.

[0076] In one embodiment of this application, such as Figure 7 As shown and combined Figure 11 The method further includes: S10, after the chip restarts, if the preset flag bit is detected as a rollback flag bit, the rollback flag bit is modified to a rollback in progress flag bit.

[0077] For example, a rollback operation is an operation that restores program data from an error / abnormal state to the previous known stable version. Its core is to undo executed but unconfirmed or problematic changes, ensuring consistency and availability.

[0078] After the chip restarts, the computing unit loads the bootloader into the chip's memory. The bootloader checks preset flags; if the flag is set to "to be rolled back," it indicates that the chip needs to perform a rollback operation on the first memory area, reverting the program data from version two to version one. Before performing the critical steps of the rollback operation, the "to be rolled back" flag can be changed to the "rollback in progress" flag, and then the subsequent critical steps of the rollback operation can be performed. This indicates that the chip is currently performing a rollback operation.

[0079] S20, obtain the reverse differential data packet from the reverse differential packet buffer area.

[0080] For example, the reverse differential data packet is the difference between the second version and the first version of the program data, that is, it represents the data difference between the second version (such as the upgraded new version) and the first version (the old version before the upgrade).

[0081] The differential data packet has a small data size and occupies a small space in the reverse differential packet temporary storage area of ​​the second storage area. The bootloader obtains the reverse differential data packet from the reverse differential packet temporary storage area and uses it to perform a rollback operation on the current program data, so that the program data can be restored to the version before the upgrade, that is, the relatively old version.

[0082] S30, based on the reverse differential data packet, perform a rollback operation on the program data.

[0083] Specifically, the chip's preset flag can be set to the rollback flag, indicating that the chip is currently performing a rollback operation. Reverse differential data packets are read from the reverse differential packet buffer.

[0084] In one embodiment, such as Figure 8 As shown, step S30 specifically includes the following steps: S31, Based on the reverse differential data packet, generate the corresponding rollback data block; S32, determine the rollback region in the first storage region; S33, the rollback data block is written into the corresponding rollback area to restore all or part of the program data to the corresponding first version.

[0085] Specifically, rollback data blocks are generated based on reverse differential data packets. These rollback data blocks are adapted to the program data and can be used to overwrite the program data. Furthermore, it is necessary to determine the location of the area in the first storage region where rollback operations need to be performed, such as the region range or address range. The rollback data blocks are used to write the program data within the corresponding region in the first storage region, thereby restoring all or part of the program data to the corresponding first version (such as the old version before the upgrade). Additionally, the regions in the first storage region where rollback operations have been performed are recorded so that they can be used for subsequent operations on the program data in the first storage region.

[0086] For example, rollback data blocks can be generated according to a fixed data size. The rollback data blocks to be written to the first storage area are cached in RAM. Once the cache reaches a certain size, such as 1KB, they are prepared to be written to the corresponding address in the first storage area. Before writing, the second version of the program data in this area is backed up to a data buffer. The data buffer can be set in a writable area of ​​a non-volatile storage medium, such as within or near the reverse differential packet buffer, and records the location information and rollback status of the program data segment to be rolled back in the first storage area. Then, the data cached in RAM is written to the corresponding address in the first storage area. If the write process fails, such as due to a power outage, the program data rollback mode will still be entered upon the next startup. The data in the data buffer will be copied to the corresponding location in the first storage area, or first copied to RAM and then to the corresponding location in the first storage area. From that location, the reverse differential packet will be called again to calculate the rollback data block and continue the rollback operation, thus achieving the effect of continuing the rollback after a power outage and restart.

[0087] S40, after the rollback operation is completed, the rollback flag is cleared.

[0088] For example, after restoring all or part of the program data to the corresponding pre-upgrade version data, it can be determined whether the rollback operation has been completed in the current situation. This can be done by checking whether the data writing operation is still in progress, or by using relevant completion flag information to determine whether the rollback operation has been completed. If the rollback operation has been completed, the rollback flag is cleared, so that the chip will not perform a rollback operation again after restarting and can be used normally.

[0089] In one embodiment of this application, such as Figure 9 As shown and combined Figure 11 The method further includes the following steps: S50, after the chip restarts, the bootloader detects that the preset flag is a rollback flag, and determines that the chip's previous rollback operation was interrupted.

[0090] For example, after the chip restarts, the computing unit loads the bootloader into the chip's memory. The bootloader detects a preset flag. If the preset flag is detected as a rollback flag, it indicates that the chip's previous rollback operation was not fully completed and a rollback interruption occurred. In the current case, it is necessary to resume the incomplete rollback operation on the first storage area.

[0091] S60, determine the portion to be rolled back in the first storage area.

[0092] For example, after a data rollback interruption during the chip's previous rollback operation, the first storage area includes a rolled-back portion and a portion to be rolled back. The rolled-back portion is the part of the first storage area where the rollback operation has been completed, and the portion to be rolled back is the part of the first storage area where the rollback operation has not yet been performed. The portion to be rolled back can also be determined using the aforementioned data buffer area, based on the data temporarily stored in the data buffer area. Specifically, this can involve obtaining data from the data buffer area stored in the non-volatile memory during the chip's previous rollback operation, where the data buffer area is used to temporarily store data in the first storage area to be rolled back. Based on the data in the data buffer area, the portion to be rolled back in the first storage area is determined.

[0093] S70, based on the portion to be rolled back, resume the rollback operation on the first storage area.

[0094] Specifically, after identifying the portion to be rolled back in the first storage area, the rollback operation is resumed on the first storage area, and then the rollback operation continues on the portion to be rolled back. This process continues until the entire rollback operation is completed. Furthermore, after the rollback operation is complete, a preset flag bit (rollback flag bit) in the chip can be cleared to prevent the chip from performing a rollback operation again upon the next restart. Because there are no duplicate rollback operations or omissions, the accuracy of the program data after the rollback operation is guaranteed.

[0095] In one embodiment of this application, after performing a rollback operation on the program data, as follows: Figure 10 As shown and combined Figure 11 The method further includes the following steps: S80, perform a verification operation on the program data in the first storage area; S90, after the verification operation is successful, the chip is restarted, the first version of the program data is read and executed.

[0096] For example, after rolling back program data, the results need to be verified to determine if they meet the requirements. Specifically, this involves verifying the program data in the first storage area, including integrity and correctness checks. Passing the verification indicates that the rolled-back program data meets the requirements. After restarting the chip, the first version of the program data is read and executed, allowing the use of the rolled-back program data. For example, an older version of the operating system or driver can be used.

[0097] In one embodiment, after updating the program data, the program data in the first storage area can also be verified. After the verification is successful, the chip is restarted, the second version of the program data is read and executed.

[0098] This application embodiment also provides a chip, including a computing unit and a non-volatile memory. The non-volatile memory is communicatively connected to the computing unit and configured to have a first storage area and a second storage area. The first storage area is used to store program data based on the operation of the chip. The second storage area has a forward differential packet buffer area and a reverse differential packet buffer area. The first storage area is larger than the second storage area. The computing unit is configured as follows: Configure the first storage area as read-only mode and the second storage area as writable mode. Obtain forward differential data packets and reverse differential data packets. Store the forward differential data packets in the forward differential packet temporary storage area and store the reverse differential data packets in the reverse differential data packet temporary storage area. The forward differential data packets are used to upgrade the program data from the first version to the second version, and the reverse differential data packets are used to roll back the program data from the second version to the first version. After the chip restarts, the first storage area is configured to be writable. If the preset flag bit of the chip is detected to meet the first preset condition, the forward differential data packet stored in the forward differential packet temporary storage area is read. The preset flag bit meeting the first preset condition indicates that the program data of the chip is in an upgrade-ready state. Based on the positive differential data packet, the program data in the first storage area is updated so that after the chip restarts, the chip's computing unit reads and executes the second version of the program data from the first storage area.

[0099] For example, after the chip restarts, the first storage area can be configured as read-only mode, and the second storage area as writable mode. Read-only mode allows only reading of data from the first storage area, preventing data writing. This ensures that the first storage area cannot be written to by other data during the acquisition of forward and reverse differential data packets, protecting the data security of the first storage area. The second storage area being writable prepares the necessary conditions for forward and reverse differential data packets to be written to the second storage area.

[0100] In one embodiment of this application, after configuring the first storage area as read-only mode and the second storage area as writable mode, the method further includes: directly reading the program data from the first storage area through the computing unit and executing it to obtain forward differential data packets and reverse differential data packets.

[0101] In this embodiment, the non-volatile memory supports fast data reading by the computing unit, allowing program data to be executed directly in the non-volatile memory. This means that computing units such as the CPU can directly read one or more program instructions from the non-volatile memory and execute them, without needing to transfer all or part of the corresponding program data to the chip's RAM for retrieval and execution. Furthermore, during program execution, only a small amount of data, such as variables, can be loaded into memory, significantly saving chip memory space.

[0102] For example, one or more computing units in the chip can directly read program data from the first storage area and execute it, and obtain corresponding forward differential data packets and reverse differential data packets from other devices according to data instructions.

[0103] Forward differential data packets are used to upgrade program data from version 1 to version 2. Version 1 can be the currently used version, such as an older version, while version 2 can be the new version to which the upgrade is desired. The forward differential data packet itself can be the difference between version 1 and version 2 of the program data. Because the difference between version 1 and version 2 is small, the size of the forward differential data packet is relatively small, yet it can still be used to upgrade the current program data.

[0104] Similarly, reverse differential packets are used to roll back program data from version 2 to version 1. Version 2 can be the upgraded new version, while version 1 can be the old version. The reverse differential packet itself can be the difference between version 2 and version 1 of the program data. Because the difference between version 2 and version 1 of the program data is small, the reverse differential packet is still small in size and can still be used to roll back the current program data, restoring it to the original version 1 (the old version).

[0105] In this embodiment, on the one hand, the computing unit can obtain forward differential data packets and reverse differential data packets from other devices in various ways, such as through a network or a host computer. The forward differential data packets are stored in the forward differential packet temporary storage area of ​​the second storage area, and the reverse differential data packets are stored in the reverse differential data packet temporary storage area of ​​the second storage area. Simultaneous acquisition and storage of both forward and reverse differential data packets eliminates the need to re-download the reverse differential data packets via networking or other means to complete the rollback operation. This avoids the second version of the program data from malfunctioning, preventing the system from being unable to download or obtain the reverse differential data packets, thus avoiding system crashes and potential functional safety hazards.

[0106] Furthermore, the timing of the steps to obtain forward differential data packets and reverse differential data packets can be flexible and is not limited here.

[0107] If program data updates are required, the chip needs to restart. After restarting, the first storage area is configured as writable, allowing subsequent writing of the necessary updated data. The chip's computing unit retrieves the bootloader from the first storage area. This computing unit can be the same as or different from the unit used to retrieve the forward and reverse differential data packets. For example, the first computing unit can retrieve the forward and reverse differential data packets and store them in the second storage area, while the second computing unit can retrieve the bootloader from the first storage area. The first and second computing units can be the same or different.

[0108] The bootloader can be stored in the first storage area of ​​non-volatile memory. When needed, it can be loaded into the chip's volatile memory via a computing unit from the first storage area and then executed. Alternatively, the bootloader can be obtained via a network, such as by directly downloading it to the chip's volatile memory. The chip's volatile memory features data loss upon power failure, fast read speed, and the ability to be shared. For example, volatile memory can be the chip's main memory, i.e., RAM.

[0109] For example, the preset flag bits can be multiple data bits in a non-volatile memory cell. Different data stored in the data bits represent different types of flags. For example, the specific content of the preset flag bits and their representational meanings are as follows: The preset flag bit has a data content of 0 (normal), indicating that the chip's program data is in normal operating condition. The preset flag bit has a data content of 1 update, indicating that the chip's program data is in a state of waiting to be upgraded; The preset flag bit contains the value 2 updating, indicating that the chip's program data is in an upgrade state. The preset flag bit contains the value 3 rollback, indicating that the chip's program data is in a state of waiting to be rolled back. The default flag contains the value 4 (rollbacking), indicating that the chip's program data is in a rollback state.

[0110] When the data content of the preset flag bit is 1 update, it indicates that the preset flag bit meets the first preset condition, and the chip's program data is in an upgrade-ready state, meaning that a complete update operation can be performed on the chip's program data version. In this embodiment, the bootloader detects whether the chip's preset flag bit meets the first preset condition. If it does, it determines that the chip's software (such as the operating system, firmware, etc.) is in an upgrade-ready state. The bootloader then obtains the forward differential data packet stored in the forward differential packet temporary storage area for subsequent update operations. If the preset flag bit does not meet the first preset condition, the chip can perform corresponding actions based on the current content of the preset flag bit, such as completing the remaining update operations or performing a rollback operation.

[0111] It should be noted that after the chip restarts again, it can be either the first restart or the Nth (N>1) restart; there is no restriction here.

[0112] For example, reading the second version of program data can be done directly from the first storage area or indirectly from the first storage area, such as first transferring the program data to volatile memory RAM, and then the computing unit reading it from volatile memory RAM.

[0113] If the chip's software is in an upgrade-ready state, the computing unit can update the program data in the first storage area based on forward differential data packets. For example, it can use data from the forward differential data packets to overwrite the differences between the second and first versions of the program data. After the chip restarts, the computing unit can directly read the second version of the program data from the first storage area and execute it, allowing the program data to be executed in the first storage area with the new version. This enables rapid upgrades of the corresponding program data. For example, the chip's operating system, drivers, and firmware can run in the first storage area with the new version. This also allows the chip's program data to run in XIP (eXecute In Place, where the CPU directly reads and executes code from non-volatile storage media without copying the code to RAM, essentially "running in place") mode on the chip's non-volatile memory (such as PFlash).

[0114] In addition, after the update operation is completed, the preset flag bit in the chip can be cleared to prevent the chip from performing the update operation again after the next restart.

[0115] Since the first storage area, capable of storing program data, can be set relatively large, while the second storage area, capable of storing forward and reverse differential data packets, can be set relatively small, the use and upgrade of program data with large amounts of data can be satisfied without expanding the space of non-volatile memory. At the same time, a larger amount of program data can be stored in the first storage area, thereby improving the chip's responsiveness.

[0116] This application also provides a chip, such as... Figure 12 As shown, it includes a memory and a processor, wherein the memory stores an executable program and the processor processes the executable program to perform the steps of the method described above.

[0117] This application also provides a vehicle that includes the chip described above.

[0118] This application also provides a storage medium carrying one or more computer programs, which, when executed by a processor, implement the steps of the method described above.

[0119] This application also provides a computer program product, including a computer program / instructions, characterized in that the computer program / instructions, when executed by a processor, implement the steps of the method described above.

[0120] It should be understood that in the embodiments of this application, the processor may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0121] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0122] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated into the processor.

[0123] It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.

[0124] It should also be understood that the first, second, third, fourth and various numerical designations used herein are merely for descriptive convenience and are not intended to limit the scope of this application.

[0125] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0126] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0127] In the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0128] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0129] In the several embodiments provided in this application, it should be understood that the disclosed methods and chips can be implemented in other ways. For example, the hardware accelerator embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0130] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0131] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0132] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0133] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for upgrading program data of a chip, characterized in that, A method applicable to a chip having a computing unit, the chip having non-volatile memory, the non-volatile memory being communicatively connected to the computing unit and configured to have a first storage region and a second storage region, the first storage region being used to store program data based on the operation of the chip, and the second storage region having a forward differential packet buffer area and a reverse differential packet buffer area, wherein the first storage region is larger than the second storage region, the method comprising: Configure the first storage area as read-only mode and the second storage area as writable mode. Obtain forward differential data packets and reverse differential data packets. Store the forward differential data packets in the forward differential packet temporary storage area and store the reverse differential data packets in the reverse differential data packet temporary storage area. The forward differential data packets are used to upgrade the program data from the first version to the second version, and the reverse differential data packets are used to roll back the program data from the second version to the first version. After the chip restarts, the first storage area is configured to be writable. If the preset flag bit of the chip is detected to meet the first preset condition, the forward differential data packet stored in the forward differential packet temporary storage area is read. The preset flag bit meeting the first preset condition indicates that the program data of the chip is in an upgrade-ready state. Based on the positive differential data packet, the program data in the first storage area is updated so that after the chip restarts, the chip's computing unit reads and executes the second version of the program data from the first storage area.

2. The chip program data upgrade processing method according to claim 1, characterized in that, After configuring the first storage area as read-only mode and the second storage area as writable mode, the method further includes: The computing unit directly reads and executes the program data from the first storage area to obtain forward differential data packets and reverse differential data packets.

3. The chip program data upgrade processing method according to claim 1, characterized in that, Before reading the forward differential data packets stored in the forward differential packet buffer, the method further includes: Change the flag to be upgraded to the flag in progress.

4. The chip program data upgrade processing method according to claim 1, characterized in that, The step of updating the program data in the first storage area based on the forward differential data packet includes: Based on the forward differential data packets, corresponding update data blocks are generated; Determine the update region within the first storage region; The updated data block is written into the corresponding update area to update part or all of the program data.

5. The chip program data upgrade processing method according to claim 1, characterized in that, After the chip restarts, the method further includes: If the preset flag is detected as an upgrade flag, it indicates that the last update operation of the chip was interrupted. Identify the portion of the first storage area to be updated; Based on the portion to be updated, the update operation on the first storage area is resumed.

6. The chip program data upgrade processing method according to claim 5, characterized in that, Determining the portion to be updated in the first storage area includes: During the last update operation of the chip, the data stored in the data buffer area of ​​the non-volatile memory is obtained, wherein the data buffer area is used to temporarily store data to be written into the first memory area; Based on the data in the data temporary storage area, the portion of the first storage area to be updated is determined.

7. The chip program data upgrade processing method according to claim 5, characterized in that, Determining the portion to be updated in the first storage area includes: During the last update operation of the chip, the data stored in the data buffer area of ​​the non-volatile memory is obtained, wherein the data buffer area is used to temporarily store the data in the first memory area that is to be overwritten; Based on the data in the data temporary storage area, the portion of the first storage area to be updated is determined.

8. The chip program data upgrade processing method according to claim 1, characterized in that, The method further includes: After the chip restarts, if the preset flag is detected as a rollback flag, the rollback flag is changed to a rollback in progress flag. The reverse differential data packet is obtained from the reverse differential packet buffer area; Based on the reverse differential data packet, the program data is rolled back. After the rollback operation is completed, the rollback flag is cleared.

9. The chip program data upgrade processing method according to claim 8, characterized in that, The rollback operation on the program data based on the reverse differential data packet includes: Based on the reverse differential data packet, a corresponding rollback data block is generated; Determine the rollback region in the first storage region; The rollback data block is written into the corresponding rollback area to restore all or part of the program data to the corresponding first version.

10. The chip program data upgrade processing method according to claim 8, characterized in that, The method further includes: After the chip restarts, if the preset flag is detected as a rollback flag, it is determined that the previous rollback operation of the chip was interrupted. Identify the portion to be rolled back in the first storage area; Based on the portion to be rolled back, the rollback operation on the first storage area is resumed.

11. The chip program data upgrade processing method according to claim 8, characterized in that, After performing a rollback operation on the program data, the method further includes: Perform a verification operation on the program data in the first storage area; After the verification operation is successful, the chip is restarted, the first version of the program data is read and executed.

12. A chip, characterized in that, The system includes a computing unit and a non-volatile memory. The non-volatile memory is communicatively connected to the computing unit and configured to have a first storage area and a second storage area. The first storage area is used to store program data based on the operation of the chip. The second storage area has a forward differential packet buffer area and a reverse differential packet buffer area. The first storage area is larger than the second storage area. The computing unit is configured as follows: Configure the first storage area as read-only mode and the second storage area as writable mode. Obtain forward differential data packets and reverse differential data packets. Store the forward differential data packets in the forward differential packet temporary storage area and store the reverse differential data packets in the reverse differential data packet temporary storage area. The forward differential data packets are used to upgrade the program data from the first version to the second version, and the reverse differential data packets are used to roll back the program data from the second version to the first version. After the chip restarts, the first storage area is configured to be writable. If the preset flag bit of the chip is detected to meet the first preset condition, the forward differential data packet stored in the forward differential packet temporary storage area is read. The preset flag bit meeting the preset condition indicates that the program data of the chip is in an upgrade-ready state. Based on the positive differential data packet, the program data in the first storage area is updated so that after the chip restarts, the chip's computing unit reads and executes the second version of the program data from the first storage area.

13. A chip, characterized in that, The system includes a memory and a processor, wherein the memory stores an executable program and the processor processes the executable program to perform the steps of the method as described in claim 1.

14. A vehicle, characterized in that, Including the chip as described in claim 12.

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