Directed acyclic graph reasoning scheduling method and system for heterogeneous computing platform

Abstract

The invention discloses a directed acyclic graph reasoning scheduling method and system for a heterogeneous computing platform, and the method comprises the steps: S1, determining task priorities: for each computing task in a DAG, calculating priority parameters of the sensitivity of the task to heterogeneous resources based on the execution performance data of a task node on a GPU and different numbers of CPU cores, the priorities of the tasks are determined according to the priority parameters; s2, opportunity cost modeling: respectively establishing opportunity cost models for GPU and CPU resources, wherein the opportunity cost models are used for quantifying potential performance loss possibly caused to subsequent tasks when the resources are allocated to the current task; s3, scheduling decision making: generating a scheduling decision according to the task priority and the opportunity cost; and S4, task execution: scheduling and executing the calculation task in the directed acyclic graph on the heterogeneous calculation platform according to the determined execution scheme. The method aims at solving the problems that in the prior art, scheduling decisions are short in view and prone to falling into local optimum, and task priority ranking is not accurate.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence model reasoning optimization technology, specifically to a directed acyclic graph reasoning scheduling method and system for heterogeneous computing platforms. Background Technology

[0002] In recent years, artificial intelligence technologies centered on deep learning have made rapid progress, particularly in areas such as object detection and natural language processing. Mainstream object detection models, such as YOLO and Faster R-CNN, have improved recognition accuracy, but their network structures have also become increasingly complex, resulting in massive computational demands. Deploying these models on edge computing devices (such as embedded systems and mobile terminals) with limited computing power, storage space, and power consumption budgets to meet the low-latency, high-throughput application requirements of real-time video analytics has become a core challenge.

[0003] To accelerate model inference on edge devices, the computation process is typically abstracted as a directed acyclic graph (DAG) with operators (tasks) as nodes and data dependencies as directed edges, and executed on heterogeneous computing hardware. A typical edge heterogeneous computing platform usually contains one or more graphics processing units (GPUs) and a multi-core central processing unit (CPU). GPUs, with their massively parallel computing architecture, excel at handling computationally intensive tasks such as convolution; while CPUs are more flexible and efficient when handling tasks with complex control flows or lower computational loads. Therefore, designing efficient scheduling algorithms to rationally allocate different operators in the DAG to GPUs or CPUs for execution, and determining the appropriate number of parallel cores for operators allocated to the CPU, are crucial to determining the end-to-end inference performance of the model.

[0004] In the existing technology, there are already some DAG scheduling algorithms for heterogeneous environments, such as the classic HEFT (Heterogeneous Earliest-Finish-Time) algorithm. This type of algorithm usually adopts a list scheduling framework. First, it calculates a static priority based on certain attributes of the task (such as the average execution time on different processors). Then, according to the priority order, it greedily selects an execution plan (i.e., which processor to allocate it to for execution) for each ready task that will enable it to "complete earliest" (Earliest Finish Time, EFT).

[0005] However, existing scheduling methods have one or more significant drawbacks when applied to the specific and common heterogeneous architecture of "GPU and shared CPU core pool": (1) The scheduling decision lacks foresight and is prone to falling into the "local optimum" trap: Existing methods (such as HEFT or Greedy algorithms) usually only focus on the immediate benefit of the current task when making scheduling decisions, that is, how to make the current task complete itself as quickly as possible. This "short-sighted" greedy strategy ignores the long-term impact of scheduling decisions on subsequent tasks. For example, in order to make a task A with low computational cost and little effect on GPU acceleration complete slightly earlier, the scheduler may allocate it to an idle GPU at that time. However, this decision may cause a critical task B that follows closely behind and has a high dependence on GPU performance to have to wait for the GPU resources to be released for a long time, thus significantly lengthening the final completion time (Makespan) of the entire computation graph. Existing technologies lack a mechanism to quantify the "resource occupation cost" and cannot predict and avoid such global performance bottlenecks caused by misallocation of resources.

[0006] (2) The task priority ranking mechanism is crude and cannot accurately identify critical tasks: Existing methods typically use the "average execution time" of a task across all available processors as its computational cost when calculating task priorities. This "averaging" approach masks the task's "preference" or "sensitivity" to specific resources. For example, a task that is highly efficient on a GPU but performs poorly on a CPU (GPU-friendly task) may have an average execution time similar to another task that is highly parallelizable on a CPU but cannot utilize a GPU (CPU-extended task), causing their priorities to be incorrectly treated as equal. This crude ranking cannot accurately identify the "true" critical tasks that are most sensitive to resource allocation choices and will cause huge performance losses if allocation is misjudged, thus affecting the rationality of the overall scheduling order.

[0007] (3) The resource allocation model for shared CPU core pools is overly simplified: Existing methods typically treat a CPU with multiple cores as a single processor with fixed computing power, or lack a fine-grained consideration of parallel efficiency when allocating cores. In fact, the more cores allocated to a single CPU task, the diminishing marginal return on its execution time (i.e., conforming to Amdahl's Law). At the same time, in a shared CPU core pool, allocating too many cores to a single task will inevitably crowd out the resources of other parallelizable tasks, potentially leading to a decrease in the overall concurrent throughput of the system. Existing technologies lack a CPU core allocation mechanism that can effectively balance "task-level parallelism" and "system-level concurrency".

[0008] In summary, designing a scheduling method that can predict and quantify the future impact of decisions, accurately identify and prioritize scheduling-sensitive tasks, and finely manage shared CPU resources to solve the performance bottleneck problem caused by short-sighted decision-making and inaccurate prioritization in existing technologies is a technical challenge that urgently needs to be addressed in this field. Summary of the Invention

[0009] The main objective of this invention is to provide a Directed Acyclic Graph (DAG) reasoning scheduling method and system for heterogeneous computing platforms. This aims to address problems in existing technologies, such as a lack of foresight in scheduling decisions, susceptibility to poor global performance due to short-sighted greedy strategies, and a crude task priority ranking mechanism that fails to accurately identify and prioritize critical tasks sensitive to resource allocation. To achieve the above objective, this invention provides a DAG reasoning scheduling method for heterogeneous computing platforms, wherein the heterogeneous computing platform includes a graphics processing unit (GPU) and a shared multi-core CPU resource pool. The method comprises the following steps: S1, Determining task priority: For each computation task in the directed acyclic graph (DAG), based on the execution performance data of the task node on the GPU and on different numbers of CPU cores, calculate the priority parameter of the task's sensitivity to heterogeneous resources, and determine the priority of the task according to the priority parameter. S2, Opportunity Cost Modeling: Establish opportunity cost models for GPU resources and CPU resources respectively. The opportunity cost models are used to quantify the potential performance loss that may be caused to subsequent tasks by allocating resources to the current task. S3, Proactive Scheduling Decision: Generating scheduling decisions based on task priority and opportunity cost; S4, Task Execution: According to the determined execution plan, schedule and execute the computing tasks in the directed acyclic graph on the heterogeneous computing platform.

[0010] Furthermore, in step S1, calculating the priority parameter reflecting the task's sensitivity to heterogeneous resources includes: The performance changes of computational tasks under different numbers of CPU cores are analyzed, and the CPU scaling sensitivity of the tasks is quantified. The CPU scaling sensitivity is used to characterize the degree to which the task execution time decreases as the number of CPU cores increases. The performance gain of computational tasks on GPUs is analyzed, and the GPU dominance of tasks is quantified. The GPU dominance of computational tasks is used to characterize the execution speedup of tasks on GPUs relative to CPUs. Based on the CPU extension sensitivity and the GPU dominance, the comprehensive heterogeneity coefficient of the task is calculated, and the comprehensive heterogeneity coefficient is incorporated into the upward sorting algorithm to calculate the final priority of the task.

[0011] Furthermore, the opportunity cost model in step S2 includes: for GPU resources, establishing an opportunity cost model for GPU resources based on future task requirements and dependencies; for CPU resources, establishing an opportunity cost model for CPU resources based on CPU core occupancy and system task congestion.

[0012] Furthermore, step S3, scheduling decision, specifically includes: generating a candidate set including GPU schemes and multiple CPU parallel schemes for each ready task to be scheduled; calculating the risk adjustment score of each candidate scheme based on the opportunity cost model and the expected completion time of the task; and selecting the scheme with the best score as the final scheduling decision.

[0013] Furthermore, the generated candidate set is filtered using a concave hull inflection point evaluation strategy, specifically including: Obtain execution time data points for tasks with different numbers of CPU cores; Construct the lower convex hull of the data points with respect to the core count minus execution time; Only the core number configuration corresponding to the vertex of the lower convex hull is selected as a candidate scheme.

[0014] Furthermore, the risk-adjusted score is calculated using the following formula:

[0015] Where score(o) is the risk-adjusted score of candidate solution o. Given the estimated completion time of task i using scheme o, The execution time of scheme o and The opportunity costs of using GPU and CPU for scheme o are respectively. , , These are configurable weighting coefficients.

[0016] This invention also discloses a directed acyclic graph reasoning scheduling system for heterogeneous computing platforms, the system comprising: The priority determination module is used to perform heterogeneity sensitivity analysis on computational tasks in acyclic graphs and determine the priority of the tasks. The opportunity cost modeling module is used to build opportunity cost models for heterogeneous computing resources; The scheduling decision module is used to generate scheduling decisions based on task priority and opportunity cost; The scheduling execution engine is used to drive the execution of tasks on the heterogeneous computing platform according to the execution plan output by the scheduling decision module.

[0017] By adopting the above technical solution, the present invention can achieve the following beneficial effects: This invention addresses the shortcomings of existing DAG inference scheduling methods, such as short-sighted decision-making, inaccurate identification of critical tasks, and coarse resource allocation. It proposes a forward-looking scheduling mechanism that integrates heterogeneous sensitivity ranking and opportunity cost-based scheduling. Through a dynamic pricing model, the scheduler quantifies the future impact of resource allocation, prioritizing critical path tasks and avoiding inefficient use of scarce resources like GPUs, thereby effectively reducing overall inference latency. Simultaneously, it automatically selects efficient CPU parallel solutions through concave hull inflection point evaluation, achieving efficient utilization of shared CPU resources. This method is applicable to various heterogeneous device architectures and complex neural network computation graphs, possessing advantages such as strong versatility, significant performance improvement, and efficient deployment. It can be widely applied to scenarios with high real-time and resource sensitivity requirements, such as edge AI inference and video analytics. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating an application scenario of the heterogeneous DAG scheduling system for edge target detection inference as described in a specific embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the directed acyclic graph reasoning and scheduling method for heterogeneous computing platforms according to a specific embodiment of the present invention.

[0020] Figure 3 This is a simplified example diagram of a directed acyclic graph to be scheduled, as described in a specific embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the timing results of scheduling a DAG using the traditional HEFT algorithm according to a specific embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the timing results of scheduling a DAG using the PICO algorithm according to a specific embodiment of the present invention.

[0023] Figure 6 This is a graph showing the execution time variation of a typical operator described in a specific embodiment of the present invention under different numbers of CPU cores.

[0024] Figure 7 This is a comparison chart of the normalized execution time of different types of operators on CPU and GPU in a specific embodiment of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026]

Example 1

[0027] like Figure 1 As shown, Figure 1 This is a schematic diagram illustrating an application scenario of the heterogeneous DAG scheduling system for edge target detection inference according to an embodiment of the present invention. The scenario includes one or more deep learning neural network models 101, a heterogeneous DAG modeling and performance profiling module 102, a PICO scheduling and acceleration scheme generation module 103, an edge terminal device 105, and a video / image input source 104. In actual deployment, the system can serve real-time scenarios such as video surveillance, drone inspection, and vehicle assistance.

[0028] In this embodiment, the deep learning neural network model 101 can be a commonly used object detection network, such as the YOLO series, Faster R-CNN, SSD, etc., or other custom models. The model is implemented using mainstream frameworks (such as PyTorch, TensorFlow), and its main operators are supported in TVM, TensorRT, or self-developed runtimes, facilitating the generation of DAGs and the analysis and scheduling of operator-level performance. The heterogeneous DAG modeling and performance analysis module 102 is responsible for converting the inference process of the neural network model 101 into a dependent directed acyclic graph, and collecting the GPU execution time and the execution time of different CPU core configurations for each task node under the target hardware configuration, forming the performance data required for subsequent scheduling. This module can run offline before deployment. The PICO scheduling and acceleration scheme generation module 103, based on the DAG and performance data, performs task priority calculation and opportunity cost evaluation, generating a scheduling scheme and deployment package for "single GPU + shared CPU core pool". This acceleration scheme includes information such as device selection, CPU core allocation, and scheduling order for each task, used to guide terminal execution. Video / image input source 104 provides continuous inference input data to the system, and the source can be a camera, video stream, or offline image set. Edge terminal device 105 is the actual operating environment, and its hardware form is an embedded platform (such as NVIDIA Jetson Orin Nano) containing a GPU and a multi-core CPU core pool, using a unified memory architecture to eliminate the explicit communication overhead of cross-device data copying. When the terminal obtains input data, it runs the code and scheduling information in acceleration scheme 103, which can produce detection results faster than the inference process without scheduling optimization.

[0029] The key features of this invention are: Model 101 is not structurally limited and is applicable to various target detection networks; scheduling optimization focuses on efficient allocation of heterogeneous resources under the UMA architecture. Module 102 analyzes the execution time of operators on GPUs and CPUs with different numbers of cores, and abstracts model inference into a DAG structure. Module 103 uses a price-guided and opportunity-cost-based scheduling method to select devices and allocate cores for ready tasks, forming an acceleration scheme. This method can proactively alleviate resource congestion and critical path blocking in an environment where shared CPU core pools and scarce GPU resources coexist, thereby reducing overall inference latency and improving throughput and latency stability. After the acceleration scheme 103 is deployed to the edge terminal 105, with continuous data supply from the video / image input source 104, the system can significantly improve inference efficiency while maintaining accuracy.

[0030]

Example 2

[0031] See Figure 2 , Figure 2 This is a schematic diagram of the directed acyclic graph reasoning and scheduling method for heterogeneous computing platforms according to an embodiment of the present invention. The entire method mainly includes a preprocessing stage and an iterative scheduling stage.

[0032] First, the deep learning neural network model to be optimized (such as...) Figure 2 The input model 201 is parsed and abstracted into a directed acyclic graph (DAG) G=(V, E), as follows: Figure 2 The computational graph (DAG) in the model is shown in Figure 202. Here, the set of nodes V represents the computational tasks (operators) in the model, and the set of directed edges E represents the dependencies between tasks. Under the Unified Memory Architecture (UMA), the communication overhead for cross-device dependencies is negligible.

[0033] Subsequently, offline analysis was performed on each task to obtain its fixed execution time on the GPU. And the execution time curve when the CPU allocates k∈{1..n} cores. .

[0034] To more intuitively illustrate the performance differences in heterogeneous computing environments and the specificity of the method of this invention, the following explanation is based on specific test data (the test platform is NVIDIA Jetson Orin Nano): First, we analyze the multi-core scalability of CPU resources. For example... Figure 6 As shown, taking a typical convolution operator (Conv) as an example, when the number of allocated CPU cores k increases from 1 to 6, its execution time exhibits a non-linear decreasing trend. Figure 6 This is used to illustrate the multi-core scalability of CPU resources. As can be seen from the figure, the performance gain gradually decreases with increasing core count (for example, the time reduction from 1 core to 2 cores is much greater than from 5 cores to 6 cores). This verifies that task execution time has discrete concavity with respect to the number of cores k. Based on this characteristic, this invention introduces the "CPU scalability sensitivity" metric in subsequent steps and employs a "concave hull inflection point evaluation strategy" to eliminate core configurations with low cost-effectiveness, thereby significantly compressing the search space without sacrificing optimality.

[0035] Secondly, the performance differences of different operators on heterogeneous devices (CPU vs GPU) are analyzed. For example... Figure 7As shown, the normalized execution time comparison of three typical operators—Pool, Conv, and Softmax—on CPU (6 cores) and GPU is presented (GPU time is used as the baseline 1.0). Figure 7 This is used to illustrate the phenomenon of heterogeneous performance differentiation of operators.

[0036] The graph reveals a significant heterogeneous performance divergence. For the pool operator, the CPU execution time is 11.7 times that of the GPU, indicating that this type of operator has a very high speedup benefit on the GPU, making it a task where the GPU has a strong advantage. For the Conv operator, the CPU execution time is approximately 2.4 times that of the GPU, and the GPU still has an advantage, but the gap is narrowing. For the Softmax operator, the CPU execution time is approximately 0.9 times that of the GPU (meaning the CPU is slightly faster than the GPU). This suggests that not all operators are suitable for execution on the GPU. Blindly scheduling such lightweight or memory-intensive operators to the GPU not only fails to provide speedup but may also reduce efficiency due to kernel startup overhead and block other critical tasks.

[0037] This performance difference fully demonstrates the necessity of the "GPU dominance" metric defined in this invention and the opportunity cost-based scheduling mechanism: the system must be able to identify critical tasks such as Pool and prioritize GPU allocation, while flexibly leaving tasks such as Softmax to the CPU for processing, in order to achieve optimal allocation of global resources.

[0038] Based on the above analysis data, the system establishes an accurate performance model, and then proceeds to the priority ranking of heterogeneity sensitivity (203): defining the baseline CPU cost for task i:

[0039] CPU extension sensitivity:

[0040] GPU advantage:

[0041] Overall heterogeneity coefficient:

[0042] in( , (as weights, configurable), and with Calculate the upward ranking value. The rank is represented numerically, with higher values ​​indicating higher priority; all tasks are arranged in descending order of rank to form a static priority list (204). Unlike existing methods that only use average execution time, the above... Explicitly distinguish between tasks that are "sensitive to the number of CPU cores" and those that are "significantly accelerated by GPUs," making the sorting more in line with heterogeneity.

[0043] Entering the iterative scheduling phase, the scheduler processes ready tasks sequentially according to the priority list. When a high-priority task becomes ready, candidate solutions are generated and evaluated (205): the candidate set includes a solution "executed on GPU" and several solutions "executed on CPU and allocated k cores", where "k" in the CPU solution refers to the number of CPU cores allocated. To improve efficiency, not all k are traversed, but a concave hull inflection point evaluation strategy is adopted, retaining only the inflection points. The lower convex hull vertices of k are considered as candidates. The implementation details are: [The sentence is incomplete and requires further context to be translated accurately.] Scan in increments by k, construct the lower convex hull using a monotone chain, and check the three nearest points in sequence. , , The direction of the vector ( )and( If the cross product of ) is ≥ 0, then For "dominated" points (located on or collinear with the lines connecting the two ends), pop them; the final retained vertices correspond to the core configurations not dominated by linear interpolation. This pruning is O(n) when k is sorted, significantly reducing the number of evaluation schemes without affecting optimality.

[0044] For each candidate solution o, a risk-adjusted score (206) is calculated to make a decision based on a uniform score. This is another core innovation of the invention, where the score integrates immediate benefits with future costs: (1) Immediate benefits: mainly reflected in the expected completion time of the plan. The earlier the plan is completed, the better the score.

[0045] (2) Execution efficiency penalty: The running time of the solution itself is also a cost, encouraging the selection of faster solutions to release resources more quickly.

[0046] (3) Future Costs (Opportunity Costs): This is the key to this invention. It draws on economic theory to dynamically price scarce resources, quantifying the potential performance loss that allocating resources to the current task may cause to subsequent tasks. When a solution uses a GPU, its opportunity cost is determined by how many tasks are currently waiting for the GPU (demand load) and whether occupying the GPU will block downstream critical GPU tasks (downstream dependency). If the GPU is in a "traffic jam" state, or the current task will block a long string of subsequent tasks that depend on the GPU, then the opportunity cost of this solution will be very high. When a solution uses a CPU, its opportunity cost is determined by the total amount of CPU resources it consumes (number of cores × time) and whether its execution will exacerbate the overall busyness of the system (global congestion). In an already very busy system, occupying a large number of CPU cores will correspondingly increase the opportunity cost.

[0047] The risk-adjusted score formula is defined as follows:

[0048] in For the estimated completion time ( , The earliest start time of this scheme satisfies the dependency constraint. And target device idle constraints). Pure runtime; and Opportunity cost. GPU opportunity cost: ,in , The GPU has a significant advantage in the ready queue. "task" The sum of As a downstream relevance factor, take the weights of GPU-dependent tasks in the successors of i (e.g., The sum of these weights represents the proportion of GPU-dependent weights across the entire graph. CPU opportunity cost: ,in For the execution interval of scheme o The average value of the internal system demand pressure P(t), where P(t) can be the sum of the ranks of ready tasks at time t; This is the congestion sensitivity coefficient. The above parameters... , , , , , It is configurable and can be tuned using a validation set.

[0049] After calculating the risk-adjusted scores of all candidate solutions, the system selects and executes the optimal solution (207), that is, selects the solution with the lowest score (i.e., the lowest overall risk and cost) to execute the task. This decision-making process avoids the "short-sightedness" defect of traditional greedy algorithms by introducing opportunity cost. For example, it prevents a task that is not sensitive to GPU acceleration from preempting the GPU for a small immediate benefit, thus reserving valuable GPU resources for subsequent critical tasks that need it more.

[0050] After task scheduling is completed, the system updates the resource usage status and the ready task queue. This iterative process continues until all tasks have been scheduled, ultimately generating a final scheduling scheme with better global performance (208). This scheme defines in detail the execution device, the number of CPU cores used, and the start and end times for each task, and can be directly used to guide efficient inference of the model on edge devices.

[0051] To more intuitively verify the advantages of the method described in this invention in solving heterogeneous resource contention and parallel scheduling, Figures 3-5 A simplified comparison of specific scheduling examples is presented. For example... Figure 3 As shown, a directed acyclic graph (DAG) with five nodes is defined, where node a is the starting task, node e is the sink task, and nodes b, c, and d are three parallel intermediate tasks, all dependent on node a. The system hardware environment is assumed to include one GPU and two shared CPU cores. The execution time (in milliseconds) of each task under different resources is set as follows: the execution time of nodes a and e on the GPU is 10ms each; intermediate nodes b, c, and d exhibit significant heterogeneity differences, with node b being hardware-insensitive (CPU single-core 62ms, dual-core 60ms, GPU 58ms), node c exhibiting moderate heterogeneity (CPU single-core 62ms, dual-core 52ms, GPU 46ms), and node d being a typical GPU-friendly task (CPU single-core 88ms, dual-core 44ms, GPU 18ms).

[0052] If the traditional HEFT algorithm is used for scheduling, it first calculates the priority based on the average execution time of the task across all devices. Since node b has the longest average execution time (60ms) and node d has the shortest (50ms), HEFT incorrectly places the highly heterogeneous node d at the end of the priority queue (in the order b>c>d). During the scheduling phase, HEFT uses an Early Finish Time (EFT) greedy strategy, first scheduling the high-priority node b to its fastest GPU. Subsequently, node c, in pursuit of the fastest completion, monopolizes both CPU cores. This leads to... Figure 4 The scheduling sequence shown is as follows: critical GPU resources are occupied for an extended period (58ms) by node b, whose acceleration effect is not significant, forcing node d, which truly needs the GPU, to wait; simultaneously, CPU resources are exclusively occupied by node c, preventing parallel masking. Ultimately, the completion time (Makespan) of the entire inference process reaches 96ms.

[0053] In contrast, the PICO algorithm proposed in this invention can generate, for example... Figure 5 The better solution is shown. First, in the priority sorting stage, the heterogeneity sensitivity index in the algorithm ( The scheduling mechanism plays a crucial role. Node d, with its approximately 4.9x GPU speedup (88ms vs 18ms), significantly amplifies its overall heterogeneity coefficient, thus elevating its scheduling priority to the top (ordering d>c>b). During the decision-making phase, the scheduler first allocates node d to the GPU, enabling it to complete quickly within 18ms. Subsequently, when processing nodes c and b, the opportunity cost mechanism of this invention avoids resource waste: when evaluating candidate solutions for node c, although allocating two CPU cores reduces its execution time from 62ms to 52ms, the CPU opportunity cost calculated by the algorithm will issue a warning—because the high-priority node b is still waiting, and exclusively using two cores will significantly increase the system's global congestion factor. This leads to a higher risk adjustment score for the dual-core solution. Therefore, the scheduler "intelligently" chooses to let node c use only one CPU core, thus freeing up the other core for node b to execute in parallel. This opportunity cost-based decision achieves load balancing between CPU and GPU and task parallelism between CPU cores, ultimately reducing the overall completion time significantly to 82ms, achieving a performance improvement of approximately 14.6%, which fully demonstrates the global optimization capability of this invention in handling heterogeneous DAG scheduling.

[0054] The above description is merely a preferred embodiment of the present invention, but the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. Any simple modifications, equivalent changes, and alterations made by those skilled in the art to the above embodiments based on the technical essence of the present invention without departing from the principles and spirit of the present invention should be included within the protection scope of the present invention.

Claims

1. A directed acyclic graph reasoning scheduling method for heterogeneous computing platforms, wherein the heterogeneous computing platform includes at least one graphics processing unit (GPU) and a shared multi-core central processing unit (CPU) resource pool, characterized in that, The method includes the following steps: S1, Determining task priority: For each computation task in the directed acyclic graph (DAG), based on the execution performance data of the task node on the GPU and on different numbers of CPU cores, calculate the priority parameter of the task's sensitivity to heterogeneous resources, and determine the priority of the task according to the priority parameter. S2, Opportunity Cost Modeling: Establish opportunity cost models for GPU resources and CPU resources respectively. The opportunity cost models are used to quantify the potential performance loss that may be caused to subsequent tasks by allocating resources to the current task. S3, Proactive Scheduling Decision: Generating scheduling decisions based on task priority and opportunity cost; S4, Task Execution: According to the determined execution plan, schedule and execute the computing tasks in the directed acyclic graph on the heterogeneous computing platform.

2. The directed acyclic graph reasoning scheduling method for heterogeneous computing platforms according to claim 1, characterized in that, In step S1, calculating the priority parameters that reflect the task's sensitivity to heterogeneous resources includes: The performance changes of computational tasks under different numbers of CPU cores are analyzed, and the CPU scaling sensitivity of the tasks is quantified. The CPU scaling sensitivity is used to characterize the degree to which the task execution time decreases as the number of CPU cores increases. The performance gain of computational tasks on GPUs is analyzed, and the GPU dominance of tasks is quantified. The GPU dominance is used to characterize the execution speedup of tasks on GPUs relative to CPUs. Based on the CPU extension sensitivity and the GPU dominance, the comprehensive heterogeneity coefficient of the task is calculated, and the comprehensive heterogeneity coefficient is incorporated into the upward sorting algorithm to calculate the final priority of the task.

3. The directed acyclic graph reasoning scheduling method for heterogeneous computing platforms according to claim 1, characterized in that, The opportunity cost model in step S2 includes: for GPU resources, establishing an opportunity cost model for GPU resources based on future task requirements and dependencies; for CPU resources, establishing an opportunity cost model for CPU resources based on CPU core occupancy and system task congestion.

4. The directed acyclic graph reasoning scheduling method for heterogeneous computing platforms according to claim 1, characterized in that, The scheduling decision in step S3 specifically includes: generating a candidate set including GPU schemes and multiple CPU parallel schemes for each ready task to be scheduled; calculating the risk adjustment score of each candidate scheme based on the opportunity cost model and the expected completion time of the task; and selecting the scheme with the best score as the final scheduling decision.

5. The directed acyclic graph reasoning scheduling method for heterogeneous computing platforms according to claim 4, characterized in that, The generated candidate set is then filtered using a concave hull inflection point evaluation strategy, which includes: Obtain execution time data points for tasks with different numbers of CPU cores; Construct the lower convex hull of the data points with respect to the core count minus execution time; Only the core number configuration corresponding to the vertex of the lower convex hull is selected as a candidate scheme.

6. The directed acyclic graph reasoning scheduling method for heterogeneous computing platforms according to claim 4, characterized in that, The risk-adjusted score is calculated using the following formula: ， Where score(o) is the risk-adjusted score of candidate solution o. Given the estimated completion time of task i using scheme o, The execution time of scheme o and The opportunity costs of using GPU and CPU for scheme o are respectively. , , These are configurable weighting coefficients.

7. A directed acyclic graph reasoning scheduling system for heterogeneous computing platforms, characterized in that, include: The priority determination module is used to perform heterogeneity sensitivity analysis on computational tasks in acyclic graphs and determine the priority of the tasks. The opportunity cost modeling module is used to build opportunity cost models for heterogeneous computing resources; The scheduling decision module is used to generate scheduling decisions based on task priority and opportunity cost; The scheduling execution engine is used to drive the execution of tasks on the heterogeneous computing platform according to the execution plan output by the scheduling decision module.

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