Chip aging test parameter optimization and failure early warning method, system and equipment

Abstract

The invention relates to the technical field of chip aging test, in particular to a chip aging test parameter optimization and failure early warning method, system and equipment, and the method comprises the steps: obtaining multi-dimensional process data of a chip in a historical aging test process and a corresponding final electrical test result; constructing a feature primitive vector for each historical test based on the multi-dimensional process data; forming a rule knowledge base based on the feature primitive vector and the final electrical test result; generating an optimized test parameter combination for the new test task based on the rule knowledge base; in the current chip aging test process, calculating a real-time feature primitive vector based on multi-dimensional process data obtained in real time so as to calculate a real-time risk score; according to the method, the test equipment has self-optimization, self-early-warning and self-evolution capabilities, and the test efficiency and economic benefits are improved while the screening reliability is guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip aging test, in particular to a chip aging test parameter optimization and failure early warning method and system. BACKGROUND

[0002] High-reliability chips must pass strict aging tests before mass production to screen out early failure products. The current industry technology evolution mainly reflects two aspects: one is to improve the physical reliability of the test environment, such as resisting long-term cyclic stress through enhanced mechanical structure design, or ensuring that the chip is in the set thermal stress environment through accurate temperature control algorithm; the other is to improve the monitoring ability of the test process itself, such as online evaluation of the health status of the test socket, modeling and prediction of the coupling relationship between the heat dissipation airflow and the chip temperature field.

[0003] These technologies change the chip aging test from a black box operation to an observable, controllable transparent process, ensuring the consistency of the test conditions. However, while making this progress, a new technical depth problem has emerged: after obtaining a large amount of accurate, multi-dimensional test process physical quantity data, how to deeply correlate these data with the final test pass or fail result of the chip, and then extract knowledge from these correlations that can guide the test practice and improve the test efficiency. Currently, test engineers set aging conditions (such as temperature, voltage, time) mainly rely on product specifications and historical experience, and the rich physical state information (such as the actual thermal history of the chip, the mechanical stress fluctuation applied by the socket) in the test process has not been systematically used to evaluate the adaptability of the test conditions to the current batch of chips, nor can it provide early warning signals based on process data anomalies for individuals that may fail during the test, which makes the information reflecting the reliability of the chip contained in the test process not fully extracted and utilized. SUMMARY

[0004] The main purpose of the present application is to provide a chip aging test parameter optimization and failure early warning method and system, aiming to establish a causal mining and quantitative evaluation mechanism from the multi-dimensional physical quantity data of the test process to the chip failure result. This method does not aim to replace or repeat the existing environmental control technology, but as a data value mining layer on top of it, the core solves two problems: first, based on historical data, how to identify the key process parameter combination and its threshold that leads to a specific failure mode, and dynamically generate a personalized aging test scheme with more controllable risk and higher efficiency for new test tasks; second, how to compare the deviation of the current process parameters from the historical "healthy" mode in real time during the test execution process, to provide early failure risk warning for the tested chip, and realize the active optimization configuration of test resources, to solve the technical problems raised in the background technology.

[0005] The application provides a chip aging test parameter optimization and failure early warning method, comprising: Obtaining multi-dimensional process data and corresponding final electrical test results of a chip in a historical aging test process, wherein the multi-dimensional process data comprises thermal stress data, electrical stress data and test socket mechanical state data; Based on the multi-dimensional process data, a feature primitive vector is constructed for each historical test, and the feature primitive vector is composed of a plurality of derived features representing clear physical meanings; Based on the feature primitive vector and the final electrical test results, a gradient boosting decision tree model is fitted, and an interpretable decision rule in the form of IF-THEN is extracted therefrom to form a rule knowledge base; According to the rule knowledge base, the decision rule is inversely analyzed into a constraint condition for the test process features, and the constraint condition is used as a boundary to optimize the search of controllable test parameters, thereby generating an optimized test parameter combination for a new test task; In the current chip aging test process, a real-time feature primitive vector is calculated based on the real-time multi-dimensional process data, the real-time feature primitive vector is matched with the rule knowledge base, and a real-time risk score is calculated according to the matching result; According to the real-time risk score, a hierarchical early warning is performed.

[0006] Preferably, the step of constructing a feature primitive vector for each historical test based on the multi-dimensional process data comprises: The thermal stress data, the electrical stress data and the mechanical state data are synchronized and aligned according to the time stamp, and a data window is divided based on a complete aging test cycle as a basic unit; For the divided thermal stress data, the cumulative time when the temperature change rate of the chip exceeds a preset threshold in the temperature change stage is calculated as a first derived feature, which is recorded as a thermal shock accumulation amount; For the divided electrical stress data, the time constant required for the autocorrelation function of the chip power consumption time series data under the target test vector to decay to a first preset value is calculated as a second derived feature, which is recorded as a power consumption change inertia; For the divided mechanical state data, the absolute value of the linear regression slope of the health state index of the test socket within a complete test period of the current chip is calculated as a third derived feature, which is recorded as a health state decay rate; The thermal shock accumulation amount, the power consumption change inertia and the health state decay rate are combined with the statistical features extracted from the original data to form the feature primitive vector.

[0007] Preferably, the step of fitting a gradient boosting decision tree model based on the feature basis vectors and the final electrical test results, and extracting interpretable decision rules in the form of IF-THEN from the model to form a rule knowledge base comprises: training a gradient boosting decision tree ensemble model with the feature basis vectors as input features and binary labels representing whether a chip is failed as output targets; analyzing the structure of each decision tree in the gradient boosting decision tree ensemble model, traversing the path from the root node to each leaf node, and converting each path into an original rule composed of multiple feature threshold judgment clauses connected by logical AND relationships; filtering the original rules based on preset lower limits of coverage and confidence, wherein the coverage refers to the proportion of the number of historical samples applicable to the rule to the total number of samples, and the confidence refers to the proportion of samples actually experiencing the corresponding failure among the samples applicable to the rule; merging and simplifying the filtered original rules to obtain multiple decision rules in the form of IF-THEN, wherein the THEN part of each decision rule represents the associated failure class and risk level; composing the rule knowledge base from all the decision rules.

[0008] Preferably, the step of inversely analyzing the decision rules from the rule knowledge base into constraints on test process features, and optimizing controllable test parameters within the constraints to generate an optimized test parameter combination for a new test task comprises: filtering all decision rules associated with the failure class of the target in the THEN part from the rule knowledge base; converting each feature threshold judgment clause contained in the IF part of each filtered decision rule into a constraint inequality about the value range of the corresponding process feature; defining a constrained optimization problem with the minimum test total duration or total energy consumption as the optimization objective function, the hardware capability limit of the test equipment as the first constraint set, and all the constraint inequalities as the second constraint set; solving the constrained optimization problem iteratively using a Bayesian optimization algorithm within the feasible region of the controllable test parameters, wherein the controllable test parameters at least include the duration of each temperature stage, the temperature change rate between adjacent stages, and the test voltage applied to the chip; outputting a set of specific values of the controllable test parameters that minimize the value of the optimization objective function and satisfy the first constraint set and the second constraint set as the optimized test parameter combination.

[0009] Preferably, the step of calculating a real-time feature primitive vector based on the real-time multi-dimensional process data obtained in the current chip aging test process, matching the real-time feature primitive vector with the rule knowledge base, and calculating a real-time risk score according to the matching result comprises: intercepting the latest data of the current test process at a preset time interval and obtaining the real-time feature primitive vector; comparing each feature value in the real-time feature primitive vector with a feature threshold judgment clause contained in the IF part of each decision rule in the rule knowledge base in turn; if the comparison results of all feature threshold judgment clauses of a decision rule are true, it is determined that the decision rule is triggered by the current state; assigning a basic risk value to each triggered decision rule, and calculating the real-time risk score according to the basic risk values of all triggered decision rules in combination with the respective confidence degrees of the decision rules in the rule knowledge base.

[0010] Preferably, the step of intercepting the latest data of the current test process at a preset time interval and obtaining the real-time feature primitive vector comprises: setting a plurality of time windows of different lengths, including a short window reflecting recent short-term changes, a medium window reflecting medium-term trends, and a long window from the start of the test to the present; simultaneously intercepting multi-dimensional process data of three data windows with the current time as the end point and the lengths of the short window, the medium window and the long window respectively for the current time; calculating a set of basic process features for each data window, including statistics of temperature, power consumption and health index, to form three window feature subsets; calculating change rate features between different window feature subsets, including a recent change rate of the short window features relative to the medium window features, and a cumulative change rate of the medium window features relative to the long window features.

[0011] Preferably, the step of performing hierarchical early warning according to the real-time risk score comprises: setting at least two increasing risk score thresholds; when the real-time risk score exceeds a lower risk score threshold, marking the current chip with a state and recording abnormal data; when the abnormal state of the real-time risk score meets a preset time duration condition or exceeds a higher risk score threshold, triggering a first-level early warning action and starting additional verification testing of the current chip; When the real-time risk score meets preset deterioration conditions after triggering the first-level early warning action, or the additional verification test fails, a second-level early warning action is triggered, and subsequent aging tests on the current chip are stopped and offline analysis is arranged.

[0012] The application further provides that the method further comprises an updating step of the rule knowledge base: new test sample data is added to the historical data set to update the historical data set; Based on the updated historical data set, periodically re-execute the rule extraction process to obtain an updated decision rule set; merge the updated decision rule set with the rule knowledge base, and arbitrate the conflict rules generated during the merging according to predetermined rules to update the rule knowledge base.

[0013] The application further provides a chip aging test parameter optimization and failure early warning system, comprising: a data acquisition module for acquiring multi-dimensional process data and corresponding final electrical test results of chips during historical aging tests, wherein the multi-dimensional process data includes thermal stress data, electrical stress data and test socket mechanical state data; a feature construction module for constructing a feature primitive vector for each historical test based on the multi-dimensional process data, the feature primitive vector being composed of a plurality of derived features representing explicit physical meanings; a rule extraction module for fitting through a gradient boosting decision tree model based on the feature primitive vector and the final electrical test results, and extracting interpretable decision rules in the form of IF-THEN from the model to form a rule knowledge base; a parameter optimization module for inversely analyzing the decision rules into constraint conditions for test process features according to the rule knowledge base, and performing optimization search on controllable test parameters with the constraint conditions as boundaries to generate an optimized test parameter combination for a new test task; a risk score module for calculating a real-time feature primitive vector based on real-time multi-dimensional process data acquired during current chip aging tests, matching the real-time feature primitive vector with the rule knowledge base, and calculating a real-time risk score according to the matching result; a hierarchical early warning module for performing hierarchical early warning according to the real-time risk score.

[0014] The application further provides a chip aging test device, comprising a test machine, an environmental test box, a plurality of process sensors, and a chip aging test parameter optimization and failure early warning system, wherein the system is communicatively connected to the test machine, the environmental test box and the process sensors, for receiving data generated thereby, and outputting the optimized test parameter combination and early warning signals.

[0015] The beneficial effects of this invention are as follows: This invention maps thermal, electrical, and mechanical stress data into feature primitive vectors with failure physical meaning, and transforms the black box model into IF-THEN logical rules that engineers can understand through interpretable rule extraction technology. This breaks down the cognitive barriers between process monitoring and failure analysis. At the optimization level, the rules are reverse-analyzed into test process constraints, and personalized parameter combinations that minimize test duration or energy consumption are dynamically generated based on meeting the constraints. This enables aging conditions to be decided based on data, and gives the test equipment the ability to self-optimize, self-warn, and self-evolve. This improves test efficiency and economic benefits while ensuring screening reliability. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a method flow according to an embodiment of this application.

[0017] Figure 2 This is a schematic diagram of the system structure according to an embodiment of this application.

[0018] Figure 3 The images show a front view, a side view, and a rear view of a support plate that is an integral structure in one embodiment of this application.

[0019] Figure 4 These are front, side, and rear views of an embodiment of the integrated support plate and gasket structure of this application.

[0020] Figure 5 The images show a front view, side view, rear view, top view, and split view of the support plate as a strip-shaped composite structure in one embodiment of this application.

[0021] Figure 6 The images show a front view, side view, rear view, top view, and split view of the support plate as a three-segment composite structure in one embodiment of this application.

[0022] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0024] like Figure 1 As shown, this application provides a method for optimizing chip aging test parameters and providing early warning of failure, including: S1, acquire multi-dimensional process data of the chip during the historical aging test and the corresponding final electrical test results, wherein the multi-dimensional process data includes thermal stress data, electrical stress data and test socket mechanical state data; S2, constructing a feature primitive vector for each historical test based on the multidimensional process data, the feature primitive vector being composed of a plurality of derived features representing explicit physical meanings; S3, based on the feature primitive vector and the final electrical test result, fitting through a gradient boosting decision tree model, and extracting interpretable decision rules in the form of IF-THEN from it to form a rule knowledge base; S4, according to the rule knowledge base, reverse analyzing the decision rules into constraint conditions for test process features, and performing an optimized search on controllable test parameters with the constraint conditions as boundaries to generate an optimized test parameter combination for a new test task; S5, in the current chip burn-in test process, calculating a real-time feature primitive vector based on real-time acquired multidimensional process data, matching the real-time feature primitive vector with the rule knowledge base, and calculating a real-time risk score according to the matching result; S6, performing a hierarchical early warning according to the real-time risk score.

[0025] As described in steps S1-S6 above, the present application learns from historical data to establish an interpretable association rule (knowledge mining) between "process features" and "failure results"; then, the safe test parameter boundaries are deduced reversely using these rules, and an optimized search is automatically performed within the boundaries to generate an efficient new test scheme (forward optimization); finally, in real-time testing, the tested chip is dynamically risk assessed and hierarchically intervened (reverse early warning) by comparing the current multidimensional process data with the historical rules. In this way, the present application not only guarantees the physical reliability of the test environment (depending on existing mature technologies), but further realizes the intellectualization of the test logic itself, so that the test conditions can better adapt to the risk characteristics of different chips, and the test process can identify potential failures in advance, realizing intelligent chip burn-in testing based on data-driven and real-time decision-making.

[0026] In an embodiment of the present application, the step of constructing a feature primitive vector for each historical test based on the multidimensional process data comprises: S21, synchronously aligning the thermal stress data, the electrical stress data and the mechanical state data according to time stamps, and dividing data windows in a complete burn-in test cycle as a basic unit; Exemplarily, the synchronization alignment by time stamp is based on a system clock of a test machine as a reference clock, all acquisition devices are time-synchronized with the reference clock, and the synchronization accuracy is controlled within ±1 ms; for data sources with different sampling frequencies, linear interpolation is used for resampling to unify the same time sequence; for abnormal data occurring in the acquisition process, 3σ criterion is used for identification, if a data point deviates from the average value of the dimension data by more than 3 times the standard deviation, it is determined as abnormal data; for occasional single abnormal data point, the average value of the adjacent data before and after is used for completion, for more than 5 continuous abnormal data segments, it is determined that the data in this period is invalid, the data segment is rejected and marked as invalid sample, and does not participate in subsequent feature calculation; S22, for the divided thermal stress data, the cumulative time of the temperature change rate of the chip exceeding the preset threshold in the temperature change stage is calculated as a first derived feature, and is recorded as thermal shock accumulation; S23, for the divided electrical stress data, the time constant required for the autocorrelation function of the chip power consumption time series data under the target test vector to decay to a first preset value is calculated as a second derived feature, and is recorded as power consumption change inertia; S24, for the divided mechanical state data, the absolute value of the linear regression slope of the health status index of the test socket changing with time in the complete test cycle of the current chip is calculated as a third derived feature, and is recorded as health status decay rate; S25, the thermal shock accumulation, the power consumption change inertia, and the health status decay rate are combined with the statistical features extracted from the original data to form the feature primitive vector.

[0027] As described in steps S21-S25 above, in the feature primitive vector construction step of the embodiment of the present application, the core is to systematically transform the original, high-dimensional sensor time series data into a series of quantitative indicators with clear physical or engineering significance, i.e. feature primitives, for subsequent correlation analysis and prediction of reliability. Those skilled in the art understand that this process is a data feature engineering for specific stress modes and failure mechanisms in chip aging test.

[0028] First, the data streams from different subsystems (tester, temperature chamber, health monitoring unit) need to be aligned in time domain. In one embodiment, the hard sync signal or soft command from the tester that marks the boundary of a test cycle is used as the reference time point, and linear interpolation or nearest neighbor resampling technique is applied to all other sensor data to unify them into a common time series. Then, each complete aging test cycle (e.g. one complete temperature shock cycle, or a fixed period of high / low temperature hold) is used as the basic analysis window, and the continuous data stream is divided into individual and comparable data segments, ensuring that each data segment contains the complete load history experienced by the chip in that time period.

[0029] To quantify the thermal mechanical stress caused by rapid temperature change, the cumulative effect of the severe temperature shock experienced by the chip in the non-steady state temperature change phase needs to be calculated. In one embodiment, the process is as follows: 1. Smooth and differentiate the temperature time series data of the chip to obtain its temperature rate of change sequence.

[0030] 2. Set a threshold value that represents "severe change", which can be set according to the characteristics of the chip packaging material or experience, for example 5°C / min.

[0031] 3. Identify all time points where the absolute value of the temperature rate of change exceeds the threshold value.

[0032] 4. Calculate the total length of the time interval corresponding to these time points, i.e. obtain the thermal shock cumulative amount. This feature directly reflects the cumulative time of severe thermal cycles that may cause thermal fatigue failure.

[0033] To characterize the dynamic behavior pattern of the chip's power consumption, especially the severity of its sudden changes, the autocorrelation characteristics of the power consumption sequence need to be analyzed. In one embodiment, the process is as follows: 1. Select a specific, stable test vector running period to obtain the power consumption time series data of the chip in that period.

[0034] 2. Calculate the autocorrelation function of the power consumption sequence.

[0035] 3. Fit the autocorrelation function using a single exponential decay model.

[0036] 4. Extract the decay time constant from the fitted model as the power consumption change inertia. The smaller the time constant, the faster the power consumption fluctuation and the stronger the suddenness; the larger the time constant, the more gradual the power consumption change. This definition captures the instantaneous thermal shock risk caused by dynamic current.

[0037] To perceive the progressive degradation trend of the mechanical contact of the test socket in advance, the rate of change of its health status indicators needs to be focused on rather than the instantaneous value. In one embodiment, the process is as follows: 1. Obtain the health index sequence sampled at fixed intervals (e.g. after each loading and unloading) throughout the current test task cycle.

[0038] 2. Perform linear regression analysis on the health index sequence.

[0039] 3. Take the absolute value of the slope of the linear regression model as the health state decay rate. The value is positive, indicating that the health degree is declining; the numerical size directly reflects the speed of performance degradation. Compared with monitoring whether the health index is lower than a certain fixed threshold, this method can provide early warning of potential contact reliability decay.

[0040] Finally, the thermal shock cumulative amount, power consumption change inertia, and health state decay rate calculated above are combined with the basic statistical features (e.g. average temperature during the high-temperature holding stage, maximum value and standard deviation of power consumption, minimum value of health index, etc.) directly extracted from the original data to form a fixed-dimensional numerical vector, i.e. a feature primitive vector. Each test of each chip corresponds to such a vector, which is a condensed and digitized quick record of the composite environmental stress experienced by the chip and its own response state during the test.

[0041] Although the existing method can collect rich multi-dimensional process data, it is difficult to use these data to evaluate the pros and cons of the test strategy or realize early failure warning. The scheme provided by the embodiments of the present part provides a key data preprocessing and information extraction method to solve this problem.

[0042] Specifically, by calculating the thermal shock cumulative amount, the nonlinear temperature history can be converted into a quantitative index of stress directly related to thermal fatigue failure, so that the analysis goes beyond simply whether the temperature is high or not, and enters the level of whether the thermal shock is strong or not. By calculating the power consumption change inertia, the limitation of only focusing on the average power consumption is avoided, and a more destructive dynamic current shock mode can be captured. By calculating the health state decay rate, the monitoring of mechanical connection reliability is upgraded from static good or bad judgment to dynamic deterioration speed prediction, and the early warning window is greatly moved forward. Therefore, the feature primitive vector constructed in this part is a high-value information carrier closely related to chip reliability distilled from the original data. It converts chaotic low-level data into high-level, interpretable engineering features, lays a solid and effective data foundation for subsequent steps (such as association rule mining and risk prediction), and is a bridge connecting process phenomena and failure mechanisms.

[0043] In an embodiment of the present application, the step of fitting the feature primitive vector and the final electrical test result through a gradient boosting decision tree model and extracting interpretable decision rules in the form of IF-THEN to form a rule knowledge base comprises: S31, training a gradient boosting decision tree ensemble model by taking the feature base vector as input features and a binary label representing whether the chip is failed as output target; For example, the hyperparameters of the gradient boosting decision tree ensemble model are set as follows: the number of decision trees is 100-500, the maximum depth of a single decision tree is 5-10 layers, the learning rate is 0.01-0.1, the minimum number of leaf nodes is 10-50, and the feature sampling ratio is 0.7-0.9. To address the data imbalance problem caused by the low proportion of failed samples in chip aging tests, the SMOTE algorithm is used to oversample the failed samples, and the normal samples are randomly undersampled, so that the proportion of failed samples and normal samples in the training data set reaches 1:1-1:2. The weighted cross-entropy loss function is used as the loss function for model training, and a higher weight coefficient (5-20) is assigned to the failed samples to improve the model's ability to identify failed samples. After the model training is completed, five-fold cross-validation is used for model evaluation, and accuracy, precision, recall, and F1 value are used as evaluation indicators to ensure that the model recall rate is not less than 85%, meeting the actual needs of failure warning; S32, analyzing the structure of each decision tree in the gradient boosting decision tree ensemble model, traversing the path from the root node to each leaf node, and converting each path into an original rule composed of multiple feature threshold judgment clauses connected by logical AND relationships; S33, filtering the original rules based on preset lower limits of coverage and confidence, wherein the coverage refers to the proportion of the number of historical samples applicable to the rule to the total number of samples, and the confidence refers to the proportion of samples that actually occur corresponding failures among the samples applicable to the rule; S34, merging the original rules filtered to eliminate redundancy and simplify their logical expressions, obtaining multiple decision rules in the form of IF-THEN, and the THEN part of each decision rule representing the associated failure category and risk level; S35, constructing the rule knowledge base from all the decision rules.

[0044] As described in steps S31-S35 above, the present application can convert the complex and nonlinear mapping relationship between the feature base vector constructed in the early stage and the final test results of the chip into a set of interpretable logical rules that can be directly understood, verified, and applied by engineers, i.e., forming a rule knowledge base. The rule knowledge base is a key medium connecting data intelligence and engineering decision-making. Those skilled in the art understand that the construction process needs to balance the predictive ability of the model and the interpretability of the rules.

[0045] To achieve accurate prediction of chip failure risk, a powerful classification model needs to be established first. In a preferred embodiment, gradient boosting decision tree algorithm is chosen to accomplish this task. Specifically, the feature vector corresponding to each chip in the historical data set is taken as the input feature of the model, and the final electrical test result of the chip is converted into a binary label: for example, if the chip is judged to be qualified (good product), the label is marked as 0; if it is judged to be failed and confirmed by failure analysis (FA) to belong to a specific failure mode (such as electromigration), the label is marked as 1, of course, independent models can also be trained for different types of failure or multi-label strategy can be used. Then the prepared feature-label pair data is used to train the gradient boosting decision tree model. The model is built by iteratively constructing a series of decision trees, each new tree is committed to correcting the residual error of the previous tree prediction, so as to combine into a powerful integrated model. The trained model can output a prediction value representing the probability of the chip belonging to the failure category for any input feature vector, which ensures that the pattern learned from the data has a high enough prediction accuracy.

[0046] Although the gradient boosting decision tree model has strong prediction ability, its internal structure (composed of numerous decision trees) is like a black box to the user. The key innovation of the present application is to translate this black box model into human-readable rules. The specific operation is to traverse each decision tree in the trained gradient boosting decision tree set. For a decision tree, starting from the root node, traverse down each path leading to different leaf nodes. Each internal node on the path represents a judgment on a certain feature (for example: "thermal shock cumulative amount ≤ 120 seconds?"). Connecting the judgment conditions of all nodes on a path with logical "and" forms the IF part of an original rule. The prediction value or category represented by the leaf node where the path eventually arrives can be regarded as the embryonic form of the THEN part of the original rule. Through this method, thousands of such original rules can be extracted from the entire model.

[0047] Since the number of original rules directly extracted from the model is large, and many of them are overfitting (only applicable to a small number of specific samples) or invalid (with weak prediction ability), the present application strictly filters them and introduces two key indicators to evaluate each original rule: 1. Coverage: calculate the number of samples in the historical data set that can "activate" or match the premise condition (IF part) of the rule, and the proportion of the total number of samples. The principle is that a rule with low coverage usually lacks universality. 2. Confidence: calculate the proportion of samples whose actual label (such as failure) is consistent with the conclusion of the rule (THEN part) among those matched by the rule. The principle is that a rule with low confidence is less accurate and less reliable.

[0048] Then set the coverage lower limit and confidence lower limit for the screening process (for example, coverage > 1%, confidence > 80%), only the original rule that meets both thresholds at the same time is retained, this step filters out noise and specific rules, and retains candidate rules with statistical significance and engineering significance. Since there may be multiple rules with similar premises but the same conclusion in the rule set obtained by screening, which may cause redundancy, it is necessary to merge and simplify the rules, for example, several rules with highly overlapping premise conditions are merged into one more general rule, and after simplification, each rule is in the form of "IF-THEN", the IF part is composed of several judgment clauses for specific features and their thresholds (for example: IF `thermal shock cumulative amount > 120` AND `health state decay rate > 0.05 / hour`), and the THEN part clearly points out the failure category (such as "electromigration risk") and a qualitative or quantitative risk level (such as "high risk") associated with the condition combination. Collect, store and manage all final decision rules that have been screened, merged and simplified, that is, form the rule knowledge base which is the core of the application.

[0049] Although the traditional black box prediction model (such as deep neural network) may have high prediction accuracy, its decision-making process lacks transparency, and engineers cannot understand the "reason" of its early warning or diagnosis, so it is difficult to trust and use it to guide actual test parameter optimization or develop maintenance strategies. This part of the scheme of the application solves this explainability problem. By adopting the strategy of "first training a high-precision GBDT model, and then extracting rules from its structure", this scheme first ensures that the knowledge mined has a solid, data-driven prediction ability foundation. More importantly, by "translating" the complex tree model structure into "IF-THEN" rules, we convert the data patterns discovered by machine learning models into logical statements that conform to the habits of human engineering thinking. This allows engineers to immediately check which specific rule (or rules) triggered when the system issues a high-risk warning for a chip, and see which feature (such as `thermal shock cumulative amount`) exceeds which threshold, providing transparent basis for decision-making, and making the extracted rules themselves a quantitative summary of the engineering knowledge of "what process condition combination is prone to cause what failure". These rules can exist independently from the original model, be reviewed by engineers, and be used as experience knowledge to be deposited into the enterprise's knowledge management system, and these explicit rules can also be directly converted into constraints on test process parameters, providing a basis for optimizing test schemes.

[0050] In one embodiment of the present application, the step of inversely parsing the decision rules into constraints on the test process characteristics according to the rule knowledge base, and performing an optimization search on the controllable test parameters within the constraints to generate an optimized test parameter combination for a new test task comprises: S41, filtering out all decision rules of the failure class of the THEN part associated target from the rule knowledge base; S42, converting each feature threshold judgment clause contained in the IF part of each filtered decision rule into a constraint inequality on the value range of the corresponding process characteristic; S43, defining a constrained optimization problem with the minimization of the total test duration or total energy consumption as the optimization objective function, the hardware capability limit of the test equipment as the first constraint set, and all the constraint inequalities as the second constraint set; S44, iteratively solving the constrained optimization problem by using a Bayesian optimization algorithm within the feasible region of the controllable test parameters, wherein the controllable test parameters at least include the duration of each temperature stage, the temperature change rate between adjacent stages, and the test voltage applied to the chip; For example, the Bayesian optimization algorithm uses a Gaussian process as a surrogate model, a radial basis function (RBF) as a kernel function, and an expected improvement (EI) function as a collection function to balance the exploration ability and utilization ability of the algorithm; the maximum number of iterations for iterative solving is 50-200 times, and the convergence accuracy is 1e-3, that is, when the change amount of the objective function value of 10 consecutive iterations is less than 1e-3, the algorithm is determined to be converged, and the iteration is stopped; the feasible region of the controllable test parameters is determined by the hardware capability limit of the test equipment, wherein the feasible region of the duration of each temperature stage is 10-3600s, the feasible region of the temperature change rate is 0.5-5℃ / min, and the feasible region of the test voltage applied to the chip is 0.8-1.2 times of the rated working voltage of the chip; in the Bayesian optimization process, the process characteristic value corresponding to each parameter combination is calculated by using the built-in process characteristic prediction model to verify whether the constraint inequalities of the second constraint set are satisfied, and if not, the parameter combination is directly discarded and the iterative search is continued; S45, outputting a set of specific values of the controllable test parameters that minimize the value of the optimization objective function and satisfy the first constraint set and the second constraint set as the optimized test parameter combination.

[0051] As described in the above steps S41-S45, the present application can apply the rule knowledge base obtained by mining the internal correlation between the process characteristics and the failure modes to guide the parameter design of a new test task, which aims to generate an optimized test parameter combination to improve the test efficiency or reduce the energy consumption while avoiding triggering high failure risk process modes.

[0052] Specifically, first, all decision rules whose THEN part is associated with one or more target failure categories that the current test task focuses on are filtered out from the established rule knowledge base. For example, if the current test aims to focus on screening hot carrier injection and electromigration failures, all rules whose THEN part contains "associated failure mode = hot carrier injection" or "associated failure mode = electromigration" are filtered out.

[0053] Next, the system automatically converts the multiple feature threshold judgment clauses contained in the IF part of each filtered decision rule into value range constraints on the corresponding derived features in the test process. One judgment clause "feature A > threshold a" is converted into the inequality constraint "feature A < threshold a" (aiming to avoid triggering high-risk conditions); while "feature B < threshold b" is converted into "feature B > threshold b". Through this reverse conversion, the "risk triggering conditions" originally used for early warning are systematically converted into "safe boundary conditions" that must be adhered to when designing test schemes. All the inequalities obtained through conversion collectively constitute the second constraint set, which represents the process safety operating window derived from historical failure data.

[0054] After the safe boundary is defined, the system searches for the optimal test parameters within the boundary. To this end, a constrained optimization problem model is constructed, including: 1. Decision variables: The decision variables of the optimization problem are the controllable test parameters, which at least include the duration of each temperature stage (such as low temperature holding, temperature rising, high temperature holding, and temperature falling) in a complete aging test Profile, the temperature change rate between adjacent stages, and the test voltage applied to the chip. These parameters collectively define the strength and course of the test.

[0055] 2. Objective function: According to the test management goal, the optimization objective function is set to minimize the total duration or total energy consumption. The total duration is the direct sum of the durations of each stage; the total energy consumption can be estimated by integrating the system power model over time.

[0056] 3. Constraint conditions: The optimization problem contains two types of hard constraints: The first constraint set: derived from the physical limits of the test equipment, such as the maximum power limit of the heating / cooling system, the maximum safe temperature rising / falling rate, the voltage / current output range of the power module, etc. This constraint set ensures that the generated scheme is physically realizable.

[0057] The second constraint set: the "safe boundary condition". The key here is that each process feature (such as "thermal shock accumulation" and "power consumption change inertia") is a complex function of the decision variables. The system has built-in process feature prediction models that can predict the corresponding process feature values based on given test parameters.

[0058] Since the objective function and the constraint functions are computationally expensive black-box functions (need to be evaluated by thermal simulation or querying pre-computed data table) with respect to the decision variables, traditional gradient-based optimization methods are not applicable, therefore, the present application preferably employs a Bayesian optimization algorithm for solving. The Bayesian optimization framework maintains a surrogate model (e.g. Gaussian process) to approximate the response surface of the objective function and the constraint functions. At each iteration, according to the current surrogate model and a sampling function that balances the trade-off between “exploration” and “exploitation”, the algorithm suggests a most promising new parameter point, and calls the simulation model or data table to compute the actual objective function value and each constraint function value at the parameter point, and updates the surrogate model with the new observation data to make its estimation of the function shape more accurate. Through multiple iterations, the Bayesian optimization can efficiently guide the search direction, and gradually approach the global optimal or near-optimal solution that satisfies all constraints and minimizes the objective function.

[0059] Finally, the optimal values of the decision variables obtained by solving are output as a specific, executable combination of optimized test parameters. The combination can be directly imported into the control system of the aging test machine, to guide the testing of a new batch of chips. Thus, the present application realizes a forward-looking optimization test scheme, which guarantees the testing quality while improving the testing efficiency or economic benefit.

[0060] In the implementation of the optimization step of the present application, the optimization objective can be flexibly constructed according to the actual testing requirements. Those skilled in the art understand that the core is to define a quantifiable scalar function to evaluate the pros and cons of different test parameter combinations, and to find the parameter combination that optimizes (e.g. minimizes) the function value through an optimization algorithm.

[0061] In an embodiment aiming to minimize the testing time, the optimization objective is constructed as a direct measure of the total length of the aging test. For example, the optimization objective can be expressed as:

[0062] where, represents the total time of the complete aging test flow calculated according to the test parameter combination to be evaluated. The optimization algorithm will search for the minimum ; In another embodiment focusing on reducing the testing energy consumption, the optimization objective can be constructed as an estimate of the total energy consumption of the testing system. For example, the optimization objective can be expressed as:

[0063] where, represents the total energy consumption of the testing system at time The real-time total power of the test system is tested, which is a function of test parameters (such as temperature, chip supply voltage) and working states of environmental control equipment (such as heater, refrigeration compressor, fan). The integral represents the total energy consumption in the total time

[0064] In a more general scenario that needs to comprehensively balance test efficiency and energy cost, a multi-objective fusion method can be used to construct the optimization objective. For example, the optimization objective may be constructed in the form of a weighted sum:

[0065] wherein, represents the total energy consumption estimated according to the test parameter combination, which can be calculated in a similar manner as the integral form or by using a simplified model; and are non-negative weight coefficients for adjusting the importance of test time and test energy consumption, respectively, and can be set according to the beat requirements of the specific production line, electricity price cost or comprehensive operation cost analysis.

[0066] Those skilled in the art should understand that the above is only an exemplary construction method of the optimization objective function. In actual application, the optimization objective function can be adaptively adjusted or expressed in other forms according to specific test reliability requirements, device performance and cost structure, which all fall within the scope of the core idea of the present application to optimize test efficiency or cost. The key innovation of optimization is to combine the process feature constraints parsed from the rule knowledge base with the optimization pursuit of the test target (time / energy consumption) to realize intelligent test parameter design through the constraint optimization framework.

[0067] In an embodiment of the present application, the step of calculating a real-time risk score based on the real-time feature primitive vector calculated based on the multi-dimensional process data acquired in real time in the current chip aging test process, matching the real-time feature primitive vector with the rule knowledge base, and calculating a real-time risk score according to the matching result comprises: S51, the latest data of the current test process is intercepted at a preset time interval, and the real-time feature primitive vector is acquired; S52, each feature value in the real-time feature primitive vector is compared with the feature threshold judgment clause contained in the IF part of each decision rule in the rule knowledge base in turn; S53, if the comparison results of all feature threshold judgment clauses of a decision rule are all true, it is determined that the decision rule is triggered by the current state; ​S54, assign a base risk value to each triggered decision rule, and calculate the real-time risk score by weighted summation of base risk values of all triggered decision rules with their respective confidence in the rule knowledge base, divided by the sum of all weights, the formula is:

[0068] wherein, represents the real-time risk score, represents the current set of triggered decision rules, represents the confidence (dimensionless coefficient) of decision rule , and represents the base risk value contributed by decision rule when triggered, which is a constant value predefined according to the risk level of the THEN part of the decision rule (for example, the base risk value is quantitatively assigned according to the risk level of the THEN part of the decision rule, the risk level is divided into three levels: low, medium and high, and the corresponding base risk values are 30, 60 and 100 respectively, the value range is 0-100, and the larger the value represents the higher the risk level of the rule triggering; the confidence is the validation confidence of the decision rule in the historical data set, the value range is 0-1, which is calculated by the proportion of samples actually occurring corresponding failure in the samples covered by the rule, and the confidence is kept to two decimal places, such as 0.85, 0.92, etc.; the value range of the real-time risk score is 0-100, and the larger the value represents the higher the failure risk of the chip at present).

[0069] As described in steps S51-S54 above, when implementing the above steps, the goal is to dynamically apply the static rule knowledge base constructed offline in advance to the ongoing chip aging test process, and realize online and quantitative evaluation of the individual failure risk of the tested chip.

[0070] The system takes a preset fixed period (for example, every 5 minutes or at the end of each test cycle) as the monitoring time point, and immediately intercepts all available latest multi-dimensional process data windows from the start of the current chip self-test to the present moment when each monitoring period arrives, and the length of the window should cover the data accumulation required for feature calculation (for example, the entire trend for calculating the `health state decay rate’). Then, the system calls the same feature calculation engine as steps S21-S25 to process the multi-dimensional process data in the window. Specifically, the system recalculates each derived feature constituting the feature primitive vector based on the current data, such as recalculating the `thermal shock accumulation’ at the current time point based on the latest temperature data, and recalculating the `health state decay rate’ based on the latest health index sequence, thereby obtaining a real-time feature primitive vector reflecting the real-time stress state experienced by the current chip.

[0071] After obtaining the real-time feature vector, the system matches it with each decision rule pre-stored in the rule knowledge base, and the matching process is a deterministic logical comparison: the system takes the IF part of a decision rule in the rule base, which is composed of multiple "feature threshold judgment clauses" (for example: `[thermal shock accumulation > 120], [health state decay rate > 0.05]`), and compares the actual value of the corresponding feature in the real-time feature vector with the pre-set threshold in the rule. Only when the comparison result of all clauses of the rule is "true" (that is, all conditions are met at the same time), it is determined that the rule is triggered by the real-time state of the current chip, otherwise, the rule is not triggered, and the system sequentially executes this matching process on all rules in the rule knowledge base. The result of rule matching is a set of triggered rules, in order to comprehensively evaluate the risk, it is necessary to fuse the information of multiple triggered rules into a single, quantitative risk score, the present application adopts a risk fusion mechanism based on confidence weighting, the specific operation is: first, give each triggered decision rule a basic risk value, this value can be pre-defined according to the risk level of the rule conclusion part, for example, "high risk" rule corresponds to basic value 100, "medium risk" corresponds to 60, "low risk" corresponds to 30, secondly, obtain the inherent confidence of each triggered rule in the knowledge base (that is, the accuracy verified in historical data), finally, calculate the real-time risk score, this calculation method ensures that the rule with higher (more reliable) confidence has greater influence on the final score, so as to obtain a more stable and more reliable risk quantification index, the present application periodically calculates the real-time features and matches them with the knowledge base, so that the system can identify those chip individuals whose multi-dimensional process data show high risk patterns while the test is still in progress, and the calculation of the score is based on the specific rules triggered, which makes each warning traceable, engineers can know whether "excessive thermal shock" or "deteriorating mechanical contact" caused the alarm, improving the credibility and operability of the warning.

[0072] The calculated real-time risk score is a continuous value, and the system maps it to discrete warning levels and specific operation and maintenance instructions through pre-set multi-level thresholds.

[0073] In one embodiment, two increasing risk score thresholds are set, which are a first threshold and a higher second threshold. Exemplarily, the risk score threshold is determined by ROC curve analysis of historical data, the first threshold is set to 40 as a risk attention threshold, the second threshold is set to 70 as a pre-warning threshold, and the third threshold is set to 90 as a serious alarm threshold, all of which are in the range of 0-100 of the risk score; the preset time duration condition is that the real-time risk score exceeds the first threshold for 3-5 monitoring periods, and the monitoring period is consistent with the calculation period of the real-time feature element vector, which is 1-5 minutes; the deterioration condition of the real-time risk score is that the risk score rises by more than 10 in 1 monitoring period or shows an upward trend for 2 consecutive monitoring periods in the pre-warning state; the additional verification test is a more stringent test for the core function of the chip, the number of test vectors is 2-3 times that of the regular test, the test time is 1-2 times that of the regular test, and the judgment standard of the verification test is that the chip function test passes at a rate of 100%, if any item of function test fails, it is determined that the additional verification test fails; When the real-time risk score first exceeds the first threshold, the chip in the current test is marked as an "observation" state, and the specific rule identifier and the corresponding feature value that cause the score to rise are recorded; When the real-time risk score continuously exceeds the first threshold for a predetermined duration, or the real-time risk score instantaneous value exceeds the second threshold, a "pre-warning" state is triggered, and a round of additional and more stringent functional test of the chip is automatically initiated; If the real-time risk score continues to rise and exceeds a higher third threshold, or the result of the additional functional test fails, a "serious alarm" state is triggered, suggesting that the operator interrupt the subsequent aging process of the chip, and list it as the highest priority offline analysis object.

[0074] In the implementation of the hierarchical pre-warning step of the present application, the core is to design a progressive and closed-loop decision and response mechanism to balance the timeliness of risk prevention and control and the stability of production operation, and to avoid false alarms or missed alarms caused by a single threshold.

[0075] The system presets a set of increasing risk score thresholds to divide different risk levels. In one embodiment, the first threshold is set as the starting point of risk attention, and the second threshold is set as the critical point that needs immediate intervention.

[0076] When the system-calculated real-time risk score first exceeds the first threshold, it indicates that the real-time multi-dimensional process data pattern of the chip starts to show early signs similar to historical failure cases. At this point, instead of immediately triggering an alarm that could disrupt the process, the system takes a non-intrusive response: marking the current chip as “watched” in the monitoring system. At the same time, the system automatically records the core “evidence” that led to the score increase, i.e., detailed records of which rules in the rule knowledge base were triggered (through rule unique identifiers), and the specific values of relevant process features (such as `thermal shock cumulative amount`, `health state decay rate`) at the time of triggering. This is intended to establish an auditable risk trajectory, accumulate data for subsequent analysis, and avoid any disturbance to the production process.

[0077] Chips in the “watched” state are continuously monitored. The system determines whether to upgrade the response through two logical paths: if the real-time risk score is not a transient fluctuation, but consistently exceeds the first threshold for a predetermined length of time (e.g., for 3 consecutive monitoring periods), it indicates that the risk state has a certain persistence, rather than accidental noise. The system determines it as a persistent anomaly; if the real-time risk score appears to jump transiently, its value directly exceeds a higher second threshold, which represents a very significant high-risk signal.

[0078] Once either of the above conditions is met, the system upgrades from the “watched” state to the “warning” state. Unlike simply issuing an alarm, the “warning” state automatically triggers a verification action: the system sends instructions to the test machine to immediately perform an additional round of more stringent functional testing on the chip. This round of testing is usually more comprehensive and stringent than the regular periodic test, aiming to verify the accuracy of the multi-dimensional process data risk warning through measured electrical performance. This step establishes a critical verification bridge between data-driven risk speculation and performance measurement in the physical world.

[0079] The “warning” state is a critical decision point. The system makes a final decision based on subsequent developments: 1. If the real-time risk score does not decrease, but continues to rise and breaks through a preset, higher third threshold, it strongly indicates that the failure process is accelerating, and the risk is extremely high; if the results of the automatically initiated additional functional testing do not pass (i.e., the chip fails to meet the electrical specifications of this stringent test), it directly confirms that the chip has a defect from a physical level.

[0080] When any of the above situations occurs, the system triggers the highest level of "serious alarm" state. At this time, the system generates clear recommended instructions: it is recommended that the operator immediately interrupt the subsequent burn-in test process of the chip. At the same time, the system identifies the chip as the highest priority offline analysis object. This means that the chip will be removed from the test socket to free up valuable test resources (machine time, bin) for other chips, and arrange in-depth failure physical analysis (FA) to confirm the root cause.

[0081] The hierarchical early warning scheme of the present application can distinguish different degrees of abnormal patterns by setting multiple threshold values and distinguishing between instantaneous over-limit and sustained over-limit, so as to adopt differentiated response strategies rather than one-size-fits-all alarms. Pure "observation" and recording do not interfere with production, but accumulate risk evidence. The early warning state forces the introduction of additional electrical test verification, which combines soft early warning based on multi-dimensional process data with hard evidence based on electrical tests, improving the accuracy and authority of the alarm and avoiding false production stops caused by sensor noise or transient disturbances. Moreover, the final serious alarm and the recommendation to interrupt the test enable the release of valuable test resources (power, high and low temperature test box machine time, test machine time) from chips that have been determined to be highly likely to fail, and the test resources are used to test other good chips. This can improve the overall process efficiency of the test equipment and achieve risk-based dynamic test length management. From recording risk rules to triggering verification tests to recommending offline analysis, the present scheme provides a complete, traceable decision chain and subsequent action items for each early warning, linking intelligent monitoring with production operation and failure analysis workflows.

[0082] In an embodiment of the present application, the step of intercepting the latest data of the current test process at preset time intervals and obtaining the real-time feature primitive vector comprises: S511, setting a plurality of time windows of different lengths, including a short window reflecting recent short-term changes, a medium window reflecting medium-term trends, and a long window from the start of the test to the present; For example, the lengths of the multi-scale time windows are set according to the cycle period of chip burn-in testing. The length of the short window is 1-2 complete burn-in test cycles, corresponding to an actual time of 10-60 minutes, which is used to capture sudden transient abnormalities. The length of the medium window is 5-10 complete burn-in test cycles, corresponding to an actual time of 1-2 hours, which is used to capture medium-term trend changes. The length of the long window is not limited, which is the entire time from the start of the test of the current chip to the present, which is used to provide a historical baseline reference for the entire test process. The length ratio of the three time windows is 1:5:≥20, ensuring that each window can capture chip state changes in different time dimensions, and the start times of the windows are aligned with the start times of the burn-in test cycles to ensure data integrity and comparability. S512, for the current time, simultaneously intercepting multi-dimensional process data of three data windows with the current time as the end point and the length of the short window, the medium window and the long window respectively; S513, for each of the data windows, a set of basic process features are calculated respectively, including the statistics of temperature, power consumption and health index, forming three window feature subsets; S514, the change rate features between different window feature subsets are calculated, including: the recent change rate of short window features relative to medium window features, and the cumulative change rate of medium window features relative to long window features; Taking the recent change rate of short window features relative to medium window features as an example (the principle of cumulative change rate is the same), the calculation formula is:

[0083] In the formula, indicates the recent change rate of short window features relative to medium window features, indicates the short window features, indicates the medium window features, and are statistical quantities of the same type and dimension).

[0084] The three window feature subsets and the change rate features are combined to form an enhanced real-time feature primitive vector.

[0085] As described above in steps S511-S514, during the real-time feature calculation step, a key problem needs to be solved: how to simultaneously capture the transient abnormality reflecting the chip state, the medium evolution trend and the historical cumulative effect from the continuously flowing test multi-dimensional process data. Using a fixed length sliding window alone may dilute the burst risk signal due to the window being too long, or may not be able to identify the slow changing degradation trend due to the window being too short. Therefore, the present application proposes an innovative multi-scale time window analysis mechanism to construct a real-time feature primitive vector that can more comprehensively reflect the current dynamic health state of the chip.

[0086] Instead of simply using a single time window, the system pre-configures a set of monitoring windows with different time lengths. In a typical embodiment, the following three windows are configured: Short window reflecting recent short-term changes: This window is short in length, for example, corresponding to the last 1-2 aging test cycles or tens of minutes. Its design purpose is to quickly respond and capture recent occurring, burst abnormal events, such as a severe temperature shock, an instantaneous execution of a high power consumption test vector, or a significant mechanical stress change caused by loading and unloading.

[0087] Medium window: This window is medium in length, several times longer than the short window, e.g. covering past several hours or tens of test cycles, and is designed to analyze trend changes that have certain persistence, such as a slow downward trend in test socket health, a gradual drift in average chip power consumption, or a systematic shift in temperature control accuracy.

[0088] Long window: This window is the longest, covering the entire test history since the current chip started testing, and is designed to provide cumulative effects and baseline references throughout the test process, such as total thermal shock cumulative time, historical average health state, overall distribution characteristics of power consumption, etc.

[0089] At each preset monitoring time point (e.g. every minute), the system takes three data stream segments of different lengths backward from the current time point, corresponding to the short window, medium window and long window respectively, and then processes these three independent window data, respectively, for each window's temperature data, power consumption data and health index data, and calculates a set of basic process characteristics. These basic characteristics mainly include various statistical quantities, such as: For temperature data: calculate the mean, maximum, minimum, and standard deviation within the window.

[0090] For power consumption data: calculate the average power, peak power, and dynamic range (maximum - minimum) within the window.

[0091] For health index data: calculate the minimum and latest value within the window.

[0092] By calculating these characteristics independently for each window, we obtain three independent window characteristic subsets: short window characteristics, medium window characteristics, and long window characteristics. Then further calculate the change rate characteristics between them, including two key change rates: 1. Recent change rate: used to measure the degree of change of the latest short-term fluctuations relative to the medium-term background, the system calculates the relative change rate between the statistical quantities (such as average power consumption) in the short window characteristic subset and the corresponding statistical quantities in the medium window characteristic subset, for example, the result is "the average power consumption of the last 10 minutes has increased by 15% relative to the average power consumption of the past 2 hours", this feature can amplify those abnormal signals that occur in the short-term window but have not been averaged out by the longer window.

[0093] 2. Accumulative change rate: used to measure the deviation of medium-term trend from the whole test history. The system calculates the relative change rate between each statistic in the medium window feature subset and the corresponding statistic in the long window feature subset, e.g. the result is "the health index minimum in the past 2 hours has decreased by 8% compared to the health index average in the whole test history", this feature can identify those degradation trends that develop slowly but have caused significant deviation of the state from the historical baseline.

[0094] The failure of a chip in the aging test can be caused by instantaneous over-stress (such as thermal shock) or long-term cumulative damage (such as contact fatigue). If a single time window is used in the traditional real-time monitoring method, it is difficult to effectively capture both risk patterns at an early stage. The scheme in this part solves this problem by introducing multi-scale time window parallel analysis and cross-window change rate calculation. Its contribution lies in realizing multi-dimensional perception of risk signals, among which, the short window feature directly reflects the instantaneous state, the medium window feature reflects the recent trend, the long window feature provides the historical baseline, the recent change rate amplifies the sudden abnormality, and the accumulative change rate quantifies the gradual deviation. The information in these five dimensions together constitutes a stereoscopic portrait of the current dynamic health status of the chip; and improves the sensitivity and accuracy of early warning, for example, an instantaneous power consumption peak may not be obvious after averaging in the long window, but by calculating its recent change rate relative to the medium window, the abnormality will be amplified and become an effective early warning signal. Similarly, a slow health degradation, whose absolute value may not trigger an alarm, may have exceeded the threshold in its accumulative change rate relative to the long window baseline, thus achieving earlier warning; and enables the matching of real-time features and offline knowledge base to be more robust. When building the rule knowledge base offline, the historical features used can also be constructed based on this multi-window, multi-change rate scheme, which makes the features calculated in real time and the rules in the knowledge base have consistent definitions and comparability in the feature space, thereby ensuring the accuracy of matching and scoring.

[0095] In an embodiment of the present application, the present application further includes an updating step of the rule knowledge base: S71, adding the data of the new chip that has completed the aging test and the final electrical test, including its feature primitive vector and final test result label, to the historical data set; S72, periodically re-executing the rule extraction process based on the updated historical data set; S73, compare and fuse the newly extracted decision rule set with the existing rule knowledge base, for rules pointing to the same failure mode but with conflicting conditions, arbitrate and replace them according to their confidence and coverage in the new data set, realize the iterative update of the rule knowledge base (for example, the predetermined rule for resolving rule conflicts is: for conflicting rules pointing to the same failure mode, calculate the comprehensive score of each rule, the comprehensive score is equal to the confidence multiplied by the coverage, keep the rule with the highest comprehensive score and eliminate the remaining conflicting rules; if the comprehensive scores are the same, keep the rule with higher coverage to ensure the universality of the rule; for the case where the newly extracted rule has no conflict with the existing rule but has complementarity, directly add the new rule to the rule knowledge base to expand the coverage of the knowledge base; the update cycle of the knowledge base is divided into timed update and quantitative update, the timed update cycle is 1 week, the quantitative update is triggered after every 100-500 effective test samples are added, the historical rule version is kept during the update process, if the new rule has a decrease in early warning accuracy in actual application, it can be rolled back to the historical optimal rule version; after each update is completed, the effectiveness of the updated rule knowledge base needs to be verified, test samples are selected for testing to ensure that the early warning accuracy is not less than 80%, and then it can be put into actual use).

[0096] As described in steps S71-S73 above, the present application can enable the rule knowledge base constructed based on historical data in the early stage to continuously adapt to new chip designs, new process batches, changing test board states, and un-covered failure modes. First, the learning cycle of the system starts with the continuous injection of new data. When a batch of chips completes the entire aging test process (including tests based on the present application or conventional processes), and after the final, authoritative electrical test determination, the complete data record of these chips becomes a new learning sample. The system will re-execute the feature construction process described in steps S21-S25 for each chip that has completed the test, generating its corresponding feature primitive vector. At the same time, the final electrical test result (pass / fail, if failed, including the failure category) is taken as the final test result label of the sample. Subsequently, this new data pair consisting of "feature vector-result label" is automatically added to the system's historical data set, and then actively and periodically refreshes its core cognitive model using new data. According to the predetermined period (for example, every 1000 chip test is completed, or every Sunday morning), the system will use the updated historical data set containing all old and new data as the new training basis, and automatically trigger a complete model and rule reconstruction process. This process re-executes the steps described in steps S31-S35: 1. Use the latest data set to retrain the gradient boosting decision tree model.

[0097] 2. From the newly trained model, re-extract a set of decision rules.

[0098] 3. Using the same coverage and confidence threshold, the new rules are filtered, merged and simplified, and a new set of decision rules is finally obtained.

[0099] This step allows the system to periodically review all known data, which may discover previously unrecognized patterns or correct the deviation of the original model due to insufficient data. After obtaining the new rule set, a knowledge fusion process is performed, and the new rule set and the existing rule knowledge base are juxtaposed and compared. The core of the fusion strategy is to handle rule conflicts: for new conditions about a failure mode proposed in the new rule set that do not exist in the old library, after verification of the confidence and coverage, they can be directly added to the knowledge base to expand its knowledge coverage; for rules in the new rule set and the old library that have similar premise conditions and the same conclusion but higher confidence, the new rule replaces the old rule to upgrade the confidence of the knowledge; when there are two rules in the new and old rule sets that point to the same failure mode, but their premise conditions (IF part) have opposite logical judgment directions or threshold conflicts (for example, the old rule says "when A>100, the risk is high", and the new rule says "when A<50, the risk is high"), a conflict occurs. The system arbitrates these two rules based on the new data, and the arbitration basis is the confidence and coverage of the two rules on the latest and most complete data set. The principle is that the rule with higher confidence and wider coverage is recognized as more reliable. The system retains the winning rule and labels the samples of the losing rule as exceptions or triggers further analysis, because this may indicate that the failure mechanism has changed or there is a new interference factor.

[0100] After fusion and arbitration are completed, the system generates an updated version of the rule knowledge base that integrates historical wisdom and the latest discoveries. After the update is completed, the system automatically points the rule reference of the subsequent parameter optimization module and real-time risk scoring module to this new version, so that subsequent test tasks will benefit from the latest refined knowledge, and newly input test chips will use more accurate risk assessment rules and more optimized test parameter combinations.

[0101] As shown in Figure 2 The application also provides a chip aging test parameter optimization and failure warning system, which comprises: A data acquisition module is configured to acquire multi-dimensional process data and corresponding final electrical test results of a chip in a historical aging test process, wherein the multi-dimensional process data comprises thermal stress data, electrical stress data, and test socket mechanical state data. A feature construction module is configured to construct a feature primitive vector for each historical test based on the multi-dimensional process data, wherein the feature primitive vector is composed of a plurality of derived features representing explicit physical meanings. a rule extraction module, configured to fit a gradient boosting decision tree model based on the feature basis vector and the final electrical test result, and extract interpretable decision rules in the form of IF-THEN from the model to form a rule knowledge base; a parameter optimization module, configured to inversely analyze the decision rules into constraint conditions for test process features according to the rule knowledge base, and perform an optimization search on controllable test parameters with the constraint conditions as boundaries to generate an optimized test parameter combination for a new test task; a risk score module, configured to calculate a real-time feature basis vector based on multi-dimensional process data acquired in real time during a current chip aging test process, match the real-time feature basis vector with the rule knowledge base, and calculate a real-time risk score according to a matching result; a hierarchical early warning module, configured to perform hierarchical early warning according to the real-time risk score.

[0102] The application further provides a chip aging test device, which comprises a test machine, an environmental test box, a plurality of process sensors, and a chip aging test parameter optimization and failure early warning system.

[0103] It should be noted that the core hardware components of the chip aging test device include: The test machine is responsible for applying electrical stress (voltage, current, frequency) and test vectors to the chip under test and collecting functional response data of the chip, and is the source of electrical stress data and final electrical test results. Figure 3 As shown in FIG. 6, the support plate 1 is integrated. Figure 4 As shown in FIG. 7, the support plate 1 and the gasket are integrated, which combines the support plate 1 and the gasket together as one part, so as to reduce the installation process and improve the assembly efficiency. Figure 5 As shown in FIG. 8, the support plate 1 is a strip combination, which is composed of an upper support plate 11, a right vertical support bar 12, a horizontal support bar 13, a vertical support bar 14, a left vertical support bar 15, and a lower support plate 16. Figure 6 As shown in FIG. 9, the support plate 1 is a three-segment combination, which is composed of a front segment support plate 17, a middle segment support plate 18, and a rear segment support plate 19. The environmental test chamber is a high-low temperature test chamber, and is responsible for providing an accurate and controllable temperature environment (including a heating, refrigeration and air circulation system) for aging test. The environmental test chamber is a source of thermal stress data (furnace temperature, air speed, etc.), and receives temperature setting instructions. A plurality of process sensors: this is a general sensor unit, at least including: Temperature sensors: distributed near the test board or chip, used to collect chip shell temperature / junction temperature and local environmental temperature; Health monitoring unit: integrated into the aging test board, used to collect dynamic mechanical signals of the mechanical state of the socket, and calculate the health index; Power monitoring unit: integrated into the power measurement module of the test machine, used to collect real-time power consumption data of the chip with high precision.

[0104] Intelligent decision and control system: a computing unit with a processor and a memory as the core, which can be physically deployed as an independent host server, integrated into a PLC controller of the test chamber, or accessed to the test network in the form of an edge computing node.

[0105] It should be noted that in this paper, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, device, article or method including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, device, article or method. Without more limitations, the element defined by the statement "includes a" does not exclude the existence of another same element in the process, device, article or method including the element.

[0106] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A method for optimizing chip aging test parameters and providing early warning of failure, characterized in that, include: Acquire multidimensional process data of the chip during historical aging test and the corresponding final electrical test results, wherein the multidimensional process data includes thermal stress data, electrical stress data and test socket mechanical state data; Based on the multidimensional process data, a feature primitive vector is constructed for each historical test. The feature primitive vector consists of multiple derived features that represent clear physical meanings. Based on the feature primitive vectors and the final electrical test results, a gradient boosting decision tree model is used for fitting, and interpretable decision rules in the form of IF-THEN are extracted to form a rule knowledge base. Based on the rule knowledge base, the decision rules are reverse-parsed into constraints on the characteristics of the testing process, and the controllable test parameters are optimized and searched using the constraints as boundaries to generate an optimized combination of test parameters for the new test task. In the current chip aging test process, a real-time feature primitive vector is calculated based on the multi-dimensional process data acquired in real time. The real-time feature primitive vector is then matched with the rule knowledge base, and a real-time risk score is calculated based on the matching result. A tiered early warning system is implemented based on the real-time risk score.

2. The chip aging test parameter optimization and failure early warning method according to claim 1, characterized in that, The step of constructing feature primitive vectors for each historical test based on the multidimensional process data includes: The thermal stress data, electrical stress data, and mechanical state data are synchronized and aligned according to timestamps, and the data window is divided with a complete aging test cycle as the basic unit. For the divided thermal stress data, the cumulative time when the chip's temperature change rate exceeds a preset threshold during the temperature change phase is calculated and recorded as the first derived feature, which is called the cumulative thermal shock amount. For the divided electrical stress data, calculate the time constant required for the autocorrelation function of the chip power consumption timing data under the target test vector to decay to the first preset value, and use it as the second derived feature, denoted as power consumption change inertia; For the divided mechanical state data, the absolute value of the linear regression slope of the health status index of the test socket over time during the complete test cycle of carrying the current chip is calculated and used as the third derived feature, denoted as the health status decay rate. The cumulative thermal shock, the power consumption change inertia, the health state decay rate, and the statistical features extracted from the original data are combined to form the feature primitive vector.

3. The chip aging test parameter optimization and failure early warning method according to claim 1, characterized in that, The steps of fitting the feature primitive vectors and the final electrical test results using a gradient boosting decision tree model, and extracting interpretable decision rules in the form of IF-THEN to form a rule knowledge base include: Using the aforementioned feature primitive vectors as input features and binary labels representing whether a chip has failed as output targets, a gradient boosting decision tree ensemble model is trained. The structure of each decision tree in the gradient boosting decision tree ensemble model is analyzed, and the path from the root node to each leaf node is traversed. Each path is converted into an original rule consisting of multiple feature threshold judgment clauses connected by logical AND relation. Based on preset coverage and confidence limits, the original rules are filtered, where coverage refers to the proportion of historical samples to which the rule applies to the total number of samples, and confidence refers to the proportion of samples that actually fail in the samples to which the rule applies. The original rules that have passed the screening are merged and simplified to obtain multiple decision rules in the form of IF-THEN. The THEN part of each decision rule represents the associated failure category and risk level. The rule knowledge base is composed of all the aforementioned decision rules.

4. The chip aging test parameter optimization and failure early warning method according to claim 1, characterized in that, The steps of reversing the decision rules into constraints on the characteristics of the testing process based on the rule knowledge base, and using the constraints as boundaries to optimize and search for controllable test parameters to generate optimized test parameter combinations for new test tasks include: From the rule knowledge base, select all decision rules for the failure categories of the THEN part of the associated targets; Each feature threshold judgment clause contained in the IF part of each selected decision rule is converted into a constraint inequality about the range of values ​​of the corresponding process feature. The optimization objective function is to minimize the total test duration or total energy consumption. The hardware capability limit of the test equipment is the first set of constraints, and all the aforementioned constraint inequalities are the second set of constraints. Together, they define a constrained optimization problem. Within the feasible region of the controllable test parameters, the constrained optimization problem is iteratively solved using a Bayesian optimization algorithm, wherein the controllable test parameters include at least the duration of each temperature stage, the rate of temperature change between adjacent stages, and the test voltage applied to the chip. The specific values ​​of the controllable test parameters obtained by solving are output as the optimized test parameter combination.

5. The chip aging test parameter optimization and failure early warning method according to claim 1, characterized in that, The steps of calculating a real-time feature primitive vector based on real-time acquired multi-dimensional process data during the current chip aging test, matching the real-time feature primitive vector with the rule knowledge base, and calculating a real-time risk score based on the matching result include: The latest data of the current test process is captured at preset time intervals, and the real-time feature primitive vector is obtained. Each feature value in the real-time feature primitive vector is compared sequentially with the feature threshold judgment clause contained in the IF part of each decision rule in the rule knowledge base. If all the feature threshold judgment clauses of a decision rule are true, then the decision rule is determined to be triggered by the current state. A base risk value is assigned to each triggered decision rule. The real-time risk score is calculated based on the base risk values ​​of all triggered decision rules and their corresponding confidence levels in the rule knowledge base.

6. The chip aging test parameter optimization and failure early warning method according to claim 5, characterized in that, The step of extracting the latest data of the current test process at preset time intervals and obtaining the real-time feature primitive vector includes: Set multiple time windows of different lengths, including: a short window reflecting recent short-term changes, a medium window reflecting medium-term trends, and a long window from the start of the test to the present. For the current moment, multidimensional process data is simultaneously extracted from three data windows, namely the short window, the medium window, and the long window, with the current moment as the endpoint. For each of the data windows, a set of basic process characteristics, including statistics on temperature, power consumption, and health index, are calculated to form three window feature subsets; Calculate the rate of change features among different window feature subsets, including: the recent rate of change of short window features relative to medium window features, and the cumulative rate of change of medium window features relative to long window features.

7. The chip aging test parameter optimization and failure early warning method according to claim 1, characterized in that, The step of executing a tiered early warning based on the real-time risk score includes: Set at least two incremental risk score thresholds; When the real-time risk score exceeds a lower risk score threshold, the current chip is marked with a status and abnormal data is recorded. When the abnormal state of the real-time risk score meets the preset time duration condition or exceeds a higher risk score threshold, the first-level warning action is triggered, and additional verification tests on the current chip are initiated. When the real-time risk score meets the preset deterioration conditions after the first-level warning action is triggered, or when the additional verification test fails, the second-level warning action is triggered to stop the subsequent aging test of the current chip and arrange offline analysis.

8. The chip aging test parameter optimization and failure early warning method according to claim 1, characterized in that, It also includes the steps for updating the rule knowledge base: Add new test sample data to the historical dataset to update the historical dataset; Based on the updated historical dataset, the rule extraction process is periodically re-executed to obtain an updated set of decision rules; The updated decision rule set is merged with the rule knowledge base, and conflicting rules generated during the merging process are arbitrated according to predetermined rules in order to update the rule knowledge base.

9. A chip aging test parameter optimization and failure early warning system, characterized in that, include: The data acquisition module is used to acquire multi-dimensional process data of the chip during the historical aging test and the corresponding final electrical test results. The multi-dimensional process data includes thermal stress data, electrical stress data and test socket mechanical state data. The feature construction module is used to construct a feature primitive vector for each historical test based on the multidimensional process data. The feature primitive vector is composed of multiple derived features that represent clear physical meanings. The rule extraction module is used to fit the feature primitive vector and the final electrical test result through a gradient boosting decision tree model, and extract interpretable decision rules in the form of IF-THEN to form a rule knowledge base. The parameter optimization module is used to reverse-parse the decision rules into constraints on the characteristics of the test process based on the rule knowledge base, and to optimize and search the controllable test parameters using the constraints as boundaries to generate an optimized combination of test parameters for the new test task. The risk scoring module is used to calculate a real-time feature primitive vector based on real-time acquired multi-dimensional process data during the current chip aging test, match the real-time feature primitive vector with the rule knowledge base, and calculate a real-time risk score based on the matching result. The graded early warning module is used to execute graded early warnings based on the real-time risk score.

10. A chip aging test device, characterized in that, The system includes a testing machine, an environmental test chamber, multiple process sensors, and the system as described in claim 9, wherein the system is communicatively connected to the testing machine, the environmental test chamber, and the process sensors, for receiving data generated therefrom, and outputting the optimized test parameter combination and early warning signal.

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