EDA tool chain real-time consistency verification method and system based on graph neural network

Abstract

The invention relates to the technical field of circuit design, in particular to an EDA tool chain real-time consistency verification method and system based on a graph neural network, and the method comprises the steps: generating a comprehensive stage and a unit library graph to be laid out; judging whether the to-be-arranged library graph is missing or not, and if yes, performing early warning; if yes, redundant nodes are checked, and whether early warning is carried out is determined; checking library file format suitability; and calculating a node feature similarity mean value through the two-layer graph convolutional network, and judging whether the two graphs are matched or not. The system comprises an acquisition module, a judgment module, an inspection module and a verification module, and can realize consistency real-time verification of logic synthesis and physical layout stages in an EDA tool chain.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit design, in particular to a graph neural network-based EDA tool chain real-time consistency checking method and system. BACKGROUND

[0002] In the "logic synthesis-physical layout" core process of the digital chip EDA tool chain, novice designers often make mistakes in operation, resulting in cell library mismatch problems, such as using a 7nm process cell library for logic synthesis and mistakenly selecting a 14nm process library for physical layout. The existing checking technology has the following defects: first, the checking link is lagging, and it is executed near the end of the tool chain (such as the physical verification stage), so the mismatch is discovered when the early synthesis and layout work has been completed, and the entire design cycle and time cost are greatly increased; second, there is a lack of hierarchical checking logic, and the integrity and format compatibility of the cell are not verified first, so the attribute matching is directly executed, which may lead to distorted checking results due to missing key cells or incompatible library file formats; third, there is no automatic correction and hierarchical warning mechanism, and the designer needs to manually troubleshoot when the cell is missing or the format is incorrect, which has a high operation threshold and low efficiency. Therefore, there is an urgent need for a real-time consistency checking solution that can be embedded in the middle of the process, has hierarchical checking, and has automatic capabilities to solve the problems of mismatch discovery lag, low checking efficiency, and poor usability. SUMMARY

[0003] In view of the above, the present application proposes a graph neural network-based EDA tool chain real-time consistency checking method and system to solve at least one of the problems in the above background technology.

[0004] In a first aspect, the present application provides a graph neural network-based EDA tool chain real-time consistency checking method, comprising the following steps: Obtain all standard cell lists used by the target logic synthesis tool in the current executed synthesis task and the core attributes of each cell, each standard cell is a node, and all nodes in the same synthesis task are connected by undirected edges to generate a synthesis stage cell library graph; obtain the standard cell list to be used before the target physical layout tool is started, and the process node and library file name attributes, each standard cell is a node, and all nodes in the same synthesis task are connected by undirected edges to generate a layout-ready cell library graph; Determine whether the layout-ready cell library graph is incomplete due to missing cells according to the node set of the key logic cells of the synthesis stage cell library graph, and when the layout-ready cell library graph is incomplete due to missing cells, terminate attribute matching and issue a warning signal; when the to-be-laid-out cell library graph is complete in cells, judging whether there is a redundant node in the to-be-laid-out cell library graph according to a node set of a key logic cell of the synthesis stage cell library graph, when there is a redundant node in the to-be-laid-out cell library graph, judging whether to issue a redundant cell warning; checking whether a library file corresponding to the to-be-laid-out cell library graph meets a format specification of the target physical layout tool, and judging whether format adaptability passes; when judging that the format adaptability passes, obtaining a node-by-node feature cosine similarity between the synthesis stage cell library graph and the to-be-laid-out cell library graph based on a two-layer graph convolution network, and obtaining an average of all node similarities, and judging whether the synthesis stage cell library graph and the to-be-laid-out cell library graph match based on the average of all node similarities.

[0005] In some embodiments, the method comprises: obtaining a list of all standard cells used in a current execution of a synthesis task by a target logic synthesis tool, and core attributes of each standard cell, each standard cell being a node, all nodes in the same synthesis task being connected by undirected edges, to generate a synthesis stage cell library graph; and obtaining a list of standard cells to be used before a target physical layout tool is started, and process nodes and library file name attributes, each standard cell being a node, all nodes in the same synthesis task being connected by undirected edges, to generate a to-be-laid-out cell library graph, comprising: in the generation of the synthesis stage cell library graph and the generation of the to-be-laid-out cell library graph, weights of the undirected edges are all 1.

[0006] In some embodiments, the method further comprises: judging whether the to-be-laid-out cell library graph is incomplete in cells according to the node set of the key logic cell of the synthesis stage cell library graph, when the to-be-laid-out cell library graph is incomplete in cells, terminating attribute matching, and issuing a warning signal, comprising: predefining the node set of the key logic cell of the synthesis stage cell library graph as a node set S, and predefining a node set corresponding to the node set S in the to-be-laid-out cell library graph as a node set P; when the node set P exists in the to-be-laid-out cell library graph, judging that the to-be-laid-out cell library graph is complete in cells; when the node set P does not exist in the to-be-laid-out cell library graph, judging that the to-be-laid-out cell library graph is initially incomplete in cells.

[0007] In some embodiments, the method further comprises: judging whether the to-be-laid-out cell library graph is incomplete in cells according to the node set of the key logic cell of the synthesis stage cell library graph, when the to-be-laid-out cell library graph is incomplete in cells, terminating attribute matching, and issuing a warning signal, comprising: When it is determined that the to-be-laid-out cell library graph is incomplete in terms of missing cells, missing cell details are obtained according to the node set S and the node set P, and it is determined whether a library file matching the missing cell details exists in the preset resource library; When the library file matching the missing cell details exists in the preset resource library, the to-be-laid-out cell library graph is regenerated, and it is determined whether the node set P exists in the to-be-laid-out cell library graph. When the library file matching the missing cell details does not exist in the preset resource library, it is determined that the to-be-laid-out cell library graph is incomplete in terms of missing cells, attribute matching is terminated, and a warning signal is issued.

[0008] In some embodiments, when the library file matching the missing cell details exists in the preset resource library, the to-be-laid-out cell library graph is regenerated, and it is determined whether the node set P exists in the to-be-laid-out cell library graph, including: When the to-be-laid-out cell library graph is regenerated, and the node set P exists in the to-be-laid-out cell library graph, it is determined that the to-be-laid-out cell library graph is complete in terms of cells. When the to-be-laid-out cell library graph is regenerated, and the node set P does not exist in the to-be-laid-out cell library graph, it is determined that the to-be-laid-out cell library graph is incomplete in terms of missing cells, attribute matching is terminated, and a warning signal is issued.

[0009] In some embodiments, when it is determined that the to-be-laid-out cell library graph is incomplete in terms of missing cells, attribute matching is terminated, and a warning signal is issued, the method further includes: When the to-be-laid-out cell library graph is incomplete in terms of missing cells, and the total number of missing cells greater than a preset weight in the missing cell details is greater than or equal to a preset missing threshold, a first warning signal is issued. When the to-be-laid-out cell library graph is incomplete in terms of missing cells, and the total number of missing cells greater than a preset weight in the missing cell details is less than a preset missing threshold, a second warning signal is issued.

[0010] In some embodiments, when the to-be-laid-out cell library graph is complete in terms of cells, it is determined whether a redundant node exists in the to-be-laid-out cell library graph according to the node set of the key logic cell of the synthesis stage cell library graph, and when the redundant node exists in the to-be-laid-out cell library graph, it is determined whether to issue a redundant cell warning, including: When no redundant node that exceeds the range of the node set of the synthesis stage cell library graph exists in the node set of the to-be-laid-out cell library graph, it is determined not to issue the redundant cell warning. determining not to issue the redundant cell warning when the redundant nodes beyond the node set range of the synthesis stage cell library graph exist in the node set of the cell library graph to be laid out and the total number of the redundant nodes is less than or equal to a preset threshold value; determining to issue the redundant cell warning when the redundant nodes beyond the node set range of the synthesis stage cell library graph exist in the node set of the cell library graph to be laid out and the total number of the redundant nodes is greater than a preset threshold value.

[0011] In some embodiments, the checking whether the library file corresponding to the cell library graph to be laid out satisfies the format specification of the target physical layout tool to determine whether the format adaptability passes includes: determining that the format adaptability passes when the library file corresponding to the cell library graph to be laid out satisfies the format specification of the target physical layout tool; determining that the format adaptability does not pass and issuing a third warning signal when the library file corresponding to the cell library graph to be laid out does not satisfy the format specification of the target physical layout tool.

[0012] In some embodiments, when it is determined that the format adaptability passes, the two-layer graph convolution network is used to obtain the node-by-node feature cosine similarity between the synthesis stage cell library graph and the cell library graph to be laid out, and the average similarity of all nodes is obtained, and whether the synthesis stage cell library graph and the cell library graph to be laid out match is determined based on the average similarity of all nodes, including: determining that the synthesis stage cell library graph and the cell library graph to be laid out match when the average similarity of all nodes is greater than or equal to a preset similarity threshold value; determining that the synthesis stage cell library graph and the cell library graph to be laid out do not match when the average similarity of all nodes is less than a preset similarity threshold value.

[0013] In a second aspect, the present application provides a real-time consistency verification system of an EDA tool chain based on a graph neural network, including: The acquisition module is configured to obtain all standard cell lists and core attributes of each cell used by a target logic synthesis tool in a currently executed synthesis task, each standard cell being a node, all nodes in the same synthesis task being connected by undirected edges to generate a synthesis stage cell library graph; and obtain standard cell lists, process nodes and library file name attributes to be used before a target physical layout tool is started, each standard cell being a node, all nodes in the same synthesis task being connected by undirected edges to generate a cell library graph to be laid out; A first judgment module is electrically connected with the acquisition module, and is configured to judge whether the unit library graph to be laid out is incomplete in units according to the node set of the key logic unit of the integrated stage unit library graph, and when the unit library graph to be laid out is incomplete in units, terminate attribute matching and issue a warning signal; A second judgment module is electrically connected with the first judgment module, and is configured to, when the unit library graph to be laid out is complete, judge whether there is a redundant node in the unit library graph to be laid out according to the node set of the key logic unit of the integrated stage unit library graph, and when there is a redundant node in the unit library graph to be laid out, judge whether to issue a redundant unit warning; An inspection module is electrically connected with the second judgment module, and is configured to inspect whether the library file corresponding to the unit library graph to be laid out meets the format specification of the target physical layout tool, and judge whether format adaptability passes; A verification module is electrically connected with the inspection module, and is configured to, when judging that format adaptability passes, acquire the node-by-node feature cosine similarity of the integrated stage unit library graph and the unit library graph to be laid out based on a two-layer graph convolution network, acquire the average of all node similarities, and judge whether the integrated stage unit library graph and the unit library graph to be laid out match based on the average of all node similarities.

[0014] Compared with the prior art, the beneficial effects of the present application are that the unit library consistency verification link is advanced from the end of the EDA tool chain to the intermediate stage of "logic synthesis-physical layout", through layered verification of unit integrity, format adaptability and attribute consistency, the unit library mismatch (such as process node, library file version error) can be found in time before the physical layout starts, the previous synthesis and layout work is avoided, the design cycle is greatly shortened, and the problem of time cost waste caused by traditional verification lag is solved.

[0015] Relying on the node-by-node feature cosine similarity calculation of the graph neural network, combined with the verification of unit key attributes (process, library file, functional semantics), the mismatched nodes and error attributes can be accurately located, the key unit missing risk can be excluded through unit integrity verification, the format adaptability verification ensures that the library file can be normally parsed by the layout tool, and the design function deviation or physical layout failure caused by distorted basic information is avoided.

[0016] The scheme realizes automatic generation of the unit library graph, automatic triggering of the verification process and visual feedback of error information, without the need for the designer to write complex codes or master the knowledge of the graph neural network; in the face of unit missing scenarios, the resource library can be automatically searched to supplement the matching library file, manual checking and manual configuration operations are reduced, especially for novice designers, and the use threshold of the EDA tool chain is lowered.

[0017] The above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure.

[0018] Other features and aspects of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 A flowchart of a real-time consistency verification method for an EDA toolchain based on graph neural networks, provided in an embodiment of the present invention; Figure 2 This is a functional block diagram of a real-time consistency verification system for an EDA toolchain based on graph neural networks, provided in an embodiment of the present invention. Detailed Implementation

[0021] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, embodiments and features in the embodiments of the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] See Figures 1-2 As shown in the first embodiment, a real-time consistency verification method for an EDA toolchain based on a graph neural network, according to an embodiment of this application, includes the following steps: S100. Obtain the list of all standard cells used by the target logic synthesis tool in the currently executed synthesis task and the core attributes of each cell. Each standard cell is a node, and all the nodes in the same synthesis task are connected by undirected edges to generate a cell library diagram for the synthesis stage. Obtain the list of standard cells to be used before the target physical layout tool starts, as well as the process node and library file name attributes. Each standard cell is a node, and all the nodes in the same synthesis task are connected by undirected edges to generate a cell library diagram to be laid out. S200. Based on the node set of the key logical units of the integrated stage unit library diagram, determine whether the unit library diagram to be laid out is incomplete or missing units. When the unit library diagram to be laid out is incomplete or missing units, terminate attribute matching and issue a warning signal. S300. When the unit library diagram to be laid out is complete, determine whether there are redundant nodes in the unit library diagram to be laid out based on the node set of the key logic units in the unit library diagram of the synthesis stage. When there are redundant nodes in the unit library diagram to be laid out, determine whether to issue a redundant unit warning. S400. Check whether the library file corresponding to the library diagram of the unit to be laid out meets the format specifications of the target physical layout tool, and determine whether the format compatibility is passed. S500. When the format compatibility is passed, the node-wise feature cosine similarity between the synthesis stage unit library graph and the unit library graph to be laid out is obtained based on a two-layer graph convolutional network, and the average similarity of all nodes is obtained. Based on the average similarity of all nodes, it is determined whether the synthesis stage unit library graph and the unit library graph to be laid out match.

[0023] In some specific embodiments, the process of obtaining a list of all standard cells used by the target logic synthesis tool in the currently executed synthesis task and the core attributes of each cell, where each standard cell is a node and all nodes in the same synthesis task are connected by undirected edges, generates a cell library diagram for the synthesis stage; and obtaining a list of standard cells to be used before the target physical layout tool starts, along with process nodes and library file name attributes, where each standard cell is a node and all nodes in the same synthesis task are connected by undirected edges, generates a cell library diagram to be laid out, including: The weights of the undirected edges in both the generated synthesis stage unit library graph and the generated unit library graph to be laid out are 1.

[0024] It should be understood that the synthesis stage cell library diagram (G_synth) is generated as follows: Information Extraction: After the logic synthesis tool (such as Synopsys Design Compiler) finishes execution, it automatically extracts the list of all standard cells used in this synthesis (such as AND gate AND2, register DFF) and the core attributes of each cell from its output log or cell library call interface: ① process node (such as 7nm, 14nm) ② cell library file name (such as "TSMC7nm.lib"). Graph structure construction: Each standard unit is a "node". The node feature vector is formed by concatenating the process node code (e.g., "7nm" is encoded as [1,0] and "14nm" is encoded as [0,1]) with the library file name hash code; all unit nodes in the same synthesis task are connected by "undirected edges" (edge ​​weight = 1, representing the "same batch use" correlation). Storage: Store G_synth in GraphML or PyTorchGeometric Data format to the EDA toolchain temporary data directory.

[0025] To be generated: Layout cell library diagram (G_place) Information extraction: Before the physical layout tool (such as CadenceInnovus) is started, it automatically reads the cell library configuration file selected by the designer and extracts the list of standard cells to be used, as well as process nodes and library file name attributes; Graph structure construction: Using node definitions, edge definitions, and feature encoding rules completely consistent with G_synth, construct the layout unit library graph G_place; Storage: Store G_place in the same format as G_synth to ensure graph structure consistency to support subsequent comparisons.

[0026] From the perspective of graph structure construction goals, the core function of the unit library graph in this scheme is to "carry unit attribute information and mark unit relationships," rather than complex topological relationship analysis—there is no need to distinguish the strength of relationships between units through weights. Therefore, setting the weight of undirected edges to 1 can clearly represent the basic relationship that "all standard units in the same synthesis / layout task belong to the same batch of parts used." This avoids increasing the complexity of the graph model due to weight differentiation design, and also ensures that the graph neural network (GNN) is not disturbed by irrelevant weight differences during feature extraction, focusing on the core attributes of the nodes themselves, such as process and library files. From the perspective of adaptability of subsequent verification processes, a unified weight of 1 ensures that the graph structures of G_synth and G_place are completely aligned: the definitions of edges and weight rules of the two are consistent, so that when GNN calculates the cosine similarity of features at each node, it only needs to compare the differences in node attributes, without having to deal with the adaptation of edge weights, thus reducing computational redundancy in the verification process. At the same time, this simplified graph structure can reduce the difficulty of automatically generating the cell library graph, ensuring that after extracting cell information from logic synthesis tools and physical layout tools, a standardized graph model can be quickly constructed, which is in line with the design goal of "automation and low complexity" of the solution.

[0027] In some specific embodiments, the step of determining whether the unit library diagram to be laid out is incomplete or missing units based on the node set of the key logical units of the unit library diagram in the synthesis stage, and terminating attribute matching and issuing a warning signal when the unit library diagram to be laid out is incomplete or missing units, includes: The node set of the key logic unit in the integrated stage unit library diagram is preset to be node set S, and the node set corresponding to node set S in the unit library diagram to be laid out is preset to be node set P; When the node set P exists in the unit library diagram to be laid out, it is determined that the unit library diagram to be laid out is complete. When the node set P is not present in the unit library diagram to be laid out, it is determined that the unit library diagram to be laid out is incomplete due to missing initial units.

[0028] It should be understood that the node set S is a set of "critical logic units" selected from the unit library diagram (G_synth) during the synthesis stage. The selection criteria are the impact of the units on the core functions and timing performance of the chip—prioritizing the inclusion of key timing path registers, main operation modules (such as AND gates and OR gates), and dedicated function units (such as RAM / ROM). The absence of these units will directly lead to the failure of chip logic functions or timing violations. Therefore, S is used as the "basic standard that must be covered" to ensure that verification focuses on core requirements. The node set P is a set of units in the unit library diagram (G_place) that correspond one-to-one with S. The matching must meet the requirement of "unit name + core attribute consistency"—not only must the unit name (such as "DFF_core" or "AND2_main") be exactly the same as S, but it must also ensure that the basic attributes of the unit (such as process node and functional semantic label) are consistent with the corresponding unit in S, avoiding the misjudgment of units with "same name but different function / process" as valid matches, and ensuring the substantive validity of the P set. If a complete set of P exists in G_place, it means that the cell library to be placed has covered all critical cells in the logic synthesis stage, satisfying the basic premise of "no missing core cells". Subsequent verification (redundant nodes, format compatibility) can proceed normally. If a set of P does not exist in G_place (e.g., "DFF_core" is missing from S or the cell attributes in P do not match S), it is directly determined that "initial cells are missing or incomplete"—because the absence of critical cells will prevent subsequent placement from realizing the core functions of the chip, and continuing the process will result in an invalid design. Therefore, attribute matching is terminated and a warning is triggered to guide the priority supplementation of critical cells and avoid rework later.

[0029] In some specific embodiments, the step of determining whether the unit library diagram to be laid out is incomplete or missing units based on the node set of the key logical units of the unit library diagram in the synthesis stage, and terminating attribute matching and issuing a warning signal when the unit library diagram to be laid out is incomplete or missing units, further includes: When it is determined that the initial unit library diagram to be laid out is incomplete, the details of the missing units are obtained according to the node set S and the node set P, and it is identified whether there is a library file in the preset resource library that matches the details of the missing units. When a library file matching the missing unit details exists in the preset resource library, the library diagram of the unit to be laid out is regenerated, and it is determined whether the node set P exists in the library diagram of the unit to be laid out. When there is no library file in the preset resource library that matches the missing unit details, the library diagram of the unit to be laid out is determined to be incomplete due to missing units, the attribute matching is terminated, and a warning signal is issued.

[0030] It should be understood that when the cell placement library diagram (G_place) is initially determined to be incomplete, the system automatically compares the key set S (key cells in the synthesis stage) with P (corresponding cells to be placed) to generate a detailed list of missing cells, including the name, functional description, and process / version requirements of the missing cells (e.g., "DFF_core, 7nm_N7H process, v1.2 version"), providing accurate retrieval basis for subsequent supplementation. Based on the missing details, the system searches the preset resource library (which stores various compatible cell library files) and uses a dual matching of "cell name + attribute tag" (e.g., name matches and process / version compatibility) to determine if there are any supplementable library files. This step aims to automatically repair the missing information using existing resources, reducing manual intervention. If a matching library file exists in the resource library, the system automatically loads the file, regenerates G_place, and checks the completeness of the P set a second time—if the supplemented P set exists (covering all S cells), the cell is considered complete, and the process continues; if it is still missing after supplementation (e.g., resource library file version mismatch causes some cells to be incompatible), the missing cell is confirmed to be irreparable. When the resource library has no matching file or the secondary verification is still missing, the system determines that the unit is "missing or incomplete", terminates the subsequent attribute matching, and issues a corresponding warning signal according to the importance of the missing unit (such as the proportion of key time sequence units). This ensures that core errors are handled first, and also lowers the verification threshold and improves the fault tolerance of the process through an automated supplementation mechanism.

[0031] In some specific embodiments, when a library file matching the missing unit details exists in the preset resource library, the process of regenerating the unit library diagram to be laid out, and determining whether the node set P exists in the unit library diagram to be laid out, includes: When the layout unit library diagram is regenerated, and the node set P exists in the layout unit library diagram, it is determined that the layout unit library diagram is complete. When the layout unit library diagram is regenerated, and the node set P does not exist in the layout unit library diagram, it is determined that the layout unit library diagram is incomplete due to missing units, attribute matching is terminated, and a warning signal is issued.

[0032] In some specific embodiments, the step of determining whether the unit library diagram to be laid out is incomplete or missing units based on the node set of the key logical units of the unit library diagram in the synthesis stage, and terminating attribute matching and issuing a warning signal when the unit library diagram to be laid out is incomplete or missing units, further includes: When the unit library diagram to be laid out is incomplete due to missing units, and the total number of missing units with a preset weight in the missing unit details is greater than or equal to a preset missing threshold, a first warning signal is issued. When the unit library diagram to be laid out is incomplete due to missing units, and the total number of missing units with a preset weight in the missing unit details is less than a preset missing threshold, a second warning signal is issued.

[0033] It should be understood that the system first presets "functional and timing weights" for each unit in the key unit set S of the synthesis stage - assigning values ​​based on the degree of influence of the unit on the core functions of the chip (such as arithmetic and storage) and timing performance (for example, units that directly determine the implementation of chip functions, such as timing path core registers and main arithmetic AND gates, are given high weights; non-core units such as auxiliary buffer units are given low weights), thus clarifying "which missing units will cause serious risks".

[0034] When the cell placement library (G_place) is determined to be incomplete due to missing cells, the system first filters out high-risk missing cells with a "weight greater than a preset value" from the missing cell details and counts their total number. Then, this total number is compared with a preset missing threshold (set according to chip design safety standards, such as "a serious warning is triggered if ≥3 high-risk cells are missing"). For small-scale chips, the total number of critical cells is small (e.g., only core registers and basic operation units), and the absence of one high-risk cell (e.g., the main clock register) may cause the entire logic timing to break, so the threshold is strictly controlled at 1-2. For large-scale chips, the number of critical cells is large (e.g., containing thousands of timing path registers), and a small number of missing cells (e.g., 3 high-risk cells in non-core paths) can be compensated for by subsequent timing optimization, so the threshold can be relaxed to 3-5, but exceeding 5 will still significantly increase the risk of functional failure. This comparison distinguishes between two risk levels. If the total number of high-risk missing units is greater than or equal to the preset threshold, it indicates that the missing units have seriously threatened the core functions and timing reliability of the chip (e.g., missing multiple critical registers will cause timing path breaks), and are judged as "high-risk missing units". If the total number of high-risk missing units is less than the preset threshold, it indicates that the missing units only involve a small number of non-core units (e.g., missing 1 auxiliary buffer unit), and have a limited impact on the core functions, and are judged as "low-risk missing units".

[0035] Corresponding warning signals are output for different risk levels: First warning signal (high risk): A strong reminder is used (e.g., a pop-up window forcibly blocking the process, a red warning icon), clearly indicating the name and impact of the high-risk missing unit (e.g., "Missing 3 core registers will lead to timing violations"), forcing designers to prioritize supplementing high-risk units to avoid invalid design from continuing the process. Second warning signal (low risk): A weak reminder is used (e.g., a sidebar prompt, a yellow icon), only informing about the missing information (e.g., "Missing 1 auxiliary buffer unit, which can be supplemented later"), allowing designers to choose "continue verification first, and supplement later," balancing risk control and design efficiency, and adapting to flexible needs in different scenarios.

[0036] In some specific embodiments, when the unit library diagram to be laid out is complete, it is determined whether there are redundant nodes in the unit library diagram to be laid out based on the node set of the key logic units in the synthesis stage unit library diagram. When there are redundant nodes in the unit library diagram to be laid out, it is determined whether to issue a redundant unit warning, including: If there are no redundant nodes in the node set of the unit library diagram to be laid out that exceed the range of the node set of the unit library diagram in the synthesis stage, it is determined that the redundant unit warning will not be issued. If there are redundant nodes in the node set of the unit library diagram to be laid out that exceed the range of the node set of the unit library diagram in the synthesis stage, and the total number of redundant nodes is less than or equal to a preset threshold, it is determined that the redundant unit warning will not be issued. When there are redundant nodes in the node set of the unit library diagram to be laid out that exceed the range of the node set of the unit library diagram in the synthesis stage, and the total number of redundant nodes is greater than a preset threshold, a redundancy warning is issued.

[0037] It should be understood that, based on the set of critical nodes S in the synthesis stage cell library diagram (G_synth), nodes "beyond the range of S" in the cell library diagram to be placed (G_place) are defined as redundant nodes—these nodes do not appear in the critical cell list of the logic synthesis stage and are not necessary for the implementation of the chip's core functions (such as additional test cells, spare buffers, etc.). This definition method clarifies the criteria for judging "redundancy" and avoids misjudging necessary cells as redundant.

[0038] Set a preset threshold (e.g., "total number of redundant nodes ≤ 5") as the warning trigger point, and distinguish the scenario based on the comparison between the total number of redundant nodes and the threshold: When G_place has no redundant nodes (completely matches the S range) or the total number of redundant nodes is less than or equal to the threshold: it is judged as "acceptable slight redundancy" - a small number of redundant nodes may be spare units reserved by the designer for layout flexibility, which usually will not significantly increase the computational load of the layout tool or cause design chaos, so no warning is needed; When the total number of redundant nodes exceeds the threshold, it is judged as "excessive redundancy" - a large number of redundant nodes will occupy the memory resources of the layout tool, prolong the netlist parsing time, and may even introduce functional conflict units (such as functional units of different processes) due to misoperation, which will substantially interfere with the subsequent layout process.

[0039] Warning signals are only issued for scenarios with "excessive redundancy". The core purpose is to prompt designers to clean up invalid nodes. When no warning is issued, the process proceeds normally, taking into account design flexibility (allowing a small number of spare units to exist).

[0040] When an alert is issued, the system will mark the details of redundant nodes (such as "a total of 8 units exceeding the S range, including TEST_1, BUF_spare, etc.") to guide designers to assess the necessity of redundancy, delete nodes that have no practical use, reduce resource waste and potential risks, and ensure that the layout tool operates efficiently.

[0041] In some specific embodiments, checking whether the library file corresponding to the library diagram of the unit to be laid out meets the format specifications of the target physical layout tool and determining whether the format compatibility is passed includes: If the library file corresponding to the unit library diagram to be laid out meets the format specifications of the target physical layout tool, the format compatibility is determined to be successful. If the library file corresponding to the unit library diagram to be laid out does not meet the format specifications of the target physical layout tool, it is determined that the format compatibility fails and a third warning signal is issued.

[0042] It should be understood that the system first pre-stores the cell library format standards supported by the target physical layout tool (such as CadenceInnovus), which mainly covers three key specifications: ① file format version (such as Libertyv2.2, LEF5.8) to ensure that the tool can recognize the file structure; ② core field naming rules (such as whether the timing parameter "rise_delay" matches the tool requirements, avoiding incompatible fields such as "cell_rise"); ③ physical / attribute data format (such as the pin coordinate units in the LEF file and the recognition rules of comment characters in the Liberty file), clarifying the quantitative standards of "compliance" and providing a basis for testing.

[0043] For the original library file corresponding to the unit library diagram to be laid out, the system initiates an automated detection process: parsing the structure, field names, and data format of the library file line by line, and comparing it with the pre-stored tool format specifications. If all key specifications match (e.g., the format version is v2.2 supported by the tool, the timing field names are completely consistent, and the physical parameter units meet the requirements), the library file is determined to be readable by the tool, and the format compatibility is passed. If any item is incompatible (e.g., the format version is v1.0 not supported by the tool, or key timing fields are missing), the format compatibility is determined to be failed.

[0044] When the format compatibility is passed: it confirms that the library file can be correctly parsed by the physical layout tool, and the node features of G_place (such as process and physical attributes) can be accurately mapped to the tool operation, clearing the "format obstacle" for the subsequent graph neural network (GNN) attribute matching verification, and the process proceeds normally to the attribute matching stage; When format compatibility fails: Immediately issue a third warning signal and simultaneously generate a "Detailed Report on Format Issues" (e.g., "Liberty file version v1.0 is incompatible and needs to be upgraded to v2.1 or above; the field 'cell_rise' needs to be replaced with 'rise_delay'"). This clearly indicates the incompatibility points and the direction of correction. This not only avoids layout tools failing to parse due to format issues (e.g., inability to recognize unit physical attributes), but also reduces the time cost for designers to manually check the format through accurate warnings, ensuring that subsequent processes are based on "format-valid" library files.

[0045] In some specific embodiments, when the format compatibility is determined to be satisfactory, the step of obtaining the node-wise feature cosine similarity between the synthesis stage unit library graph and the unit library graph to be laid out based on a two-layer graph convolutional network, obtaining the mean similarity of all nodes, and determining whether the synthesis stage unit library graph and the unit library graph to be laid out match based on the mean similarity of all nodes includes: When the average similarity of all nodes is greater than or equal to a preset similarity threshold, it is determined that the integrated stage unit library map matches the unit library map to be laid out. When the average similarity of all nodes is less than a preset similarity threshold, it is determined that the integrated stage unit library map does not match the unit library map to be laid out.

[0046] It should be understood that, for the synthesized unit library graph (G_synth) and the unit library graph to be laid out (G_place) after format adaptation, the two layers of graph convolutional network (GCN) perform feature learning sequentially: The first layer of GCN focuses on the aggregation of local features of nodes: it fuses the original attributes of each node (such as process node, library file version, functional semantic label) with the attributes of adjacent nodes (connected by undirected edges with a weight of 1) to generate a local feature vector containing "unit self-attributes + features of units related to the same task". The second layer of GCN achieves global feature enhancement: based on local features, it further captures the global correlation across nodes (such as the attribute synergy of different units under the same process), and finally outputs a high-dimensional feature vector that can fully characterize the core attributes of the unit (v_s is the feature of the G_synth node, and v_p is the feature of the corresponding node of G_place).

[0047] For the one-to-one correspondence between nodes in G_synth and G_place, the similarity is calculated using the formula sim(v_s,v_p)=(v_s・v_p) / (||v_s||・||v_p||). The closer this value is to 1, the more consistent the attributes (process, version, etc.) of the two nodes are; the closer it is to 0, the greater the attribute difference (e.g., the G_synth node is a 7nm process, and the corresponding node in G_place is a 14nm process). By calculating node by node, cells with inconsistent attributes are accurately located.

[0048] Calculate the average similarity of all corresponding nodes and compare it with a preset threshold (e.g., 0.95): If the mean is greater than or equal to the threshold, it means that the vast majority of node attributes are highly consistent (such as more than 95% of the units matching the process and version). The two unit library diagrams are determined to be "matched", and the physical layout process can be safely started. If the mean is less than the threshold, it indicates that there are a large number of nodes with mismatched attributes (such as process mismatch or version conflict). The system will determine "mismatch" and automatically locate nodes with similarity less than 0.95 and output the attribute difference details (such as "DFF_core process: 7nm→14nm") to guide the designer to make corrections before proceeding, so as to avoid the layout result from failure due to attribute mismatch.

[0049] The training process of GCN: Using historical cell library data from the "Logic Synthesis-Physical Placement" stage in the EDA toolchain as the training set: Select the cell library diagram (G_synth) generated in past design tasks and the cell library diagram to be placed (G_place) as graph pairs, and label them as "Match" (the core attributes such as cell process and library file are consistent between the two graphs) or "Mismatch" (such as process mismatch or key attribute difference); The structure and features of the graph are constructed according to the file rules - the nodes are standard cells, and the node features are formed by concatenating the process node code (such as "7nm" is encoded as [1,0]) and the library file name hash code, and the weight of the undirected edges is 1.

[0050] A two-layer graph convolutional network was used as the training model. The first layer of GCN focuses on the aggregation of local features of nodes, and merges the original attributes of each node with the attributes of adjacent nodes to generate a local feature vector containing "the unit's own attributes + features of units related to the same task".

[0051] The second layer of GCN enhances global correlation (such as the attribute synergy of units under the same process) based on local features, and finally outputs a high-dimensional feature vector that can characterize the core attributes of the unit.

[0052] The loss function is designed around "node-wise feature cosine similarity": for graph pairs labeled "matched," the cosine similarity of their corresponding nodes should be as close to 1 as possible, and the mean similarity of all nodes should approach a preset matching threshold (e.g., 0.95 in the example); for graph pairs labeled "mismatched," the similarity of their corresponding nodes should be as close to 0 as possible, and the mean should be below the threshold. The training objective is to enable the model to learn the ability to accurately extract core attribute features such as process and library files from the unit library graphs, ensuring that subsequent accurate matching between two graphs can be achieved through node similarity and mean. Figure 1 To the point of being responsive.

[0053] A second embodiment of the present application provides a real-time consistency verification system for an EDA toolchain based on a graph neural network, comprising: The acquisition module is configured to acquire a list of all standard cells used by the target logic synthesis tool in the currently executed synthesis task and the core attributes of each cell. Each standard cell is a node, and all nodes in the same synthesis task are connected by undirected edges to generate a cell library diagram for the synthesis stage. The module is also configured to acquire a list of standard cells to be used before the target physical layout tool is started, as well as the process node and library file name attributes. Each standard cell is a node, and all nodes in the same synthesis task are connected by undirected edges to generate a cell library diagram to be laid out. A primary judgment module is electrically connected to the acquisition module. The primary judgment module is configured to determine whether the unit library diagram to be laid out is incomplete or missing units based on the node set of the key logical units of the integrated stage unit library diagram. When the unit library diagram to be laid out is incomplete or missing units, attribute matching is terminated and an early warning signal is issued. The secondary judgment module is electrically connected to the primary judgment module. The secondary judgment module is configured to determine whether there are redundant nodes in the unit library diagram to be laid out when the unit library diagram to be laid out is complete, based on the node set of the key logic units in the unit library diagram of the synthesis stage. When there are redundant nodes in the unit library diagram to be laid out, it is determined whether to issue a redundant unit warning. The inspection module is electrically connected to the secondary judgment module. The inspection module is configured to check whether the library file corresponding to the library diagram of the unit to be laid out meets the format specifications of the target physical layout tool, and to determine whether the format compatibility is passed. The verification module is electrically connected to the inspection module. The verification module is configured to, when the format adaptability is passed, obtain the node-wise feature cosine similarity between the synthesis stage unit library graph and the unit library graph to be laid out based on a two-layer graph convolutional network, obtain the mean similarity of all nodes, and determine whether the synthesis stage unit library graph and the unit library graph to be laid out match based on the mean similarity of all nodes.

[0054] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program goods. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program goods embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0055] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program goods according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0056] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0057] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for real-time consistency checking of a graph neural network based EDA tool chain, characterized in that, The method comprises the following steps: obtaining a list of all standard cells used by a target logic synthesis tool in a currently executed synthesis task and core attributes of each cell, each standard cell being a node, all nodes in the same synthesis task being connected by undirected edges, to generate a synthesis stage cell library graph; obtaining a list of standard cells to be used before the target physical layout tool is started and process nodes and library file name attributes, each standard cell being a node, all nodes in the same synthesis task being connected by undirected edges, to generate a cell library graph to be laid out; determining whether the cell library graph to be laid out is incomplete due to missing cells according to a node set of key logic cells of the synthesis stage cell library graph, and terminating attribute matching and issuing a warning signal when the cell library graph to be laid out is incomplete due to missing cells; when the cell library graph to be laid out is complete, determining whether there are redundant nodes in the cell library graph to be laid out according to a node set of key logic cells of the synthesis stage cell library graph, and determining whether to issue a redundant cell warning when there are redundant nodes in the cell library graph to be laid out; checking whether the library file corresponding to the cell library graph to be laid out meets the format specification of the target physical layout tool, and determining whether the format adaptability passes; when the format adaptability passes, obtaining a node-by-node feature cosine similarity between the synthesis stage cell library graph and the cell library graph to be laid out based on a two-layer graph convolution network, and obtaining an average similarity of all nodes, and determining whether the synthesis stage cell library graph and the cell library graph to be laid out match based on the average similarity of all nodes.

2. The graph neural network-based EDA toolchain real-time consistency checking method according to claim 1, characterized in that, The method of obtaining a list of all standard cells used by a target logic synthesis tool in a currently executed synthesis task and core attributes of each cell, each standard cell being a node, all nodes in the same synthesis task being connected by undirected edges, to generate a synthesis stage cell library graph; obtaining a list of standard cells to be used before the target physical layout tool is started and process nodes and library file name attributes, each standard cell being a node, all nodes in the same synthesis task being connected by undirected edges, to generate a cell library graph to be laid out, comprises: The weights of the undirected edges in the generated synthesis stage cell library graph and the generated cell library graph to be laid out are both 1.

3. The graph neural network based EDA toolchain real-time consistency checking method according to claim 2, characterized in that, The method of determining whether the cell library graph to be laid out is incomplete due to missing cells according to a node set of key logic cells of the synthesis stage cell library graph, and terminating attribute matching and issuing a warning signal when the cell library graph to be laid out is incomplete due to missing cells, comprises: presetting the node set of key logic cells of the synthesis stage cell library graph as a node set S, and presetting a node set corresponding to the node set S in the cell library graph to be laid out as a node set P; when the node set P exists in the cell library graph to be laid out, determining that the cell library graph to be laid out is complete; when the node set P does not exist in the cell library graph to be laid out, determining that the cell library graph to be laid out is initially incomplete due to missing cells.

4. The graph neural network based EDA toolchain real-time consistency checking method according to claim 3, characterized in that, The method further comprises: When it is determined that the to-be-laid-out cell library graph is initially incomplete, obtaining a missing cell detail according to the node set S and the node set P, and identifying whether a library file matching the missing cell detail exists in the preset resource library; When the library file matching the missing cell detail exists in the preset resource library, regenerating the to-be-laid-out cell library graph, and determining whether the node set P exists in the to-be-laid-out cell library graph; When the library file matching the missing cell detail does not exist in the preset resource library, determining that the to-be-laid-out cell library graph is incomplete, terminating attribute matching, and issuing a warning signal.

5. The graph neural network based EDA toolchain real-time consistency checking method according to claim 4, characterized in that, The method further comprises: When the to-be-laid-out cell library graph is complete, determining whether a redundant node exists in the to-be-laid-out cell library graph according to the node set of the key logic cell of the integrated stage cell library graph, and when the redundant node exists in the to-be-laid-out cell library graph, determining whether to issue a redundant cell warning, comprising: When no redundant node exceeding the range of the node set of the integrated stage cell library graph exists in the node set of the to-be-laid-out cell library graph, it is determined that the redundant cell warning is not issued; 6. The graph neural network based EDA toolchain real-time consistency checking method according to claim 5, characterized in that, When the redundant node exceeding the range of the node set of the integrated stage cell library graph exists in the node set of the to-be-laid-out cell library graph, and the total number of the redundant nodes is less than or equal to a preset threshold, it is determined that the redundant cell warning is not issued. The method further comprises: When the to-be-laid-out cell library graph is incomplete, and the total number of missing cells greater than a preset weight in the missing cell detail is greater than or equal to a preset missing threshold, a first warning signal is issued; 7. The graph neural network-based EDA toolchain real-time consistency checking method according to claim 6, characterized in that, When the to-be-laid-out cell library graph is incomplete, and the total number of missing cells greater than a preset weight in the missing cell detail is less than a preset missing threshold, a second warning signal is issued. The method further comprises: When the to-be-laid-out cell library graph is complete, determining whether a redundant node exists in the to-be-laid-out cell library graph according to the node set of the key logic cell of the integrated stage cell library graph, and when the redundant node exists in the to-be-laid-out cell library graph, determining whether to issue a redundant cell warning, comprising: When no redundant node exceeding the range of the node set of the integrated stage cell library graph exists in the node set of the to-be-laid-out cell library graph, it is determined that the redundant cell warning is not issued; When the redundant node exceeding the range of the node set of the integrated stage cell library graph exists in the node set of the to-be-laid-out cell library graph, and the total number of the redundant nodes is less than or equal to a preset threshold, it is determined that the redundant cell warning is not issued. When there are redundant nodes in the node set of the to-be-laid-out cell library graph that are out of the range of the node set of the synthesis stage cell library graph, and the total number of the redundant nodes is greater than a preset threshold, it is determined that the redundant cell warning is issued.

8. The graph neural network-based EDA toolchain real-time consistency checking method according to claim 7, characterized in that, The checking whether the library file corresponding to the to-be-laid-out cell library graph meets the format specification of the target physical layout tool to determine whether the format adaptability passes includes: When the library file corresponding to the to-be-laid-out cell library graph meets the format specification of the target physical layout tool, it is determined that the format adaptability passes. When the library file corresponding to the to-be-laid-out cell library graph does not meet the format specification of the target physical layout tool, it is determined that the format adaptability does not pass, and a third warning signal is issued.

9. The graph neural network-based EDA toolchain real-time consistency checking method according to claim 8, characterized in that, When it is determined that the format adaptability passes, the two-layer graph convolution network is used to obtain the node-by-node feature cosine similarity of the synthesis stage cell library graph and the to-be-laid-out cell library graph, and the average of all node similarities is obtained, and whether the synthesis stage cell library graph and the to-be-laid-out cell library graph match is determined based on the average of all node similarities, including: When the average of all node similarities is greater than or equal to a preset similarity threshold, it is determined that the synthesis stage cell library graph and the to-be-laid-out cell library graph match. When the average of all node similarities is less than a preset similarity threshold, it is determined that the synthesis stage cell library graph and the to-be-laid-out cell library graph do not match.

10. A graph neural network-based EDA toolchain real-time consistency checking system, characterized in that, The EDA tool chain real-time consistency verification method based on the graph neural network according to any one of claims 1 to 9 includes: A collection module is configured to obtain all standard cell lists and core attributes of each cell used by a target logic synthesis tool in a currently executed synthesis task, each standard cell being a node, all nodes in the same synthesis task being connected by undirected edges to generate a synthesis stage cell library graph; and obtain standard cell lists, process nodes, and library file name attributes to be used before a target physical layout tool is started, each standard cell being a node, all nodes in the same synthesis task being connected by undirected edges to generate a to-be-laid-out cell library graph. A first determination module is electrically connected to the collection module, and is configured to determine whether the to-be-laid-out cell library graph is incomplete due to missing cells according to a node set of a key logic cell of the synthesis stage cell library graph, and terminate attribute matching and issue a warning signal when the to-be-laid-out cell library graph is incomplete due to missing cells. A second determination module is electrically connected to the first determination module, and is configured to determine whether there are redundant nodes in the to-be-laid-out cell library graph according to the node set of the key logic cell of the synthesis stage cell library graph when the to-be-laid-out cell library graph is complete, and determine whether to issue a redundant cell warning when there are redundant nodes in the to-be-laid-out cell library graph. An inspection module is electrically connected to the second determination module, and is configured to check whether a library file corresponding to the to-be-laid-out cell library graph meets the format specification of the target physical layout tool to determine whether the format adaptability passes. The verification module is electrically connected with the checking module, and is configured to, when judging that the format adaptability passes, acquire a node-by-node feature cosine similarity of the integrated stage cell library graph and the to-be-laid-out cell library graph based on a two-layer graph convolution network, acquire an average of all node similarities, and judge whether the integrated stage cell library graph and the to-be-laid-out cell library graph match based on the average of all node similarities.

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