Semiconductor device radio frequency modeling method and model for silicon-on-insulator (SOI) platform

Abstract

The invention provides a semiconductor device radio frequency modeling method and model for a silicon-on-insulator (SOI) platform. The method comprises the following steps: constructing an equivalent circuit model comprising a gate / body end parasitic impedance network, an intrinsic capacitance module, a body resistance module and a substrate network module; an intrinsic capacitance parameter is extracted through a low-frequency CV test, Cg is decomposed into overlapping capacitance, depletion capacitance and accumulation capacitance, and a hyperbolic tangent function and polynomial correction are introduced; extracting parasitic resistance inductance by using layout information and square resistance; bulk resistance parameters modulated by voltage are extracted based on the high-frequency S parameters, and the body resistance is fitted by adopting an exponential function. The model provided by the invention can accurately reflect the back gate effect and the bulk resistance modulation effect of the SOI device, and shows excellent fitting precision in a wide frequency band, wide voltage and wide temperature range.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and model for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform. Background Technology

[0002] Silicon-on-Insulator (SOI) technology plays an important role in radio frequency integrated circuit design due to its superior low power consumption and high frequency performance. Unlike traditional bulk silicon processes, the wafer substrate used in SOI platforms typically has a unique three-layer structure, consisting of a top silicon layer, an insulating buried layer (usually a buried oxide BOX), and a high-resistivity substrate from top to bottom.

[0003] This unique substrate structure leads to significant differences in the physical characteristics of SOI devices compared to traditional bulk silicon devices. When building device models, directly using the polysilicon / well capacitor model of the traditional bulk silicon platform often fails to accurately describe the RF characteristics of SOI devices.

[0004] The existing technical problems mainly manifest in the following aspects:

[0005] Capacitance characteristic differences: Actual test results show that the capacitance-voltage (CV) test curves of poly / well capacitors on the SOI platform are significantly different from those of bulk silicon devices in terms of shape and inflection points, and traditional models cannot accurately fit this change.

[0006] Substrate parasitic effects: Traditional bulk silicon models fail to effectively account for the complex parasitic capacitance and resistance networks introduced by the buried insulating layer (BOX) and high-resistivity substrate, resulting in distortion of S-parameter simulations in the radio frequency band.

[0007] The bulk resistance modulation effect in SOI devices results in a thinner top silicon layer, leading to a larger and no longer constant bulk resistance, which is significantly modulated by the gate voltage. Existing models typically treat the bulk resistance as a constant, failing to reflect the nonlinear characteristics of the bulk resistance as a function of bias voltage caused by channel modulation.

[0008] Therefore, there is an urgent need for a poly / well capacitor RF model and model improvement method for SOI platforms that can accurately reflect the special structure of SOI process, precisely describe the bulk resistance modulation effect and complex parasitic parameters. Summary of the Invention

[0009] This invention provides a method for radio frequency (RF) modeling of semiconductor devices on a silicon-on-insulator (SOI) platform, an equivalent circuit model, and a simulation device. It aims to solve the technical problems that existing RF models cannot accurately reflect the special physical structure of SOI devices, cannot accurately describe the modulation effect of bulk resistance with voltage, and fail to fully account for back gate capacitance and complex substrate parasitic effects, resulting in large deviations between high-frequency simulation results and measured data over a wide frequency band and temperature range.

[0010] This invention provides a method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform, wherein the semiconductor device includes a gate conductive material and a capacitor structure formed by a well region. The method includes the following steps:

[0011] Step 1: Construct the equivalent circuit model of the semiconductor device. The equivalent circuit model includes a gate connection terminal, a body connection terminal, a gate parasitic impedance network, a body parasitic impedance network, an intrinsic capacitance module, a body resistance module, and a substrate network module. The gate connection terminal is connected to an internal gate node via the gate parasitic impedance network; the body connection terminal is connected to a body connection node via the body parasitic impedance network; the body connection node is connected to an internal body node via the body resistance module; the intrinsic capacitance module is connected between the internal gate node and the internal body node; and the substrate network module is connected between the internal body node and a reference ground.

[0012] Step 2: Obtain test data for the semiconductor device, including low-frequency capacitance-voltage data, high-frequency S-parameter data, and sheet resistance measurement data;

[0013] Step 3: Extract the model parameters of the intrinsic capacitance module based on the low-frequency capacitance-voltage data;

[0014] Step 4: Based on the layout information of the semiconductor device and the sheet resistance measurement data, determine the resistance parameters of the gate parasitic impedance network and the body parasitic impedance network, and determine the inductance parameters of the gate parasitic impedance network and the body parasitic impedance network based on the layout information and the high-frequency resonant point.

[0015] Step 5: Determine the parameters of the substrate network module based on the thickness of the buried insulating layer of the semiconductor device and the structural characteristics of the substrate network module;

[0016] Step 6: Based on the high-frequency S-parameter data, extract and fit the parameters of the volume resistance module to obtain the voltage-modulated volume resistance model parameters.

[0017] Preferably, in step one, the equivalent circuit model is specifically configured as follows:

[0018] The gate parasitic impedance network includes a gate parasitic inductance and a gate parasitic resistance connected in series;

[0019] The body-end parasitic impedance network includes a body-end parasitic inductance and a body-end parasitic resistance connected in series.

[0020] The substrate network module includes a back gate capacitor assembly, a substrate parasitic capacitance, and a substrate parasitic resistance; one end of the back gate capacitor assembly is connected to the internal node of the bulk, and the other end is connected to the substrate node; the substrate parasitic capacitance and the substrate parasitic resistance are connected in parallel between the substrate node and the reference ground;

[0021] The equivalent circuit model also includes a leakage current source connected in parallel across the intrinsic capacitor module to characterize oxide layer leakage.

[0022] Preferably, in step one, the current value Cur of the leakage current source is related to the voltage Vgibi between the gate internal node and the body internal node. The calculation relationship includes a combination of exponential terms and power functions, and includes a temperature coefficient term to correct the effect of temperature on the leakage current. The calculation relationship is: Cur ∝ Vgb × |Vgibi|^Pwr × exp(C1 × Vgibi- C2); where Vgb is the voltage between the gate connection terminal and the body connection terminal, Pwr is the power exponent parameter, and C1 and C2 are fitting constants.

[0023] Preferably, in step three, the total capacitance Cg of the intrinsic capacitance module consists of three parts: overlapping capacitance Cov, depletion capacitance Cdep, and accumulation capacitance Cac; the overlapping capacitance Cov represents the overlapping region and the gate-to-body capacitance after full depletion; the depletion capacitance Cdep represents the gate-to-body capacitance when partially depleted; and the accumulation capacitance Cac represents the gate-to-body capacitance during accumulation.

[0024] Preferably, in step three, the formula for calculating the overlapping capacitance Cov is: Cov = mult × (Cov_area × area + Cov_w × nf × 2 × w); where: mult is the device multiplication factor; area is the device area; Cov_area is the overlapping capacitance area fitting coefficient; w is the width of a single finger of the device; nf is the number of fingers of the device; and Cov_w is the overlapping capacitance width fitting coefficient.

[0025] Preferably, in step three, the calculation model of the depletion capacitance Cdep includes a hyperbolic tangent function term tanh(·) and a polynomial correction term; the mathematical model of the depletion capacitance Cdep is described as: Cdep = Scaling_Factor ×(1.0 + tanh((Vgibi - dVgb_dep) / Vgnorm_dep)) × Poly_Corr_Dep; where: Scaling_Factor is the scaling factor; Vgibi is the voltage between the gate internal node and the body internal node; dVgb_dep is the depletion region voltage offset; Vgnorm_dep is the normalization parameter; Poly_Corr_Dep is the depletion region polynomial correction term.

[0026] Preferably, in step three, the calculation model of the accumulation capacitance Cac includes a hyperbolic tangent function term tanh(·) and a polynomial correction term; the mathematical model of the accumulation capacitance Cac is described as: Cac = Scaling_Factor × (1.0 + tanh((Vgibi - dVgb_ac) / Vgnorm_ac)) × Poly_Corr_Ac; where: Vgibi is the voltage between the gate internal node and the body internal node; dVgb_ac is the voltage offset of the accumulation region; Vgnorm_ac is the normalization parameter; Poly_Corr_Ac is the polynomial correction term of the accumulation region.

[0027] Preferably, the depletion region polynomial correction term Poly_Corr_Dep is a fourth-order polynomial, and its expression is: Poly_Corr_Dep = 1 + vc1 × Vgibi + vc2 × Vgibi^2 + vc3 × Vgibi^3 + vc4 ×Vgibi^4; where vc1, vc2, vc3, and vc4 are all depletion region voltage fitting coefficients.

[0028] Preferably, the polynomial correction term Poly_Corr_Ac in the accumulation region is a fourth-order polynomial, and its expression is: Poly_Corr_Ac = 1 + vc12 × Vgibi + vc22 × Vgibi^2 + vc32 × Vgibi^3 + vc42 × Vgibi^4; where vc12, vc22, vc32, and vc42 are all voltage fitting coefficients in the accumulation region.

[0029] Preferably, the scaling factor Scaling_Factor is used to calculate the total capacitance based on the device's geometric dimensions, and its calculation formula is: Scaling_Factor = mult × (Cw × 2 × w × nf + Cl × 2 × lr + Carea × area); where: mult is the device multiplication factor; w is the width of a single finger of the device; nf is the number of fingers of the device; Cw is the capacitance fitting coefficient related to the width; lr is the device length; Cl is the capacitance fitting coefficient related to the length; area is the device area; and Carea is the capacitance fitting coefficient related to the area.

[0030] Preferably, in step three, the depletion region voltage offset dVgb_dep and the normalized parameter Vgnorm_dep include temperature-related terms; the normalized parameter Vgnorm_dep is calculated as: Vgnorm_dep = vgnorm0_dep + vgnorm_temp_dep × (temper - 25); the calculation formula for the depletion region voltage offset dVgb_dep involves minimum value operation and exponential operation, and its expression is: dVgb_dep = min(dvgb0_dep, dvgb0_dep + Delta_temp); where the temperature correction Delta_temp is expressed as: Delta_temp = dvgb_temp_dep_1 × exp(Term_Index × (temper - 25)); where the internal coefficient Term_Index of the exponential term includes a length-related term, and its expression is: Term_Index = dvgb_temp_dep_2 × (1 + lr^dvgb_temp_dep_2_lr); In the above formula: temper is the current temperature; dvgb0_dep and vgnorm0_dep are reference parameters; vgnorm_temp_dep, dvgb_temp_dep_1, and dvgb_temp_dep_2 are all temperature coefficients; lr is the device length; and dvgb_temp_dep_2_lr is the length power coefficient.

[0031] Preferably, in step three, the accumulation region voltage offset dVgb_ac and the normalized parameter Vgnorm_ac include a temperature-related term, which is proportional to the difference between the current temperature and the nominal temperature; the normalized parameter Vgnorm_ac is calculated as: Vgnorm_ac = vgnorm0_ac + vgnorm_temp_ac × (temper - 25); the accumulation region voltage offset dVgb_ac is calculated as: dVgb_ac = dvgb0_ac + dvgb_temp_ac × (temper - 25); where: temper is the current temperature; vgnorm0_ac and dvgb0_ac are reference parameters; vgnorm_temp_ac and dvgb_temp_ac are temperature coefficients.

[0032] Preferably, in step four, the gate parasitic resistance and the gate parasitic inductance include components introduced by the conductive connection structure and components introduced by the gate material.

[0033] Preferably, in step five, the thickness of the insulating buried layer is used to estimate the capacitance value of the back-gate capacitor assembly, which is set as a planar capacitor model.

[0034] Preferably, in step six, the resistance value Rb of the bulk resistor module is not a fixed value, but a variable modulated according to the voltage Vgibi between the gate internal node and the bulk internal node; the resistance value Rb is fitted using an exponential function, and its calculation formula is: Rb = rb1 × exp(Vgibi × rbv); where rb1 is a reference resistance parameter based on the device size, and rbv is a fitting coefficient; the reference resistance parameter rb1 is directly proportional to the device channel length and inversely proportional to the device width, the number of fingers, and the multiplication factor.

[0035] Another aspect of the present invention provides a radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform, the equivalent circuit model comprising:

[0036] Gate connection terminal, body connection terminal, gate parasitic impedance unit, body parasitic impedance unit, body resistance unit, intrinsic capacitance unit, and substrate network unit;

[0037] The gate connection terminal is connected to the internal gate node through the gate parasitic impedance unit;

[0038] The body connection end is connected to the internal body connection node through the body end parasitic impedance unit;

[0039] The internal body connection node is connected to the internal body node through the body resistor unit;

[0040] The intrinsic capacitor unit is connected between the internal gate node and the internal body node;

[0041] The substrate network unit is connected between the internal volume node and the reference ground.

[0042] Preferably, the substrate network unit further includes a back gate capacitor element, a substrate resistor element, and a substrate capacitor element; one end of the back gate capacitor element is connected to the internal body node, and the other end is connected to the internal substrate node; the substrate resistor element and the substrate capacitor element are connected in parallel, and one end of the parallel connection is connected to the internal substrate node, and the other end is connected to the reference ground; the back gate capacitor element is used to characterize the capacitance characteristics of the insulating buried layer in the SOI platform.

[0043] Preferably, the bulk resistance unit is configured as a variable resistance model, and its resistance value Rb is dynamically modulated according to the voltage difference Vgibi between the internal gate node and the internal bulk node; the resistance value Rb follows an exponential function relationship, and its mathematical expression includes: Rb = rb1 × exp(Vgibi × rbv); where rb1 is the reference bulk resistance under zero bias, and rbv is the bulk resistance voltage coefficient; the reference bulk resistance rb1 is directly proportional to the device channel length L and inversely proportional to the device width W, the number of fingers NF, and the multiplication factor mult.

[0044] Preferably, the total capacitance Cg of the intrinsic capacitance unit is composed of three superimposed parts: overlapping capacitance Cov, depletion capacitance Cdep, and accumulation capacitance Cac; wherein, the overlapping capacitance Cov represents a fixed capacitance component related to the device area and width; the depletion capacitance Cdep and the accumulation capacitance Cac are both nonlinear functions of the voltage difference Vgibi between the internal gate node and the internal body node; the nonlinear functions both include a hyperbolic tangent function term tanh(·), which is used to characterize the smooth transition characteristics of the capacitor in different operating regions.

[0045] Preferably, the formula for calculating the overlapping capacitance Cov is: Cov = mult × (Cov_area × area +Cov_w × nf × 2 × w); where: mult is the device multiplication factor; area is the device area; w is the width of a single finger of the device; nf is the number of fingers of the device; and Cov_area and Cov_w are fitting coefficients.

[0046] Preferably, the mathematical expression for the depletion capacitance Cdep includes: Cdep = Scaling_Factor × (1.0 + tanh((Vgibi - dVgb_dep) / Vgnorm_dep)) × Poly_Corr_Dep; where: Scaling_Factor is the scaling factor; Poly_Corr_Dep is the fourth-order polynomial correction term in the depletion region, and its expression is: Poly_Corr_Dep = 1 + vc1 × Vgibi + vc2 × Vgibi^2 + vc3 × Vgibi^3 + vc4 × Vgibi^4.

[0047] Preferably, the mathematical expression for the accumulation capacitance Cac includes: Cac = Scaling_Factor × (1.0 + tanh((Vgibi - dVgb_ac) / Vgnorm_ac)) × Poly_Corr_Ac; where: Poly_Corr_Ac is the fourth-order polynomial correction term in the accumulation region, and its expression is: Poly_Corr_Ac = 1 + vc12 × Vgibi + vc22 × Vgibi^2 + vc32 × Vgibi^3 + vc42 × Vgibi^4.

[0048] Preferably, the model further includes a leakage current source unit, which is connected in parallel with the intrinsic capacitance unit between the internal gate node and the internal body node; the current Cur generated by the leakage current source unit is related to the power function and exponential function of the voltage difference between the internal gate node and the internal body node, and includes a temperature coefficient term for correcting for temperature effects.

[0049] Preferably, the gate parasitic impedance unit includes a gate inductor and a gate resistor connected in series; the parameter values ​​of the gate inductor and the gate resistor include a first component introduced by the gate conductive connection structure and a second component introduced by the gate material itself.

[0050] Preferably, the potential at the connection point between the bulk resistance unit and the internal bulk node is jointly affected by one end of the intrinsic capacitance unit and one end of the substrate network unit, and the bulk resistance unit is used to characterize the resistance characteristics of the top semiconductor in the SOI device due to its thin thickness.

[0051] Preferably, the semiconductor device is a well capacitor structure on a silicon-on-insulator (SOI) platform; the capacitor structure specifically includes:

[0052] The insulating layer located at the bottom;

[0053] The well region located on the insulating buried layer has an N-type or P-type conductivity; the well region constitutes the body region of the capacitor structure.

[0054] Heavily doped regions located on both sides of the well region, the conductivity type of the heavily doped regions being the same as that of the well region, are used to bring out the body connection terminals;

[0055] A gate structure located above the well region is used to bring out the gate connection terminal; and

[0056] A shallow channel isolation structure located around the well region and the heavily doped region.

[0057] As described above, the RF modeling method and model for semiconductor devices on a silicon-on-insulator (SOI) platform of the present invention have the following beneficial effects:

[0058] This invention, by introducing a hyperbolic tangent function (tanh) and multi-order polynomial correction terms, can smoothly and accurately describe the transition characteristics of SOI device capacitance from the depletion region to the accumulation region or inversion region, significantly improving the fitting accuracy under wide bias conditions. It employs an exponential function to fit the modulation effect of bulk resistance with gate voltage, overcoming the limitations of the traditional constant bulk resistance model and accurately reproducing the nonlinear behavior of high-frequency S-parameters. By establishing an independent substrate network module and clearly distinguishing between bulk nodes and substrate nodes, it successfully incorporates the unique back-gate effect and complex substrate coupling of SOI devices, improving simulation accuracy over a wide frequency band. Furthermore, by introducing a leakage current model including a temperature coefficient, it achieves accurate prediction of oxide layer leakage current over a wide temperature range. Overall, this model exhibits excellent fitting accuracy over a wide frequency band, wide voltage range, and wide temperature range. Attached Figure Description

[0059] Figure 1 The diagram shown is a schematic representation of the method flow of the present invention.

[0060] Figure 2 The diagram shown is a schematic diagram of the circuit structure of the radio frequency equivalent circuit model of the present invention;

[0061] Figure 3 The diagram shows the characteristic curves of each component of the intrinsic capacitor of the present invention as a function of gate voltage.

[0062] Figure 4 The diagram shows a comparison of the capacitance-voltage characteristics fitting at different sizes and temperatures according to the present invention.

[0063] Figure 5 The diagram shows a comparison of the leakage current characteristics fitting at different temperatures according to the present invention.

[0064] Figure 6The diagram shows a high-frequency characteristic fitting of the capacitor under a specific bias as a function of frequency according to the present invention.

[0065] Figure 7 The diagram shows the fitting results of the total capacitance as a function of gate voltage in this invention.

[0066] Figure 8 The diagram shows the fitting results of the quality factor of the present invention as a function of gate voltage.

[0067] Figure 9 The diagram shows the fitting results of the real part of the resistance as a function of the gate voltage according to the present invention.

[0068] Figure 10 The diagram shows the fitting results of the capacitance value as a function of frequency according to the present invention.

[0069] Figure 11 The diagram shows the fitting results of the quality factor as a function of frequency in this invention.

[0070] Figure 12 The diagram shown is a cross-sectional view of a Poly / Nwell capacitor based on the SOI platform in an embodiment of the present invention. Detailed Implementation

[0071] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0072] like Figure 12The diagram illustrates a cross-sectional view of a semiconductor device according to an embodiment of this application. Specifically, this semiconductor device is a well capacitor based on SOI technology. The bottom of the device is an insulating buried layer (BOX), which is specifically shown as a silicon dioxide layer (SiO2) in the illustrated embodiment. In other embodiments, the insulating buried layer can also be made of silicon nitride (Si3N4), silicon oxynitride (SiON), sapphire, or other suitable low-k or high-insulating materials. A top-layer silicon active region is formed on top of the insulating buried layer. This active region is mainly composed of a central well region (Nwell in the diagram, but could also be a Pwell in other embodiments). This well region serves as the "body" of the capacitor, and its resistance characteristics correspond to the body resistance module (Rb) in the equivalent circuit model. A gate structure is disposed above the well region, with a gate oxide layer sandwiched between the gate structure and the well region, together forming the intrinsic capacitance module (Cg). To achieve low-resistance ohmic contacts in the well region, heavily doped regions (N+ in the figure, P+ if the well is a Pwell) are provided on the outer side of the well region on both sides of the gate. These two heavily doped regions are typically shorted together in the circuit connection to serve as the body connection terminal (b). Furthermore, the active region of the device is surrounded by a shallow channel isolation (STI) structure to achieve electrical isolation between devices. This specific physical structure directly determines the source of various parasitic parameters in the model: for example, the edge capacitance effect of the STI contributes to some of the edge parasitic capacitance; the geometry and doping concentration of the well region determine the magnitude of the body resistance Rb and its voltage modulation characteristics; while the thickness and dielectric constant of the bottom insulating buried layer (such as a silicon dioxide layer) are directly related to the parameter extraction of the back gate capacitor assembly (Cox) in the model.

[0073] This application provides a method for radio frequency (RF) modeling of semiconductor devices on a silicon-on-insulator (SOI) platform, wherein the semiconductor device includes a gate conductive material and a capacitor structure formed by a well region. The method includes the following steps.

[0074] like Figure 1 As shown, firstly, step one involves constructing the equivalent circuit model of the semiconductor device. The equivalent circuit model includes a gate connection terminal, a body connection terminal, a gate parasitic impedance network, a body parasitic impedance network, an intrinsic capacitance module, a body resistance module, and a substrate network module. Specifically, the gate connection terminal is connected to the internal gate node via the gate parasitic impedance network, the body connection terminal is connected to the body connection node via the body parasitic impedance network, and the body connection node is connected to the internal body node via the body resistance module. The intrinsic capacitance module is connected between the internal gate node and the internal body node. The substrate network module is connected between the internal body node and the reference ground. This architecture fully reflects the unique physical structure of SOI devices, especially by clearly distinguishing the substrate network from the body node, which helps improve the accuracy of high-frequency simulations.

[0075] In some embodiments, the specific structural configuration of the equivalent circuit model in step one is as follows: Figure 2 As shown: In the figure, the gate terminal (g) and the body terminal (b) are the external ports; the gate parasitic impedance network includes a gate parasitic inductance (Lgm) and a gate parasitic resistance (Rg) connected in series between the gate connection terminal (g) and the gate internal node (gi); the body parasitic impedance network includes a body parasitic inductance (Lbm) and a body parasitic resistance (Rbm) connected in series between the body connection terminal (b) and the body connection node (b1, shown in the figure as between nodes b1 and b2); the substrate network module includes a back gate capacitor assembly (Cox) and a substrate. Parasitic capacitance (Csub) and substrate parasitic resistance (Rsub); one end of the back gate capacitor assembly (Cox) is connected to the body internal node (bi) and the other end is connected to the substrate node (e); the substrate parasitic capacitance (Csub) and substrate parasitic resistance (Rsub) are connected in parallel between the substrate node (e) and the reference ground (sub); the intrinsic capacitance module (Cg) is connected between the gate internal node (gi) and the body internal node (bi); the equivalent circuit model also includes a leakage current source (gbc) connected in parallel across the intrinsic capacitance module (Cg) to characterize oxide leakage.

[0076] The gate conductive material can be selected from polysilicon, doped polysilicon, metal gate, titanium nitride, tantalum nitride, tungsten, aluminum, copper, or alloys thereof; the well region can be formed based on N-type doped or P-type doped silicon. The silicon-on-insulator (SOI) platform can include a top silicon layer, an insulating buried layer, and a high-resistivity silicon substrate, wherein the insulating buried layer material can be silicon dioxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0077] In some embodiments, in step one, the current value Cur of the leakage current source is related to the voltage Vgibi between the gate internal node and the body internal node. The calculation relationship includes a combination of exponential and power functions, and includes a temperature coefficient to correct for the effect of temperature on the leakage current. The calculation relationship is: Cur ∝ Vgb × |Vgibi|^Pwr × exp(C1 × Vgibi -C2). Where Vgb is the voltage between the gate connection and the body connection, Pwr is the power exponent parameter, and C1 and C2 are fitting constants.

[0078] The specific calculation formula can be expressed as: cur = mult * v(g,b) * pwr(abs(v(gi,bi)),gcie) * (gcarc * area * exp(gcevgc * v(gi,bi) - gcetc * pwr(tox, gcete))) * 2* (1 + (temper - 25) * igg_tc). Where mult is the device multiplication factor, v(g,b) is the voltage between the gate and body terminals, pwr represents exponentiation, abs represents taking the absolute value, v(gi,bi) is the voltage between the gate internal node and the body internal node, gcie is the exponent parameter, gcarc is the leakage current area fitting coefficient, area is the device area, exp represents exponentiation, gcevgc is the voltage exponent coefficient, gcetc is the thickness exponent coefficient, tox is the oxide layer thickness, gcete is the thickness exponent, temper is the current temperature, and igg_tc is the leakage current temperature coefficient. By introducing a combination of power and exponential functions, this model can more accurately fit the quantum tunneling effect of the ultrathin gate oxide layer under different voltage biases, thus providing accurate DC leakage current prediction over a wide voltage range.

[0079] Figure 5 This figure shows a comparison of the simulated leakage current (solid line) and the measured leakage current (point) as a function of the gate voltage Vg at different temperatures. The results are displayed from top to bottom under three temperature conditions: -50°C, 25°C, and 150°C. The horizontal axis represents the gate voltage Vg (unit: volts V), and the vertical axis represents the leakage current I12 (unit: amperes A, logarithmic scale). Figure 5 As shown, under different temperature environments, the leakage current curves (blue solid lines) calculated by the model of this application and the measured data (dark blue dots) maintain a high degree of consistency throughout the voltage scan range (especially the high voltage leakage region), which verifies the accuracy of the temperature coefficient term and the combination of exponential / power functions in the model, and proves that the model can accurately describe the oxide layer leakage characteristics over a wide temperature range.

[0080] Step 2: Acquire test data for the semiconductor device. This data includes low-frequency capacitance-voltage data, high-frequency S-parameter data, and sheet resistance measurement data. Data acquisition can be performed using a vector network analyzer (VNA), an LCR meter, and a semiconductor parameter analyzer. For high-frequency S-parameters, the test frequency range can cover from several megahertz to tens of gigahertz. Sheet resistance measurement can be performed using the four-probe method or a transmission line model structure.

[0081] Figure 6This paper presents the fitting results of the high-frequency characteristics of the device capacitance as a function of frequency under specific DC bias conditions. The horizontal axis represents frequency (freq, in Hertz, logarithmic scale, ranging from 1E+8 to 1E+11 Hz), and the vertical axis represents capacitance (C12.m, in Farads F). Different colored dots correspond to different gate bias voltages (Vg) (-3.000V to 3.000V), with triangles representing measured data points. The results show that the model proposed in this application can effectively track the measured capacitance decay characteristics with frequency in the high-frequency range (up to tens of GHz), especially accurately capturing the complex impedance frequency response caused by the interaction of bulk resistance Rb, back-gate capacitance Cox, and substrate parasitic network Csub / Rsub, thus verifying the effectiveness of the model in high-frequency RF applications.

[0082] Figure 10 and Figure 11 The fitting results of capacitance value C12 and quality factor Q12 under different biases over a wide bandwidth are further presented. Figure 10 This is a curve showing the change of capacitance C12 with frequency freq. Figure 11 The graph shows the quality factor Q12 as a function of frequency freq (logarithmic scale). Different colors in the two graphs represent different gate biases Vg (from -3.000V to 3.000V). It can be seen that even under complex operating conditions with both low and high biases, the model output (solid line) maintains a high degree of agreement with the broadband high-frequency measured data (triangular scatter plot), especially... Figure 11 As shown in the Q-value decay trend with frequency, the model successfully predicted the high-frequency loss characteristics, proving the accuracy of the bulk resistance and parasitic impedance network modeling.

[0083] Step 3: Extract model parameters of the intrinsic capacitance module based on low-frequency capacitance-voltage data.

[0084] In some embodiments, in step three, the total capacitance Cg of the intrinsic capacitance module consists of three parts: overlapping capacitance Cov, depletion capacitance Cdep, and accumulation capacitance Cac. Overlapping capacitance Cov represents the gate-to-body capacitance in the overlapping region and after full depletion; depletion capacitance Cdep represents the gate-to-body capacitance during partial depletion; and accumulation capacitance Cac represents the gate-to-body capacitance during accumulation. This region-based modeling method clearly decouples the physical mechanisms of the capacitor under different operating modes, facilitating parameter adjustment.

[0085] Figure 3 The graph shows the relationship between the three components of intrinsic capacitance Cg (Cov, Cdep, and Cac) and gate voltage Vg; the horizontal axis represents the gate voltage Vg (unit: volts V), and the vertical axis represents the capacitance value (unit: farads F); the dark blue dotted lines in the graph represent the measured data points of the total intrinsic capacitance. Figure 3 As shown, the blue solid line represents the overlap capacitance Cov, which is approximately constant across the entire voltage range and is mainly determined by the overlap area between the gate and the source / drain regions and the body region. The green solid line represents the depletion capacitance Cdep, which increases slightly with increasing voltage at lower gate voltages (negative bias region), exhibiting characteristics of partial depletion, and then tends to saturate. The yellow solid line represents the accumulation capacitance Cac, which rises rapidly and dominates at higher gate voltages (positive bias region), indicating that the device has entered the accumulation region. By decomposing the total capacitance Cg into these three independently varying curves and fitting them separately, the nonlinear trend of the dark blue measured data points can be reproduced with extremely high accuracy.

[0086] Figure 4 The figure demonstrates the fitting results of the model to the capacitance-voltage (CV) characteristics under different sizes and temperatures. The top row of charts corresponds to device size parameters W=10.00µm, L=0.2500µm; the bottom row corresponds to device size parameters W=60.00µm, L=60.00µm. The charts cover different test temperatures: -50°C, 25°C, and 150°C. The solid blue line in the figure represents the simulation curve of the model, and the dark blue scatter points represent the measured data. The comparison results clearly show that, regardless of whether the device is small or large, and regardless of whether it is at low temperature (-50°C), room temperature (25°C), or high temperature (150°C), the simulation curve of this model highly overlaps with the measured CV data, especially in the depletion-accumulation transition region where the capacitance value changes drastically, demonstrating excellent fitting accuracy.

[0087] Figure 7 This demonstrates the model's fit to the total capacitance C12 over a finer gate voltage scan range (Vg from -3V to 3V). The horizontal axis represents the gate voltage vg [E+0], and the vertical axis represents the simulated capacitance value C12 (C12sim [E-15]). The magenta solid line represents the model's simulation results, and the yellow triangles represent measured data points. It can be seen that the model reproduces the complete S-shaped curve of capacitance change with gate voltage from the inversion region, depletion region, weak inversion region to strong accumulation region. The model shows a high degree of agreement across the flat region, rising edge, and saturation region.

[0088] In some embodiments, in step three, the formula for calculating the overlapping capacitance Cov is: Cov = mult × (Cov_area × area + Cov_w × nf × 2 × w). Where: mult is the device multiplication factor; area is the device area; Cov_area is the overlapping capacitance area fitting coefficient; w is the width of a single finger of the device; nf is the number of fingers of the device; and Cov_w is the overlapping capacitance width fitting coefficient.

[0089] In some embodiments, in step three, the calculation model of the depletion capacitance Cdep includes a hyperbolic tangent function term tanh(·) and a polynomial correction term; the mathematical model of the depletion capacitance Cdep is described as: Cdep = Scaling_Factor × (1.0 + tanh((Vgibi - dVgb_dep) / Vgnorm_dep)) × Poly_Corr_Dep. Where: Scaling_Factor is the scaling factor; Vgibi is the voltage between the gate internal node and the body internal node; dVgb_dep is the depletion region voltage offset; Vgnorm_dep is the normalization parameter; and Poly_Corr_Dep is the depletion region polynomial correction term.

[0090] In some embodiments, the depletion region polynomial correction term Poly_Corr_Dep is a fourth-order polynomial, expressed as: Poly_Corr_Dep = 1 + vc1 × Vgibi + vc2 × Vgibi^2 + vc3 × Vgibi^3 + vc4 × Vgibi^4. Where vc1, vc2, vc3, and vc4 are all depletion region voltage fitting coefficients.

[0091] In some embodiments, in step three, the depletion region voltage offset dVgb_dep and the normalization parameter Vgnorm_dep include temperature-related terms; the normalization parameter Vgnorm_dep is calculated as follows: Vgnorm_dep = vgnorm0_dep + vgnorm_temp_dep × (temper - 25). The calculation formula for the depletion region voltage offset dVgb_dep involves minimum value operation and exponential operation, and its expression is: dVgb_dep = min(dvgb0_dep, dvgb0_dep + Delta_temp). The expression for the temperature correction Delta_temp is: Delta_temp = dvgb_temp_dep_1 × exp(Term_Index × (temper - 25)). The exponential term's internal coefficient, Term_Index, includes a length-related term, expressed as: Term_Index = dvgb_temp_dep_2 × (1 + lr^dvgb_temp_dep_2_lr). In the above formula: temper is the current temperature; dvgb0_dep and vgnorm0_dep are reference parameters; vgnorm_temp_dep, dvgb_temp_dep_1, and dvgb_temp_dep_2 are all temperature coefficients; lr is the device length; and dvgb_temp_dep_2_lr is the length exponent coefficient.

[0092] In some embodiments, in step three, the calculation model of the accumulation capacitance Cac includes a hyperbolic tangent function term tanh(·) and a polynomial correction term; the mathematical model of the accumulation capacitance Cac is described as: Cac = Scaling_Factor × (1.0 + tanh((Vgibi - dVgb_ac) / Vgnorm_ac)) × Poly_Corr_Ac. Where: Vgibi is the voltage between the gate internal node and the body internal node; dVgb_ac is the voltage offset of the accumulation region; Vgnorm_ac is the normalization parameter; Poly_Corr_Ac is the polynomial correction term of the accumulation region. In some embodiments, the polynomial correction term Poly_Corr_Ac of the accumulation region is a fourth-order polynomial, and its expression is: Poly_Corr_Ac = 1 + vc12 × Vgibi + vc22 × Vgibi^2 + vc32 × Vgibi^3 + vc42 × Vgibi^4. Among them, vc12, vc22, vc32, and vc42 are all voltage fitting coefficients in the accumulation region.

[0093] In some embodiments, in step three, the accumulation region voltage offset dVgb_ac and the normalization parameter Vgnorm_ac include a temperature-related term, which is proportional to the difference between the current temperature and the nominal temperature. The normalization parameter Vgnorm_ac is calculated as follows: Vgnorm_ac = vgnorm0_ac + vgnorm_temp_ac × (temper - 25). The accumulation region voltage offset dVgb_ac is calculated as follows: dVgb_ac = dvgb0_ac + dvgb_temp_ac × (temper - 25). Where: temper is the current temperature; vgnorm0_ac and dvgb0_ac are reference parameters; vgnorm_temp_ac and dvgb_temp_ac are temperature coefficients.

[0094] In some embodiments, the scaling factor Scaling_Factor is used to calculate the total capacitance based on the device's geometry. The formula is: Scaling_Factor = mult × (Cw × 2 × w × nf + Cl × 2 × lr + Carea × area). Where: mult is the device scaling factor; w is the width of a single finger; nf is the number of fingers; Cw is the capacitance fitting coefficient related to width; lr is the device length; Cl is the capacitance fitting coefficient related to length; area is the device area; and Carea is the capacitance fitting coefficient related to area. Introducing the hyperbolic tangent function (tanh) smoothly describes the transition characteristics of capacitance from the depletion region to the accumulation region or inversion region, avoiding the discontinuities of piecewise functions at connection points, thereby improving simulation convergence. Simultaneously, in conjunction with a fourth-order polynomial correction term, it can accurately fit the second-order effects that deviate from the ideal CV curve in actual processes.

[0095] Step 4: Based on the layout information of the semiconductor device and the sheet resistance measurement data, determine the resistance parameters of the gate parasitic impedance network and the body parasitic impedance network, and determine the inductance parameters of the gate parasitic impedance network and the body parasitic impedance network based on the layout information and the high-frequency resonant point.

[0096] In some embodiments, in step four, the gate parasitic resistance and gate parasitic inductance include components introduced by the conductive interconnect structure and components introduced by the gate material. This step considers not only the impedance of the conventional gate material itself but also the parasitic effects introduced by the metal interconnects, which is of great significance for modeling the interconnect delay effects that are becoming increasingly prominent as process nodes shrink.

[0097] Figure 8 This describes the variation of the quality factor Q12 with the gate voltage Vg at high frequencies. The horizontal axis of the figure represents the gate voltage Vg, and the vertical axis represents the simulated quality factor Q12 (Q12sim). The magenta solid line represents the model simulation, and the yellow triangles represent the measured points. Figure 8 As shown, the model achieves a good fit not only in capacitance but also in Q value, which reflects losses, especially in the trough region near -2V and the transition region near 0V. The model curve accurately tracks the non-monotonic variation characteristics of the measured data.

[0098] Figure 9 The figure further illustrates the fitting of the real impedance (resistance component) Rm Rsim with the gate voltage. As can be seen from the figure, as the gate voltage increases from negative to positive, both the real part of the resistance in the model (magenta line) and the measured value (yellow triangle) show a trend of rapidly decreasing from high resistance and then leveling off, accurately reflecting the physical nature of the change in channel resistance / bulk resistance with bias.

[0099] Step 5: Determine the parameters of the substrate network module based on the thickness of the buried insulating layer of the semiconductor device and the structural characteristics of the substrate network module.

[0100] In some embodiments, in step five, the thickness of the buried insulating layer is used to estimate the capacitance value of the back-gate capacitor assembly, which is set as a planar capacitor model. Simplifying the back-gate capacitor to a planar capacitor model greatly reduces computational complexity while ensuring accuracy. The substrate type can be a standard silicon substrate or a high-resistivity substrate optimized for radio frequency. For different substrate types, the extraction parameters of substrate parasitic resistance and capacitance can be fine-tuned based on measured S-parameters.

[0101] Step 6: Based on the high-frequency S-parameter data, extract and fit the parameters of the volume resistance module to obtain the parameters of the voltage-modulated volume resistance model.

[0102] In some embodiments, in step six, the resistance Rb of the bulk resistance module is not a fixed value, but a variable modulated according to the voltage Vgibi between the gate internal node and the bulk internal node. The resistance Rb is fitted using an exponential function, and its calculation formula is: Rb = rb1 × exp(Vgibi × rbv). Here, rb1 is a reference resistance parameter based on the device size, and rbv is the fitting coefficient. The reference resistance parameter rb1 is directly proportional to the device channel length and inversely proportional to the device width, the number of fingers, and the multiplication factor. Unlike traditional bulk silicon models, SOI devices, due to their thinner top silicon layer, are significantly modulated by the gate bias voltage. By introducing an exponential function to fit the change in bulk resistance with voltage, the nonlinear behavior of the S-parameters at high frequencies can be accurately reproduced, thereby significantly improving the model's accuracy over a wide bandwidth.

[0103] This application also provides a radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform. The equivalent circuit model includes: a gate connection terminal, a body connection terminal, gate parasitic impedance units, body parasitic impedance units, body resistance units, intrinsic capacitance units, and a substrate network unit. The gate connection terminal is connected to an internal gate node via gate parasitic impedance units; the body connection terminal is connected to an internal body connection node via body parasitic impedance units; the internal body connection node is connected to an internal body node via body resistance units; the intrinsic capacitance unit is connected between the internal gate node and the internal body node; and the substrate network unit is connected between the internal body node and a reference ground. This model architecture directly corresponds to the aforementioned modeling method and, when implemented in a hardware description language (such as Verilog-A) or circuit simulation software, can provide a netlist description highly consistent with the actual physical structure.

[0104] In some embodiments, the substrate network unit further includes a back-gate capacitor element, a substrate resistor element, and a substrate capacitor element; one end of the back-gate capacitor element is connected to an internal body node, and the other end is connected to an internal substrate node; the substrate resistor element and the substrate capacitor element are connected in parallel, with one end of the parallel connection connected to an internal substrate node and the other end connected to a reference ground; the back-gate capacitor element is used to characterize the capacitance characteristics of the insulating buried layer in the SOI platform. By introducing the back-gate capacitor element, the model successfully captures the back-gate effect unique to SOI devices, which is particularly crucial for threshold voltage drift prediction and substrate noise coupling analysis of ultra-thin body SOI devices.

[0105] In some embodiments, the bulk resistance unit is configured as a variable resistance model, with its resistance Rb dynamically modulated according to the voltage difference Vgibi between the internal gate node and the internal bulk node. The resistance Rb follows an exponential function relationship, and its mathematical expression includes: Rb = rb1 × exp(Vgibi × rbv). Here, rb1 is the reference bulk resistance at zero bias, and rbv is the bulk resistance voltage coefficient. The reference bulk resistance rb1 is directly proportional to the device channel length L and inversely proportional to the device width W, the number of fingers NF, and the multiplication factor mult. The dynamically modulated bulk resistance model breaks the limitations of the traditional constant resistance model, accurately simulating the effective bulk resistance fluctuations caused by changes in the depletion layer width under different bias states, thus exhibiting better convergence and accuracy when simulating large-signal RF characteristics.

[0106] In some embodiments, the total capacitance Cg of the intrinsic capacitance cell is composed of three superimposed parts: overlapping capacitance Cov, depletion capacitance Cdep, and accumulation capacitance Cac. Among them, the overlapping capacitance Cov represents the fixed capacitance component related to the device area and width; the depletion capacitance Cdep and the accumulation capacitance Cac are both nonlinear functions of the voltage difference Vgibi between the internal gate node and the internal body node; the nonlinear functions both include the hyperbolic tangent function term tanh(·), which is used to characterize the smooth transition characteristics of the capacitor in different operating regions.

[0107] In some embodiments, the overlapping capacitance Cov is calculated as follows: Cov = mult × (Cov_area ×area + Cov_w × nf × 2 × w). Where: mult is the device multiplication factor; area is the device area; w is the width of a single finger; nf is the number of fingers; Cov_area and Cov_w are fitting coefficients. In some embodiments, the depletion capacitance Cdep is mathematically expressed as: Cdep = Scaling_Factor × (1.0 + tanh((Vgibi - dVgb_dep) / Vgnorm_dep)) × Poly_Corr_Dep. Where: Scaling_Factor is the scaling factor; Poly_Corr_Dep is the fourth-order polynomial correction term for the depletion region, expressed as: Poly_Corr_Dep = 1 + vc1 × Vgibi + vc2 × Vgibi^2 + vc3 × Vgibi^3 + vc4 × Vgibi^4.

[0108] In some embodiments, the mathematical expression for the accumulation capacitance Cac includes: Cac = Scaling_Factor ×(1.0 + tanh((Vgibi - dVgb_ac) / Vgnorm_ac)) × Poly_Corr_Ac. Where: Poly_Corr_Ac is the fourth-order polynomial correction term in the accumulation region, and its expression is: Poly_Corr_Ac = 1 + vc1² × Vgibi + vc2² × Vgibi² + vc3² × Vgibi³ + vc4² × Vgibi⁴.

[0109] In some embodiments, the model further includes a leakage current source unit connected in parallel with the intrinsic capacitance unit between the internal gate node and the internal body node. The current Cur generated by the leakage current source unit is related to the power function and exponential function of the voltage difference between the internal gate node and the internal body node, and includes a temperature coefficient term to correct for temperature effects. The integrated leakage current source enables the model to be used not only for RF AC analysis, but also for DC power consumption assessment and reliability analysis, especially providing the necessary simulation capabilities for the significant gate tunneling current in deep submicron processes.

[0110] In some embodiments, the gate parasitic impedance unit includes a gate inductor and a gate resistor connected in series; the parameter values ​​of the gate inductor and the gate resistor include a first component introduced by the gate conductive connection structure and a second component introduced by the gate material itself. Refining the extraction model of the gate parasitic parameters allows simulation results to reflect the impact of layout and routing on device performance, providing guidance for layout optimization.

[0111] In some embodiments, the potential at the connection point between the bulk resistance unit and the internal bulk node is jointly influenced by one end of the intrinsic capacitance unit and one end of the substrate network unit, and the bulk resistance unit is used to characterize the resistance characteristics of the top semiconductor layer in the SOI device due to its thinness. This model correctly handles the floating characteristics of the bulk node potential, which is one of the core features that distinguishes SOI devices from bulk silicon devices, ensuring that the model can correctly reflect historical effects and self-heating effects in transient simulations.

[0112] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0113] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform, characterized in that, The semiconductor device includes a gate conductive material and a capacitor structure formed by a well region, comprising at least: Step 1: Construct the equivalent circuit model of the semiconductor device. The equivalent circuit model includes a gate connection terminal, a body connection terminal, a gate parasitic impedance network, a body parasitic impedance network, an intrinsic capacitance module, a body resistance module, and a substrate network module. The gate connection terminal is connected to an internal gate node via the gate parasitic impedance network; the body connection terminal is connected to a body connection node via the body parasitic impedance network; the body connection node is connected to an internal body node via the body resistance module; the intrinsic capacitance module is connected between the internal gate node and the internal body node; and the substrate network module is connected between the internal body node and a reference ground. Step 2: Obtain test data for the semiconductor device, including low-frequency capacitance-voltage data, high-frequency S-parameter data, and sheet resistance measurement data; Step 3: Extract the model parameters of the intrinsic capacitance module based on the low-frequency capacitance-voltage data; Step 4: Based on the layout information of the semiconductor device and the sheet resistance measurement data, determine the resistance parameters of the gate parasitic impedance network and the body parasitic impedance network, and determine the inductance parameters of the gate parasitic impedance network and the body parasitic impedance network based on the layout information and the high-frequency resonant point. Step 5: Determine the parameters of the substrate network module based on the thickness of the buried insulating layer of the semiconductor device and the structural characteristics of the substrate network module; Step 6: Based on the high-frequency S-parameter data, extract and fit the parameters of the volume resistance module to obtain the voltage-modulated volume resistance model parameters.

2. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 1, characterized in that: In step one, the equivalent circuit model is specifically configured as follows: The gate parasitic impedance network includes a gate parasitic inductance and a gate parasitic resistance connected in series; The body-end parasitic impedance network includes a body-end parasitic inductance and a body-end parasitic resistance connected in series. The substrate network module includes a back gate capacitor assembly, a substrate parasitic capacitance, and a substrate parasitic resistance; one end of the back gate capacitor assembly is connected to the internal node of the bulk, and the other end is connected to the substrate node; the substrate parasitic capacitance and the substrate parasitic resistance are connected in parallel between the substrate node and the reference ground; The equivalent circuit model also includes a leakage current source connected in parallel across the intrinsic capacitor module to characterize oxide layer leakage.

3. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 2, characterized in that: In step one, the leakage current source current value Cur is related to the voltage Vgibi between the gate internal node and the body internal node. Its calculation relationship includes a combination of exponential and power functions, and incorporates a temperature coefficient to correct for the effect of temperature on the leakage current. The calculation relationship is as follows: Cur ∝ Vgb × |Vgibi|^Pwr × exp(C1 × Vgibi - C2); Where Vgb is the voltage between the gate connection and the body connection, Pwr is the power exponent parameter, and C1 and C2 are fitting constants.

4. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 1, characterized in that: In step three, the total capacitance Cg of the intrinsic capacitance module consists of three parts: the overlap capacitance Cov, the depletion capacitance Cdep, and the accumulation capacitance Cac. The overlapping capacitance Cov represents the overlapping region and the gate-to-body capacitance after full depletion. The depletion capacitance Cdep represents the gate-to-body capacitance when partially depleted. The accumulation capacitance Cac represents the gate-to-body capacitance during accumulation.

5. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 4, characterized in that: In step three, the formula for calculating the overlapping capacitance Cov is: Cov = mult × (Cov_area × area + Cov_w × nf × 2 × w); in: mult is the device multiplication factor; area is the device area, and Cov_area is the fitting coefficient for the area of ​​the overlapping capacitor. w represents the width of a single finger of the device, nf represents the number of fingers of the device, and Cov_w represents the fitting coefficient for the width of the overlapping capacitor.

6. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 4, characterized in that: In step three, the calculation model of the depletion capacitance Cdep includes a hyperbolic tangent function term tanh(·) and a polynomial correction term; the mathematical model of the depletion capacitance Cdep is described as follows: Cdep = Scaling_Factor × (1.0 + tanh((Vgibi - dVgb_dep) / Vgnorm_dep)) ×Poly_Corr_Dep; in: Scaling_Factor is the scaling factor; Vgibi is the voltage between the gate internal node and the body internal node; dVgb_dep is the voltage offset in the depletion region; Vgnorm_dep is the normalization parameter; Poly_Corr_Dep is the polynomial correction term for the depletion region.

7. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 4, characterized in that: In step three, the calculation model of the accumulated capacitance Cac includes a hyperbolic tangent function term tanh(·) and a polynomial correction term; the mathematical model of the accumulated capacitance Cac is described as follows: Cac = Scaling_Factor × (1.0 + tanh((Vgibi - dVgb_ac) / Vgnorm_ac)) ×Poly_Corr_Ac; in: Vgibi is the voltage between the gate internal node and the body internal node; dVgb_ac is the voltage offset in the accumulation region; Vgnorm_ac is the normalization parameter; Poly_Corr_Ac is the polynomial correction term in the accumulation region.

8. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 6, characterized in that: The polynomial correction term Poly_Corr_Dep in the depletion region is a fourth-order polynomial, and its expression is: Poly_Corr_Dep = 1 + vc1 × Vgibi + vc2 × Vgibi^2 + vc3 × Vgibi^3 + vc4× Vgibi^4; Among them, vc1, vc2, vc3, and vc4 are all fitting coefficients for the depletion region voltage.

9. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 7, characterized in that: The polynomial correction term Poly_Corr_Ac in the accumulation region is a fourth-order polynomial, and its expression is: Poly_Corr_Ac = 1 + vc12 × Vgibi + vc22 × Vgibi^2 + vc32 × Vgibi^3 +vc42 × Vgibi^4; Among them, vc12, vc22, vc32, and vc42 are all voltage fitting coefficients in the accumulation region.

10. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 6 or 7, characterized in that: The scaling factor is used to calculate the total capacitance based on the device's geometry, and its calculation formula is as follows: Scaling_Factor = mult × (Cw × 2 × w × nf + Cl × 2 × lr + Carea ×area); in: mult is the device multiplication factor; w is the width of a single finger of the device, nf is the number of fingers of the device, and Cw is the capacitance fitting coefficient related to the width. lr is the device length, and Cl is the capacitance fitting coefficient related to the length; area is the device area, and Carea is the capacitance fitting coefficient related to the area.

11. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 6, characterized in that: In step three, the depletion region voltage offset dVgb_dep and the normalized parameter Vgnorm_dep include temperature-related terms; The formula for calculating the normalization parameter Vgnorm_dep is as follows: Vgnorm_dep = vgnorm0_dep + vgnorm_temp_dep × (temper - 25); The calculation formula for the depletion region voltage offset dVgb_dep involves minimum value calculation and exponential calculation, and its expression is as follows: dVgb_dep = min(dvgb0_dep, dvgb0_dep + Delta_temp); The expression for the temperature correction Delta_temp is: Delta_temp = dvgb_temp_dep_1 × exp(Term_Index × (temper - 25)); The internal coefficient Term_Index of the exponent term includes a length-related term, expressed as: Term_Index = dvgb_temp_dep_2 × (1 + lr^dvgb_temp_dep_2_lr); In the above formula: temper is the current temperature; dvgb0_dep and vgnorm0_dep are reference parameters; vgnorm_temp_dep, dvgb_temp_dep_1, and dvgb_temp_dep_2 are all temperature coefficients; lr is the device length; and dvgb_temp_dep_2_lr is the length power coefficient.

12. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 7, characterized in that: In step three, the accumulation region voltage offset dVgb_ac and the normalization parameter Vgnorm_ac include a temperature-related term, which is proportional to the difference between the current temperature and the nominal temperature. The formula for calculating the normalization parameter Vgnorm_ac is as follows: Vgnorm_ac = vgnorm0_ac + vgnorm_temp_ac × (temper - 25); The formula for calculating the voltage offset dVgb_ac in the accumulation region is: dVgb_ac = dvgb0_ac + dvgb_temp_ac × (temper - 25); Where: temper is the current temperature; vgnorm0_ac and dvgb0_ac are the baseline parameters; vgnorm_temp_ac and dvgb_temp_ac are the temperature coefficients.

13. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 2, characterized in that: In step four, the gate parasitic resistance and the gate parasitic inductance include components introduced by the conductive connection structure and components introduced by the gate material.

14. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 2, characterized in that: In step five, the thickness of the insulating buried layer is used to estimate the capacitance value of the back-gate capacitor assembly, which is set as a planar capacitor model.

15. The method for radio frequency modeling of semiconductor devices on a silicon-on-insulator (SOI) platform according to claim 1, characterized in that: In step six, the resistance value Rb of the body resistor module is not a fixed value, but a variable modulated according to the voltage Vgibi between the gate internal node and the body internal node; the resistance value Rb is fitted using an exponential function, and its calculation formula is as follows: Rb = rb1 × exp(Vgibi × rbv); Wherein, rb1 is a reference resistance parameter based on device size, and rbv is a fitting coefficient; the reference resistance parameter rb1 is directly proportional to the device channel length and inversely proportional to the device width, the number of fingers, and the multiplication factor.

16. A radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform, characterized in that, The equivalent circuit model includes: Gate connection terminal, body connection terminal, gate parasitic impedance unit, body parasitic impedance unit, body resistance unit, intrinsic capacitance unit, and substrate network unit; The gate connection terminal is connected to the internal gate node through the gate parasitic impedance unit; The body connection end is connected to the internal body connection node through the body end parasitic impedance unit; The internal body connection node is connected to the internal body node through the body resistor unit; The intrinsic capacitor unit is connected between the internal gate node and the internal body node; The substrate network unit is connected between the internal volume node and the reference ground.

17. The radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform according to claim 16, characterized in that: The substrate network unit further includes a back gate capacitor element, a substrate resistor element, and a substrate capacitor element; One end of the back gate capacitor element is connected to the internal body node, and the other end is connected to the internal substrate node; The substrate resistive element and the substrate capacitor element are connected in parallel, with one end of the parallel connection connected to the internal substrate node and the other end connected to the reference ground; The back-gate capacitor element is used to characterize the capacitance characteristics of the insulating buried layer in the SOI platform.

18. The radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform according to claim 16, characterized in that: The bulk resistor unit is configured as a variable resistor model, and its resistance value Rb is dynamically modulated according to the voltage difference Vgibi between the internal gate node and the internal bulk node. The resistance value Rb follows an exponential function relationship, and its mathematical expression includes: Rb = rb1 × exp(Vgibi × rbv); Where rb1 is the reference bulk resistance under zero bias, and rbv is the bulk resistance voltage coefficient; The reference resistance rb1 is directly proportional to the device channel length L and inversely proportional to the device width W, the number of fingers NF, and the multiplication factor mult.

19. The radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform according to claim 16, characterized in that: The total capacitance value Cg of the intrinsic capacitor unit is composed of three parts: overlapping capacitance Cov, depletion capacitance Cdep, and accumulation capacitance Cac. Wherein, the overlapping capacitance Cov represents a fixed capacitance component that is related to the device area and width; Both the depletion capacitance Cdep and the accumulation capacitance Cac are nonlinear functions of the voltage difference Vgibi between the internal gate node and the internal body node. The nonlinear functions all include a hyperbolic tangent term tanh(·), which is used to characterize the smooth transition characteristics of the capacitor in different operating regions.

20. The radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform according to claim 19, characterized in that: The formula for calculating the overlapping capacitance Cov is: Cov = mult × (Cov_area × area + Cov_w × nf × 2 × w); Where: mult is the device multiplication factor; area is the device area; w is the width of a single finger of the device; nf is the number of fingers of the device; Cov_area and Cov_w are fitting coefficients.

21. The radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform according to claim 19, characterized in that: The mathematical expression for the depletion capacitance Cdep includes: Cdep = Scaling_Factor × (1.0 + tanh((Vgibi - dVgb_dep) / Vgnorm_dep)) ×Poly_Corr_Dep; in: Scaling_Factor is the scaling factor; Poly_Corr_Dep is the fourth-order polynomial correction term in the exhaustion region, and its expression is: Poly_Corr_Dep = 1 + vc1 × Vgibi + vc2 × Vgibi^2 + vc3 × Vgibi^3 + vc4 × Vgibi^4.

22. The radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform according to claim 19, characterized in that: The mathematical expression for the accumulated capacitance Cac includes: Cac = Scaling_Factor × (1.0 + tanh((Vgibi - dVgb_ac) / Vgnorm_ac)) ×Poly_Corr_Ac; in: Poly_Corr_Ac is the fourth-order polynomial correction term in the accumulation region, and its expression is: Poly_Corr_Ac = 1 + vc12 × Vgibi + vc22 × Vgibi^2 + vc32 × Vgibi^3 +vc42 × Vgibi^4.

23. The radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform according to claim 16, characterized in that: The model also includes a leakage current source unit, which is connected in parallel with the intrinsic capacitance unit between the internal gate node and the internal body node. The current Cur generated by the leakage current source unit is related to the power function and exponential function of the voltage difference between the internal gate node and the internal body node, and includes a temperature coefficient term for correcting for temperature effects.

24. The radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform according to claim 16, characterized in that: The gate parasitic impedance unit includes a gate inductor and a gate resistor connected in series; the parameter values ​​of the gate inductor and the gate resistor include a first component introduced by the gate conductive connection structure and a second component introduced by the gate material itself.

25. The radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform according to claim 16, characterized in that: The potential at the connection point between the bulk resistance unit and the internal bulk node is jointly affected by one end of the intrinsic capacitance unit and one end of the substrate network unit, and the bulk resistance unit is used to characterize the resistance characteristics of the top semiconductor in the SOI device due to its thinness.

26. The radio frequency equivalent circuit model for a semiconductor device on a silicon-on-insulator (SOI) platform according to claim 16, characterized in that: The semiconductor device is a well capacitor structure on a silicon-on-insulator (SOI) platform; the capacitor structure specifically includes: The insulating layer located at the bottom; The well region located on the insulating buried layer has an N-type or P-type conductivity; the well region constitutes the body region of the capacitor structure. Heavily doped regions located on both sides of the well region, the conductivity type of the heavily doped regions being the same as that of the well region, are used to bring out the body connection terminals; A gate structure located above the well region is used to bring out the gate connection terminal; and A shallow channel isolation structure located around the well region and the heavily doped region.

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