Gate drive circuit, display panel and display device
By employing a time-sharing current path design for the cascade module and the output module in the gate drive circuit, the load is shared by power supply signals of different voltages, which solves the problem of cascade failure caused by gate control signal delay and reduces power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-24
- Publication Date
- 2026-04-10
AI Technical Summary
The delay in the level change of the gate control signal in the gate drive circuit causes cascading failure in cascaded designs, and also results in high power consumption.
By designing the cascade module and output module, the current paths of the cascade signal and gate control signal are controlled by using time-sharing current paths, and power supply signals of different voltages are used to share the load and reduce power consumption.
The transition time of the gate control signal level change was shortened, the stage failure problem was improved, and the power consumption of the gate drive circuit was reduced.
Smart Images
Figure CN121838685A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of display, in particular to a gate driving circuit, a display panel and a display device. BACKGROUND
[0002] When the level of the gate control signal output by the gate driving sub-circuit changes, the level change speed of the gate control signal slows down with the decrease of the output capability of the output transistor in the gate driving sub-circuit, resulting in a long transition time of the level change of the gate control signal and a delay of the level change of the gate control signal. When the gate control signal is multiplexed to realize the cascade design of multiple gate driving sub-circuits, the delay of the level change of the gate control signal will cause the stage transmission failure problem due to the increase of the load corresponding to the gate control signal and the cascade accumulation effect. SUMMARY
[0003] The present application provides a gate driving circuit, a display panel and a display device, which are used to improve the stage transmission failure problem caused by the delay of the level change of the gate control signal and are beneficial to reduce the power consumption of the gate driving circuit.
[0004] The present application provides a gate driving circuit, which includes multiple cascaded gate driving sub-circuits. At least one gate driving sub-circuit includes a stage transmission module and an output module. The stage transmission module is configured to control the stage transmission output end to form a current path between the first power supply end and the second power supply end in time according to the corresponding clock signal and the corresponding start signal. The voltage of the second power supply signal supplied by the second power supply end is less than the voltage of the first power supply signal supplied by the first power supply end. The output module is electrically connected with the stage transmission module. The output module is configured to control the signal output end to form a current path between the third power supply end and the fourth power supply end in time. The voltage of the fourth power supply signal supplied by the fourth power supply end is less than the voltage of the third power supply signal supplied by the third power supply end. The start signal corresponding to the Nth gate driving sub-circuit is the start signal or the stage transmission signal output by the N-Ath gate driving sub-circuit. The voltage of the first power supply signal is less than the voltage of the third power supply signal. N≥1, A≥1, N-A>0.
[0005] The present application also provides a display panel, which includes any of the above-mentioned gate driving circuits and multiple sub-pixels. The multiple sub-pixels are electrically connected with the gate driving circuit. The multiple sub-pixels are configured to receive the corresponding gate control signal.
[0006] The present application also provides a display device, which includes any of the above-mentioned display panels and a timing controller. The timing controller is electrically connected with the gate driving circuit. The timing controller is configured to output the corresponding clock signal to the gate driving circuit.
[0007] In the technical solution, the at least one gate driving sub-circuit comprises a stage transmission module and an output module, the stage transmission module is used to control the stage transmission output end to form a current path with the first power supply end and the second power supply end at different times, thereby controlling the stage transmission signal output by the stage transmission output end. The output module is used to control the signal output end to form a current path with the third power supply end and the fourth power supply end at different times, thereby controlling the gate control signal output by the signal output end. The cascade arrangement of the plurality of gate driving sub-circuits is realized by using the stage transmission signal, the stage transmission signal is used to share the load of the gate control signal, thereby being beneficial to shortening the transition time corresponding to the level change of the gate control signal, improving the delay caused by the level change of the gate control signal, and improving the stage transmission failure caused by the delay of the level change of the gate control signal. In addition, the voltage of the first power supply signal supplied by the first power supply end is less than the voltage of the third power supply signal supplied by the third power supply end, so that the power consumption of the gate driving circuit can be reduced. BRIEF DESCRIPTION OF DRAWINGS
[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor based on the drawings shown.
[0009] Figure 1 Structure diagram of a gate driving circuit according to an example embodiment of the present disclosure;
[0010] Figure 2 Principle block diagram of a gate driving sub-circuit according to an example embodiment of the present disclosure; Figure 3 Circuit diagram of a gate driving sub-circuit according to an example embodiment of the present disclosure; Figure 4 Timing diagram corresponding to a gate driving sub-circuit according to an example embodiment of the present disclosure; Figure 5 Circuit diagram of a gate driving sub-circuit according to a comparative example embodiment; Figure 6 Timing diagram corresponding to a gate driving sub-circuit according to a comparative example embodiment; Figure 7 Structure diagram of a display panel according to an example embodiment of the present disclosure; Figure 8 Structure diagram of a display device according to an example embodiment of the present disclosure; The implementation, functional features and advantages of the embodiments of the present application will be further described with reference to the drawings. DETAILED DESCRIPTION
[0011] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort fall within the scope of the present application.
[0012] It should be noted that the electrical connection referred to in the present application can include direct connection or indirect connection. The indirect connection can include the connection between the connected modules, devices, nodes through electrical elements, wired or wireless media, etc. The electrical connection can refer to the physically objectively existing connection, or can refer to the connection established through signals.
[0013] In addition, the description such as "first", "second" and the like in the embodiments of the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited. In addition, the embodiments, implementation manners and related technical features in the present application can be combined or replaced with each other without conflict. The technical features in the present application can be applied to realize different combinations, not limited to the technical solutions formed by the combinations listed in the embodiments. The technical solutions of each embodiment can be combined with each other, but it must be based on the realization of a person of ordinary skill in the art. When the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope of the present application. "Optionally", "in some embodiments" in the present application means that the technical content introduced can be selectively set.
[0014] In addition, the description provided in the description of the background art should not be assumed to be prior art only because it is described in the description of the background art or it is associated with the description of the background art. The description of the background art can include information describing one or more aspects of the subject technology, and the description in this part does not limit the present application.
[0015] Figure 1 The structure schematic diagram of the gate drive circuit of the exemplary embodiment of the present disclosure is shown. The present application provides a gate drive circuit GDC, which includes a plurality of cascaded gate drive sub-circuits GA, each of which is configured to output a gate control signal Scan.
[0016] Figure 2A schematic diagram of a gate driving sub-circuit according to an exemplary embodiment of the present disclosure. At least one gate driving sub-circuit GA includes a stage transmission module 10 and an output module 20.
[0017] The stage transmission module 10 is configured to control a stage transmission signal Stn outputted by the stage transmission output OT1 according to a corresponding clock signal CK and a corresponding start signal STV.
[0018] In some embodiments, the stage transmission module 10 is configured to control the stage transmission signal Stn outputted by the stage transmission output OT1 according to a corresponding clock signal CK and a corresponding start signal STV by forming a current path between the stage transmission output OT1 and the first power supply end VA and the second power supply end VB in time-sharing manner, so as to realize the control of the stage transmission signal Stn outputted by the stage transmission output OT1.
[0019] Optionally, in order to make the stage transmission signal Stn have a level variation, the voltage of the second power supply signal supplied by the second power supply end VB is different from the voltage of the first power supply signal supplied by the first power supply end VA.
[0020] In some embodiments, the voltage of the second power supply signal supplied by the second power supply end VB is greater than or less than the voltage of the first power supply signal supplied by the first power supply end VA.
[0021] Optionally, the stage transmission signal Stn can be used to realize a cascade arrangement of a plurality of gate driving sub-circuits GA. That is, the corresponding start signal STV of the Nth gate driving sub-circuit GA(N) can be the initial signal stv or the (N-A)th stage transmission signal Stn(N-A) outputted by the (N-A)th gate driving sub-circuit GA(N-A).
[0022] As in some embodiments, the corresponding start signal STV of the 1st gate driving sub-circuit GA(1) is the initial signal stv, the corresponding start signal STV of the 2nd gate driving sub-circuit GA(2) is the 1st stage transmission signal Stn(1) outputted by the 1st gate driving sub-circuit GA(1); the corresponding start signal STV of the 3rd gate driving sub-circuit GA(3) is the 2nd stage transmission signal Stn(2) outputted by the 2nd gate driving sub-circuit GA(2), and so on, so as to obtain the corresponding start signal STV of each gate driving sub-circuit GA.
[0023] It is to be noted that when each gate driving sub-circuit GA includes a corresponding stage transmission module 10, the clock signals CK corresponding to the plurality of gate driving sub-circuits GA can be different.
[0024] As in some embodiments, the gate drive circuit GDC includes Z clock lines configured to transmit Z clock signals sequentially having the same phase difference therebetween. Among them, the gate drive sub-circuit GA(ZK+B) at the ZK+B level is electrically connected with the Bth clock line among the Z clock lines, so as to make the gate drive sub-circuit GA(ZK+B) at the ZK+B level receive the clock signal transmitted by the Bth clock line. Z≥2, K≥0, 1≤B≤Z. In some embodiments, Z=2, 6 or 8, etc.
[0025] As please continue to see Figure 1 Taking Z=4 as an example for illustration, the 4 clock lines include the first clock line CKL1~the fourth clock line CKL4. Among them, the first clock line CKL1 transmits the first clock signal CK1, the second clock line CKL2 transmits the second clock signal CK2, the third clock line CKL3 transmits the third clock signal CK3, and the fourth clock line CKL4 transmits the fourth clock signal CK4, sequentially having the same phase difference therebetween. The gate drive sub-circuit GA(4K+1) at the 4K+1 level is electrically connected with the first clock line CKL1, the gate drive sub-circuit GA(4K+2) at the 4K+2 level is electrically connected with the second clock line CKL2, the gate drive sub-circuit GA(4K+3) at the 4K+3 level is electrically connected with the third clock line CKL3, and the gate drive sub-circuit GA(4K+4) at the 4K+4 level is electrically connected with the fourth clock line CKL4.
[0026] It should be understood that, Figure 1 The matching design of the clock lines and the gate drive sub-circuit GA shown is only illustrative and is not used to limit the present application, and the matching design of the clock lines and the gate drive sub-circuit GA can be changed by the person skilled in the art according to different actual applications, which is allowed and included by the present application.
[0027] In addition, the clock signals transmitted by the Z clock lines are shared by the plurality of gate drive sub-circuits GA, so that at least two gate drive sub-circuits GA share the clock signal transmitted by the same clock line, which is beneficial to reduce the number of clock signals applied by the gate drive circuit GDC, and further beneficial to reduce the power consumption of the gate drive circuit GDC.
[0028] As please continue to see Figure 2 The output module 20 is electrically connected with the stage transmission module 10, and the output module 20 is configured to control the gate control signal Scan output by the signal output end OT2.
[0029] In some embodiments, the output module 20 is configured to control the signal output end OT2 to form a current path between the third power supply end VC and the fourth power supply end VD in time sharing, so as to realize the control of the gate control signal Scan output by the gate drive sub-circuit GA.
[0030] Optionally, in order to make the level of the gate control signal Scan change, the voltage of the fourth power signal supplied by the fourth power terminal VD is different from the voltage of the third power signal supplied by the third power terminal VC.
[0031] In some embodiments, the voltage of the fourth power signal supplied by the fourth power terminal VD is greater than or less than the voltage of the third power signal supplied by the third power terminal VC.
[0032] The present application outputs the stage transmission signal Stn by the stage transmission module 10, outputs the gate control signal Scan by the output module 20, and realizes the cascade arrangement of the plurality of gate drive sub-circuits GA by the stage transmission signal Stn. The stage transmission signal Stn can share the load of the gate control signal Scan, so as to shorten the transition time of the gate control signal Scan corresponding to the level change, improve the delay of the level change of the gate control signal Scan, and improve the stage transmission failure caused by the delay of the level change of the gate control signal Scan.
[0033] The stage transmission module 10 outputs the stage transmission signal Stn under the action of the corresponding clock signal CK and the corresponding start signal STV. Therefore, the stage transmission module 10 works at a high frequency with the periodic change of the clock signal CK, and has a large dynamic power consumption. The output module 20 is not directly controlled by the clock signal CK, and the level switching times of the gate control signal Scan are less. Therefore, the output module 20 can work at a low frequency. However, in order to meet the driving requirement, the output module 20 needs to control the gate control signal Scan to have strong driving capability. Therefore, in order to reduce the power consumption of the gate drive sub-circuit GA and make the gate control signal Scan output by the gate drive sub-circuit GA have strong driving capability, the voltage of the power signal used to provide a large voltage to the stage transmission module 10 can be reduced, and the voltage of the power signal used to provide a large voltage to the output module 20 can be greater than the voltage of the power signal used to provide a large voltage to the stage transmission module 10.
[0034] In order to facilitate the understanding of the present application, the voltage of the second power signal is less than the voltage of the first power signal, and the voltage of the fourth power signal is less than the voltage of the third power signal. The first power terminal VA is used to provide a power signal with a large voltage to the stage transmission module 10, and the third power terminal VC is used to provide a power signal with a large voltage to the output module 20. Therefore, the voltage of the first power signal can be less than the voltage of the third power signal, so as to reduce the corresponding dynamic power consumption of the stage transmission module 10, and make the gate control signal Scan output by the gate drive sub-circuit GA have strong driving capability.
[0035] In some embodiments, the voltage difference between the first power signal and the second power signal is smaller than the voltage difference between the third power signal and the fourth power signal, so that the level transition of the stage transfer signal Stn can be completed in a shorter time, and the rising edge of the level transition of the stage transfer signal Stn is steeper, which is beneficial to improve the delay and distortion of the level transition of the stage transfer signal Stn, thereby improving the reliability of the stage transfer.
[0036] In some embodiments, the voltage of the second power signal can be greater than or equal to the voltage of the fourth power signal, so that the voltage difference between the first power signal and the second power signal is smaller than the voltage difference between the third power signal and the fourth power signal.
[0037] In some embodiments, in order to further shorten the transition time when the stage transfer signal Stn appears level switching, and make the gate control signal Scan have a larger voltage difference change, so as to enhance the driving ability of the gate control signal Scan, the voltage of the second power signal can be greater than the voltage of the fourth power signal.
[0038] It should be understood that, with the reduction of the power consumption of the gate driving sub-circuit GA, the power consumption of the gate driving circuit GDC will also be reduced.
[0039] It should be noted that the "level transition delay of a signal" of the present application can refer to the longer transition time corresponding to the level transition of the signal from the first level to the second level, that is, the level transition delay of the signal is manifested as the signal completing the level switching in a longer time. Among them, the first level is one of high level and low level, and the second level is the other of high level and low level.
[0040] Optionally, in order to make the signal output end OT2 form a current path between the third power end VC and the fourth power end VD in time, the output module 20 can include a first output unit 201 and a second output unit 202, as shown in Figure 2 The first output unit 201 is electrically connected to the first node No1 of the gate driving sub-circuit GA of the current stage and is electrically connected to the signal output end OT2, and the first output unit 201 is configured to control the signal transmission between the third power end VC and the signal output end OT2 according to the signal of the first node No1. The second output unit 202 is electrically connected to the second node No2 of the gate driving sub-circuit GA of the current stage and is electrically connected to the signal output end OT2, and the second output unit 202 is configured to control the signal transmission between the fourth power end VD and the signal output end OT2 according to the signal of the second node No2.
[0041] Optionally, to make the stage transmission output terminal OT1 time-sharingly form a current path with the first power terminal VA and the second power terminal VB, the stage transmission module 10 can include a first stage transmission output unit 101 and a second stage transmission output unit 102, as shown in Figure 2 . The first stage transmission output unit 101 is electrically connected with the first node No1 and the stage transmission output terminal OT1, and is configured to control the signal transmission between the first power terminal VA and the stage transmission output terminal OT1 according to the signal of the first node No1. The second stage transmission output unit 102 is electrically connected with the second node No2 and the stage transmission output terminal OT1, and is configured to control the signal transmission between the second power terminal VB and the stage transmission output terminal OT1 according to the signal of the second node No2.
[0042] In some embodiments, the first output unit 201 can be made to connect the current path between the third power terminal VC and the signal output terminal OT2 at the time period when the first stage transmission output unit 101 connects the current path between the first power terminal VA and the stage transmission output terminal OT1. The second output unit 202 can be made to connect the current path between the fourth power terminal VD and the signal output terminal OT2 at the time period when the second stage transmission output unit 102 connects the current path between the second power terminal VB and the stage transmission output terminal OT1.
[0043] Optionally, to make the stage transmission output terminal OT1 time-sharingly receive the first power signal and the second power signal under the control of the signal of the first node No1 and the signal of the second node No2, and make the signal output terminal OT2 time-sharingly receive the third power signal and the fourth power signal, the potential of the first node No1 and the potential of the second node No2 can be controlled.
[0044] As in some embodiments, the stage transmission module 10 includes an input unit 103 and a first control unit 104, as shown in Figure 2 . The input unit 103 is electrically connected with the third node No3 and the second node No2 through the third node No3 of the gate drive sub-circuit GA of the current stage, and is configured to control the signal transmission between the start signal line of the transmission start signal STV and the third node No3 and the second node No2 according to the clock signal CK. The first control unit 104 is electrically connected with the third node No3 and the second node No2, and is electrically connected with the first node No1, and is configured to control the signal of the first node No1 and the signal of the second node No2 to be opposite according to the signal of the third node No3.
[0045] In some embodiments, the first control unit 104 can include a first sub-unit configured to control signal transmission between the first node No1 and the first power terminal VA according to the signal of the third node No3, and a second sub-unit configured to control signal transmission between the first node No1 and the second power terminal VB according to the signal of the third node No3, so that the signal of the first node No1 has a level variation.
[0046] In some embodiments, the time period during which the first sub-unit controls the formation of a current path between the first power terminal VA and the first node No1 does not overlap with the time period during which the second sub-unit controls the formation of a current path between the second power terminal VB and the first node No1, so as to reduce the probability of offsetting between the first power signal and the second power signal at the first node No1, thereby improving the working stability of the gate drive sub-circuit GA.
[0047] Optionally, during the time period when the first sub-unit controls the formation of a current path between the first power terminal VA and the first node No1, the first stage transmission output unit 101 disconnects the current path between the first power terminal VA and the stage transmission output terminal OT1 according to the signal of the first node No1. During the time period when the second sub-unit controls the formation of a current path between the second power terminal VB and the first node No1, the first stage transmission output unit 101 connects the current path between the first power terminal VA and the stage transmission output terminal OT1 according to the signal of the first node No1.
[0048] Optionally, during the time period when the first sub-unit controls the formation of a current path between the first power terminal VA and the first node No1, the first output unit 201 disconnects the current path between the third power terminal VC and the signal output terminal OT2 according to the signal of the first node No1. During the time period when the second sub-unit controls the formation of a current path between the second power terminal VB and the first node No1, the first output unit 201 connects the current path between the third power terminal VC and the signal output terminal OT2 according to the signal of the first node No1.
[0049] Optionally, the stage transmission module 10 can further include a second control unit 105 electrically connected with the first node No1 and the stage transmission output terminal OT1. When the second stage transmission output unit 102 connects the current path between the second power terminal VB and the stage transmission output terminal OT1, the second control unit 105 is configured to connect the current path between the second power terminal VB and the stage transmission output terminal OT1 according to the signal of the first node No1, so as to increase the number of current transmission paths between the second power terminal VB and the stage transmission output terminal OT1, accelerate the speed of voltage variation of the stage transmission signal Stn to the voltage variation of the second power signal, and facilitate the improvement of the level switching speed of the stage transmission signal Stn.
[0050] Optionally, the at least one gate driving sub-circuit GA further comprises a shielding module 30 electrically connected between the fourth node No4 and the second node No2 of the gate driving sub-circuit GA at the current stage, and the shielding module 30 is configured to block the coupling effect of the signal of the fourth node No4 on the signal of the second node No2. The shielding module 30 and the second output unit 202 are electrically connected to the fourth node No4.
[0051] Figure 3 A circuit diagram of the gate driving sub-circuit in the exemplary embodiment of the present disclosure is shown in FIG. 1. For the purpose of understanding the gate driving sub-circuit GA of the present application, the gate driving sub-circuit GA is exemplarily illustrated in the form of a circuit diagram in FIG. 1. Figure 3 The gate driving sub-circuit GA is exemplarily illustrated in the form of a circuit diagram in FIG. 1.
[0052] The first sub-unit 1041 of the first control unit 104 can include a first transistor T1 having a control terminal electrically connected to the third node No3, a first source / drain terminal electrically connected to the first power supply terminal VA, and a second source / drain terminal electrically connected to the first node No1. When the first transistor T1 is turned on, the current path between the first power supply terminal VA and the first node No1 is connected. When the first transistor T1 is turned off, the current path between the first power supply terminal VA and the first node No1 is disconnected.
[0053] The second sub-unit 1042 of the first control unit 104 can include a second transistor T2 having a control terminal electrically connected to the third node No3, a first source / drain terminal electrically connected to the second power supply terminal VB, and a second source / drain terminal electrically connected to the first node No1. When the second transistor T2 is turned on, the current path between the second power supply terminal VB and the first node No1 is connected. When the second transistor T2 is turned off, the current path between the second power supply terminal VB and the first node No1 is disconnected.
[0054] In some embodiments, to reduce the probability of the first power supply signal and the second power supply signal colliding at the first node No1, the first transistor T1 can be one of a P-type transistor and an N-type transistor, and the second transistor T2 can be the other of the P-type transistor and the N-type transistor.
[0055] Optionally, to reduce the probability of the first node No1 leaking current to the power supply terminal with lower voltage, at least one of the first transistor T1 and the second transistor T2 can be an oxide transistor.
[0056] In some embodiments, the voltage of the first power supply signal is greater than the voltage of the second power supply signal, and the second transistor T2 can be an oxide transistor to reduce the leakage current between the first node No1 and the second power supply terminal VB.
[0057] Optionally, to make the first stage transmission output unit 101 disconnect the current path between the first power supply end VA and the stage transmission output end OT1 according to the signal of the first node No1 faster, the first transistor T1 can be a silicon transistor, so as to utilize the advantages of the silicon transistor, i.e., the faster switching speed and the higher carrier mobility, to make the first power supply signal be transmitted to the first node No1 faster, thereby making the first stage transmission output unit 101 disconnect the current path between the first power supply end VA and the stage transmission output end OT1 according to the signal of the first node No1.
[0058] Optionally, the second transistor T2 can include two control ends, and the two control ends of the second transistor T2 are electrically connected with the third node No3.
[0059] Optionally, the input unit 103 of the stage transmission module 10 includes a third transistor T3, the third transistor T3 includes a control end configured to receive a clock signal CK, a first source-drain end electrically connected with the start signal line, and a second source-drain end electrically connected with the third node No3. When the third transistor T3 is turned on, the current path between the third node No3 and the start signal line is connected, and when the third transistor T3 is turned off, the current path between the third node No3 and the start signal line is disconnected.
[0060] Optionally, the first output unit 201 of the output module 20 can include a first output transistor To1, the first output transistor To1 includes a control end electrically connected with the first node No1, a first source-drain end electrically connected with the third power supply end VC, and a second source-drain end electrically connected with the signal output end OT2.
[0061] The second output unit 202 of the output module 20 includes a second output transistor To2 and a first capacitor C1, the second output transistor To2 includes a control end electrically connected with the second node No2, a first source-drain end electrically connected with the fourth power supply end VD, and a second source-drain end electrically connected with the signal output end OT2; and the first capacitor C1 is electrically connected between the control end of the second output transistor To2 and the signal output end OT2.
[0062] In some embodiments, to accelerate the level switching speed of the gate control signal Scan, at least one of the first output transistor To1 and the second output transistor To2 can be a silicon transistor.
[0063] In some embodiments, when the first sub-unit 1041 controls the first power signal to be transmitted to the first node No1, the first output unit 201 is required to disconnect the current path between the third power terminal VC and the signal output terminal OT2. Therefore, in order to reduce the risk of the first output transistor To1 being misdirected on in the period when the first sub-unit 1041 controls the first power signal to be transmitted to the first node No1, the voltage difference between the first power signal and the second power signal can be related to the threshold voltage of the first output transistor To1.
[0064] Optionally, the first output transistor To1 is a P-type transistor, and the voltage difference between the first power signal and the third power signal is greater than the threshold voltage of the first output transistor To1, so as to reduce the risk of the first output transistor To1 being misdirected on in the period when the first sub-unit 1041 controls the first power signal to be transmitted to the first node No1.
[0065] Optionally, the voltage difference between the first power signal and the third power signal is greater than -2V, so as to reduce the risk of the first output transistor To1 being misdirected on in actual application.
[0066] In some embodiments, the voltage of the first power signal is greater than or equal to 5V, the voltage of the second power signal is less than or equal to -8V, the voltage of the third power signal is greater than or equal to 6V, and the voltage of the fourth power signal is less than or equal to -10V.
[0067] Optionally, the first stage transfer output unit 101 of the stage transfer module 10 includes a first stage transfer transistor Ts1, and the first stage transfer transistor Ts1 includes a control terminal electrically connected to the first node No1, a first source-drain terminal electrically connected to the first power terminal VA, and a second source-drain terminal electrically connected to the stage transfer output terminal OT1.
[0068] The second stage transfer output unit 102 of the stage transfer module 10 includes a second stage transfer transistor Ts2 and a second capacitor C2, the second stage transfer transistor Ts2 includes a control terminal electrically connected to the second node No2, a first source-drain terminal electrically connected to the second power terminal VB, and a second source-drain terminal electrically connected to the stage transfer output terminal OT1, and the second capacitor C2 is electrically connected between the control terminal of the second stage transfer transistor Ts2 and the stage transfer output terminal OT1.
[0069] In some embodiments, in order to shorten the transition time of the stage transfer signal Stn corresponding to the level conversion, at least one of the first stage transfer transistor Ts1 and the second stage transfer transistor Ts2 can be a silicon transistor.
[0070] Optionally, the second control unit 105 of the stage transmission module 10 includes a fourth transistor T4, the fourth transistor T4 includes a control terminal electrically connected with the first node No1, a first source-drain terminal electrically connected with the second power supply terminal VB, and a second source-drain terminal electrically connected with the stage transmission output terminal OT1. The fourth transistor T4 is turned on to connect the current path between the second power supply terminal VB and the stage transmission output terminal OT1, and the fourth transistor T4 is turned off to disconnect the current path between the second power supply terminal VB and the stage transmission output terminal OT1.
[0071] In some embodiments, to reduce the leakage current between the stage transmission output terminal OT1 and the second power supply terminal VB, the fourth transistor T4 is an oxide transistor.
[0072] Optionally, the fourth transistor T4 can include two control terminals, and the two control terminals of the fourth transistor T4 are electrically connected with the first node No1.
[0073] Optionally, the shielding module 30 of the at least one gate driving sub-circuit GA includes a fifth transistor T5, the fifth transistor T5 includes a control terminal electrically connected with the fourth power supply terminal VD, a first source-drain terminal electrically connected with the second node No2, and a second source-drain terminal electrically connected with the fourth node No4.
[0074] It should be noted that each transistor included in the gate driving sub-circuit GA can be a P-type transistor or an N-type transistor. Each transistor included in the gate driving sub-circuit GA can be implemented in the form of a bipolar junction transistor, a field effect transistor, or a thin film transistor, etc. When the transistor is implemented in the form of a field effect transistor or a thin film transistor, etc., the above-mentioned control terminal can be a gate, the first source-drain terminal can be one of a source and a drain, and the second source-drain terminal can be the other of the source and the drain. When the transistor is implemented in the form of a bipolar junction transistor, the above-mentioned control terminal can be a base, the first source-drain terminal can be one of a collector and an emitter, and the second source-drain terminal can be the other of the collector and the emitter. Each transistor can adopt a single-gate or double-gate design. The active layer of each transistor can include a silicon semiconductor material or an oxide semiconductor material. The silicon semiconductor material includes monocrystalline silicon, polycrystalline silicon, amorphous silicon, etc. The oxide semiconductor material includes indium gallium zinc oxide, indium zinc oxide, etc.
[0075] It should be understood that, Figure 3 Only as an example of a schematic diagram, and not limited to the gate driving sub-circuit GA of the present application can only adopt Figure 3 the design, those skilled in the art can still change the design of each module in the gate driving sub-circuit GA according to the content disclosed in the present application, and each module in the gate driving sub-circuit GA can also be implemented in a simpler or more complex form or with a larger number of components. The components include but are not limited to transistors, capacitors, etc.
[0076] Figure 4 This is a timing diagram corresponding to the gate driver sub-circuit of an exemplary embodiment of this disclosure. To facilitate understanding of the working principle of the gate driver sub-circuit GA of this application, [the diagram is shown]. Figure 3 In this circuit, the first transistor T1, the third transistor T3, the fifth transistor T5, the first stage transistor Ts1, the second stage transistor Ts2, the first output transistor To1, and the second output transistor To2 are P-type transistors; the second transistor T2 and the fourth transistor T4 are N-type transistors. The voltage of the first power supply signal is lower than the voltage of the third power supply signal, the voltage of the second power supply signal is lower than the voltage of the first power supply signal, and the voltage of the fourth power supply signal is lower than the voltage of the second power supply signal. The first power supply terminal VA is the first high-voltage terminal VGH1, the second power supply terminal VB is the first low-voltage terminal VGL1, the third power supply terminal VC is the second high-voltage terminal VGH2, and the fourth power supply terminal VD is the second low-voltage terminal VGL2. Taking the clock signal CK corresponding to the Nth stage gate driver sub-circuit GA(N) as the first clock signal CK1 transmitted by the first clock line CKL1, combined with... Figure 4 The timing sequence is illustrated by example. Here, Nos1 represents the signal of the first node No1, Nos2 represents the signal of the second node No2, and Nos3 represents the signal of the third node No3. Figure 4 The horizontal axis represents time, and the vertical axis represents voltage value.
[0077] In the first stage t1: the first clock signal CK1 and the start signal STV corresponding to the Nth stage gate driver sub-circuit GA(N) are at low level. The first transistor T1, the third transistor T3, the fourth transistor T4, the second stage transfer transistor Ts2, and the second output transistor To2 in the Nth stage gate driver sub-circuit GA(N) are turned on, while the second transistor T2, the first stage transfer transistor Ts1, and the first output transistor To1 are turned off. The Nth stage transfer signal Stn(N) and the Nth stage gate control signal Scan(N) output by the Nth stage gate driver sub-circuit GA(N) are at low level.
[0078] In the second stage t2: the first clock signal CK1 and the start signal STV corresponding to the Nth stage gate driver sub-circuit GA(N) are high. The first transistor T1, the fourth transistor T4, the second stage transfer transistor Ts2, and the second output transistor To2 in the Nth stage gate driver sub-circuit GA(N) are turned on, while the second transistor T2, the third transistor T3, the first stage transfer transistor Ts1, and the first output transistor To1 are turned off. The Nth stage transfer signal Stn(N) and the Nth stage gate control signal Scan(N) output by the Nth stage gate driver sub-circuit GA(N) are low.
[0079] The third stage t3: the first clock signal CK1 is low, the starting signal STV corresponding to the Nth gate driving sub-circuit GA(N) is high, the second transistor T2, the third transistor T3, the first stage transfer transistor Ts1 and the first output transistor To1 in the Nth gate driving sub-circuit GA(N) are turned on, and the first transistor T1, the fourth transistor T4, the second stage transfer transistor Ts2 and the second output transistor To2 are cut off. The Nth stage transfer signal Stn(N) and the Nth gate control signal Scan(N) output by the Nth gate driving sub-circuit GA(N) are high.
[0080] The fourth stage t4: the first clock signal CK1 is high, the starting signal STV corresponding to the Nth gate driving sub-circuit GA(N) is low, the second transistor T2, the first stage transfer transistor Ts1 and the first output transistor To1 in the Nth gate driving sub-circuit GA(N) are turned on, and the first transistor T1, the third transistor T3, the fourth transistor T4, the second stage transfer transistor Ts2 and the second output transistor To2 are cut off. The Nth stage transfer signal Stn(N) and the Nth gate control signal Scan(N) output by the Nth gate driving sub-circuit GA(N) are high.
[0081] The fifth stage t5: the first clock signal CK1 and the starting signal STV corresponding to the Nth gate driving sub-circuit GA(N) are low, and the Nth gate driving sub-circuit GA(N) repeats the operation of the first stage t1, so that the Nth stage transfer signal Stn(N) and the Nth gate control signal Scan(N) output by the Nth gate driving sub-circuit GA(N) are low.
[0082] Similarly, the working principles of the remaining gate driving sub-circuits GA can also be obtained, which will not be described here.
[0083] It should be noted that the above embodiments are described by taking the voltage of the first power signal being less than the voltage of the third power signal, the voltage of the second power signal being less than the voltage of the first power signal, and the voltage of the fourth power signal being less than the voltage of the second power signal as an example, but this should not be understood as a limitation of the present application. For example, in actual application, the voltage of the second power signal can be greater than the voltage of the first power signal, the voltage of the fourth power signal can be greater than the voltage of the third power signal, and the voltage of the second power signal can be less than the voltage of the fourth power signal.
[0084] Figure 5 The circuit diagram of the gate driving sub-circuit of the comparative example embodiment is as follows: Figure 6The timing diagram corresponding to the gate driving sub-circuit of the embodiment is shown in FIG. 6. The gate driving sub-circuit of the embodiment includes the first to seventh switching tubes Ta1-Ta7 and the capacitor C. VGL represents the fifth power supply terminal, VGH represents the sixth power supply terminal, the fifth power supply terminal is used to supply the fifth power supply signal, and the sixth power supply terminal is used to supply the sixth power supply signal. Ms represents the signal of the first sub-node M, Ps represents the signal of the second sub-node P, and Qs represents the signal of the third sub-node Q. Figure 6 The horizontal axis in FIG. 6 represents time, and the vertical axis represents voltage value.
[0085] The timing diagram corresponding to the gate driving sub-circuit of the embodiment is shown in FIG. 6. The gate driving sub-circuit of the embodiment includes the first to seventh switching tubes Ta1-Ta7 and the capacitor C. VGL represents the fifth power supply terminal, VGH represents the sixth power supply terminal, the fifth power supply terminal is used to supply the fifth power supply signal, and the sixth power supply terminal is used to supply the sixth power supply signal. Ms represents the signal of the first sub-node M, Ps represents the signal of the second sub-node P, and Qs represents the signal of the third sub-node Q. Figure 6 In the level switching period ta in FIG. 6, the voltage difference between the control terminal of the fifth switching tube Ta5 and the output terminal OT of the gate driving sub-circuit of the embodiment is the largest at the beginning of the first period, so that the fifth switching tube Ta5 has strong output capability. As the potential of the output terminal OT decreases, the voltage difference between the control terminal of the fifth switching tube Ta5 and the output terminal OT gradually decreases, the current flowing through the fifth switching tube Ta5 decreases, and the pull-down effect of the sixth power supply signal transmitted to the output terminal OT through the fifth switching tube Ta5 on the potential of the output terminal OT decreases. When the potential of the output terminal OT approaches the potential corresponding to the sixth power supply terminal, the voltage difference between the control terminal of the fifth switching tube Ta5 and the output terminal OT is only -6V, the output capability of the fifth switching tube Ta5 is very weak, and the potential of the output terminal OT decreases very slowly, thereby causing the transition time of the gate control signal output by the gate driving sub-circuit of the embodiment from high level to low level to be unable to be reduced, and the level switching delay of the gate control signal to appear to be unable to be reduced. Even if the width-length ratio of the fifth switching tube Ta5 is increased within an acceptable range, the level switching delay of the gate control signal to appear cannot be reduced. When the gate driving sub-circuit of the embodiment is applied to a display panel, the level switching delay of the gate control signal output by the gate driving sub-circuit of the embodiment to appear is amplified due to the cumulative effect of the cascade design, thereby affecting the working stability of the gate driving circuit and the display effect of the display panel.
[0086] In the embodiment, the gate driving sub-circuit GA includes the stage transmission module 10 and the output module 20, the stage transmission signal Stn output by the stage transmission module 10 is used to realize the cascade design of the plurality of gate driving sub-circuits GA, the load of the signal output terminal OT2 outputting the gate control signal Scan in the gate driving sub-circuit GA can be reduced, and the level switching delay of the gate control signal Scan can be reduced. In addition, the voltage relationship between the first to fourth power supply signals is set, the level switching delay of the stage transmission signal Stn can be reduced, the stage transmission failure problem can be further improved, and the power consumption of the gate driving circuit GDC can be reduced.
[0087] Figure 7A structural schematic diagram of a display panel provided by an embodiment of the present application is shown. The present application provides a display panel comprising any of the above-described gate drive circuits GDC. The above-described start signal stv can be a frame start signal.
[0088] Please continue to refer to Figure 7 , the display panel comprises a plurality of sub-pixels Spx, the plurality of sub-pixels Spx are electrically connected with a plurality of gate drive sub-circuits GA, the plurality of gate drive sub-circuits GA are configured to transmit gate control signals Scan to the plurality of sub-pixels Spx, and the plurality of sub-pixels Spx are configured to realize the display function of the display panel according to the received gate control signals Scan and data signals.
[0089] Optionally, the display panel can be a passive light-emitting display panel or a self-luminous display panel. The passive light-emitting display panel includes a liquid crystal display panel, etc., and the self-luminous display panel includes a display panel with a light-emitting device as a sub-pixel Spx. The light-emitting device can include at least one of an organic light-emitting diode, a sub-millimeter light-emitting diode, and a micro light-emitting diode.
[0090] It should be understood that the display panel provided by the present application has all the beneficial effects of the above-described gate drive circuit GDC, and thus the display panel also has all the beneficial effects of the above-described gate drive circuit GDC, which will not be described here.
[0091] As Figure 8 A structural schematic diagram of a display device provided by an embodiment of the present application is shown. The present application also provides a display device comprising any of the above-described display panels.
[0092] The display device can further comprise a timing controller electrically connected with the gate drive circuit GDC, and the timing controller is configured to output a corresponding clock signal CK to the gate drive circuit GDC.
[0093] In some embodiments, the timing controller is further configured to output a start signal stv to the gate drive circuit GDC.
[0094] It should be understood that the display device can further comprise a source driver, and the timing controller is electrically connected with the gate drive circuit GDC and the source driver. The source driver can generate data signals according to the control signals output by the timing controller, so as to output to the plurality of sub-pixels Spx, thereby controlling the display content of the plurality of sub-pixels Spx.
[0095] It should be noted that the display device can further comprise a power management chip, a graphics processor, and the like, which are not shown. The power management chip is used to provide power for the display of the display panel, and the graphics processor is used to transmit image data information to the timing controller, so as to control the display of the display panel.
[0096] It should be understood that the display device provided by the present application has all the beneficial effects of the display panel described above, and therefore, the display device also has all the beneficial effects of the display panel described above, which will not be described here.
[0097] The display device can be a mobile phone, a computer, a virtual reality display, an augmented reality display, and the like. The display device can be a device for realizing a display function applied to education, entertainment, transportation, medical treatment, national defense, and the like.
[0098] The above is only an optional embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation made by using the content of the present application specification and drawings, or directly / indirectly applied to other related technical fields within the inventive concept of the present application is included in the patent protection scope of the present application.
Claims
1. A gate driving circuit, characterized in that, The circuit includes multiple cascaded gate drive sub-circuits, at least one of which includes: The transmission module is configured to control the stage transmission output terminal to form a current path with the first power supply terminal and the second power supply terminal in a time-division manner according to the corresponding clock signal and the corresponding start signal; the voltage of the second power signal supplied by the second power supply terminal is less than the voltage of the first power signal supplied by the first power supply terminal; and, The output module, electrically connected to the transmission module, is configured to form a current path between the control signal output terminal and the third power supply terminal and the fourth power supply terminal in a time-division manner; the voltage of the fourth power supply signal supplied by the fourth power supply terminal is less than the voltage of the third power supply signal supplied by the third power supply terminal. Wherein, the start signal corresponding to the Nth stage gate driver sub-circuit is either a start signal or a stage transmission signal output by the NAth stage gate driver sub-circuit; the voltage of the first power supply signal is less than the voltage of the third power supply signal; N≥1, A≥1, NA>0.
2. The gate driving circuit according to claim 1, characterized in that, The voltage of the second power signal is greater than the voltage of the fourth power signal.
3. The gate driving circuit according to claim 1, characterized in that, The output module includes: The first output unit, electrically connected to the first node of the gate drive sub-circuit of this stage and electrically connected to the signal output terminal, is configured to control the signal transmission between the third power supply terminal and the signal output terminal according to the signal from the first node; and The second output unit is electrically connected to the second node of the gate drive sub-circuit of the same stage and to the signal output terminal, and is configured to control the signal transmission between the fourth power supply terminal and the signal output terminal according to the signal of the second node.
4. The gate driving circuit according to claim 3, characterized in that, The transmission module includes: A first-stage transmission output unit, electrically connected to the first node and the stage transmission output terminal, is configured to control signal transmission between the first power supply terminal and the stage transmission output terminal based on the signal from the first node; and The second-stage transmission unit is electrically connected to the second node and the stage transmission output terminal, and is configured to control the signal transmission between the second power supply terminal and the stage transmission output terminal according to the signal from the second node.
5. The gate driving circuit according to claim 3 or 4, characterized in that, The transmission module includes: The input unit is electrically connected to the second node through the third node of the gate drive sub-circuit described in this stage, and is configured to control the signal transmission between the start signal line transmitting the start signal and the third node and the second node according to the clock signal; The first control unit, electrically connected to the second node via the third node and electrically connected to the first node, is configured to control the signal of the first node to be out of phase with the signal of the second node based on the signal of the third node.
6. The gate driving circuit according to claim 5, characterized in that, The first control unit includes: The first transistor includes a control terminal electrically connected to the third node, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the first node. The second transistor includes a control terminal electrically connected to the third node, a first source-drain terminal electrically connected to the second power supply terminal, and a second source-drain terminal electrically connected to the first node. The first transistor is either a P-type transistor or an N-type transistor, and the second transistor is either a P-type transistor or an N-type transistor.
7. The gate driving circuit according to claim 6, characterized in that, The first output unit includes a first output transistor, which includes a control terminal electrically connected to the first node, a first source-drain terminal electrically connected to the third power supply terminal, and a second source-drain terminal electrically connected to the signal output terminal. The second output unit includes a second output transistor and a first capacitor. The second output transistor includes a control terminal electrically connected to the second node, a first source-drain terminal electrically connected to the fourth power supply terminal, and a second source-drain terminal electrically connected to the signal output terminal. The first capacitor is electrically connected between the control terminal and the signal output terminal of the second output transistor. Wherein, the first output transistor is a P-type transistor, and the difference between the voltage of the first power supply signal and the voltage of the third power supply signal is greater than the threshold voltage of the first output transistor.
8. The gate driving circuit according to claim 5, characterized in that, The input unit includes: The third transistor includes a control terminal configured to receive the clock signal, a first source-drain terminal electrically connected to the start signal line, and a second source-drain terminal electrically connected to the third node.
9. The gate driving circuit according to claim 4, characterized in that, The first-stage transmission output unit includes a first-stage transmission transistor, which includes a control terminal electrically connected to the first node, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the stage transmission output terminal. The second-stage transmission output unit includes a second-stage transmission transistor and a second capacitor. The second-stage transmission transistor includes a control terminal electrically connected to the second node, a first source-drain terminal electrically connected to the second power supply terminal, and a second source-drain terminal electrically connected to the stage transmission output terminal. The second capacitor is electrically connected between the control terminal of the second-stage transmission transistor and the stage transmission output terminal.
10. The gate driving circuit according to claim 4 or 9, characterized in that, The transmission module also includes: The second control unit is electrically connected to the first node and the stage transmission output terminal; Specifically, when the second-stage transmission output unit connects the current path between the second power supply terminal and the stage transmission output terminal, the second control unit is configured to connect the current path between the second power supply terminal and the stage transmission output terminal according to the signal of the first node.
11. The gate driving circuit according to claim 10, characterized in that, The second control unit includes a fourth transistor, which includes a control terminal electrically connected to the first node, a first source-drain terminal electrically connected to the second power supply terminal, and a second source-drain terminal electrically connected to the stage output terminal.
12. The gate driving circuit according to claim 3 or 4, characterized in that, At least one of the gate drive sub-circuits further includes: The shielding module is electrically connected between the fourth node and the second node of the gate drive sub-circuit of this stage, and is configured to block the coupling effect of the signal of the fourth node on the signal of the second node. The shielding module is electrically connected to the second output unit at the fourth node.
13. The gate driving circuit according to claim 12, characterized in that, The shielding module includes: The fifth transistor includes a control terminal electrically connected to the fourth power supply terminal, a first source-drain terminal electrically connected to the second node, and a second source-drain terminal electrically connected to the fourth node.
14. A display panel, characterized in that, Includes multiple gate drive circuits as described in any one of claims 1 to 13; as well as, Multiple sub-pixels, electrically connected to the gate driving circuit, are configured to receive corresponding gate control signals.
15. A display device, characterized in that, include: The display panel as described in claim 14; as well as A timing controller, electrically connected to the gate drive circuit, is configured to output the corresponding clock signal to the gate drive circuit.