Full-range optimization modulation method for bus capacitance current of three-level inverter

Abstract

The invention discloses a full-range optimization modulation method for bus capacitance current of a three-level inverter, which is used for systematically identifying and replacing a small vector which causes large ripple current in the traditional SVPWM (Space Vector Pulse Width Modulation) to realize the suppression of direct-current bus capacitance current ripple and prolong the service life of a capacitor. According to the method, the high-frequency current ripples of the direct-current bus capacitor are effectively suppressed in the full modulation range and the full power factor angle range of the TNPC type three-phase three-level inverter, the method can be realized through simple software programming, the problem is solved from a capacitor current ripple generation source, extra hardware cost does not need to be introduced, and the method is suitable for large-scale popularization and application. The requirement for model selection of the direct-current bus support capacitor is relaxed, a high-capacity capacitor allowing large ripple current does not need to be selected, the size of equipment is reduced, the power density is improved, and the predicted service life of the direct-current bus support capacitor is greatly prolonged.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of power electronics, and more specifically, is a full-range optimization modulation method for high-frequency current ripple of a DC bus capacitor of a three-phase three-level inverter. BACKGROUND

[0002] Three-level NPC inverters are widely used in medium and high power applications such as wind power generation, photovoltaic grid-connected and energy storage systems due to their advantages in output voltage harmonic characteristics, device voltage withstand level, etc. Such inverters usually need to use capacitors to stabilize the DC bus voltage and absorb the ripple current. Electrolytic capacitors are widely used in DC buses due to their low cost and large capacitance per unit volume. The volume, weight and life of power electronic converters are often subject to the DC bus support capacitor. However, electrolytic capacitors have a high equivalent series resistance (ESR), and the high-frequency current ripple flowing through the capacitor will cause losses, leading to an increase in the core temperature of the capacitor and internal self-heating, and causing the ESR to increase. In addition, electrolytic capacitors have weak resistance to electro-thermal stress, and such stress will accelerate the evaporation of electrolyte, causing the capacitance to decrease. When the capacitance decreases to 80% of the existing value or the ESR increases by one time, it is usually considered as the end of the working life of the electrolytic capacitor. In order to alleviate the burden caused by the above stress, a large-capacity capacitor that allows a large ripple current or a capacitor series connection method needs to be selected, but these solutions will all cause the system volume to increase and the cost to rise. Therefore, the optimization and suppression of the capacitor current ripple is crucial to improve the reliability of the DC bus support capacitor, prolong the life of the capacitor, reduce the volume of the equipment, and improve the power density of the equipment. However, the existing modulation methods for three-phase inverters have the problems of not being applicable to three-level converters, insufficient suppression effect on the capacitor current ripple, and being able to optimize the capacitor current ripple only at a specific modulation degree or power factor angle. SUMMARY

[0003] To solve the above problems, the present application provides a full-range optimization modulation method for the bus capacitor current of a three-level inverter.

[0004] A full-range optimization modulation method for the bus capacitor current of a three-level inverter, comprising the following steps: Step A, determining the quantitative relationship between the DC bus capacitor ripple current and the neutral point current of the three-level inverter, and identifying the core control basis for reducing the capacitor ripple current by suppressing the neutral point current ripple; analyzing the neutral point current amplitudes corresponding to different switching states of the three-level inverter, identifying the target small vector that will introduce the maximum phase current to the neutral point and generate the highest neutral point current ripple, and taking the target small vector that will introduce the maximum phase current to the neutral point and generate the highest neutral point current ripple as the core object for subsequent virtual small vector replacement and reconstruction; Step B, sector reconstruction is performed on the space vector diagram of the three-level inverter, which is averagely divided into six large sectors, and each large sector is averagely divided into four small sectors, so as to realize fine matching of the reference voltage vector, and determine the sector matching rule to ensure that the modulation degree is in the range of 0~1, and the expected reference voltage vector can be synthesized linearly and without distortion; Step C, the power factor angle of the three-level inverter is detected, and a corresponding virtual small vector synthesis mode is matched for different power factor angle ranges, and the virtual small vector synthesis mode satisfies: I) The virtual small vector is synthesized by the equal proportion of the pair of basic voltage vectors with opposite effects on the midpoint potential; II) The synthesized virtual small vector can accurately synthesize the expected reference voltage vector through the volt-second balance principle; III) When the synthesized virtual small vector acts, the current introduced to the neutral point is the minimum value in the three-phase current of the current sector, so as to realize the maximum suppression of the midpoint current ripple; Step D, the vector action sequence is redesigned according to the virtual small vector synthesis mode selected in step C, and the action time of each basic vector is calculated to ensure smooth switching of the switch and no P-N state jump, and the number of switching is minimized; Step E, the driving PWM signal of each power switch device is designed according to the vector action sequence designed in step D.

[0005] Further improvement, in step A, the quantitative relationship between the DC bus capacitor current and the midpoint current is as follows:

[0006] Wherein represents the capacitor current on the DC bus, represents the capacitor current on the DC bus, represents the midpoint current; The target small vector that introduces the maximum phase current to the neutral point and generates the highest midpoint current ripple is the small vector closest to the reference voltage vector in the SVPWM method.

[0007] Further improvement, the specific steps of step B are as follows: B1: According to the SVPWM method, the space vector diagram is divided into six large sectors, and each large sector is reconstructed from six small sectors to four small sectors; in a large sector, a virtual zero vector is included V VZ , the first virtual small vector V VS1 , the second virtual small vector V VS2 , the virtual middle vector V VM , the first virtual large vector V VL1 , and the second virtual large vectorV VL2 ; B2: judging the sector where the reference voltage vector is located, synthesizing the reference voltage vector using three adjacent virtual vectors, specifically as follows: in the first sector A1, using V VS1 、 V VZ 、 V VM to synthesize the reference voltage vector; in the second sector A2, using V VS2 、 V VZ 、 V VM to synthesize the reference voltage vector; in the third sector A3, using V VS1 、 V VM 、 V VL1 to synthesize the reference voltage vector; in the fourth sector A4, using V VS2 、 V VM 、 V VL2 to synthesize the reference voltage vector.

[0008] Further improvement, the specific steps of step C are as follows: Step C1: using the first virtual small vector V VS1 , the second virtual small vector V VS2 to synthesize two basic voltage vectors with opposite effects on the midpoint potential, wherein there are three synthesis methods with different contributions of midpoint current amplitudes, the first vector synthesis method introduces a midpoint current amplitude |Ib|, the second vector synthesis method introduces a midpoint current amplitude |Ic|, and the third vector synthesis method introduces a midpoint current amplitude |Ia|, |Ia|, |Ib|, |Ic| respectively represent the amplitudes of three-phase load currents at the current time; the virtual zero vector V VZ uses the basic zero vector V OOO ; the virtual middle vector V VM uses the basic middle vector V PON ; the first virtual large vector V VL1 and the second virtual large vector V VL2 use the basic large vector V PNN and VPPN ; Step C2: Determine the load type and switch the first virtual small vector for different power factor angles. V VS1 Second virtual small vector V VS2 The synthesis strategy ensures that the midpoint current flowing through the neutral point is the minimum value among the three-phase currents of the current sector.

[0009] Further improvements include the following steps in step C2: Vector synthesis method three is used within the power factor angle range of (-5π / 12, -π / 6); vector synthesis method one is used within the power factor angle range of (-π / 6, π / 6); vector synthesis method two is used within the power factor angle range of (π / 6, 5π / 12); and the SVPWM synthesis strategy is used within the power factor angle ranges of (-π / 2, -5π / 12) and (5π / 12, π / 2). In vector composition method one:

[0010] Where P represents the P state, i.e., the output voltage of the inverter. for state, The voltage at state 0 is the DC power supply voltage; the voltage at state 0 is the inverter output voltage. The N state is the inverter's output voltage; the N state is the inverter's output voltage. for The state; This indicates that the three-phase switch state is OOO, meaning that the three phases A, B, and C are connected to the basic zero vector of the neutral point O. This indicates that the three-phase switch is in the PON state, meaning that phase A is connected to the positive busbar P, phase B is connected to the neutral point O, and phase C is connected to the negative busbar N. This indicates that the three-phase switch is in the ONO state, meaning that phases A and C are connected to the neutral point O, and phase B is connected to the negative bus N. This indicates that the three-phase switch is in the state of OPO, meaning that phases A and C are connected to the neutral point O, and phase B is connected to the positive busbar P. This is the basic small vector. The basic large vector representing the three-phase switch state as PNN, i.e., phase A is connected to the positive busbar P, and phases B and C are connected to the negative busbar N; This indicates that the three-phase switch state is PPN, meaning that phases A and B are connected to the positive busbar P, and phase C is connected to the negative busbar N.

[0011] In vector composition method two:

[0012] in, represents a basic middle vector of a three-phase switch state PNO, i.e. A phase is connected to a positive bus P, B phase is connected to a negative bus N, and C phase is connected to a neutral point O; represents a basic small vector of a three-phase switch state OON, i.e. A, B phases are connected to a neutral point O, and C phase is connected to a negative bus N; represents a basic small vector of a three-phase switch state PPO, i.e. A, B phases are connected to a positive bus P, and C phase is connected to a neutral point O.

[0013] In the third vector synthesis mode:

[0014] wherein, represents a basic small vector of a three-phase switch state POO, i.e. A phase is connected to a positive bus P, and B, C phases are connected to a neutral point O, represents a basic small vector of a three-phase switch state ONN, i.e. A phase is connected to a neutral point O, and B, C phases are connected to a negative bus N, represents a basic middle vector of a three-phase switch state OPN, i.e. A phase is connected to a neutral point O, B phase is connected to a positive bus P, and C phase is connected to a negative bus N.

[0015] Further improvement, the vector action sequence of the four small sectors corresponding to the first vector synthesis mode is as follows: A1: [PON]-[OOO]-[ONO]-[OOO]-[PON]; A2: [PON]-[OOO]-[OPO]-[OOO]-[PON]; A3: [PON]-[PNN]-[ONO]-[PNN]-[PON]; A4: [PON]-[PPN]-[OPO]-[PPN]-[PON]; The vector action sequence of the four small sectors corresponding to the second vector synthesis mode is as follows: A1: [OOO]-[OON]-[PON]-[PNO]-[PON]-[OON]-[OOO]; A2: [OOO]-[OON]-[PON]-[PPO]-[PON]-[OON]-[OOO]; A3: [OON]-[PON]-[PNN]-[PNO]-[PNN]-[PON]-[OON]; A4: [OON]-[PON]-[PPN]-[PPO]-[PPN]-[PON]-[OON]; The vector action sequence of the four small sectors corresponding to the third vector synthesis mode is as follows: A1: [OOO]-[POO]-[PON]-[ONN]-[PON]-[POO]-[OOO]; A2: [OOO]-[POO]-[PON]-[OPN]-[PON]-[POO]-[OOO]; A3: [POO]-[PON]-[PNN]-[ONN]-[PNN]-[PON]-[POO]; A4: [POO]-[PON]-[PPN]-[OPN]-[PPN]-[PON]-[POO].

[0016] In a further improvement, in step D, the vector action sequence follows the following principles: D1: When the switching state changes from P to N or from N to P, a transition through state O is required to prevent the switch from being shot-through and causing serious damage to the inverter. D2: Prioritize vector action sequences with fewer switching operations per phase.

[0017] In a further improvement, in step E, the required modulation wave signal is calculated based on the vector action sequence and the vector action time, and the carrier signal of different segments is calculated. The modulation wave signal and the carrier signal are compared to output a PWM signal to realize the control of the switching transistor.

[0018] Further improvements include the three-level inverter being a T-type inverter, an NPC-type inverter, or a hybrid ANPC inverter.

[0019] A further improvement is that the three-level inverter includes a DC power supply U. dc DC power supply U dc The positive terminal is connected to one end of capacitor C1 and the A-side switch S. a1 The drain of the B-switch transistor - S b1 The drain and C switching transistor - S c1 The drain electrode; DC power supply U dc The negative terminal of capacitor C2 is connected to the four-phase switching transistor A. a4 The source, B switch, four S b4 The source and C switch of the four S c4 The source of the capacitor; the other end of the upper capacitor C1 and the other end of the lower capacitor C2 are electrically connected to the neutral point O; Neutral point O electrical connection A switch transistor two S a2 The drain of the B-switch transistor is S. b2 The drain and C switching transistor 2S c2 The drain electrode; A switching transistor 2S a2 The source of the A-type switching transistor is connected to the S-type source. a3source of the A switch tube one S a3 drain of the A switch tube one S a1 source and one end of the A phase filter inductor, the other end of the A phase filter inductor is electrically connected to the A phase end of the load; source of the B switch tube one S b2 source of the B switch tube one S b3 source of the B switch tube one S b3 drain of the B switch tube one S b1 source and one end of the B phase filter inductor, the other end of the B phase filter inductor is electrically connected to the B phase end of the load; source of the B switch tube one S C2 source of the B switch tube one S c3 source of the B switch tube one S c3 drain of the B switch tube one S c1 source and one end of the C phase filter inductor, the other end of the C phase filter inductor is electrically connected to the C phase end of the load.

[0020] Advantages of the present application: 1. The present application realizes effective suppression of high-frequency current ripple of the DC bus capacitor in the full modulation range and full power factor angle range of the TNPC type three-phase three-level inverter by adopting different vector synthesis methods according to different load characteristics.

[0021] 2. Due to the significant reduction of the DC bus capacitor ripple current, the ESR loss of the DC bus support capacitor and its hotspot temperature are also reduced, which can greatly extend the predicted life of the DC bus support capacitor.

[0022] 3. Due to the significant reduction of the effective value of the DC bus capacitor ripple current, the requirements for selecting the DC bus support capacitor are relaxed, and there is no need to select a large-capacity capacitor with a large ripple current, which reduces the size of the device and improves the power density.

[0023] 4. The present application is an improvement of a pure software modulation algorithm, which solves the problem from the source of the capacitor current ripple without increasing any hardware cost, and is implemented by software programming in the existing digital controller, which is economical and efficient. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a T-type three-level inverter topology structure.

[0025] Figure 2 is a three-level SVPWM space vector diagram.

[0026] Figure 3 is a first large sector division schematic diagram.

[0027] Figure 4ais the traditional SVPWM switching state and midpoint current amplitude diagram.

[0028] Figure 4b is the switching state and midpoint current amplitude diagram of the method of the present application.

[0029] Figure 5a is a schematic diagram of a virtual small vector synthesis mode.

[0030] Figure 5b is a schematic diagram of a virtual small vector synthesis mode.

[0031] Figure 5c is a schematic diagram of a virtual small vector synthesis mode.

[0032] Figure 6 is a comparison diagram of the effective value of the upper DC bus support capacitor current.

[0033] Figure 7a is a diagram of the output voltage, output current and upper DC bus support capacitor ripple current of the SVPWM method.

[0034] Figure 7b is a diagram of the output voltage, output current and upper DC bus support capacitor ripple current of the method of the present application. DETAILED DESCRIPTION

[0035] The present application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein and the accompanying drawings are only used to illustrate the present application and cannot be understood as limiting the present application.

[0036] Figure 1 A TNPC three-phase three-level inverter is shown, each phase consisting of four switching tubes. The DC side is composed of a DC power supply U dc and upper and lower capacitors C1 and C2.

[0037] The present application provides a full-range optimization modulation method for the bus capacitor current of a three-level inverter, comprising: Taking X as the general phase of A, B and C three-phase, and the potential of point O as the reference potential. When switching tubes S X1 , S X2 are turned on, and switching tubes S X3 , S X4 are turned off, the output voltage of the inverter is , and the circuit state at this time is called P state; when switching tubes S X2 , S X3 are turned on, and switching tubes S X1 , S X4 are turned off, the output voltage of the inverter is 0, and the circuit state at this time is called O state; when switching tubes SX3 , S X4 turned on, switch S X1 , S X2 turned off, output voltage of inverter This state is called N state. X = a or b or c.

[0038] During O state, current flows through neutral point, charging or discharging DC bus support capacitor, causing capacitor voltage change, therefore, the ripple current of DC bus support capacitor is caused by the neutral point current .

[0039] According to Kirchhoff's current law, neutral point current is expressed as: represents upper capacitor current, represents lower capacitor current. If the upper and lower capacitor capacitance values are equal, it can be concluded that the upper capacitor current and the lower capacitor current can be expressed as:

[0040]

[0041] represents upper capacitor voltage, represents lower capacitor voltage. By combining the above formula, it can be concluded that:

[0042] As can be seen from the above formula, the ripple current of the DC bus capacitor is half of the neutral point current, and the ripple current of the bus capacitor can be suppressed by suppressing the fluctuation of the neutral point current . Therefore, the ripple current of the upper and lower DC support capacitors can be reduced by reducing the neutral point ripple current.

[0043] Only in O state, phase current flows to neutral point through inner switch Sx2 or Sx3 connected to neutral point. For example, if the switching state is [PON], the b-phase current I b flows to neutral point O; on the contrary, in the case of [POO], the b-phase and c-phase currents I b + I c flow to the neutral point. The amplitude of the neutral point current is equal to the sum of the currents of the phase corresponding to the O state. In a balanced three-phase circuit, the sum of the three-phase currents is zero, so when two-phase currents flow through the neutral point, the sum of their currents is equal to the amplitude of the third-phase current.

[0044] ​Table 1 shows the mid-point current amplitude for each switching state, the resulting mid-point current is the amplitude of the three-phase current or its opposite. By observing all sectors, it can be found that the small vector closest to the reference voltage will produce the highest mid-point current.

[0045] Table 1 Mid-point current amplitude for different switching states

[0046] Figure 2 The vector diagram of the conventional SVPWM is shown, for the conventional SVPWM, in the first large sector uses small vectors [POO], [ONN], [PPO], [OON] to synthesize the reference voltage vector, which introduces a mid-point current amplitude of I a , I c , I b ,

[0047] uses the middle vector [PON] and the small vector [POP] to synthesize a virtual small vector V VS1 , V VS2 , V VS1 , V VS2 , I b ,

[0048] Figure 3 The results of the proposed method of sector reconstruction of the space vector diagram are shown, which divides six large sectors, each large sector is divided into four small sectors. In the first small sector, uses V VS1 , V VZ , V VM to synthesize the reference voltage vector; in the second small sector, uses V VS2 , V VZ , V VM to synthesize the reference voltage vector; in the third small sector, uses V VS1 , VVM 、 V VL1 Synthesizing the reference voltage vector; in the fourth subsector, using V VS2 、 V VM 、 V VL2 Synthesizing the reference voltage vector, thereby ensuring that the proposed algorithm can be applied to the modulation degree Synthesizing the required reference voltage linearly and without distortion in a wide range from 0 to 1.

[0049] Table 2 shows the action time of the virtual vector in each subsector calculated by the volt-second balance principle.

[0050] Table 2 Action time of virtual vector in each subsector in the first large sector

[0051] Table 3 shows the vector action sequence redesigned according to the proposed optimized modulation method.

[0052] Table 3 Vector action sequence one

[0053] If the reference voltage vector is located in other large sectors, it is mapped to the first large sector, ensuring the effectiveness of the proposed method in the full cycle range.

[0054] Figure 4a The switching sequence of the 6th subsector in the first large sector and the neutral point current when using the traditional space vector pulse width modulation (SVPWM) are shown, and the switching sequence is: [OON] - [PON]- [PPN]- [PPO]- [PPN]-[PON]- [OON]. In this sector, the size relationship of the three-phase current is I c|>| I a|>| I b|, so when the small vectors [PPO] and [OON] are applied, the maximum phase current (corresponding to phase C) flows through the neutral point.

[0055] Figure 4b The switching sequence of the same reference voltage vector and the neutral point current when using the proposed method are shown, and the switching sequence is: [PON] - [PPN]- [OPO] - [PPN]- [PON], as can be seen from the figure, the maximum phase C current is replaced by a smaller B phase current, which greatly reduces the neutral point current ripple, thereby suppressing the DC bus capacitor current ripple, and does not introduce additional switching times.

[0056] The above method is referred to as vector synthesis method one. Vector synthesis method one ensures that the power factor angle , i.e. the midpoint current ripple can be suppressed when the pure resistive load is connected, but if the power factor angle is not 0, the current leads or lags the voltage, the relationship of the three-phase current magnitude changes, and it cannot be guaranteed that the B-phase current magnitude is the minimum in the first large sector, and thus the suppression effect of the midpoint current ripple cannot be guaranteed, so the bus capacitor current ripple suppression strategy needs to be expanded to the full range of the power factor angle.

[0057] When the C-phase is the phase with the minimum current magnitude, the typical working condition is , at this time, the A-phase and the B-phase are the phases with larger current magnitude in the first large sector, and the virtual small vector synthesis mode is reconstructed by analogy with the above pure resistive working condition, and the vector synthesis mode two is defined as follows:

[0058] Figure 5b The vector synthesis mode two is shown, which synthesizes the virtual small vector V VS1 by using the middle vector [PNO] and the small vector [OON] in equal proportion, synthesizes the virtual small vector V VS2 by using the small vector [PPO] and the small vector [OON] in equal proportion, V VS1 and V VS2 The generated midpoint current magnitude is I c , at this time, the midpoint current ripple is the minimum, and the purpose of suppressing the DC bus capacitor current ripple is achieved.

[0059] Table 4 shows the redesigned vector action sequence under this vector synthesis mode.

[0060] Table 4 Vector Action Sequence Two

[0061] When the A-phase is the phase with the minimum current magnitude, the typical working condition is , at this time, the B-phase and the C-phase are the phases with larger current magnitude in the first large sector, and the virtual small vector synthesis mode is reconstructed, and the vector synthesis mode three is defined as follows:

[0062] Figure 5c The vector synthesis mode three is shown, which synthesizes the virtual small vector V VS1 by using the small vector [POO] and the small vector [ONN] in equal proportion, synthesizes the virtual small vector V VS2 by using the middle vector [OPN] and the small vector [POO] in equal proportion, V ​VS1 and V VS2 The amplitude of the generated midpoint current is | I a At this point, the midpoint current ripple is minimized, thus achieving the purpose of suppressing the DC bus capacitor current ripple.

[0063] Table 5 shows the redesigned vector action sequence under this vector synthesis method.

[0064] Table 5 Vector Action Sequence 3

[0065] Figure 6 This paper demonstrates the effective values ​​of DC capacitor ripple current under different power factor angles for traditional SVPWM and various vector synthesis methods. Therefore, for different load types, the optimal vector synthesis method is selected, i.e., [the method is chosen]. Figure 6 By using vector synthesis method three for the lower envelope of the effective value of the capacitor current within the power factor angle range of (-5π / 12, -π / 6); vector synthesis method one for the power factor angle range of (-π / 6, π / 6); vector synthesis method two for the power factor angle range of (π / 6, 5π / 12); and traditional SVPWM for the power factor angle ranges of (-π / 2, -5π / 12) and (5π / 12, π / 2), high-frequency current ripple of the DC bus capacitor can be suppressed across the entire modulation range and the entire power factor angle range.

[0066] Figure 7a The output voltage, output current, and upper DC bus support capacitor ripple current are shown when the power factor angle is 0 using conventional SVPWM. Figure 7b The output voltage, output current, and ripple current of the upper DC bus support capacitor using the proposed method are shown. Comparative observation reveals that the high-frequency current ripple of the DC bus capacitor is significantly suppressed after using the proposed method, reducing its effective value by 64.3%, thus verifying the effectiveness of the proposed method.

[0067] The above is only one specific implementation method of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept shall be considered as infringing the protection scope of the present invention.

Claims

1. A full range optimized modulation method for three-level inverter bus capacitor current, characterized in that, Comprising the following steps: Step A, determining the quantitative relationship between the DC bus capacitor current and the neutral point current of the three-level inverter, and identifying the core control basis for reducing the capacitor current ripple by suppressing the neutral point current ripple; analyzing the neutral point current amplitude corresponding to different switching states of the three-level inverter, identifying the target small vector that will introduce the maximum phase current to the neutral point and generate the highest neutral point current ripple, and taking the target small vector that will introduce the maximum phase current to the neutral point and generate the highest neutral point current ripple as the core object of subsequent virtual small vector replacement and reconstruction; Step B, reconstructing the space vector diagram of the three-level inverter, dividing it into six large sectors, and dividing each large sector into four small sectors to realize fine matching of the reference voltage vector, and determining the sector matching rule to ensure that the modulation degree is within the range of 0~1, and the expected reference voltage vector can be synthesized linearly and without distortion; Step C, detecting the power factor angle of the three-level inverter, and matching the corresponding virtual small vector synthesis method for different power factor angle ranges, the virtual small vector synthesis method meets: One) The virtual small vector is synthesized by a pair of basic voltage vectors with opposite effects on the neutral point potential in equal proportions; two) The synthesized virtual small vector can accurately synthesize the expected reference voltage vector through the volt-second balance principle; three) When the synthesized virtual small vector acts, the current introduced to the neutral point is the minimum value of the three-phase current in the current sector, so as to realize the maximum suppression of the neutral point current ripple; Step D, redesigning the vector action sequence according to the virtual small vector synthesis method selected in step C, and calculating the action time of each basic vector to ensure smooth switching of the switch and prevent P-N state jumping, and the number of switching is minimized; Step E, designing the driving PWM signal of each power switch device according to the vector action sequence designed in step D.

2. The full range optimized modulation method of three-level inverter bus capacitor current as claimed in claim 1, wherein, In step A, the quantitative relationship between the DC bus capacitor current and the neutral point current is as follows: ； wherein represents the capacitor current on the DC bus, represents the capacitor current on the DC bus, represents the midpoint current; The target small vector that will introduce the maximum phase current to the neutral point and generate the highest neutral point current ripple is the small vector closest to the reference voltage vector in the SVPWM method.

3. The full range optimized modulation method of three-level inverter bus capacitor current as claimed in claim 1 wherein, The specific steps of step B are as follows: B1: divide the space vector diagram into 6 large sectors according to the SVPWM method, and reconstruct each large sector into 4 small sectors from 6 small sectors; include a virtual zero vector in a large sector V VZ , a first virtual small vector V VS1 , a second virtual small vector V VS2 , a virtual middle vector V VM , a first virtual large vector V VL1 , and a second virtual large vector V VL2 ; B2: judging the small sector where the reference voltage vector is located, using three adjacent virtual vectors to synthesize the reference voltage vector, specifically as follows: in the first small sector A1, using V VS1 、 V VZ 、 V VM to synthesize the reference voltage vector; in the second small sector A2, using V VS2 、 V VZ 、 V VM to synthesize the reference voltage vector; in the third small sector A3, using V VS1 、 V VM 、 V VL1 to synthesize the reference voltage vector; in the fourth small sector A4, using V VS2 、 V VM 、 V VL2 to synthesize the reference voltage vector.

4. The full range optimized modulation method of three-level inverter bus capacitor current according to claim 3, characterized in that, The specific steps of step C are as follows: Step C1: first virtual small vector V VS1 , second virtual small vector V VS2 Two basic voltage vectors with opposite effects on the midpoint potential are used for synthesis, and there are three synthesis methods with different contributions to the midpoint current amplitude. Vector synthesis method one introduces a midpoint current amplitude of |Ib|, vector synthesis method two introduces a midpoint current amplitude of |Ic|, and vector synthesis method three introduces a midpoint current amplitude of |Ia|. |Ia|, |Ib|, and |Ic| represent the amplitudes of the three-phase load currents at the current time, respectively. V VZ Use basic zero vector V OOO ; virtual middle vector V VM Use basic middle vector V PON ; first virtual large vector V VL1 and second virtual large vector V VL2 Use basic large vector V PNN and V PPN ; Step C2: judging the load type, switching the first virtual small vector for different power factor angles V VS1 and the second virtual small vector V VS2 The synthesis strategy makes the neutral point current flowing through the neutral point the minimum value of the three-phase current in the current sector.

5. The full range optimized modulation method of three-level inverter bus capacitor current according to claim 4, characterized in that, In step C2, vector synthesis method three is used when the power factor angle is in the range of (-5π / 12, -π / 6); vector synthesis method one is used when the power factor angle is in the range of (-π / 6, π / 6); vector synthesis method two is used when the power factor angle is in the range of (π / 6, 5π / 12); and the synthesis strategy of the SVPWM method is used when the power factor angle is in the range of (-π / 2, -5π / 12) and (5π / 12, π / 2); In vector synthesis method one: ； where P represents the P state, i.e. the output voltage of the inverter is the state in which is the state in which is the state in which is the state in which is the state in which​ represents a three-phase switching state of OOO, i.e. a basic zero vector in which phases A, B, C are connected to the neutral point (O); represents a three-phase switching state of PON, i.e. a basic middle vector in which phase A is connected to the positive busbar (P), phase B is connected to the neutral point (O), and phase C is connected to the negative busbar (N); represents a three-phase switching state of ONO, i.e. a basic small vector in which phases A, C are connected to the neutral point (O), and phase B is connected to the negative busbar (N); represents a three-phase switching state of OPO, i.e. a basic small vector in which phases A, C are connected to the neutral point (O), and phase B is connected to the positive busbar (P); represents a three-phase switching state of PNN, i.e. a basic large vector in which phase A is connected to the positive busbar (P), and phases B, C are connected to the negative busbar (N); represents a three-phase switching state of PPN, i.e. a basic large vector in which phases A, B are connected to the positive busbar (P), and phase C is connected to the negative busbar (N); In vector synthesis method two: ； wherein, represents a basic middle vector for which the three-phase switching state is PNO, i.e. A is connected to the positive busbar (P), B is connected to the negative busbar (N) and C is connected to the neutral point (O); represents a basic small vector for which the three-phase switching state is OON, i.e. A and B are connected to the neutral point (O) and C is connected to the negative busbar (N); represents a basic small vector for which the three-phase switching state is PPO, i.e. A and B are connected to the positive busbar (P) and C is connected to the neutral point (O); In vector synthesis method three: ； wherein, represents a basic small vector for which the three-phase switching state is P00, i.e. the A phase is connected to the positive busbar (P) and the B, C phases are connected to the neutral point (O), represents a basic small vector for which the three-phase switching state is ONN, i.e. the A phase is connected to the neutral point (O) and the B, C phases are connected to the negative busbar (N), represents a basic small vector for which the three-phase switching state is OPN, i.e. the A phase is connected to the neutral point (O) and the B phase is connected to the positive busbar (P) and the C phase is connected to the negative busbar (N).

6. The full range optimized modulation method of three-level inverter bus capacitor current as claimed in claim 4 wherein, The vector action sequence corresponding to vector synthesis method one of the four small sectors is as follows: A1: [PON]-[OOO]-[ONO]-[OOO]-[PON]; A2: [PON]-[OOO]-[OPO]-[OOO]-[PON]; A3: [PON]-[PNN]-[ONO]-[PNN]-[PON]; A4: [PON]-[PPN]-[OPO]-[PPN]-[PON]; The vector action sequence of the corresponding vector synthesis mode two of the four small sectors is as follows: A1: [OOO]-[OON]-[PON]-[PNO]-[PON]-[OON]-[OOO]; A2: [OOO]-[OON]-[PON]-[PPO]-[PON]-[OON]-[OOO]; A3: [OON]-[PON]-[PNN]-[PNO]-[PNN]-[PON]-[OON]; A4: [OON]-[PON]-[PPN]-[PPO]-[PPN]-[PON]-[OON]; The vector action sequence of the corresponding vector synthesis mode three of the four small sectors is as follows: A1: [OOO]-[POO]-[PON]-[ONN]-[PON]-[POO]-[OOO]; A2: [OOO]-[POO]-[PON]-[OPN]-[PON]-[POO]-[OOO]; A3: [POO]-[PON]-[PNN]-[ONN]-[PNN]-[PON]-[POO]; A4: [POO]-[PON]-[PPN]-[OPN]-[PPN]-[PON]-[POO].

7. The full range optimized modulation method of three-level inverter bus capacitor current as claimed in claim 4 wherein, In the step D, the vector action sequence follows the following principles: D1: When the switching state is switched from P to N or N to P, the state O needs to be used for transition to prevent the direct-through of the switch tube from causing serious damage to the inverter; D2: Preferentially select the vector action sequence with less switching times of each phase switch.

8. The full range optimized modulation method of three-level inverter bus capacitor current of claim 1, wherein, In the step E, the modulation wave signal required is calculated according to the vector action sequence and the vector action time, and the carrier wave signal of different sections is calculated, the modulation wave signal is compared with the carrier wave signal to output the PWM signal, and the switch tube is controlled.

9. The full range optimized modulation method of three-level inverter bus capacitor current of claim 1, wherein, The three-level inverter is a T-type inverter, an NPC-type inverter or a hybrid ANPC inverter.

10. The full range optimized modulation method of three-level inverter bus capacitor current of claim 9, wherein, The three-level inverter is a T-type inverter, which comprises a direct current power supply (U dc ); a positive electrode of the direct current power supply (U dc ) is electrically connected with one end of a capacitor (C1), a drain of an A switch tube one (S a1 ), a drain of a B switch tube one (S b1 ) and a drain of a C switch tube one (S c1 ). The negative pole of the direct current power supply (U dc ) is electrically connected to one end of the lower capacitor (C2), the source of the fourth A switch tube (S a4 ), the source of the fourth B switch tube (S b4 ), and the source of the fourth C switch tube (S c4 ). The other end of the upper capacitor (C1) and the other end of the lower capacitor (C2) are electrically connected to the neutral point (O). The neutral point (O) is electrically connected to the drain of the second A switch tube (S a2 ), the drain of the second B switch tube (S b2 ), and the drain of the second C switch tube (S c2 ). The source of the A switch tube two (S a2 ) is electrically connected with the source of the A switch tube three (S a3 ), the drain of the A switch tube three (S a3 ) is electrically connected with the source of the A switch tube one (S a1 ) and one end of the A phase filter inductor, and the other end of the A phase filter inductor is electrically connected with the A phase end of the load. The source of the B switch tube two (S b2 ) is electrically connected with the source of the B switch tube three (S b3 ), the drain of the B switch tube three (S b3 ) is electrically connected with the source of the B switch tube one (S b1 ) and one end of the B phase filter inductor, and the other end of the B phase filter inductor is electrically connected with the B phase end of the load. The source of the C switch tube two (S C2 ) is electrically connected to the source of the C switch tube three (S c3 ), the drain of the C switch tube three (S c3 ) is electrically connected to the source of the C switch tube one (S c1 ) and one end of the C phase filter inductor, and the other end of the C phase filter inductor is electrically connected to the C phase end of the load.

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