Dual-core quadrature LC oscillator circuit and module

Abstract

The invention discloses a dual-core quadrature LC oscillator circuit and module, and relates to the technical field of quadrature LC oscillators. According to the invention, a master-slave dual-core design is adopted, the output of the quadrature phase is realized through a mutual injection locking mode, the number and power consumption of oscillators are effectively reduced, and the layout area of the circuit is reduced. According to the invention, on one hand, the negative resistance unit of the noise circulation structure is connected with the resonant cavity, so that a part of thermal noise generated by the transistor can circulate in the negative resistance unit under the condition that the negative resistance is not changed to reduce the amount of noise entering the resonant cavity, and on the other hand, phase shift is carried out on an injected signal by adopting a passive phase shift network technology; noise influence generated by an active device is directly avoided physically, so that the total noise amount injected into the resonant cavity is reduced, and the phase noise of the oscillator is effectively optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of quadrature LC oscillator, more particularly, it relates to: 1. A dual-core quadrature LC oscillator circuit; 2. A dual-core quadrature LC oscillator module. BACKGROUND

[0002] Quadrature LC oscillator is a kind of element based on inductance L and capacitance C to form a frequency selection network and can output sine wave and cosine wave at the same time, common types are: digital control type, voltage control type, and are widely used in wireless communication, radar and imaging system fields.

[0003] The traditional quadrature LC oscillator is generally composed of one main oscillator and two slave oscillators, and the signal injection is realized through active devices, which has the disadvantages of large circuit area and high power consumption; Moreover, the phase noise of the main oscillator and the noise generated by the active device will be injected into the resonant cavity of the slave oscillator, thereby deteriorating the overall phase noise characteristics and leading to high phase noise. SUMMARY

[0004] Therefore, it is necessary to provide a dual-core quadrature LC oscillator circuit and module to solve the problems of large circuit area, high power consumption and high overall phase noise of the traditional quadrature LC oscillator.

[0005] The present application adopts the following technical solutions: In a first aspect, the present application provides a dual-core quadrature LC oscillator circuit, which comprises: two LC oscillators that inject each other and have no master-slave relationship.

[0006] The first LC oscillator comprises: a first resonant cavity based on inductance-capacitance resonance to generate I-channel oscillation signal VoutI ＋ ~VoutI - A first noise circulating structure negative resistance unit connected to the first resonant cavity and used to reduce thermal noise injection into the first resonant cavity under the condition of providing constant negative resistance, and a first passive phase-shifting and current-limiting unit connected to the first noise circulating structure negative resistance unit and used to inject Q-channel oscillation signal VoutQ ＋ ~VoutQ -

[0007] The second LC oscillator comprises: a second resonant cavity based on inductance-capacitance resonance to generate VoutQ ＋ ~VoutQ - A second noise circulating structure negative resistance unit connected to the second resonant cavity and used to reduce thermal noise injection into the second resonant cavity under the condition of providing constant negative resistance, and a first passive phase-shifting and current-limiting unit connected to the first noise circulating structure negative resistance unit and used to inject Q-channel oscillation signal VoutQ ＋ ~VoutI - ​The second passive phase-shifting and current-limiting unit.

[0008] VoutI ＋ VoutQ - VoutI - VoutQ ＋ The phases of the two output signals are sequentially 90 degrees apart.

[0009] The implementation of the dual-core quadrature LC oscillator circuit is based on the method or process according to the embodiments of the present disclosure.

[0010] In the second aspect, the present disclosure discloses a dual-core quadrature LC oscillator module, which adopts the dual-core quadrature LC oscillator circuit layout disclosed in the first aspect.

[0011] The implementation of the dual-core quadrature LC oscillator module is based on the method or process according to the embodiments of the present disclosure.

[0012] Compared with the prior art, the present disclosure has the following beneficial effects: 1. The present disclosure adopts a dual-core design without master and slave, and realizes the output of quadrature phases by mutual injection locking, effectively reducing the number of oscillators and power consumption, and reducing the circuit layout area.

[0013] 2. On one hand, the present disclosure adopts a noise circulation structure negative resistance unit connected with a resonant cavity, which can circulate a part of the thermal noise generated by the transistor inside to reduce the noise amount entering the resonant cavity while providing constant negative resistance, and on the other hand, the present disclosure adopts a passive phase-shifting network technology to phase-shift the injected signal, which directly avoids the noise influence of active devices in physics, thereby reducing the total noise amount injected into the resonant cavity and effectively optimizing the phase noise of the oscillator. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0015] Figure 1 The architecture diagram of the dual-core quadrature LC oscillator circuit provided for the embodiment 1 of the present disclosure; Figure 2 The circuit diagram of the fine tuning capacitor array for Figure 1 The circuit diagram of the resonant cavity for the digital controlled oscillator; Figure 3 The circuit diagram of the fine tuning capacitor array for Figure 2 The circuit diagram of the resonant cavity for the digital controlled oscillator; Figure 4 Figure 2 ​Circuit diagram of the middle coarse tuning capacitance array; Figure 5 For Figure 2 Circuit diagram of the middle fine tuning capacitance array; Figure 6 For Figure 1 Circuit diagram of the voltage-controlled oscillator resonant cavity; Figure 7 Signal simulation diagram provided for the embodiment 2 of the present application; Figure 8 Oscillator phase noise comparison diagram provided for the embodiment 2 of the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0017] It should be noted that when a component is referred to as being "mounted on" another component, it can be directly on the other component or there can be a middle component. When a component is referred to as being "disposed on" another component, it can be directly disposed on the other component or there can be a middle component. When a component is referred to as being "fixed on" another component, it can be directly fixed on the other component or there can be a middle component.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and the like are specifically intended to be open-ended terms. The terms "or / and" as used herein encompass any and all combinations of one or more of the associated listed items.

[0019] Embodiment 1 Referring to Figure 1 , which shows a dual-core quadrature LC oscillator circuit provided by the present embodiment 1, which adopts a dual-core design and includes: 2 LC oscillators that are mutually injection-locked and have no master-slave distinction, for generating an I-channel oscillation signal VoutI ＋ ~VoutI - , a Q-channel oscillation signal VoutQ ＋ ~VoutQ - .

[0020] , VoutQ ＋ , VoutQ - , VoutI- VoutQ ＋ The phases of the elements are successively 90° apart.

[0021] It should be noted that, as Figure 1 As shown, the two LC oscillators have the same structure and can be divided into three functional regions: resonant cavity, noise loop structure negative resistance unit, and passive phase shift and current limiting unit. The difference lies in the fact that the injected signal and the output signal are different.

[0022] Specifically: I. The first LC oscillator includes: a first resonant cavity, a first noise loop structure negative resistance unit, and a first passive phase shifting and current limiting unit.

[0023] ① The first resonant cavity generates VoutI based on inductor-capacitor resonance. ＋ ~VoutI - .

[0024] Generally, the first resonant cavity is designed to include: a fixed inductor L and a tuning capacitor section connected in parallel. L is a differential inductor, with its center tap connected to the power supply VDD. In the first resonant cavity: L and the first terminal of the tuning capacitor section collectively output VoutI. + The second end summarizes and outputs VoutI - .

[0025] LC oscillators are mainly divided into two categories: digitally controlled oscillators (DCO) and voltage-controlled oscillators (VCO). The difference lies in the design of the tuning capacitor section. I. See Figure 2 If a numerically controlled type is used, the tuning capacitor section can be designed to include: one coarse tuning capacitor array, one intermediate tuning capacitor array, and one fine tuning capacitor array connected in parallel. Then, the first ends of the coarse tuning capacitor array, the intermediate tuning capacitor array, and the fine tuning capacitor array are combined to form the first end of the tuning capacitor section, and the second ends are combined to form the second end of the tuning capacitor section.

[0026] For the coarse-adjustment capacitor array, it is used for: based on the coarse-adjustment thermometer code CB[2] C -1:0] (i.e., including 2) C coarse adjustment thermometer code CB[0]~CB[2 C -1) Perform coarse frequency adjustment on the C bits. See [link / reference] Figure 3 The coarse-tuning capacitor array can be designed to include: 2 capacitors connected in parallel. C A coarse adjustment capacitor unit. Taking the c-th coarse adjustment capacitor unit as an example, it can be designed to include: one NMOS switch NM8, two fixed capacitors C8~C9, two fixed resistors R8~R9, and one inverter INV. CTU; in the cth coarse tuning capacitor unit: the drain of NM8 is connected to the first end of capacitor C8, the second end of R8, the source is connected to the first end of C9, the second end of R9, and the gate is connected to CB[c-1]; the first ends of R8-R9 are connected to the output of INV CTU , and the input end of INV CTU is connected to CB[c-1]; c∈[1,2 C ]. In addition, the second ends of all C8 in the coarse tuning capacitor array are collectively the first end of the coarse tuning capacitor array, and the second ends of all C9 are collectively the second end of the coarse tuning capacitor array. In this way, the NM8 switch is controlled by CB[c-1] to change the capacitance value connected to the resonant cavity, realizing frequency coarse tuning.

[0027] For the middle tuning capacitor array, it is used for: based on the middle tuning thermometer code MB[2 M -1:0] (i.e. including 2 M middle tuning thermometer codes MB[0]-MB[2 M -1]) to perform M-bit frequency middle tuning. Referring to Figure 4 , the middle tuning capacitor array can be designed to include: 2 M middle tuning capacitor units in parallel. Taking the mth middle tuning capacitor unit as an example, it can be designed to include: 1 NMOS switch NM9, 2 constant value capacitors C 10 -C 11 , 2 constant value resistors R 10 -R 11 , 1 inverter INV MTU ; in the mth middle tuning capacitor unit: the drain of NM9 is connected to the first end of capacitor C 10 , the second end of R 10 , the source is connected to the first end of C 11 , the second end of R 11 , and the gate is connected to MB[m-1]; the first ends of R 10 -R 11 are connected to the output of INV MTU , and the input end of INV MTU is connected to MB[m-1]; m∈[1,2 M ]. In addition, the second ends of all C 10 in the middle tuning capacitor array are collectively the first end of the middle tuning capacitor array, and the second ends of all C 11 are collectively the second end of the middle tuning capacitor array. In this way, the NM9 switch is controlled by MB[m-1] to change the capacitance value connected to the resonant cavity, realizing frequency middle tuning.

[0028] It should be noted that "middle tuning" here is relative to "coarse tuning" and "fine tuning", indicating medium precision adjustment.

[0029] For fine-tuned capacitor arrays, they are used for: based on fine-tuned thermometer code FB[2] F -1:0] (i.e., including 2) F The medium-regulation thermometer code FB[0]~FB[2 F -1) Perform F-bit frequency fine-tuning. See [link / reference] Figure 5 Taking the f-th fine-tuning capacitor unit as an example, it can be designed to include: two PMOS switches PM4~PM5; in the f-th fine-tuning capacitor unit: the drain of PM4 is connected to the drain of PM5, and the source is connected to the source of PM5; the substrates of PM4~PM5 are connected to ground VSS, FB[f-1]; f∈[1,2 f Furthermore, the gates of all PM4s in the fine-tuning capacitor array are combined to form the first end of the fine-tuning capacitor array, and the gates of all PM5s are combined to form the second end of the fine-tuning capacitor array. In this way, the connection state of PM4~PM5 is adjusted by FB[f-1] to change the capacitance value connected to the resonant cavity, thereby achieving frequency fine-tuning.

[0030] It is important to note that C < M < F. Commonly used values ​​are C=5, M=6, and F=7, but these values ​​can be adjusted according to actual precision requirements. Furthermore, it should be noted that the structures of the three types of tuned capacitor arrays mentioned above can also be varied according to specific needs.

[0031] II. See Figure 6 If a voltage-controlled type is used, the tuning capacitor section can be designed to include two varactor transistors, VAR0 and VAR1, connected in series. The input terminals of VAR0 and VAR1 are connected to the tuning voltage V. CTRL The output of VAR0 and the first terminal of L are combined to form the first terminal of C, and the output of VAR1 and the second terminal of L are combined to form the second terminal of C. Thus, through V... CTRL Tuning is achieved by adjusting the capacitance values ​​of the two varactor tubes, thereby changing the capacitance value connected to the resonant cavity. Similarly, the structure of the tuning capacitor section can be modified according to actual needs.

[0032] ② The negative resistance unit of the first noise loop structure is connected to the first resonant cavity and is used to reduce thermal noise injected into the first resonant cavity while providing constant negative resistance.

[0033] See Figure 1 The first noise cycle structure negative resistance unit adopts the following design, which includes: 2 NMOS transistors NM0~NM1, 2 PMOS transistors PM0~PM1, 2 coupling capacitors C0~C1, and 2 bias resistors R0~R1.

[0034] The drain connection of NM0 is VoutI. + The source is connected to the source of PM0, and the gate is connected to VoutI. - The drain connection of NM1 is VoutI.- The source is connected to the source of PM1, and the gate is connected to VoutI. + The drain of PM0 is used to connect to the first passive phase-shifting and current-limiting unit, and its gate is connected to the first terminal of C1 and the first terminal of R0; the drain of PM1 is used to connect to the first passive phase-shifting and current-limiting unit, and its gate is connected to the first terminal of C0 and the first terminal of R1; the second terminal of C0 is connected to VoutI. - The second end of C1 is connected to VoutI. + The second terminals of R0~R1 are connected to the bias voltage V. bias0 .

[0035] Among them, NM0~NM1 are negative resistance transistors.

[0036] It should be noted that the first noise cycling structure negative resistance unit is an adjustment based on cross-coupling. It adds PMOS transistors (PM0~PM1) connected to the sources of the two negative resistance transistors (NM0~NM1), and couples the gates of PM0~PM1 to the first resonant cavity via coupling capacitors (C0~C1) and DC biased via bias resistors (R0~R1). By making the transconductance of NM0 the same as that of PM0, and the transconductance of NM1 the same as that of PM1, the equivalent negative resistance of the entire negative resistance unit after adding PM0~PM1 remains consistent with that without cross-coupling, ensuring sufficient negative resistance and preventing insufficient resistance. Furthermore, the addition of PM0~PM1 allows a portion of the thermal noise generated by NM0~NM1 to circulate within the negative resistance unit, rather than being entirely injected into the first resonant cavity.

[0037] ③ The first passive phase-shifting and current-limiting unit is connected to the first noise loop structure negative resistance unit, and is passively injected with VoutQ. ＋ ~VoutQ - .

[0038] See Figure 1 The first passive phase-shifting and current-limiting unit adopts the following design, which includes: two NMOS transistors NM2~NM3, two coupling capacitors C2~C3, and two bias resistors R2~R3.

[0039] The drain of NM2 is connected to the negative resistance unit of the first noise cycle structure and to the drain of PM0. Its source is connected to ground VSS, and its gate is connected to the second terminal of C2 and the first terminal of R2. The drain of NM3 is connected to the negative resistance unit of the first noise cycle structure and to the drain of PM1. Its source is connected to ground VSS, and its gate is connected to the second terminal of C3 and the first terminal of R3. The first terminal of C2 is connected to VoutQ. - The first end of C3 is connected to VoutQ. + The second terminals of R2~R3 are connected to the bias voltage V.bias1 .

[0040] NM2 to NM3 act as a pair of split tail current transistors to achieve current limiting. NM2 to NM3 will generate corresponding gate-source parasitic capacitances C. gs2 ~C gs3 (It does not actually exist, but is equivalent to it), and works with C2~C3 and R2~R3 to achieve passive phase shifting.

[0041] So, VoutQ ＋ ~VoutQ - After being phase-shifted and amplitude-attenuated by the first passive phase-shifting and current-limiting unit, it is injected into the first LC oscillator to achieve VoutI. ＋ ~VoutI - The output of VoutQ is directly avoided by the fact that the first passive phase-shifting and current-limiting unit does not introduce active devices to inject signals, thus physically avoiding the noise effects generated by active devices; and VoutQ ＋ ~VoutQ - The current is injected into the gate of the split tail current transistor through C2~C3 (which are passive devices), thereby controlling the current source to turn on alternately in each cycle, which can also reduce the power consumption to a certain extent.

[0042] II. Similar to the first LC oscillator, the second LC oscillator includes: a second resonant cavity, a second noise loop structure negative resistance unit, and a second passive phase shifting and current limiting unit.

[0043] ① The second resonant cavity generates VoutQ based on inductor-capacitor resonance. ＋ ~VoutQ - .

[0044] The second resonant cavity has the same structure as the first resonant cavity, and is also designed to include: a fixed inductor L connected in parallel and a tuning capacitor section. L is a differential inductor, with its center tap connected to the power supply VDD.

[0045] However, it should be noted that in the second resonant cavity: L and the first terminal of the tuning capacitor section sum up to output VoutQ. + The second end summarizes and outputs VoutQ. - .

[0046] For details on the design of the tuning capacitor section, please refer to the relevant introduction for the first LC oscillator; it will not be repeated here.

[0047] ② The negative resistance unit of the second noise loop structure is connected to the second resonant cavity and is used to reduce thermal noise injected into the second resonant cavity while providing constant negative resistance.

[0048] See Figure 1Similar to the first noise cycle structure negative resistance unit, the first noise cycle structure negative resistance unit adopts the following design, which includes: 2 NMOS transistors NM4~NM5, 2 PMOS transistors PM2~PM3, 2 coupling capacitors C4~C5, and 2 bias resistors R4~R5.

[0049] NM4 drain connection VoutQ + The source is connected to the source of PM2, and the gate is connected to VoutQ. - The drain connection of NM5 is VoutI. - The source is connected to the source of PM3, and the gate is connected to VoutQ. + The drain of PM2 is used to connect to the second passive phase-shifting and current-limiting unit, and its gate is connected to the first terminal of C4 and the first terminal of R4; the drain of PM3 is used to connect to the second passive phase-shifting and current-limiting unit, and its gate is connected to the first terminal of C5 and the first terminal of R5; the second terminal of C4 is connected to VoutQ. - The second end of C5 is connected to VoutQ. + The second terminals of R4~R5 are connected to the bias voltage V. bias0 .

[0050] Among them, NM4~NM5 are negative resistance tubes; the transconductance of NM4 is the same as that of PM2; the transconductance of NM5 is the same as that of PM3.

[0051] Because it adopts the same structural design as the negative resistance unit of the first noise cycling structure, the negative resistance unit of the second noise cycling structure will not cause insufficient negative resistance, and can make a part of the thermal noise generated by NM4~NM5 circulate inside the negative resistance unit instead of being injected entirely into the second resonant cavity.

[0052] ③ The second passive phase-shifting and current-limiting unit is connected to the second noise loop structure negative resistance unit, and is passively injected with VoutI. ＋ ~VoutI - .

[0053] See Figure 1 Similar to the first passive phase-shifting and current-limiting unit, the second passive phase-shifting and current-limiting unit adopts the following design, which includes: two NMOS transistors NM6~NM7, two coupling capacitors C6~C7, and two bias resistors R6~R7. The drain of NM6 is used to connect to the negative resistance unit of the second noise cycle structure and to the drain of PM2. Its source is connected to ground VSS, and its gate is connected to the second terminal of C6 and the first terminal of R6. The drain of NM7 is used to connect to the negative resistance unit of the second noise cycle structure and to the drain of PM3. Its source is connected to ground VSS, and its gate is connected to the second terminal of C7 and the first terminal of R7. The first terminal of C7 is connected to VoutI. - The first end of C6 is connected to VoutI.+ The second terminals of R6~R7 are connected to the bias voltage V. bias1 .

[0054] Among them, NM6~NM7 are a pair of split tail current tubes.

[0055] Because it adopts the same structural design as the first passive phase-shifting and current-limiting unit, the second passive phase-shifting and current-limiting unit can also physically avoid the noise effect generated by active devices and reduce operating power consumption to a certain extent.

[0056] In summary, the dual-core quadrature LC oscillator circuit described above eliminates the traditional master and slave oscillators, requiring only two LC oscillators to achieve quadrature signal output. This effectively reduces the number of oscillators, power consumption, and circuit layout area. Furthermore, circuit improvements to the LC oscillators effectively reduce oscillator phase noise.

[0057] This embodiment 1 also discloses a dual-core quadrature LC oscillator module, which adopts the layout of the dual-core quadrature LC oscillator circuit disclosed in embodiment 1. The modular packaging makes it easier to promote and apply the aforementioned circuit.

[0058] Of course, the above dual-core quadrature LC oscillator circuit can also be designed as a chip—if designed as a chip, the corresponding terminals can be designed as pins.

[0059] Example 2 To demonstrate the effectiveness and superiority of the dual-core quadrature LC oscillator circuit proposed in Example 1, Example 2 constructs a corresponding numerically controlled dual-core quadrature LC oscillator based on the circuit results of Example 1, and conducts simulation experiments.

[0060] 1. Signal simulation was performed on the constructed numerically controlled dual-core quadrature LC oscillator. See the results below. Figure 7 —It showcased VoutI ＋ VoutQ - VoutI - VoutQ ＋ The time-domain waveform.

[0061] Depend on Figure 7 It can be seen that VoutI ＋ VoutQ - VoutI - VoutQ ＋ It consists of four oscillation signals with a 90-degree phase difference, which meets the requirements for quadrature oscillation output.

[0062] 2. The phase noise of the constructed numerically controlled dual-core quadrature LC oscillator was compared with that of the traditional quadrature LC oscillator. See the results below.Figure 8 —It demonstrates how the phase noise of two quadrature LC oscillators changes with frequency shift.

[0063] Depend on Figure 8 It can be seen that, in quadrature LC oscillators, the 10 is of greater concern. 4 ~10 7 In the Hz frequency offset range, the phase noise of the digitally controlled dual-core quadrature LC oscillator is significantly lower than that of the traditional quadrature LC oscillator, which is a great advantage.

[0064] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A dual-core quadrature LC oscillator circuit, characterized in that, It includes: Two mutually injected and locked LC oscillators, without master-slave distinction; The first LC oscillator includes: an I-channel oscillation signal VoutI generated based on inductor-capacitor resonance. ＋ ~VoutI - The first resonant cavity, connected to the first resonant cavity, and used to reduce thermal noise injection into the first resonant cavity while providing constant negative resistance, and the first noise loop structure negative resistance unit connected to the first noise loop structure negative resistance unit, and passively injecting the Q-path oscillation signal VoutQ. ＋ ~VoutQ - The first passive phase-shifting and current-limiting unit; The second LC oscillator includes: VoutQ generated based on inductor-capacitor resonance. ＋ ~VoutQ - The second resonant cavity, connected to the second resonant cavity, and used to reduce thermal noise injection into the second resonant cavity while providing constant negative resistance, and the second noise loop structure negative resistance unit connected to the second noise loop structure negative resistance unit and passively injected VoutI ＋ ~VoutI - The second passive phase-shifting and current-limiting unit; Among them, VoutI ＋ VoutQ - VoutI - VoutQ ＋ The phases of the elements are successively 90° apart.

2. The dual-core quadrature LC oscillator circuit according to claim 1, characterized in that, The first noise cycling structure negative resistance unit includes: 2 NMOS transistors NM0~NM1, 2 PMOS transistors PM0~PM1, 2 coupling capacitors C0~C1, and 2 bias resistors R0~R1; The drain connection of NM0 is VoutI. + The source is connected to the source of PM0, and the gate is connected to VoutI. - The drain connection of NM1 is VoutI. - The source is connected to the source of PM1, and the gate is connected to VoutI. + The drain of PM0 is used to connect to the first passive phase-shifting and current-limiting unit, and its gate is connected to the first terminal of C1 and the first terminal of R0; the drain of PM1 is used to connect to the first passive phase-shifting and current-limiting unit, and its gate is connected to the first terminal of C0 and the first terminal of R1; the second terminal of C0 is connected to VoutI. - The second end of C1 is connected to VoutI. + The second terminals of R0~R1 are connected to the bias voltage V. bias0 ; Among them, the transconductance of NM0 is the same as that of PM0; the transconductance of NM1 is the same as that of PM1.

3. The dual-core quadrature LC oscillator circuit according to claim 2, characterized in that, The first passive phase-shifting and current-limiting unit includes: two NMOS transistors NM2~NM3, two coupling capacitors C2~C3, and two bias resistors R2~R3; The drain of NM2 is connected to the negative resistance unit of the first noise cycle structure and to the drain of PM0. Its source is connected to ground VSS, and its gate is connected to the second terminal of C2 and the first terminal of R2. The drain of NM3 is connected to the negative resistance unit of the first noise cycle structure and to the drain of PM1. Its source is connected to ground VSS, and its gate is connected to the second terminal of C3 and the first terminal of R3. The first terminal of C2 is connected to VoutQ. - The first end of C3 is connected to VoutQ. + The second terminals of R2~R3 are connected to the bias voltage V. bias1 .

4. The dual-core quadrature LC oscillator circuit according to claim 1, characterized in that, The second noise cycling structure negative resistance unit includes: 2 NMOS transistors NM4~NM5, 2 PMOS transistors PM2~PM3, 2 coupling capacitors C4~C5, and 2 bias resistors R4~R5; NM4 drain connection VoutQ + The source is connected to the source of PM2, and the gate is connected to VoutQ. - The drain connection of NM5 is VoutI. - The source is connected to the source of PM3, and the gate is connected to VoutQ. + The drain of PM2 is used to connect to the second passive phase-shifting and current-limiting unit, and its gate is connected to the first terminal of C4 and the first terminal of R4; the drain of PM3 is used to connect to the second passive phase-shifting and current-limiting unit, and its gate is connected to the first terminal of C5 and the first terminal of R5; the second terminal of C4 is connected to VoutQ. - The second end of C5 is connected to VoutQ. + The second terminals of R4~R5 are connected to the bias voltage V. bias0 ; Among them, the transconductance of NM4 is the same as that of PM2; the transconductance of NM5 is the same as that of PM3.

5. The dual-core quadrature LC oscillator circuit according to claim 4, characterized in that, The second passive phase-shifting and current-limiting unit includes: two NMOS transistors NM6~NM7, two coupling capacitors C6~C7, and two bias resistors R6~R7; The drain of NM6 is used to connect to the negative resistance unit of the second noise cycle structure and to the drain of PM2. Its source is connected to ground VSS, and its gate is connected to the second terminal of C6 and the first terminal of R6. The drain of NM7 is used to connect to the negative resistance unit of the second noise cycle structure and to the drain of PM3. Its source is connected to ground VSS, and its gate is connected to the second terminal of C7 and the first terminal of R7. The first terminal of C7 is connected to VoutI. - The first end of C6 is connected to VoutI. + The second terminals of R6~R7 are connected to the bias voltage V. bias1 .

6. The dual-core quadrature LC oscillator circuit according to claim 1, characterized in that, The first resonant cavity and the second resonant cavity have the same structure, both including: a fixed inductor L and a tuning capacitor section connected in parallel; L is a differential inductor, with its middle tap connected to the power supply VDD; In the first resonant cavity: L and the first terminal of the tuning capacitor section sum up to output VoutI + The second end summarizes and outputs VoutI - ; In the second resonant cavity: L and the first terminal of the tuning capacitor section sum up to output VoutQ + The second end summarizes and outputs VoutQ. - .

7. The dual-core quadrature LC oscillator circuit according to claim 6, characterized in that, The tuning capacitor section includes: a coarse tuning capacitor array, a medium tuning capacitor array, and a fine tuning capacitor array connected in parallel; The coarse adjustment capacitor array is used for: coarse adjustment thermometer code CB[2] C -1:0] performs coarse frequency adjustment of C bits; the mid-modulation capacitor array is used for: based on the mid-modulation thermometer code MB[2] M -1:0] performs M-bit frequency modulation; the fine-tuning capacitor array is used for: based on the fine-tuning thermometer code FB[2] F [-1:0] Perform F-bit frequency fine-tuning; C < M < F; The first ends of the coarse adjustment capacitor array, the intermediate adjustment capacitor array, and the fine adjustment capacitor array are combined to form the first end of the tuning capacitor section, and the second ends are combined to form the second end of the tuning capacitor section.

8. The dual-core quadrature LC oscillator circuit according to claim 7, characterized in that, The coarse-adjustment capacitor array includes: 2 capacitors connected in parallel. C One coarse adjustment capacitor unit; The c-th coarse adjustment capacitor unit includes: one NMOS switch NM8, two fixed capacitors C8~C9, two fixed resistors R8~R9, and one inverter INV. CTU In the c-th coarse adjustment capacitor unit: the drain of NM8 is connected to the first terminal of capacitor C8 and the second terminal of R8, the source is connected to the first terminal of C9 and the second terminal of R9, and the gate is connected to CB[c-1]; the first terminals of R8~R9 are connected to INV. CTU The output, INV CTU The input terminals are connected to CB[c-1]; c∈[1,2] C ]; The second ends of all C8 in the coarse adjustment capacitor array are combined to form the first end of the coarse adjustment capacitor array, and the second ends of all C9 are combined to form the second end of the coarse adjustment capacitor array. The intermediate-regulation capacitor array includes: 2 capacitors connected in parallel. M One intermediate capacitor unit; The m-th adjustment capacitor unit includes: one NMOS switch NM9 and two fixed capacitors C. 10 ~C 11 2 fixed resistors R 10 ~R 11 1 inverter INV MTU In the m-th intermediate adjustment capacitor unit: the drain connection capacitor C of NM9 10 The first end, R 10 The second end, source connection C 11 The first end, R 11 The second terminal, the gate is connected to MB[m-1]; R 10 ~R 11 The first end is connected to INV MTU The output, INV MTU The input terminals are connected to MB[m-1]; m∈[1,2] M ]; All C in the medium-tuned capacitor array 10 The second end is summarized into the first end of the medium-regulation capacitor array, and all C 11 The second end of the capacitor array is formed by combining the two ends of the capacitor array. The fine-tuning capacitor array includes: 2 capacitors connected in parallel F One fine-tuning capacitor unit; The f-th fine-tuning capacitor unit includes: two PMOS switches PM4~PM5; in the f-th fine-tuning capacitor unit: the drain of PM4 is connected to the drain of PM5, and the source is connected to the source of PM5; the substrates of PM4~PM5 are connected to ground VSS and FB[f-1]; f∈[1,2 f ]; The gates of all PM4 in the fine-tuning capacitor array are combined to form the first end of the fine-tuning capacitor array, and the gates of all PM5 are combined to form the second end of the fine-tuning capacitor array.

9. The dual-core quadrature LC oscillator circuit according to claim 6, characterized in that, The tuning capacitor section includes two varactor transistors VAR0 to VAR1 connected in series; The input terminals of VAR0 and VAR1 are connected to the tuning voltage V. CTRL The output of VAR0 and the first end of L are combined to form the first end of C, and the output of VAR1 and the second end of L are combined to form the second end of C.

10. A dual-core quadrature LC oscillator module, characterized in that, It adopts the layout of a dual-core quadrature LC oscillator circuit as described in any one of claims 1-9.

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