K-band voltage-controlled oscillator, phase-locked loop and chip based on noise circulation structure

Abstract

The application relates to the field of integrated circuits, in particular to a K-band voltage-controlled oscillator based on a noise circulation structure, a phase-locked loop and a chip. The voltage-controlled oscillator comprises an oscillation circuit and a tuning circuit. The oscillation circuit comprises an upper resonant cavity composed of a basic oscillation circuit adopting a noise circulation structure and a lower resonant cavity composed of a noise suppression circuit adopting a Colpitts structure. The oscillation circuit adopts two groups of cross-coupled negative resistances of NMOS and PMOS, the former adopts a noise circulation structure of capacitive coupling, the latter adopts a Colpitts structure, and the two are connected through a tail inductor to improve the phase noise and power consumption of the circuit. The tuning circuit adopts a variable capacitor connected to the oscillation circuit and composed of a digital-controlled capacitor array and / or a self-tuning capacitor circuit; the capacitance value of the variable capacitor is adjusted to finely adjust the oscillation frequency. The application can solve the problem that the traditional noise circulation structure oscillator is difficult to comprehensively optimize the phase noise and power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a K-band voltage-controlled oscillator based on a noise cycling structure, and its corresponding phase-locked loop and radio frequency chip. Background Technology

[0002] Microwave and millimeter-wave technologies have been widely applied in radar, communications, imaging, and navigation. Millimeter waves have shorter operating wavelengths, effectively reducing the size of devices and systems; secondly, they possess abundant spectrum resources, capable of meeting the demands of future ultra-high-speed communications. Furthermore, millimeter waves offer higher resolution in radar and imaging applications. To date, researchers have conducted extensive research on millimeter waves, and various millimeter-wave systems have been widely adopted.

[0003] However, in high-frequency domains such as the K-band, the phase noise of the oscillation signal often deteriorates, directly affecting the stability of the voltage-controlled oscillator (VCO) output signal. To address this, many researchers have innovatively optimized phase noise performance. For CLASS structures, for example, reducing the conduction angle of the negative resistance transistor in CLASS-C optimizes phase noise, while transformer coupling in CLASS-F increases the third harmonic component. Optimizing the ISF function improves phase noise. However, the traditional CLASS structure's phase noise performance optimization still has limitations, and problems such as worsening oscillation conditions, reducing oscillation amplitude, and increasing power consumption exist. Furthermore, the phase noise is still limited by the size of the noise source injected into the resonant cavity. In response, some researchers have proposed a noise-recirculating structure, which reduces injected noise through source degradation. Only a portion of the noise current flows into the resonant cavity, while the majority of the noise current circulates within the transistor, effectively reducing the amplitude of the noise source.

[0004] While traditional noise cycling structures reduce phase noise to some extent, they still have the following drawbacks: 1. It is difficult to achieve a balance between phase noise and power consumption; reducing phase noise often leads to higher power consumption. 2. The noise cycling transistor introduces additional parasitic capacitance and increases the source voltage of the cross-coupled negative resistance transistor, worsening the oscillation conditions. 3. Phase noise fluctuates significantly with the oscillation frequency. Summary of the Invention

[0005] To address the challenge of achieving comprehensive optimization of phase noise and power consumption in oscillators based on traditional noise cycling structures, this invention provides a K-band voltage-controlled oscillator based on a noise cycling structure, along with its corresponding phase-locked loop and radio frequency chip.

[0006] The technical solution provided by this invention is as follows:

[0007] This invention also includes a K-band voltage-controlled oscillator based on a noise cycling structure, comprising an oscillation circuit and a tuning circuit. The oscillation circuit includes an upper resonant cavity constructed from a basic oscillation circuit using a noise cycling structure and a lower resonant cavity constructed from a noise suppression circuit using a Colpitts structure. The DC output terminal of the upper resonant cavity is connected to the power supply terminal of the lower resonant cavity via a DC transmission channel. The noise suppression circuit consists of four PMOS transistors P1-P4, four capacitors C5-C8, and an inductor L2. One end of C5 and C6 is connected to the source of P3 and P4, serving as the power supply terminal of the lower resonant cavity; the other end of C5 is connected to one end of C7, the drain of P3, and the source of P1. The other end of C7 is connected to the drain of P1 and the gates of P2 and P4, with node E connected to the non-inverting output terminal VOP of the upper resonant cavity via an AC transmission channel. The other end of C6 is connected to one end of C8, the drain of P4, and the source of P2. The other end of C8 is connected to the drain of P2 and the gates of P1 and P3. Node F is connected to the inverting output terminal VON of the upper resonant cavity through an AC transmission channel. The two ends of L2 are connected to the drains of P1 and P2 respectively; the tap of L2 is connected to VSS.

[0008] The tuning circuit uses an adjustable capacitor connected between VOP and VON; the oscillation frequency of the oscillation circuit can be dynamically adjusted by changing the capacitance value of the adjustable capacitor.

[0009] As a further improvement of this invention, the basic oscillation circuit consists of two NMOS transistors N1 and N2, two PMOS transistors P5 and P6, two capacitors C1 and C2, two resistors R1 and R2, and one inductor L1. The drain of N2 is connected to the gate of N1 and one end of C1, serving as the inverting output terminal VON. The drain of N1 is connected to the gate of N2 and one end of C2, serving as the non-inverting output terminal VOP. The other end of C1 is connected to one end of R2 and the gate of P6; the other end of C2 is connected to one end of R1 and the gate of P5. The other ends of R1 and R2 are connected to VSS. The source of N1 is connected to the source of P5. The source of N2 is connected to the source of P6. The drain of P5 is connected to the drain of P6, serving as the DC output port of the upper resonant cavity.

[0010] As a further improvement of the present invention, in the basic oscillation circuit, the capacitance values ​​of C1 and C2 are more than 10 times the parasitic capacitances of P5 and P6.

[0011] As a further improvement of the present invention, the DC output port of the upper resonant cavity is connected to the power supply terminal of the lower resonant cavity through a wire or a tail inductor Ltail to form a DC transmission channel. Node E and VOP are connected through capacitor C3; node F and VON are connected through capacitor C4 to form an AC transmission channel.

[0012] As a further improvement of the present invention, the tuning circuit includes a numerically controlled capacitor array and / or a self-tuning capacitor circuit.

[0013] The numerically controlled capacitor array comprises multiple capacitor units connected in parallel; each capacitor unit is connected between VOP and VON via an independent switching circuit; the capacitance ratio of each capacitor unit is 1:2:4:…2. N-1 N represents the number of capacitor units in the numerically controlled capacitor array. An N-bit digital control signal switches the switching states of the circuits in each capacitor unit, thereby adjusting the oscillation frequency of the oscillation circuit.

[0014] The self-adjusting capacitor consists of two symmetrically arranged self-biased variable capacitors Cvar and one fixed capacitor C0 connected in parallel. A voltage control signal Vctrl changes the voltage difference between the positive and negative terminals of each self-biased variable capacitor Cvar, thereby continuously adjusting the oscillation frequency of the oscillation circuit.

[0015] As a further improvement of this invention, each capacitor unit consists of two PMOS transistors P7 and P8, three NMOS transistors N3 to N5, two resistors R7 and R8, and two basic capacitors C13 and C14. The sources of P7 and P8 are connected to VDD; the drain of P7 is connected to one end of R7; the other end of R7 is connected to the drain of N4, the source of N3, and one end of C13. The drain of P8 is connected to the drain of N5 through R8; the drain of P8 is connected to one end of R8; the other end of R8 is connected to the drains of N3 and N5, and one end of C14; the other ends of C13 and C14 serve as external ports for capacitor voltage and are used to connect to VOP and VON, respectively. The sources of N4 and N5 are connected to VSS; the gates of P7, P8, and N3 to N5 are connected and connected to the corresponding digital control signal B.

[0016] The two base capacitors in each capacitor cell have the same capacitance value. The ratio of the capacitance values ​​of the base capacitors in each capacitor cell, as well as the width-to-length ratio of N3, are all 1:2:4:…2. N-1 .

[0017] As a further improvement of the present invention, the self-adjusting capacitor circuit includes four variable capacitors Cvar1~Cavr4, four DC blocking capacitors C9~C12, four capacitors R3~R6, and a fixed capacitor C0. One end of C0 is connected to one end of C9 and C11, serving as one external port; the other end of C0 is connected to one end of C10 and C12, serving as the other external port. The other end of C9 is connected to one end of R3 and the positive terminal of Cvar1; the other end of C10 is connected to one end of R4 and the positive terminal of Cvar2; the other end of C11 is connected to one end of R5 and the positive terminal of Cvar3; the other end of C12 is connected to one end of R6 and the positive terminal of Cvar4. The other ends of R3 and R4 are connected to the first bias voltage VB1; the other ends of R5 and R6 are connected to the second bias voltage VB2. The negative terminals of Cvar1~Cavr4 are connected and used to connect to the voltage control signal Vctrl.

[0018] As a further improvement of the present invention, in the self-adjusting capacitor circuit, C9, C10, Cvar1, Cvar2, R3, and R4 constitute one variable capacitor branch; C11, C12, Cvar3, Cvar4, R5, and R6 constitute another variable capacitor branch; by adjusting the Kvco-V curves of the two parallel variable capacitor branches respectively through VB1 and VB2, the flatness range of the self-adjusting capacitor is increased, thereby improving the linearity of the oscillation circuit.

[0019] The present invention also includes a phase-locked loop that employs a K-band voltage-controlled oscillator based on a noise cycling structure as described above.

[0020] The present invention also includes an radio frequency chip that employs a phase-locked loop as described above.

[0021] The present invention has the following beneficial effects:

[0022] The voltage-controlled oscillator (VCO) provided by this invention employs a noise cycling technique based on an improved Colpitts structure. This VCO features two oscillation cores; a high impedance at twice the resonant frequency is provided by the tail inductor Ltail, reducing phase noise. The basic oscillation circuit based on noise cycling is stacked on top of a PMOS cross-coupled oscillator, resolving the strict trade-off between power consumption and phase noise. The degenerate transistors P5 and P6 used for noise cycling are biased in the transistor region rather than the saturation region to provide optimal delay for loop gain, resulting in more symmetrical positive and negative phase changes at the output and significantly improving the 1 / f3 phase noise of the circuit. A transconductance boosting technique is introduced at the negative resistance transistor of the noise suppression circuit based on the Colpitts structure, further optimizing power consumption and phase noise. This invention can further reduce circuit power consumption while improving the phase noise of the VCO. Attached Figure Description

[0023] Figure 1 This is a circuit diagram of a K-band voltage-controlled oscillator based on a noise cycling structure provided in Embodiment 1 of the present invention.

[0024] Figure 2 This is a circuit diagram of the capacitor unit used in the numerically controlled capacitor array of the voltage-controlled oscillator in Embodiment 1 of the present invention.

[0025] Figure 3 This is a circuit diagram of the self-adjusting capacitor circuit used in the voltage-controlled oscillator in Embodiment 1 of the present invention.

[0026] Figure 4 This is the equivalent circuit diagram of the voltage-controlled oscillator in Embodiment 1 of the present invention.

[0027] Figure 5 The circuit structure and small-signal model diagram of the voltage-controlled oscillator of the present invention and the traditional Colpitts structure are shown.

[0028] Figure 6 This is a circuit diagram of a traditional noise-controlled cyclic oscillator based on capacitive coupling used in a performance testing experiment.

[0029] Figure 7 The circuit diagram of the present invention is shown for performance testing experiments where the Colpitts structure is not used.

[0030] Figure 8 The diagram shows the positive and negative output waveforms of the oscillator of this invention at the center frequency during the test experiment.

[0031] Figure 9 The figure shows the simulation results of the phase noise of the oscillators of the present invention and the control group at the center frequency in the test experiment.

[0032] Figure 10 The figure shows the simulation results of the operating current of the oscillators of the present invention and the control group at the center frequency in the test experiment.

[0033] Figure 11 The graph shows the relationship between the phase noise of the oscillators of the present invention and the control group at different offset frequencies in the test experiment.

[0034] Figure 12 The simulation results of the frequency modulation curves of the oscillators of the present invention and the control group in the test experiment are shown in the figure. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] Example 1

[0038] To address the problem of balancing phase noise and power consumption control in existing oscillators, this embodiment introduces a Colpitts structure with gain enhancement technology on the basis of the traditional noise loop structure used in the oscillator. This new circuit structure effectively suppresses circuit power consumption while optimizing the phase noise of the oscillator, thus effectively overcoming the performance limitations of traditional oscillators.

[0039] Specifically, such as Figure 1 As shown, the K-band voltage-controlled oscillator based on a noise cycling structure provided in this embodiment includes an oscillation circuit and a tuning circuit. The tuning circuit uses a variable capacitor connected between VOP and VON; the oscillation frequency of the oscillation circuit is adjusted by regulating the capacitance value of the variable capacitor. In the voltage-controlled oscillator (VCO) of this embodiment, the oscillation circuit includes two LC resonant cavities; the upper resonant cavity is composed of a basic oscillation circuit employing a noise cycling structure; the lower resonant cavity is composed of a noise suppression circuit employing a Colpitts structure.

[0040] In this embodiment, the circuit for the fundamental oscillation of the upper cavity is a noise cycling structure composed of NMOS negative resistance transistors, consisting of two NMOS transistors N1 and N2, two PMOS transistors P5 and P6, two capacitors C1 and C2, two resistors R1 and R2, and one inductor L1. The drain of N2 is connected to the gate of N1 and one end of C1, serving as the inverting output terminal VON. The drain of N1 is connected to the gate of N2 and one end of C2, serving as the non-inverting output terminal VOP. The other end of C1 is connected to one end of R2 and the gate of P6; the other end of C2 is connected to one end of R1 and the gate of P5. The other ends of R1 and R2 are connected to VSS. The source of N1 is connected to the source of P5. The source of N2 is connected to the source of P6. The drain of P5 is connected to the drain of P6, serving as the DC output port of the upper resonant cavity.

[0041] The noise suppression circuit for the lower resonant cavity is a Colpitts structure composed of PMOS negative resistance transistors. Specifically, the noise suppression circuit consists of four PMOS transistors P1~P4, four capacitors C5~C8, and inductor L2. One end of C5 and C6 is connected to the source of P3 and P4, serving as the power supply terminal for the lower resonant cavity; the other end of C5 is connected to one end of C7, the drain of P3, and the source of P1. The other end of C7 is connected to the drain of P1 and the gates of P2 and P4, and node E is connected to the non-inverting output terminal VOP of the upper resonant cavity through an AC transmission channel. The other end of C6 is connected to one end of C8, the drain of P4, and the source of P2. The other end of C8 is connected to the drain of P2 and the gates of P1 and P3, and node F is connected to the inverting output terminal VON of the upper resonant cavity through an AC transmission channel. The two ends of L2 are connected to the drains of P1 and P2, respectively; the tap of L2 is connected to VSS.

[0042] In this embodiment, the noise suppression circuit employs a traditional transconductance enhancement technique on the PMOS negative resistor, applying it from the NMOS negative resistor to the PMOS negative resistor because PMOS has better flicker noise performance than NMOS. Figure 1 As shown in the lower half of the resonant cavity, P1 and P2 are cross-coupled negative resistors, and P3 and P4 act as current sources. The gates of P3 and P4 are directly connected to the gates of P1 and P2, which reduces the voltage margin requirement. The gate phases of P1 and P2 are the same as the drain phases of P2 and P1, respectively. Connecting them together will produce the effect of a transconductance boosting strategy. Capacitors C5, C6, C7, and C8 are feedback capacitors used to adjust the transconductance enhancement ratio. Their values ​​also affect the overall resonant frequency and phase noise performance. In this embodiment, the values ​​of each feedback capacitor can be reasonably selected through circuit simulation and testing. Compared with the direct application of traditional PMOS negative resistors, this design adopts a Colpitts structure with transconductance boosting technology, which reduces the oscillator's operating current, significantly improves power consumption, and also improves phase noise to a certain extent.

[0043] In the circuit scheme of this embodiment, the circuits of the two resonant cavities are electrically connected through a DC transmission channel and an AC transmission channel. Specifically, the DC output terminal of the upper resonant cavity is connected to the power supply terminal of the lower resonant cavity through the DC transmission channel. The positive and negative output terminals of the upper and lower resonant cavities are respectively electrically connected through AC transmission channels. In practical applications, the DC transmission channel can be implemented using a wire or a tail inductor to allow the DC signal component to pass through; while the AC channel can be implemented using a capacitor with an ideal capacitance value to allow only the AC signal component to pass through. For example, in... Figure 1In the typical circuit shown, the DC output port of the upper resonant cavity is connected to the power supply terminal of the lower resonant cavity through the tail inductor Ltail to form a DC transmission channel. Node E and VOP are connected through capacitor C3; node F and VON are connected through capacitor C4 to form an AC transmission channel.

[0044] To make the advantages of the K-band voltage-controlled oscillator based on a noise cycling structure provided in this embodiment clearer, the following provides a detailed description of the circuit's function from a circuit principle perspective:

[0045] Traditional noise cycling structures are divided into two types: transformer-coupled and capacitor-coupled. The capacitor-coupled noise cycling structure is shown in the basic oscillation circuit of the upper resonant cavity in this embodiment. The noise cycling structure... Figure 1 In this circuit, additional noise cycling transistors P5 and P6 are introduced between the sources of the negative resistance transistors N1 and N2 and the reference ground to reduce the noise injected into the LC resonant cavity by N1 and N2, thereby optimizing their contribution to phase noise. However, this circuit has a significant power consumption problem, and the additional parasitic capacitance introduced by the noise cycling transistors increases the source voltage of the cross-coupled negative resistance transistors, worsening the start-up conditions of the VCO.

[0046] In the novel oscillation circuit structure provided in this embodiment, the basic oscillation circuit and the noise suppression circuit form two resonant cavities based on capacitive coupling. The noise suppression circuit introduces additional PMOS cross-coupled negative resistance transistors P1 and P2, which serve a dual purpose: Firstly, P1 and P2 provide additional negative resistance to the upper resonant cavity, solving the problem of stringent start-up conditions in traditional noise cycling structures and reducing operating current, thus optimizing the overall power consumption of the circuit. Secondly, the introduced negative resistance transistors P1 and P2 increase the drain voltage of noise cycling transistors P5 and P6. Since the drain of the noise cycling transistor in the traditional structure is directly grounded, it has a large drain-source voltage Vds, causing the traditional noise cycling transistor to operate in the saturation region. However, in this embodiment, after P1 and P2 increase the drain voltage of P5 and P6, the drain-source voltage Vds can be made much smaller than the gate-source voltage Vgs-Vth. At this time, the noise cycling transistor operates in the linear region, which significantly reduces the contribution of the noise cycling transistor to phase noise compared to the traditional structure. Meanwhile, in the circuit of this embodiment, the gates of P5 and P6 are directly grounded through resistors. A lower gate voltage reduces the loss of the noise cycling transistor's impact on the oscillator's start-up conditions. Capacitors C1 and C2 are coupling capacitors between the NMOS negative resistance transistors N1 and N2 and the noise cycling transistors P5 and P6. Their values ​​must be much larger than the parasitic capacitances of P5 and P6 during design to avoid amplitude loss. For example, in practical applications, the capacitance values ​​of C1 and C2 can be more than 10 times the parasitic capacitances of P5 and P6. Capacitors C3 and C4 are coupling capacitors between the two cavities, maintaining consistent oscillation behavior between them. Furthermore, the two cavities are connected using a tail inductor Ltail. Compared to direct wire connection, Ltail, through a properly selected inductance value, ensures that its oscillation behavior is consistent with the oscillator's oscillation characteristics. ω A high impedance is provided at 0, which further optimizes phase noise.

[0047] In this embodiment, the tuning circuit uses an adjustable capacitor connected between VOP and VON; by changing the capacitance value of the adjustable capacitor, the oscillation frequency of the oscillation circuit can be dynamically adjusted. In practical applications, the tuning circuit of this embodiment can use any one of a digitally controlled capacitor array and a self-adjusting capacitor circuit, or a circuit that includes both. A digitally controlled capacitor array is an adjustable capacitor whose capacitance value is discretely adjusted using digital signals. In this embodiment, using a digitally controlled capacitor array in the tuning circuit allows for discrete adjustment of the oscillation frequency of the oscillation circuit "by level." A self-adjusting capacitor circuit is a variable capacitor whose capacitance value can be continuously adjusted. Based on its continuously adjustable characteristic, using a self-adjusting capacitor circuit in the tuning circuit allows for continuous adjustment of the oscillation frequency of the oscillation circuit. In practical applications, combining a digitally controlled capacitor array and a self-adjusting capacitor circuit allows for more precise control of the oscillation frequency of the oscillation circuit.

[0048] In this embodiment, the numerically controlled capacitor array includes multiple capacitor units connected in parallel; each capacitor unit is connected between VOP and VON through an independent switching circuit; the capacitance ratio of each capacitor unit is 1:2:4:…2. N-1 N represents the number of capacitor units in the numerically controlled capacitor array. An N-bit digital control signal switches the switching states of the circuits in each capacitor unit, thereby adjusting the oscillation frequency of the oscillation circuit.

[0049] Among them, such as Figure 2 As shown, each capacitor unit consists of two PMOS transistors P7 and P8, three NMOS transistors N3 to N5, two resistors R7 and R8, and two basic capacitors C13 and C14. The sources of P7 and P8 are connected to VDD; the drain of P7 is connected to one end of R7; the other end of R7 is connected to the drain of N4, the source of N3, and one end of C13. The drain of P8 is connected to the drain of N5 through R8; the drain of P8 is connected to one end of R8; the other end of R8 is connected to the drains of N3 and N5, and one end of C14; the other ends of C13 and C14 serve as external terminals for the capacitor voltage and are used to connect to VOP and VON, respectively. The sources of N4 and N5 are connected to VSS; the gates of P7, P8, and N3 to N5 are connected and connected to the corresponding digital control signal B. In each capacitor cell, the two base capacitors have the same capacitance value. The ratio of the capacitance values ​​of the base capacitors in each capacitor cell, as well as the width-to-length ratio of N3, are all 1:2:4:…2. N-1 .

[0050] In the numerically controlled capacitor array, P7 and P8 act as pull-up transistors, and N4 and N5 act as pull-down transistors. Together, they change the source-drain voltage of N3. N3 acts as a switch and directly controls whether the base capacitors on both sides can be connected to the resonant cavity. When the control signal for any capacitor unit is high, pull-up transistors P7 and P8 are turned off, pull-down transistors N4 and N5 are turned on, and the source and drain of N3 are pulled down to a low level, thus turning on N3. At this time, the base capacitors on both sides are connected to the oscillation circuit, thereby reducing the oscillation frequency of the oscillation circuit. When the control signal for any capacitor unit in the numerically controlled capacitor array is low, pull-down MOSFETs N4 and N5 are turned off, pull-up MOSFETs P7 and P8 are turned on, and the source and drain of N3 are made high through pull-up resistors R7 and R8, thus turning off N3. At this time, the base capacitors on both sides are isolated from the resonant cavity, thereby increasing the oscillation frequency of the oscillation circuit.

[0051] In a numerically controlled capacitor array, multiple parallel connections are used to increase the frequency adjustment range. This is because the capacitance values ​​of each capacitor unit are in a ratio of 1:2:4:…2. N-1Each capacitor unit can be switched on and off using a single-bit digital control signal. Therefore, an N-bit digital control signal can be used to independently adjust the connection state of each capacitor unit, thereby achieving gradient adjustment of the capacitance value connected to the oscillation circuit. The tuning accuracy of the digitally controlled capacitor array depends on the number of capacitor units introduced into the circuit. The decimal number converted from the binary digital control signal represents the multiplier of the base capacitance currently connected to the resonant cavity; this ensures consistent capacitance value changes across the entire digitally controlled capacitor array and guarantees a stable Q-value.

[0052] For example, suppose a numerically controlled capacitor array includes four capacitor units, and the digital control signals for the four capacitor units are denoted as B0, B1, B2, and B3, respectively. A 4-bit digital control signal B<3:0> can be used to gradient adjust the capacitance value of the numerically controlled capacitor array connected to the oscillation circuit, with an adjustment range of 0~15C0, where C0 represents the unit capacitance of the capacitor unit. When the digital control signal B<3:0> is set to 1111, all capacitor units are connected to the resonant cavity, resulting in the lowest oscillation frequency; when B<3:0> is set to 0000, all capacitor units are isolated from the resonant cavity, resulting in the highest oscillation frequency.

[0053] A typical self-adjusting capacitor circuit consists of two symmetrically arranged self-biased variable capacitors Cvar and one fixed capacitor C0 connected in parallel. A voltage control signal Vctrl changes the voltage difference between the positive and negative terminals of each self-biased variable capacitor Cvar, thereby continuously adjusting the oscillation frequency of the oscillation circuit. For example, the circuit diagram of the self-adjusting capacitor circuit provided in this embodiment is as follows: Figure 3 As shown, the self-adjusting capacitor circuit includes four variable capacitors Cvar1~Cavr4, four DC blocking capacitors C9~C12, four capacitors R3~R6, and a fixed capacitor C0. One end of C0 is connected to one end of C9 and C11, serving as one external port; the other end of C0 is connected to one end of C10 and C12, serving as the other external port. The other end of C9 is connected to one end of R3 and the positive terminal of Cvar1; the other end of C10 is connected to one end of R4 and the positive terminal of Cvar2; the other end of C11 is connected to one end of R5 and the positive terminal of Cvar3; the other end of C12 is connected to one end of R6 and the positive terminal of Cvar4. The other ends of R3 and R4 are connected to the first bias voltage VB1; the other ends of R5 and R6 are connected to the second bias voltage VB2. The negative terminals of Cvar1~Cavr4 are connected and used to connect to the voltage control signal Vctrl.

[0054] In the self-adjusting capacitor circuit, C9, C10, Cvar1, Cvar2, R3, and R4 form one variable capacitor branch; C11, C12, Cvar3, Cvar4, R5, and R6 form another variable capacitor branch. The fixed capacitor C0 is the coarse adjustment capacitor, directly connected to the positive and negative terminals of the resonant cavity. Changing its capacitance value can adjust the approximate upper and lower limits of the frequency, and also roughly adjust the tuning range, playing a coordinating role. Taking one of the variable capacitor branches as an example, variable capacitors Cvar1 and Cvar2 are self-biased. Capacitors C9 and C10 are used to isolate the DC signal from the resonant cavity. The first bias voltage VB1 provides bias to one end of Cvar1 and Cvar2 through resistors R3 and R4, and the other end is connected to the voltage control signal Vctrl. Changing Vctrl alters the voltage difference between Cvar1 and Cvar2, thereby changing the capacitance value of Cvar1 and adjusting the oscillation frequency.

[0055] Because the linearity range of the CV curve of a variable capacitor is limited, if the variable capacitor is directly connected to the resonant cavity, the value of V depends on the DC voltage of the oscillation. When the value of V is too large or too small, it may enter the nonlinear region or even the flat region of the CV curve, which will seriously affect the frequency tuning efficiency. However, the circuit of this embodiment, by connecting a first bias voltage VB1 to one end of the variable capacitor, can make the variable capacitor accurately positioned in the region with the best linearity of the CV curve, thereby improving the frequency adjustment efficiency.

[0056] Specifically, this embodiment employs two symmetrically arranged variable capacitor branches, connected to a first bias voltage VB1 and a second bias voltage VB2, respectively. Since the Kvco-V curve of a single variable capacitor branch approximates a downward-opening parabola, it is relatively flat near the extreme values. However, as it moves away from the extreme values, Kvco becomes sensitive to changes in the voltage difference V. Since Kvco represents the slope of the oscillation frequency F as a function of the voltage control signal Vctrl, Kvco sensitivity leads to poor linearity in the tuning curve of the oscillation circuit. Therefore, by connecting two sets of variable capacitor branches in parallel and connecting them to different first bias voltages VB1 and second bias voltages VB2, their Kvco-V curves are superimposed. The superimposed curve exhibits a significantly increased flatness range, which helps improve the linearity of the VCO tuning curve. In other words, by adjusting the Kvco-V curves of the two parallel variable capacitor branches using VB1 and VB2 respectively, the flatness range of the self-adjusting capacitor can be increased, thereby improving the linearity of the oscillation circuit.

[0057] To make the performance and advantages of the K-band voltage-controlled oscillator based on the noise cycling structure provided in this embodiment clearer, the phase noise and transconductance enhancement techniques of this circuit scheme are analyzed from the perspective of circuit principle:

[0058] First, the circuit principle of the oscillation circuit section of the voltage-controlled oscillator provided in this embodiment is as follows: Figure 4 As shown in the figure, it can be seen that the cross-coupled negative resistance transistors N1 and N2 and the noise circulation transistors P5 and P6 degrade with each other. Let the transconductance ratio be... α and β For N1, its noise current is I. n,N1 And only β· I n,N1 The noise current is injected into the resonant cavity and converted into phase noise, the remaining... α· I n,N1 A portion of the current still circulates within the device and does not contribute to phase noise. The same applies to N2. For the noise-circulating transistor P6, its noise current is I. n,P6 And only α· I n,P6 The noise current is injected into the resonant cavity, and the remaining... β· I n,P6 Some parts are retained within P6. The same applies to P5.

[0059] Therefore, for Figure 4 Considering the phase noise contributed by P1 and P2 in the lower Colpitts structure oscillator section, the differential output noise current power spectral density of the entire voltage-controlled oscillator is as follows: It can be represented as:

[0060]

[0061] In the above formula, k Represents the Boltzmann constant; T Indicates Kelvin temperature; γ This represents the noise figure of the device, which is related to the device channel length; g mn1,2 Indicates the transconductance of the device between N1 and N2; g mp5,6 Indicates the transconductance between P5 and P6; g mp1,2 Indicates the transconductance between P1 and P2; I n,P1 I represents the noise current of P1; n,P2 I represents the noise current of P2; n,P5 Indicates the noise current of P5; I n,N2 This represents the noise current of N2, and so on.

[0062] Since P5 and P6 always operate in the linear region, they can be equivalent to two resistors with a resistance of R. Therefore, the above equation can be further expressed as:

[0063]

[0064] Among them, the circuit and small-signal model of the traditional Colpitts structure, such as Figure 5Part (a) and Figure 5 As shown in section (b) of the document. This embodiment proposes a PMOS-Colpitts structure with transconductance boosting technology and its small-signal model as follows: Figure 5 Part (c) and Figure 5 As shown in section (d) of the diagram. Here, Z1 and Z2 represent the equivalent negative resistance in the conventional Colpitts structure and the circuit of this embodiment, respectively. V x and I x These are represented as the analog voltage source for calculating the equivalent negative resistance and the current flowing into the port, respectively. V S This is the source voltage of transistor N1; V S1 , V D1 , V G1 These are the source, drain, and gate voltages of P1, respectively. V S2 , V D2 , V G2 These represent the source, drain, and gate voltages of P2, respectively. 1 / sC1 and 1 / sC2 are the small-signal AC equivalent resistances of capacitors C1 and C2, respectively. g mn and g mp These represent the transconductance of NMOS and PMOS, respectively.

[0065] Analysis using the small-signal model yields the equivalent conductance Re[Y2] of the PMOS-Colpitts structure in this embodiment as follows:

[0066]

[0067] In the above formula, ω Represents angular frequency; g mp This indicates the transconductance of the negative resistance transistor.

[0068] The equivalent conductance Re[Y1] of the traditional Colpitts structure is:

[0069]

[0070] By comparison, the above two equations show that, thanks to the transconductance enhancement technology composed of differential structure and feedback capacitor, the PMOS-Colpitts structure used in this embodiment has an equivalent conductance that is increased by (2+C2 / C1) times compared to the traditional structure. This helps to optimize the oscillation conditions and can reduce circuit power consumption to a certain extent.

[0071] Example 2

[0072] Building upon the K-band voltage-controlled oscillator with lower phase noise and lower power consumption based on a noise-cycle structure provided in Example 1, this embodiment further provides a phase-locked loop (PLL) and an RF chip that employ the K-band PLL based on a noise-cycle structure as described in Example 1. Applying this PLL can improve the phase noise and power consumption of the PLL circuit and the RF chip.

[0073] To verify the performance of the K-band voltage-controlled oscillator based on a noise cycling structure provided by this invention, technicians used the complete circuit scheme of this invention as the experimental group. Figure 6 The traditional noisy cyclic voltage-controlled oscillator based on capacitive coupling shown, and such as Figure 7 The proposed solution without the Colpitts structure serves as a control group. Simulations and performance tests were conducted on the circuit schemes of each voltage-controlled oscillator using a 28nm CMOS process.

[0074] 1. Basic performance

[0075] This experiment first tested the output characteristics of the circuit of the present invention, and obtained the following results: Figure 8 The positive and negative output waveforms shown are at the center frequency of the K-band. Analysis of the data in the figure shows that the voltage-controlled oscillator provided by this invention has positive and negative output waveforms close to standard sine waves at a center frequency of 20GHz, with a common mode value of 1.2V and an amplitude of about 0.8V~1.6V. The basic performance of the circuit can meet the actual needs.

[0076] 2. Phase noise

[0077] To evaluate the noise performance of the voltage-controlled oscillator (VCO) in different schemes, this experiment further simulated the phase noise of the VCO of this invention and the control group at the center frequency. The simulation results are as follows: Figure 9 As shown.

[0078] Analysis of the data in the figure shows that the phase noise of the voltage-controlled oscillator provided by this invention is -111.9 dBc / Hz@1MHz, while the phase noise of the control group is -107 dBc / Hz@1MHz; therefore, the phase noise of the voltage-controlled oscillator of this invention is significantly reduced. The main reason for this performance advantage is likely that the circuit scheme of this invention, through a special circuit structure, allows the noise-cycled MOS transistor to always operate in the linear region.

[0079] 3. Circuit power consumption

[0080] To evaluate the power consumption advantage of the voltage-controlled oscillator provided by this invention, this experiment further simulated the operating current of the voltage-controlled oscillators of this invention and the control group at the center frequency. The simulation results are as follows: Figure 10 As shown.

[0081] Analysis of the data in the figure reveals that the operating current of the voltage-controlled oscillator of the present invention is significantly reduced, with a power consumption of only 3.42mW. Compared with the scheme that does not use the Colpitts structure, its power consumption is reduced by 0.8mW, and the power consumption of this structure is much less than the 9.97mW of the traditional noise cycling structure.

[0082] Furthermore, the above experiments can further confirm that the voltage-controlled oscillator of the present invention improves the noise loop structure, and the transconductance boosting technology used solves the limitation that the phase noise and power consumption of the traditional structure cannot be balanced. This solution optimizes the phase noise of the voltage-controlled oscillator and reduces the power consumption of the circuit.

[0083] 4. Phase noise

[0084] This experiment further compared the phase noise response with frequency in the experimental and control circuits, and obtained the following results: Figure 11 As shown in the image, analysis of the data in the image shows that the phase noise of the VCO of the present invention is stable with frequency variation, which improves the problem of large phase noise fluctuation with frequency in traditional structures.

[0085] 5. Tuning performance

[0086] This experiment further tested the effectiveness of the circuit of this invention in regulating the oscillation frequency using a combination of a 4-bit digital control signal and a voltage control signal Vctrl. The frequency response curves under different regulation strategies are shown below. Figure 12 As shown in the figure, the frequency adjustment range of the voltage-controlled oscillator of this invention is 18.3~21.5GHz, with a wide tuning range of 16.1%; the overlap rate of adjacent sub-bands is about 38.5%, ensuring the continuous tuning frequency of the oscillator throughout the entire frequency band.

[0087] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A K-band voltage controlled oscillator based on a noise-circulation structure, characterized by, It includes: The oscillation circuit includes an upper resonant cavity composed of a basic oscillation circuit employing a noise cycling structure and a lower resonant cavity composed of a noise suppression circuit employing a Colpitts structure. The DC output terminal of the upper resonant cavity is connected to the power supply terminal of the lower resonant cavity through a DC transmission channel. The noise suppression circuit consists of four PMOS transistors P1~P4, four capacitors C5~C8, and an inductor L2. One end of C5 and C6 is connected to the source of P3 and P4, serving as the power supply terminal of the lower resonant cavity. The other end of C5 is connected to one end of C7, the drain of P3, and the source of P1. The terminals of C7 and P8 are connected together; the other end of C7 is connected to the drain of P1 and the gates of P2 and P4, and the connection point is denoted as node E; node E is connected to the non-inverting output terminal VOP of the upper resonant cavity through the AC transmission channel; the other end of C6 is connected to one end of C8, the drain of P4, and the source of P2; the other end of C8 is connected to the drain of P2 and the gates of P1 and P3, and the connection point is denoted as node F; node F is connected to the inverting output terminal VON of the upper resonant cavity through the AC transmission channel; the two ends of L2 are connected to the drains of P1 and P2 respectively; the tap of L2 is connected to VSS; The tuning circuit employs an adjustable capacitor connected between VOP and VON; the oscillation frequency of the oscillation circuit can be dynamically adjusted by changing the capacitance value of the adjustable capacitor.

2. The K-band voltage controlled oscillator based on a noise-circulation structure according to claim 1, characterized in that: The basic oscillation circuit consists of two NMOS transistors N1 and N2, two PMOS transistors P5 and P6, two capacitors C1 and C2, two resistors R1 and R2, and one inductor L1. The drain of N2 is connected to the gate of N1 and one end of C1, serving as the inverting output terminal VON. The drain of N1 is connected to the gate of N2 and one end of C2, serving as the non-inverting output terminal VOP. The other end of C1 is connected to one end of R2 and the gate of P6. The other end of C2 is connected to one end of R1 and the gate of P5. The other ends of R1 and R2 are connected to VSS. The source of N1 is connected to the source of P5. The source of N2 is connected to the source of P6. The drain of P5 is connected to the drain of P6, serving as the DC output port of the upper resonant cavity.

3. The K-band voltage controlled oscillator based on a noise-circulation structure according to claim 2, characterized in that: The capacitance values ​​of C1 and C2 are more than 10 times the parasitic capacitances of P5 and P6.

4. The K-band voltage-controlled oscillator based on a noise cycling structure according to claim 1, characterized in that: The DC output port of the upper resonant cavity is connected to the power supply terminal of the lower resonant cavity through a wire or a tail inductor Ltail to form a DC transmission channel. Node E and VOP are connected via capacitor C3; Node F and VON are connected via capacitor C4 to form an AC transmission channel.

5. The K-band voltage-controlled oscillator based on a noise cycling structure according to claim 1, characterized in that: The tuning circuit includes a digitally controlled capacitor array and / or a self-tuning capacitor circuit. The numerically controlled capacitor array comprises multiple capacitor units connected in parallel; each capacitor unit is connected between VOP and VON via an independent switching circuit; the capacitance ratio of each capacitor unit is 1:2:4:…2. N-1 N represents the number of capacitor units in the numerically controlled capacitor array; the switching state of the switching circuit in each capacitor unit is switched by an N-bit digital control signal to adjust the oscillation frequency of the oscillation circuit. The self-adjusting capacitor circuit consists of two sets of symmetrically arranged self-biased variable capacitors Cvar and one fixed capacitor C0 connected in parallel. The voltage difference between the positive and negative terminals of each set of self-biased variable capacitors Cvar is changed by a voltage control signal Vctrl to continuously adjust the oscillation frequency of the oscillation circuit.

6. The K-band voltage controlled oscillator based on a noise-circuited structure according to claim 5, wherein: Each capacitor unit consists of two PMOS transistors P7 and P8, three NMOS transistors N3 to N5, two resistors R7 and R8, and two basic capacitors C13 and C14. The sources of P7 and P8 are connected to VDD. The drain of P7 is connected to one end of R7. The other end of R7 is connected to the drain of N4, the source of N3, and one end of C13. The drain of P8 is connected to the drain of N5 through R8. The drain of P8 is connected to one end of R8. The other end of R8 is connected to the drain of N3 and N5 and one end of C14. The other ends of C13 and C14 serve as external ports for capacitor voltage and are used to connect to VOP and VON, respectively. The sources of N4 and N5 are connected to VSS. The gates of P7, P8, and N3 to N5 are connected and connected to the corresponding digital control signal B. The two base capacitors in each capacitor cell have the same capacitance value. The ratio of the capacitance values ​​of the base capacitors in each capacitor cell, as well as the width-to-length ratio of N3, are all 1:2:4:…2. N-1 .

7. The K-band voltage controlled oscillator based on a noise-circulation structure according to claim 5, wherein: The self-adjusting capacitor circuit includes four variable capacitors Cvar1~Cavr4, four DC blocking capacitors C9~C12, four capacitors R3~R6, and a fixed capacitor C0. One end of C0 is connected to one end of C9 and C11, serving as one external port. The other end of C0 is connected to one end of C10 and C12, serving as the other external port. The other end of C9 is connected to one end of R3 and the positive terminal of Cvar1. The other end of C10 is connected to one end of R4 and the positive terminal of Cvar2. The other end of C11 is connected to one end of R5 and the positive terminal of Cvar3. The other end of C12 is connected to one end of R6 and the positive terminal of Cvar4. The other ends of R3 and R4 are connected to the first bias voltage VB1. The other ends of R5 and R6 are connected to the second bias voltage VB2. The negative terminals of Cvar1~Cavr4 are connected and used to connect to the voltage control signal Vctrl.

8. The K-band voltage controlled oscillator based on a noise-circulation structure according to claim 7, characterized in that: In the self-adjusting capacitor circuit, C9, C10, Cvar1, Cvar2, R3, and R4 constitute one variable capacitor branch; C11, C12, Cvar3, Cvar4, R5, and R6 constitute another variable capacitor branch; by adjusting the Kvco-V curves of the two parallel variable capacitor branches through VB1 and VB2 respectively, the flatness range of the self-adjusting capacitor is increased, thereby improving the linearity of the oscillation circuit.

9. A phase-locked loop, characterized by: It employs a K-band voltage-controlled oscillator based on a noise cycling structure as described in any one of claims 1-8.

10. A radio frequency chip, characterized by It employs the phase-locked loop as described in claim 9.

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