Analog-to-digital conversion method and successive approximation type converter

Abstract

The invention discloses an analog-to-digital conversion method and a successive approximation type converter, and relates to the technical field of integrated circuits. According to the method, the capacitance weights of the positive and negative capacitor arrays are subjected to weight processing, offset control strategies corresponding to the weight processing are obtained, and pre-offset overturning processing is performed aiming at capacitance overturning so as to obtain different offset control strategies. Through simultaneous processing of a first charge quantity equation of accumulated charges of positive and negative capacitor arrays in a sampling stage and a second charge quantity equation of each offset control strategy, voltage deviation signals respectively corresponding to a non-inverting input end and an inverting input end of a comparator under different offset control strategies are obtained; and thus, variable reference signals under different offset control strategies can be obtained. And substituting each change reference signal into a quantized voltage formula to obtain a corresponding differential offset code, and determining a final differential offset code according to a zero offset interval to ensure that the final differential offset code is eliminated at a zero point discontinuity and improve a signal-to-noise ratio.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an analog-to-digital conversion method and a successive approximation converter. Background Technology

[0002] (Sigma-Delta) modulators are widely used in wide dynamic range and low-noise applications such as audio, sensor interfaces, and precision measurements. To ensure high conversion accuracy while considering power consumption and chip area, modern high-performance designs often employ successive approximation analog-to-digital converters (SAR ADCs). Multi-bit quantizers in the modulator loop. Traditional SARADC architectures are typically based on mid-rise quantization, which is simple in structure, has low delay, and is easy to implement. However, this quantizer exhibits code level jumps when the input crosses zero (input less than 0, output -1; input greater than 0, output +1), equivalent to discontinuous steps at zero. When the input signal amplitude is weakly close to zero, the quantization error becomes strongly correlated with the input signal, causing the system to fall into a limit cycle oscillation state, producing a deterministic periodic code stream at the output. This phenomenon manifests in the frequency domain as an increase in idle tone and noise floor, severely degrading the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR).

[0003] Therefore, how to achieve zero continuity from the quantizer transfer characteristics without introducing additional noise sources and power consumption, so as to suppress idle tones and improve system linearity, is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide an analog-to-digital conversion method and a successive approximation converter to solve the problems of zero discontinuity, deterioration of signal-to-noise ratio and spurious-free dynamic range caused by using a medium-rise successive approximation quantizer without introducing additional noise sources and power consumption overhead.

[0005] To address the aforementioned technical problems, this application provides an analog-to-digital conversion method applied to the logic control circuit of a successive approximation converter. The successive approximation converter includes a differential capacitor array, a comparator, and a logic control circuit. A corresponding analog voltage signal is applied to the power supply terminals of the positive and negative capacitor arrays of the differential capacitor array. The output ports of the positive and negative capacitor arrays are connected to the input terminals of the comparator, and the output terminals of the comparator are connected to the logic control circuit. The method includes:

[0006] The weights of the weighted capacitors in the positive and negative capacitor array are weighted to obtain the offset control strategy corresponding to each weight processing.

[0007] The first charge equation of the positive and negative capacitor arrays during the sampling phase and the second charge equation corresponding to each offset control strategy are obtained; the first charge equation and each of the second charge equations are then combined to obtain the voltage deviation signals corresponding to the positive and negative input terminals of the comparator, so as to determine the corresponding change reference signals.

[0008] The final differential offset code is determined based on the quantization voltage formula of the differential capacitor array, the various changing reference signals, and the zero-point offset interval; and the positive and negative capacitor arrays are offset according to the final differential offset code to successively approximate the analog voltage signal to obtain the corresponding digital signal.

[0009] On the one hand, when sampling the first plate of the positive and negative capacitor array, the weights of the weighted capacitors of the positive and negative capacitor array are weighted to obtain the offset control strategy corresponding to each weighted processing, including:

[0010] Obtain the symmetrical weighted capacitors of the positive and negative capacitor array;

[0011] In each symmetrical weighted capacitor, the weights of the first target symmetrical weighted capacitor are merged to obtain the corresponding first weight allocation strategy; wherein, the first target symmetrical weighted capacitor has at least one pair of symmetrical weighted capacitors.

[0012] The weights of the weight capacitors in each first weight allocation strategy are pre-shifted to obtain the corresponding offset control strategy.

[0013] On the other hand, the process of determining the second charge equation corresponding to each of the aforementioned offset control strategies includes:

[0014] Obtain the first target symmetric weighted capacitor corresponding to the weight merging process of the positive and negative capacitor arrays and the first non-target symmetric weighted capacitor corresponding to the one that has not undergone weight merging process;

[0015] Connect one of the weighted capacitors of the first non-target symmetrical weighted capacitor to the reference voltage signal, and connect the other weighted capacitor to the ground signal.

[0016] The first target symmetrical weighted capacitor is connected to the ground signal for the weighted capacitor corresponding to the positive capacitor array, and the weighted capacitor corresponding to the negative capacitor array is connected to the reference voltage signal.

[0017] The charge equations of the positive and negative capacitor arrays are determined based on the first target symmetric weighted capacitor and the first non-target symmetric weighted capacitor after each signal is received, and are used as the second charge equations.

[0018] On the other hand, when sampling the second plate of the positive and negative capacitor array, the weights of the weighted capacitors of the positive and negative capacitor array are weighted to obtain the offset control strategy corresponding to each weighting, including:

[0019] Acquire the symmetrical weighted capacitors of the positive and negative capacitor array during the sampling phase;

[0020] Determine the second target symmetric weight capacitor among all symmetric weight capacitors;

[0021] In each symmetrical weighted capacitor, the weights of the second non-target symmetrical weighted capacitor (excluding the second target symmetrical weighted capacitor) are frozen, and the weights of the second target symmetrical weighted capacitor are pre-offset to obtain the corresponding offset control strategy; wherein, the second target symmetrical weighted capacitor has at least one pair of symmetrical weighted capacitors.

[0022] On the other hand, the process of determining the changing reference signal includes:

[0023] The initial voltage deviation signal of the positive and negative capacitor array before weighting is obtained based on the law of charge conservation.

[0024] The initial voltage deviation signal and each of the weighted voltage deviation signals are subtracted from each other to obtain the corresponding initial change reference signal;

[0025] The initial change reference signals under each offset control strategy are summed to obtain the final change reference signal under each offset control strategy.

[0026] On the other hand, the final differential offset code is determined based on the quantization voltage formula of the differential capacitor array, each of the aforementioned changing reference signals, and the zero-point offset interval, including:

[0027] Substitute each of the aforementioned change reference signals into the quantization voltage formula to obtain the corresponding initial differential offset code;

[0028] In each of the initial differential offset codes, the integer form of the initial differential offset code is excluded according to the zero-point offset interval to obtain the remaining initial differential offset code;

[0029] The remaining initial differential offset code is used as the final differential offset code.

[0030] On the other hand, using the remaining initial differential offset code as the final differential offset code includes:

[0031] When the number of remaining initial differential offset codes is one, the remaining initial differential offset code is used as the final differential offset code;

[0032] When there are multiple remaining initial differential offset codes, the smallest remaining initial differential offset code is taken as the final differential offset code.

[0033] On the other hand, the first target symmetrical weighted capacitor is subjected to corresponding weight merging processing in each symmetrical weighted capacitor to obtain the corresponding first weight allocation strategy, including:

[0034] When the first target symmetrical weighted capacitor is a pair of symmetrical weighted capacitors, the two weighted capacitors of the pair of symmetrical weighted capacitors are connected in parallel to obtain a single weighted capacitor, thereby completing the weight merging process of the first target symmetrical weighted capacitor.

[0035] When the first target symmetrical weighted capacitor consists of multiple pairs of symmetrical weighted capacitors, all weighted capacitors of the multiple pairs of symmetrical weighted capacitors are connected in parallel to obtain a single weighted capacitor, thereby completing the weight merging process of the first target symmetrical weighted capacitor.

[0036] On the other hand, during the successive approximation process of the analog voltage signal, when the digital signals output by the comparator are all 1 in each successive decision, the method further includes:

[0037] Obtain the symmetrical weighted capacitors of the positive and negative capacitor arrays when all digital signals are 1;

[0038] The weighted capacitor corresponding to the first target symmetrical weighted capacitor in the positive capacitor array is flipped from the access ground signal to the access reference voltage signal;

[0039] The first target symmetrical weighted capacitor is flipped from the reference voltage signal to the ground signal to achieve full-range symmetry of the differential capacitor array.

[0040] To address the aforementioned technical problems, this application also provides a successive approximation converter, comprising a differential capacitor array, a comparator, and a logic control circuit; a corresponding analog voltage signal is applied to the power supply terminals of the positive and negative capacitor arrays of the differential capacitor array, the output ports of the positive and negative capacitor arrays are connected to the input terminals of the comparator, and the output terminals of the comparator are connected to the logic control circuit;

[0041] The logic control circuit is used to execute the steps of the analog-to-digital conversion method described above to complete the conversion process.

[0042] This application provides an analog-to-digital conversion method. First, the method is applied to the logic control circuit of a successive approximation converter. The successive approximation converter includes a differential capacitor array, a comparator, and a logic control circuit. A corresponding analog voltage signal is applied to the power supply terminals of the positive and negative capacitor arrays of the differential capacitor array. The output ports of the positive and negative capacitor arrays are connected to the input terminals of the comparator, and the output terminals of the comparator are connected to the logic control circuit, providing hardware support for subsequent successive approximation processing. Second, the capacitor weights of the positive and negative capacitor arrays of the differential capacitor array are weighted to obtain the offset control strategy corresponding to each weight. Considering that the differential capacitor array includes upper plate sampling and lower plate sampling, in the lower plate sampling structure, after the sampling phase, a reference voltage switch needs to be performed on the lower plate. The charge redistribution process is naturally introduced during the lower plate flipping phase. The lower plate offset strategy utilizes the existing flipping phase of the lower plate to perform weight merging processing on the weighted capacitors for pre-offset control of the redistribution process, without requiring additional processing timing. For upper plate sampling, the weighting processing of the weighted capacitor involves controlling the weighted capacitor to perform a frozen weight pre-offset process, requiring an additional independent capacitor configuration or flipping stage to complete the function. Regardless of the sampling method, pre-offset flipping processing is performed on the capacitor flipping to obtain different offset control strategies. Next, by simultaneously processing the first charge equation of the accumulated charge of the positive and negative capacitor arrays in the sampling stage and the second charge equation of each offset control strategy, the voltage deviation signals corresponding to the non-inverting and inverting inputs of the comparator under different offset control strategies are obtained through the law of charge conservation, thus obtaining the changing reference signals under different offset control strategies. Finally, the changing reference signals are substituted into the quantization voltage formula to obtain the corresponding differential offset code. The final differential offset code is then determined based on the zero-point offset interval to ensure that the final differential offset code eliminates discontinuities at zero points, improving the signal-to-noise ratio. This eliminates the zero-crossing transition of the rising-mode at the source, significantly reduces small-signal limiting loops and idle tones, and suppresses DC deviation and even harmonics. The above method, based on mid-leveling, weakens the correlation between quantization error and input, resulting in a flatter error spectrum. Therefore, noise shaping can more effectively push quantization noise out of the in-band, making the in-band noise closer to the theoretical value and allowing for greater improvement in dynamic range (DR). Clean in-band spectra and high small-signal SNR can be obtained without injecting dither or requiring a programmable gain amplifier (PGA). This avoids the complexity and uncertainty associated with gain switching and calibration, while also not introducing additional noise sources or functional overhead.

[0043] In addition, this application also provides a successive approximation converter that has the same beneficial effects as the analog-to-digital conversion method described above. Attached Figure Description

[0044] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A flowchart of an analog-to-digital conversion method provided in an embodiment of this application;

[0046] Figure 2 A schematic diagram of a discrete CIFF structure sigma delta modulator, representing a conventional technical solution.

[0047] Figure 3 A schematic diagram illustrating the transmission characteristics of a conventional technical solution using a mid-rise successive approximation converter;

[0048] Figure 4 This is a schematic diagram of the structure of a successive approximation converter provided in an embodiment of this application;

[0049] Figure 5 This application provides a schematic diagram of the structure of a lower electrode sampling stage.

[0050] Figure 6 A schematic diagram of a lower electrode sampling SAR ADC provided for an embodiment of this application;

[0051] Figure 7 A schematic diagram of the charge distribution stage after weight pre-offset processing of P1 and N1 of a first target symmetrical weighted capacitor provided in an embodiment of this application;

[0052] Figure 8 A schematic diagram illustrating the transmission characteristics of a mid-flat successive approximation converter provided in an embodiment of this application;

[0053] Figure 9 A schematic diagram of an extended decision stage provided in this embodiment;

[0054] Figure 10 This application provides a schematic diagram of the upper electrode sampling stage.

[0055] Figure 11 This is a schematic diagram of the structure of the comparison stage during sampling of the lower electrode plate, provided in an embodiment of this application.

[0056] Figure 12 This is a schematic diagram of the pre-offset stage during sampling of the lower electrode plate, provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0058] The core of this application is to provide an analog-to-digital conversion method and a successive approximation converter, so as to solve the problems of zero discontinuity, deterioration of signal-to-noise ratio and spurious-free dynamic range caused by the use of a medium-rise successive approximation quantizer without introducing additional noise sources and power consumption overhead.

[0059] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] Modulators are analog-to-digital converters (ADCs) designed for high-precision applications. They convert analog input signals into digital signals and are commonly used in audio, sensor interfaces, and precision measurement applications where low noise performance is critical. Quantizers are the main nonlinear units in ADC systems; their quantization characteristics directly determine the system's signal-to-noise ratio, dynamic range, and linearity. Successive approximation ADCs are often used as... The quantizer implementation of the modulator. When using a medium-amplitude SAR ADC, its quantization transfer characteristics exhibit discontinuous steps at zero, which can easily lead to limiting loop behavior and idle tone when the input amplitude is small, thus degrading the in-band noise performance.

[0061] When considering embedding a successive approximation quantizer to address zero-point discontinuities, the following solutions are employed: 1. Adding a programmable gain amplifier (PGA): At the analog input, a PGA is added to increase the amplitude of small signals, thereby improving the equivalent resolution. The drawbacks are: the PGA introduces additional noise and distortion sources, and gain switching and calibration are complex, increasing power consumption. 2. Injecting dither: Dither is injected into the front end or loop to break up mode noise and alleviate idle tone. The drawbacks are: increased noise power, leading to a deterioration in dynamic range (DR); and a trade-off exists between dither intensity and noise spectrum selection, making it unsuitable for weak signals. 3. Increasing the quantization bit width: By using a higher bit width quantizer to reduce the least significant bit (LSB), idle tone can be somewhat suppressed. The cost is a significant increase in area, power consumption, and speed margin. 4. Digital post-processing compensation involves remedial processing in the digital processing section, such as offset estimation, even-order harmonic correction, and codeword remapping. Its drawback is that it cannot eliminate the structural nonlinearity and error correlation of the quantizer at the source, leading to additional latency and power consumption. The above solutions essentially acknowledge the inherent nonlinearity of the riser quantizer during zero-crossing and attempt to disrupt the deterministic tone it generates by introducing random noise, rather than eliminating the root cause of the nonlinearity. This compensatory approach inevitably leads to performance compromises, sacrificing overall noise floor for the suppression of specific tones. The analog-to-digital conversion method provided in this application can solve the above technical problems.

[0062] Figure 1 A flowchart of an analog-to-digital conversion method provided in this application embodiment is shown below. Figure 1 As shown, a logic control circuit is applied to a successive approximation converter; the successive approximation converter includes a differential capacitor array, a comparator, and a logic control circuit; corresponding analog voltage signals are applied to the power supply terminals of the positive and negative capacitor arrays of the differential capacitor array, the output ports of the positive and negative capacitor arrays are connected to the input terminals of the comparator, and the output terminals of the comparator are connected to the logic control circuit; the method includes:

[0063] S11: Perform weight processing on the weights of the weighted capacitors in the positive and negative capacitor array to obtain the offset control strategy corresponding to each weight processing.

[0064] S12: Obtain the first charge equation of the positive and negative capacitor arrays and the second charge equation corresponding to each offset control strategy during the sampling phase; and perform simultaneous processing of the first charge equation and each second charge equation to obtain the voltage deviation signal corresponding to the positive input terminal and the negative input terminal of the comparator, so as to determine the corresponding change reference signal.

[0065] S13: Determine the final differential offset code based on the quantization voltage formula of the differential capacitor array, each changing reference signal, and the zero-point offset interval; and perform offset processing on the positive and negative capacitor arrays based on the final differential offset code to successively approximate the analog voltage signal to obtain the corresponding digital signal.

[0066] Specifically, Figure 2 A schematic diagram of a discrete CIFF structure sigma delta modulator using conventional technical solutions, as shown below. Figure 2 As shown, the 100 sigma delta modulator includes: discrete-time integrator 1, discrete-time integrator 2, discrete-time integrator 3, feedforward coefficient amplifiers (a1, a2, a3), feedback coefficient amplifier b, adder, and quantizer 4. This application optimizes the quantizer; while traditional schemes use a medium-rise SAR ADC, this application uses a medium-flat SAR ADC. Figure 3 This is a schematic diagram illustrating the transmission characteristics of a conventional technical solution using a mid-rise successive approximation converter, such as... Figure 3 As shown, between the intermediate values ​​0111 and 1000 in the digital output code, directly flipping from 0111 to 1000 will result in discontinuous zero points.

[0067] Figure 4 This application provides a schematic diagram of the structure of a successive approximation converter, as shown in the embodiments. Figure 4 As shown, the differential capacitor array consists of a positive capacitor array and a negative capacitor array, realizing input sampling and charge pre-offset. The comparator determines the current threshold relationship bit by bit; the logic control circuit is responsible for successive comparisons, state machine switching, and specific offset processing control to output an N-bit digital code.

[0068] In step S11, the weighted capacitors of the positive and negative capacitor arrays are weighted. The purpose is to reduce the number of capacitors by reasonably configuring the capacitor weights while ensuring quantization resolution, thereby reducing chip area and power consumption. Taking a 4-bit differential capacitor array as an example, the quantization accuracy corresponds to 16 quantization levels. If an equal-weighted capacitor structure is used, multiple unit capacitors need to be combined to achieve each level, resulting in a large total number of capacitors. In contrast, using a binary weighted capacitor configuration, with the positive and negative capacitor arrays set to weight distributions of 1C, 2C, 4C, and 8C respectively, significantly reduces the number of capacitors required while ensuring quantization accuracy. In the differential capacitor array, the capacitor weights of the positive and negative capacitor arrays are strictly symmetrical, and their operating rules are consistent, thus ensuring the symmetry and linearity of the differential conversion process. In addition, the differential capacitor array can be distinguished into upper plate sampling or lower plate sampling depending on the input signal access position during sampling. In the upper plate sampling method, during the sampling phase, the differential input signals VIP and VIN are connected to the upper plate of the capacitor, and the lower plate is fixedly connected to the ground potential or the common-mode voltage VCM. In the lower plate sampling method, during the sampling phase, the differential input signal is connected to the lower plate of the capacitor, and the upper plate is connected to the ground potential or the common-mode voltage VCM during the sampling period, and is suspended during the holding phase to participate in the subsequent charge redistribution process. Figure 5 This application provides a schematic diagram of the structure of a lower electrode sampling stage, as shown in the embodiment. Figure 5 As shown, during the lower plate sampling phase, the external differential input is sampled onto the lower plate of the positive and negative capacitor array of the Capacitive Digital-to-Analog Converter (CDAC), while the upper plate is connected to ground (GND) to accumulate charge. After sampling, the sampling switches for both the upper and lower plates are disconnected. During the upper plate sampling phase, the external differential input is sampled onto the upper plate of the CDAC's positive and negative capacitor array, while the lower plate is connected to ground (GND) to accumulate charge. After sampling, the sampling switches for both the upper and lower plates are disconnected.

[0069] In the upper and lower plate sampling structure, charge redistribution is not determined by the sampling method itself, but by the switching behavior of the capacitor plate voltages. According to the law of conservation of charge, when the voltage of any plate of the capacitor changes, in order to satisfy the conservation of total charge, the charge across the capacitor will be redistributed, thereby causing a change in the voltage of the corresponding node.

[0070] For the lower plate sampling structure, after the sampling phase ends and before the first comparison, it is usually necessary to switch the lower plate from the input signal to ground potential or common-mode voltage to establish initial comparison conditions. This switching process naturally introduces a charge redistribution process. Therefore, the pre-offset strategy of this application can be embedded in this existing voltage switching phase without adding additional comparison or control procedures.

[0071] In contrast, in the upper plate sampling structure, after the sampling phase ends and before the first comparison, the lower plate typically maintains a fixed potential and does not undergo voltage switching. Therefore, no corresponding charge redistribution process naturally occurs at this time. If an equivalent pre-offset effect is required before the first comparison, an additional dedicated voltage switching or capacitor configuration process is needed to achieve pre-offset control.

[0072] Therefore, in the lower plate sampling method, since a plate voltage switching process already exists after the sampling phase and before the first comparison, this application can embed the weight merging and pre-offset operations into this existing voltage switching phase, thereby completing the weight processing without adding additional comparison or control procedures. In contrast, in the upper plate sampling method, there is usually no corresponding voltage switching process before the first comparison. If an equivalent pre-offset or weight modulation function is required, it is necessary to freeze part of the weight contribution to introduce an additional voltage switching process to achieve weight processing.

[0073] Figure 6 This is a schematic diagram of a lower electrode sampling SAR ADC provided in an embodiment of this application, as shown below. Figure 6 As shown, after adding weight merging, the original weighted capacitors of the positive and negative capacitor arrays (8:8:4:4:2:2:1:1:1:1) are merged into (8:8:4:4:2:2:2:1:1). The ratio of capacitors P4a:P4b:P3a:P3b:P2a:P2b:P1:P0a:P0b in the positive capacitor array is 8:8:4:4:2:2:2:1:1; the ratio of capacitors N4a:N4b:N3a:N3b:N2a:N2b:N1:N0a:N0b in the negative capacitor array is 8:8:4:4:2:2:2:1:1.

[0074] Therefore, the weighting process during sampling at the lower plate involves merging the weights of multiple weighted capacitors. However, the weighting process during sampling at the upper plate cannot merge weights; instead, the weight contributions need to be frozen and not included in the voltage calculation.

[0075] Since there are multiple weighted capacitors in the positive and negative capacitor array, there are various schemes for weight processing of different weighted capacitors. Therefore, this application obtains the offset control strategy corresponding to each weight processing under all possible combinations of weight processing methods. For example, when sampling the lower plate, the original multiple weighted capacitors (1C:1C:1C) are weighted and merged (3C). The weighted capacitors are then combined and their original 1C:1C:1C upper plate reference voltage is uniformly changed to VREF or GND to achieve zero-point offset. Alternatively, when sampling the upper plate, an additional voltage switching process is used to flip the original 1C:1C:1C lower plate reference voltage to VREF or GND, freezing the weight processing to achieve zero-point offset.

[0076] The first charge equation for the positive and negative capacitor array in step S12 during the sampling phase is described above. Figure 5 When the lower plate is sampled, the charge accumulated in the positive capacitor array is: The accumulated charge of the negative capacitor array is .

[0077] The second charge equation corresponding to each offset control strategy is based on the fact that the determination process of the second charge equation is the same regardless of whether the upper plate sampling or the lower plate sampling is performed.

[0078] The second charge equations (two second charge equations for the positive and negative capacitor arrays) under each offset control strategy are combined with the first charge equations for the positive and negative capacitor arrays during the sampling phase to obtain the voltage deviation signals corresponding to the positive and negative input terminals of the comparator. It should be noted that the number of offset control strategies is the same as the number of voltage deviation signals corresponding to the positive and negative input terminals, and the voltage deviation signals are obtained through the law of charge conservation.

[0079] Regarding the change reference signal, it is obtained by subtracting the voltage deviation signal obtained by the law of charge conservation without weighting in the conventional technical solution from the actual voltage deviation signal obtained after weighting in step S12, and then using the difference obtained as the change reference signal.

[0080] The quantization voltage formula for the differential capacitor array in step S13 is calculated using the weight range and quantization bit depth of the differential capacitor array. For example, a 4-bit differential quantizer has 16 quantization levels. LSB = full-scale voltage range / number of quantization levels. Substituting the values, we get: .

[0081] Substituting the varying reference signals into the aforementioned quantization voltage formula yields different differential offset codes. If the introduced offset is an integer multiple of LSB, it only causes an overall shift in the quantization transmission characteristics, without altering the quantizer's mid-rise quantization characteristics at zero, thus making it difficult to resolve the idle tone problem under small signal conditions. If the offset is not an integer multiple of LSB, the current offset falls exactly in the middle range of the mid-level quantizer, such as the transition range from 0 to 0.5 to 1. This avoids causing an overall signal jump and perfectly matches the zero-point buffer characteristics of the mid-level quantizer. Signals near zero do not exhibit abrupt transitions between 0 and 1, but rather fall within the middle region, thus alleviating the problem of zero-point discontinuity. Therefore, it is necessary to filter the final differential offset code from all differential offset codes based on the zero-point offset interval. The zero-point offset interval must fall within the offset interval, belong to the middle range of the mid-level quantizer, and not be an integer multiple of 1 LSB.

[0082] After offsetting the positive and negative capacitor arrays according to the final differential offset code selected, the process enters the conventional N-bit successive approximation process. The comparator makes decisions bit by bit, and the control logic sequentially flips the corresponding weight capacitors to obtain an N-bit codeword, which converts the analog voltage signal into the corresponding digital signal.

[0083] It should be noted that while some existing technical solutions also involve adjusting capacitor weights, they typically achieve equivalent weight reconstruction by changing the amplitude or ratio of the reference voltage connected to different weighted capacitors. In contrast, this application uses a uniform reference voltage VREF during the weighting process, meaning it does not change the amplitude relationship of the reference voltage. Instead, it processes the configuration and connection state of the weighted capacitors to achieve pre-offset and weight modulation.

[0084] This application provides an analog-to-digital conversion method. First, the method is applied to the logic control circuit of a successive approximation converter. The successive approximation converter includes a differential capacitor array, a comparator, and a logic control circuit. A corresponding analog voltage signal is applied to the power supply terminals of the positive and negative capacitor arrays of the differential capacitor array. The output ports of the positive and negative capacitor arrays are connected to the input terminals of the comparator, and the output terminals of the comparator are connected to the logic control circuit, providing hardware support for subsequent successive approximation processing. Second, the capacitor weights of the positive and negative capacitor arrays of the differential capacitor array are weighted to obtain the offset control strategy corresponding to each weight. Considering that the differential capacitor array includes upper plate sampling and lower plate sampling, in the lower plate sampling structure, after the sampling phase, a reference voltage switch needs to be performed on the lower plate. The charge redistribution process is naturally introduced during the lower plate flipping phase. The lower plate offset strategy utilizes the existing flipping phase of the lower plate to perform weight merging processing on the weighted capacitors for pre-offset control of the redistribution process, without requiring additional processing timing. For upper plate sampling, the weighting processing of the weighted capacitor involves controlling the weighted capacitor to perform a frozen weight pre-offset process, requiring an additional independent capacitor configuration or flipping stage to complete the function. Regardless of the sampling method, pre-offset flipping processing is performed on the capacitor flipping to obtain different offset control strategies. Next, by simultaneously processing the first charge equation of the accumulated charge of the positive and negative capacitor arrays in the sampling stage and the second charge equation of each offset control strategy, the voltage deviation signals corresponding to the non-inverting and inverting inputs of the comparator under different offset control strategies are obtained through the law of charge conservation, thus obtaining the changing reference signals under different offset control strategies. Finally, the changing reference signals are substituted into the quantization voltage formula to obtain the corresponding differential offset code. The final differential offset code is then determined based on the zero-point offset interval to ensure that the final differential offset code eliminates discontinuities at zero points, improving the signal-to-noise ratio. This eliminates the zero-crossing transition of the rising-mode at the source, significantly reduces small-signal limiting loops and idle tones, and suppresses DC deviation and even harmonics. The above method, based on mid-leveling, weakens the correlation between quantization error and input, resulting in a flatter error spectrum. Therefore, noise shaping can more effectively push quantization noise out of the in-band, making the in-band noise closer to the theoretical value and allowing for greater improvement in dynamic range (DR). Clean in-band spectra and high small-signal SNR can be obtained without injecting dither or requiring a programmable gain amplifier (PGA). This avoids the complexity and uncertainty associated with gain switching and calibration, while also not introducing additional noise sources or functional overhead.

[0085] In some embodiments, when sampling the first plate of the positive and negative capacitor array, the weights of the weighted capacitors of the positive and negative capacitor array are weighted to obtain the offset control strategy corresponding to each weighting, including:

[0086] Obtain the symmetrical weighted capacitors of the positive and negative capacitor array;

[0087] In each symmetrical weighted capacitor, the weights of the first target symmetrical weighted capacitor are merged to obtain the corresponding first weight allocation strategy; wherein, the first target symmetrical weighted capacitor has at least one pair of symmetrical weighted capacitors.

[0088] The weights of the weight capacitors in each first weight allocation strategy are pre-shifted to obtain the corresponding offset control strategy.

[0089] Specifically, the first plate sample here can be either the lower plate sample or the upper plate sample. If the current lower plate sample is the first plate sample, then the corresponding current upper plate sample is the second plate sample; conversely, if the current lower plate sample is the second plate sample, then the corresponding current upper plate sample is the first plate sample. There is no limitation here; it can be set according to the actual situation.

[0090] In this embodiment, the first plate sampling is the lower plate sampling. In the lower plate sampling structure, the symmetrical weighted capacitors in the positive and negative capacitor arrays are obtained, where a set of symmetrical weighted capacitors can be represented as P1a and P1b. The symmetrical weighted capacitors are located in the positive capacitor array and the negative capacitor array, respectively, and have the same capacitance value and weight configuration, and follow the same control rules in the successive approximation process. Due to the strict symmetry of the positive and negative capacitor arrays in terms of structure and control, the positive input signal and the reverse input signal with the same amplitude will produce a capacitance difference with equal amplitude and opposite sign during the differential calculation process, thereby ensuring that the differential quantization relationship is symmetrical about the zero point.

[0091] In each symmetrical weighted capacitor, the weights of the first target symmetrical weighted capacitor are merged accordingly. This first target symmetrical weighted capacitor can be a pair of symmetrical weighted capacitors, such as P1a and P1b, or multiple pairs, such as P1a and P1b, P2a and P2b, etc. Each time a weight merging process of the first target symmetrical weighted capacitor occurs, a corresponding first weight allocation strategy is obtained. Based on the weighted capacitors of each first weight allocation strategy, a weight pre-offset process is performed to obtain the corresponding offset control strategy.

[0092] Taking the merging of P1a and P1b as an example, the corresponding first weight allocation strategy is as follows: in the positive capacitor array, the ratio of capacitors P4a:P4b:P3a:P3b:P2a:P2b:P1:P0a:P0b is 8:8:4:4:2:2:2:1:1; in the negative capacitor array, the ratio of capacitors N4a:N4b:N3a:N3b:N2a:N2b:N1:N0a:N0b is 8:8:4:4:2:2:2:1:1.

[0093] The weights of the capacitors in the first weight allocation strategy undergo a weight pre-offset process. The conventional flipping process results in the following values ​​for the positive capacitor array: P4a: VREF, P4b: GND, P3a: VREF, P3b: GND, P2a: VREF, P2b: GND, P1a: VREF, P1b: GND, P0a: VREF, P0b: GND. The negative capacitor array results in: N4a: VREF, N4b: GND, N3a: VREF, N3b: GND, N2a: VREF, N2b: GND, N1a: VREF, N1b: GND, N0a: VREF, N0b: GND. After the weight pre-offset process, the results are: P4a: VREF, P4b: GND, P3a: VREF, P3b: GND, P2a: VREF, P2b: GND, P1: GND, P0a: VREF, P0b: GND. Negative capacitor array N4a:VREF, N4b:GND, N3a:VREF, N3b:GND, N2a:VREF, N2b:GND, N1:VREF, N0a:VREF, N0b:GND.

[0094] The weight merging process provided in this embodiment during the sampling of the lower plate yields corresponding offset control strategies, enabling charge redistribution under different first weight allocation strategies. The weight merging process of symmetrical weighted capacitors makes the difference calculation of the positive and negative capacitor arrays more accurate and symmetrical, thus structurally improving zero-point stability.

[0095] In some embodiments, the process of determining the second charge equation corresponding to each offset control strategy includes:

[0096] Obtain the first target symmetric weighted capacitor corresponding to the weight merging process of the positive and negative capacitor arrays and the first non-target symmetric weighted capacitor corresponding to the one that has not undergone weight merging process;

[0097] Connect one of the weighted capacitors of the first non-target symmetrical weighted capacitor to the reference voltage signal, and connect the other weighted capacitor to the ground signal.

[0098] The first target symmetrical weighted capacitor is connected to the ground signal for the weighted capacitor corresponding to the positive capacitor array, and the weighted capacitor corresponding to the negative capacitor array is connected to the reference voltage signal.

[0099] The charge equations of the positive and negative capacitor arrays are determined based on the first target symmetric weighted capacitor and the first non-target symmetric weighted capacitor after each signal is received, and are used as the second charge equations.

[0100] Specifically, taking the above example of merging P1a and P1b, the corresponding first target symmetric weight capacitor is P1, and the first non-target symmetric weight capacitors are P4, P3, P2, and P0.

[0101] One weighted capacitor of the first non-target symmetrical weighted capacitor is connected to the reference voltage signal, and the other weighted capacitor is connected to the ground signal. This applies to both positive and negative capacitor arrays, i.e., positive capacitor array P4a:VREF, P4b:GND, P3a:VREF, P3b:GND, P2a:VREF, P2b:GND, P0a:VREF, P0b:GND. Negative capacitor array N4a:VREF, N4b:GND, N3a:VREF, N3b:GND, N2a:VREF, N2b:GND, N0a:VREF, N0b:GND.

[0102] The first target symmetrical weighted capacitor corresponds to the weighted capacitor of the positive capacitor array connected to the ground signal: P1: GND; the weighted capacitor of the negative capacitor array is connected to the reference voltage signal: N1: VREF.

[0103] Figure 7 This is a schematic diagram of the charge distribution stage after weight pre-offset processing of P1 and N1 of a first target symmetrical weighted capacitor provided in an embodiment of this application, as shown below. Figure 7 As shown, we can process P1 and N1's 2C.

[0104] Based on the first target symmetrical weighted capacitor and the first non-target symmetrical weighted capacitor after each signal is received, the charge equation of the positive and negative capacitor array is determined, as follows:

[0105] ;

[0106] ;

[0107] in, As a reference voltage signal, The voltage signal at the positive input terminal of the comparator. This is the voltage signal at the negative input terminal of the comparator.

[0108] The determination process of the second charge equation provided in this embodiment is based on the weight pre-offset processing process under each offset control strategy in the above embodiments. By symmetrically flipping the corresponding weight capacitors in the positive and negative capacitor arrays, charge redistribution is triggered, so that the decision threshold near the zero point is moved from the integer multiple LSB alignment position to the middle position of the quantization level, thereby reconstructing the original mid-rise quantization level structure into a mid-flat quantization level structure and improving the quantization continuity near the zero point.

[0109] In some embodiments, when sampling the second plate of the positive and negative capacitor array, the weights of the weighted capacitors of the positive and negative capacitor array are weighted to obtain the offset control strategy corresponding to each weighting, including:

[0110] Acquire the symmetrical weighted capacitors of the positive and negative capacitor array during the sampling phase;

[0111] Determine the second target symmetric weight capacitor among all symmetric weight capacitors;

[0112] In each symmetrical weighted capacitor, the weights of the second non-target symmetrical weighted capacitor (excluding the second target symmetrical weighted capacitor) are frozen, and the weights of the second target symmetrical weighted capacitor are pre-offset to obtain the corresponding offset control strategy; wherein, the second target symmetrical weighted capacitor has at least one pair of symmetrical weighted capacitors.

[0113] Specifically, the second plate sampling here refers to the upper plate sampling. Considering that no voltage switching of the capacitor plates occurs between the end of the sampling phase and the first comparison in the upper plate sampling structure, a charge redistribution process has not yet been introduced. First, the second target symmetrical weighted capacitor is determined among the symmetrical weighted capacitors. During the sampling phase, each symmetrical weighted capacitor is sampled according to the rule of one end VREF and the other end GND. In the current weight processing, the weights of the second non-target symmetrical weighted capacitors (excluding the second target symmetrical weighted capacitor) are frozen. This freezing means that no additional flipping rules are introduced for the second non-target symmetrical weighted capacitors. The weight pre-offset processing of the second target symmetrical weighted capacitor is performed because the differential pair of the second target symmetrical weighted capacitors are all connected to the same level signal, and the charge difference between them is 0. This means that this bit does not participate in the voltage calculation in this flipping, and only the frozen weights of bits P4, P3, P2, and P0 are effective, resulting in the corresponding offset control strategy.

[0114] The additional switching rule introduced here is used in digital circuits, but it can also be implemented in analog circuits by introducing an independent capacitor configuration. This independent capacitor configuration refers to connecting the capacitor configuration corresponding to P1b to the same reference voltage as the capacitor configuration corresponding to P1a. Whether digital or analog, the change involves altering the voltage across the capacitor corresponding to P1b.

[0115] The standard flipping process is as follows: Positive capacitor array P4a:VREF, P4b:GND, P3a:VREF, P3b:GND, P2a:VREF, P2b:GND, P1a:VREF, P1b:GND, P0a:VREF, P0b:GND. Negative capacitor array N4a:VREF, N4b:GND, N3a:VREF, N3b:GND, N2a:VREF, N2b:GND, N1a:VREF, N1b:GND, N0a:VREF, N0b:GND. If P1a and P1b are the second target weight capacitors, an additional flipping stage is introduced, involving weight pre-offset processing, and both are grounded. The second target symmetrical weight capacitors must have at least one pair of symmetrical weight capacitors; that is, it can be one pair or multiple pairs of symmetrical weight capacitors, depending on the actual situation.

[0116] In the process of determining the offset control strategy corresponding to the upper plate sampling provided in this embodiment, when the voltage range of the input signal does not require the participation of the second target symmetrical weight capacitor, it can be shielded by fixing the level signal of the second target weight capacitor, that is, weight pre-offset processing, to avoid introducing small errors.

[0117] In some embodiments, the process of determining the changing reference signal includes:

[0118] The initial voltage deviation signal of the positive and negative capacitor array before weighting is obtained based on the law of charge conservation.

[0119] The initial voltage deviation signal and the voltage deviation signals after weighting are subtracted accordingly to obtain the corresponding initial change reference signal;

[0120] The initial change reference signals under each offset control strategy are summed to obtain the final change reference signal under each offset control strategy.

[0121] Specifically, the initial voltage deviation signal of the positive and negative capacitor arrays before weighting is obtained based on the law of charge conservation. Taking a 4-bit differential capacitor array as an example, its initial voltage deviation signal is: , The voltage deviation signal in this embodiment is obtained by simultaneously processing the charge formulas after sampling and weighted pre-offset processing for each offset control strategy. Taking the sampling of the lower plate combined with a pair of symmetrical weighted capacitors (P1a and P1b) as an example, the corresponding voltage deviation signal is as follows: , .

[0122] The initial voltage deviation signal is obtained by subtracting the actual voltage deviation signal after weight pre-offset processing in this embodiment. , It should be noted that this corresponds to the initial change reference signal under an offset control strategy. The final change reference signal for each offset control strategy is obtained by adding the initial change reference signals under each offset control strategy. In the example above, it is 1 / 16VREF.

[0123] The process for determining the changing reference signal under each offset control strategy provided in this embodiment is based on comparing the initial voltage deviation signal of a traditional SAR ADC with the subsequent changing reference signal, and then determining the offset code. This is to eliminate the discontinuity of the zero point in the transmission characteristics, so that the quantization output remains stable and does not flip near the zero point.

[0124] In some embodiments, the final differential offset code is determined based on the quantization voltage formula of the differential capacitor array, each changing reference signal, and the zero-point offset interval, including:

[0125] Substitute each of the changing reference signals into the quantization voltage formula to obtain the corresponding initial differential offset code;

[0126] In each initial differential offset code, the integer form of the initial differential offset code is excluded according to the zero-point offset interval to obtain the remaining initial differential offset code;

[0127] Use the remaining initial differential offset code as the final differential offset code.

[0128] In conjunction with the above embodiments, each changing reference signal is substituted into the quantization voltage formula to obtain the corresponding initial differential offset code. Among these initial differential offset codes, there are integer multiples and non-integer differential offset codes. The integer multiples, along with the LSB of the medium-rise SAR ADC used in conventional schemes, are all near the zero point, failing to address the zero-point discontinuity issue. Therefore, it is necessary to delete the integer-form initial differential offset codes. The remaining initial differential offset codes are then filtered based on the flat regions within the zero-point offset interval.

[0129] Figure 8 A schematic diagram illustrating the transmission characteristics of a mid-flat successive approximation converter provided in this application embodiment is shown below. Figure 8As shown, compared to the potential of a traditional SAR ADC, the plate potential under the positive capacitor array is shifted towards GND by 0.25 LSB, and the plate potential under the negative capacitor array is shifted towards VREF by 0.25 LSB. The combined effect with the positive plate is an inherent shift of 0.5 LSB. This causes the zero point of the transfer characteristic curve to shift to the right by 0.5 LSB, forming a transfer characteristic curve segment from 00000 to 01111. From this transfer characteristic curve, the discontinuity at the zero point is eliminated, ensuring the quantization output remains stable and does not flip near the zero point, thus suppressing small-signal limiting loops and idle tones at the source.

[0130] This embodiment provides the remaining initial differential offset code corresponding to the flat area within the zero offset interval to eliminate the discontinuity of the zero point, so that the quantization output remains stable and does not flip near the zero point, thereby suppressing small signal limit loops and idle tones from the source.

[0131] In some embodiments, the remaining initial differential offset code is used as the final differential offset code, including:

[0132] When the number of remaining initial differential offset codes is one, the remaining initial differential offset codes are used as the final differential offset codes.

[0133] When there are multiple remaining initial differential offset codes, the smallest remaining initial differential offset code is used as the final differential offset code.

[0134] Specifically, in conjunction with the above embodiments, considering the number of remaining initial differential offset codes, if only one remains, it is used as the final differential offset code. If multiple remain, it is necessary to filter among the multiple remaining initial differential offset codes. The filtering adopts a descending order from largest to smallest, selecting the smallest remaining initial differential offset code as the final differential offset code.

[0135] In this embodiment, the final differential offset code is determined based on the number of remaining initial differential offset codes to ensure that the zero points are continuous while performing the minimum degree of offset, thus simplifying the complexity of the operation steps.

[0136] In some embodiments, the first target symmetrical weighted capacitor is subjected to corresponding weight merging processing in each symmetrical weighted capacitor to obtain a corresponding first weight allocation strategy, including:

[0137] When the first target symmetrical weighted capacitor is a pair of symmetrical weighted capacitors, the two weighted capacitors of the pair of symmetrical weighted capacitors are connected in parallel to obtain a single weighted capacitor, thereby completing the weight merging process of the first target symmetrical weighted capacitors.

[0138] When the first target symmetrical weighted capacitor consists of multiple pairs of symmetrical weighted capacitors, all weighted capacitors of the multiple pairs of symmetrical weighted capacitors are connected in parallel to obtain a single weighted capacitor, thereby completing the weight merging process of the first target symmetrical weighted capacitor.

[0139] Specifically, the weight merging process here considers the case where the first target symmetrical weighted capacitor is a pair of symmetrical weighted capacitors. In this case, the two weighted capacitors of the pair are connected in parallel to obtain a single weighted capacitor. If there are multiple pairs of symmetrical weighted capacitors, all the weighted capacitors of the multiple pairs are connected in parallel to obtain a single weighted capacitor. Regardless of the case, the final result is a single weighted capacitor.

[0140] Additionally, a pre-offset value of 0.5 LSB is recommended: too small a value results in insufficient flatness, while too large a value significantly alters the linearity near zero. Preferably, this preset value is 0.5 LSB to form a zero-code region. However, for effective suppression of limiting cycles, the offset can also be selected in the range of, for example, 0.25 LSB to 0.75 LSB.

[0141] The specific capacitor parallel connection process for weight merging provided in this embodiment not only achieves charge redistribution of the weighted capacitors, but also saves on the setting of switches and the connection settings of the weighted capacitors with each switch and each signal, thereby reducing the layout area and the device cost of the switches.

[0142] The above embodiments address the issue of zero-point discontinuity, thereby mitigating the asymmetry in the zero-point distribution of the codeword after pre-offset, which causes the mean value at zero input to deviate from zero. The integrator continuously accumulates an equivalent DC bias within the loop, manifesting as baseline drift and even-order harmonic enhancement, thus worsening total harmonic distortion (THD) and spurious-free dynamic range (SFDR), and introducing measurement bias.

[0143] In some embodiments, during the successive approximation processing of the analog voltage signal, when the digital signals output by the comparator are all 1 in each successive decision, the method further includes:

[0144] Obtain the symmetrical weighted capacitors of the positive and negative capacitor arrays when all digital signals are 1;

[0145] The weighted capacitor corresponding to the first target symmetrical weighted capacitor in the positive capacitor array is flipped from the access ground signal to the access reference voltage signal;

[0146] The first target symmetrical weighted capacitor is flipped from the reference voltage signal to the ground signal to achieve full-range symmetry of the differential capacitor array.

[0147] Specifically, the symmetrical weighted capacitors of the positive and negative capacitor arrays corresponding to the condition where all digital signals are 1 are obtained. At this time, the weighted capacitor of the positive capacitor array corresponding to the first target symmetrical weighted capacitor is connected to the reference voltage signal by the grounding signal flip-up bit. Similarly, the weighted capacitor of the negative capacitor array is flipped from the reference voltage signal to the grounding signal. In conjunction with the above embodiment, the first 4 capacitors (P4a, P4b, P3a, P3b, P2a, P2b, N4a, N4b, N3a, N3b, N2a, N2b) have completed the flip-up before the 4th decision. When the 4th decision ends and the output is still 1, the flip-up of capacitors P1 and N1 will begin. The upper plate of P1 will flip from GND to VREF, and the upper plate of N1 will flip from VREF to GND.

[0148] Flipping P1 causes the potential to shift towards VREF by 1 / 16VREF, or 0.5 LSB; flipping N1 causes the potential of the lower plate of the negative capacitor array to shift towards GND by 1 / 16VREF, or 0.5 LSB, thus artificially introducing a threshold offset of 1 LSB. A subsequent decision further subdivides the positive full-scale range into two states: "01111" and "10000," thereby expanding the 4-bit 16-level range to an equivalent 17-level range. Shifting the zero point 0.5 LSB to the right completes the 10000 segment of the transmission characteristic curve, maintaining the symmetrical mapping of the codeword about the zero point and achieving full-scale symmetry. This expansion improves resolution and loop stability without significantly increasing latency and power consumption, while also avoiding the introduction of new biases.

[0149] Figure 9 This is a schematic diagram of an extended decision stage provided in this embodiment, as shown below. Figure 9 As shown, the weighted capacitors of the first target symmetrical weighted capacitor corresponding to the positive capacitor array are flipped from the access ground signal to the access reference voltage signal (VREF); the weighted capacitors of the first target symmetrical weighted capacitor corresponding to the negative capacitor array are flipped from the access reference voltage signal to the access ground signal (GND).

[0150] The equivalent threshold shift for the extended decision is suggested to be approximately 1.0 LSB, and it is designed in conjunction with the comparator regeneration time and CDAC parasitic capacitance.

[0151] The extended decision mechanism provided in this embodiment achieves range symmetry: when the conventional successive approximation reaches full range (all digital codes are 1), a threshold shift + re-decision extension mechanism is triggered, expanding the 16 levels to 17 levels (generalized to...). Level expansion The +1 level makes the end-transmission characteristics more symmetrical and the boundaries easier to handle, while improving the stability of the loop. The output codeword is symmetrical about the zero point and has a time mean of 0, so the integrator no longer accumulates the equivalent DC bias; therefore, DC drift and even harmonics are significantly reduced, the total harmonic distortion (THD) and spurious-free dynamic range (SFDR) are improved, and the measurement deviation is reduced accordingly.

[0152] Furthermore, this application also provides a successive approximation converter, including a differential capacitor array, a comparator, and a logic control circuit; the power supply terminals of the positive and negative capacitor arrays of the differential capacitor array are supplied with corresponding analog voltage signals, the output ports of the positive and negative capacitor arrays are connected to the input terminals of the comparator, and the output terminals of the comparator are connected to the logic control circuit.

[0153] The logic control circuit is used to execute the steps of the above analog-to-digital conversion method to complete the conversion process.

[0154] Specifically, in the logic control circuit, the functions are: coordinating the switching states of the differential capacitor array (CDAC) at each stage, receiving the comparator output and generating codewords; and simultaneously implementing pre-offset (forming a zero-code flat region) and extended decision (…). → +1) Two key controls.

[0155] Inputs: Start signal, comparator decision bit, reference voltage selection signal, reset / clear.

[0156] Outputs: control switches for each weighted capacitor, encoding results, full-scale detection, and extended decision triggering.

[0157] Logical form: Since the logic is clear, it can be implemented with simple sequential logic circuits. This application uses a finite state machine to manage timing and conditional branches; the output encoding and state control are decoupled, which facilitates synthesis and timing convergence.

[0158] One embodiment is provided, consisting of a state mechanism: S0 Sampling: The differential input is sampled to the CDAC; an initial charge distribution is established. S1 Pre-offset (flattening): The positive and negative capacitor arrays are pre-offset, introducing an equivalent offset of 0.5 LSB to form a zero-code flat region. S2 Successive Approximation: The weighted capacitors are switched sequentially from high to low according to their bit weights, and the comparator makes a bit decision until an N-bit normal code is obtained. S3 Full-scale Detection: If the normal code is full-scale (all 1s), the process continues; otherwise, it proceeds to S5 to output the code. S4 Extended Decision Stage: The weighted capacitors P1 and N1 are switched synchronously, the shift threshold is 1 LSB, and a re-decision is performed to subdivide the full-scale end into two unique codes (equivalent). +1 level). S5 output: Outputs the final codeword; resets necessary control bits, preparing for the next sampling.

[0159] Note: Extended decision occurs only on the full-scale path. When a preliminary full-scale code is detected (e.g., all bits are '1' for positive full scale), the control logic initiates an extended decision phase. In this phase, the comparison threshold is shifted by a preset amount (e.g., approximately 1 LSB) by reconfiguring the states of one or more capacitors within the array. A final comparison is then performed based on this shifted threshold to resolve the input signal into one of two distinct full-scale output codes.

[0160] The embodiments of this application achieve the following functions:

[0161] (1) Zero-point stability, suppressing limit cycles and idle tones;

[0162] By pre-flipping to form a zero-code flat region near the zero point, the quantization characteristics at the zero point are continuous and the average value of zero input is 0; therefore, the small signal no longer flips repeatedly near the zero point, the loop is difficult to form a deterministic repeating sequence, the in-band spectrum is significantly cleaner, and the small signal signal-to-noise ratio (SNR) is improved accordingly.

[0163] (2) Linearity is improved and even-order distortion is significantly reduced;

[0164] The output codeword is symmetrical about the zero point and has a time mean of 0, so the integrator no longer accumulates the equivalent DC bias; therefore, DC drift and even harmonics are significantly reduced, total harmonic distortion (THD) and spurious-free dynamic range (SFDR) are improved, and measurement deviation is reduced accordingly.

[0165] (3) Noise statistics are closer to whitening, and noise shaping efficiency is improved;

[0166] Medium flattening weakens the correlation between quantization error and input, making the error spectrum flatter; therefore, noise shaping can more fully push quantization noise out of the band, making the in-band noise closer to the theoretical value, and the dynamic range (DR) has greater room for improvement.

[0167] (4) The digital back-end is simplified, and latency and power consumption are reduced;

[0168] The code contains zeros and is symmetric about zero, so the average output is 0 when there is zero input. Therefore, the dependence of the digital signal processing side on offset correction and codeword remapping is significantly reduced, and the corresponding operation path, storage and timing protection can be simplified, resulting in a reduction in overall latency and power consumption.

[0169] (5) It is friendly to weak signals and can obtain clean spectral lines without dithering or pre-gain;

[0170] Clean in-band spectral lines and high small-signal SNR can be obtained without injecting dither and without the need for a programmable gain amplifier (PGA); the complexity and uncertainty caused by gain switching and calibration are avoided.

[0171] (6) Better boundary stability and improved full-scale resolution;

[0172] Extended decision is triggered only in full-scale state, unlike the regular decision. Level expansion to +1 level (e.g., 16 levels expanded to 17 levels); therefore, the quantization transmission characteristics are more symmetrical at the boundaries and the overload recovery is more stable.

[0173] (7) Low cost and easy to scale up for mass production;

[0174] The solution is mainly reflected in the lightweight adjustment of the CDAC connection and control phase sequence, as well as the control logic of one extended decision; therefore, the area, power consumption and timing margin are controllable, which is convenient for large-scale integration in low-power, low-area audio system-on-chip (ASoC) and sensor readout chips.

[0175] This application, employing the approach of "pre-flipping to achieve mid-scale characteristics + full-scale extended decision," balances three key attributes: zero-point stability, output symmetry, and weak error correlation. In engineering, it simultaneously offers the potential to improve SNR / THD / SFDR / DR while reducing implementation complexity, making it suitable for widespread application in high-fidelity audio and weak signal precision measurement scenarios. Furthermore, this application is applicable to audio... Quantizers for modulators, high-precision instrument measurement ADCs, and front-end readout circuits for sensors / MEMS (Micro-Electro-Mechanical Systems) are all applications requiring strict control over DC error, low-frequency noise, and output symmetry. Pre-offset and extended decision techniques are applicable to SAR ADCs of arbitrary resolution N, can be used in single-ended or differential architectures, and can be applied to various capacitor array topologies, including but not limited to binary weighting, split capacitors, charge scaling, and C-2C.

[0176] Figure 10 This application provides a schematic diagram of the upper electrode sampling stage, as shown in the embodiment. Figure 10 As shown, during the sampling phase of the upper plate, the upper plate is connected to the input signal, and the lower plate is connected to the reference voltage. Once the voltage stabilizes, the input signal is disconnected, and the sampling phase ends. This is illustrated using the charge of a positive capacitor array as an example. The voltage across the upper plate of the positive capacitor array and the voltage at the positive input terminal of the comparator are both: .

[0177] Figure 11 This is a schematic diagram of the structure of the comparison stage during sampling of the lower electrode plate, as provided in an embodiment of this application. Figure 11 As shown, since the reference voltage of the lower plates of the positive and negative capacitor arrays remains unchanged, the voltages of their upper plates remain VIP and VIN, i.e. The comparator starts working, and subsequently, the 8C capacitor is toggled based on the decision result. If... If the result is 1, the output is 1; otherwise, it's 0. This determines the decision of the highest bit, which is the dividing point between 1000 and 0000. An additional flipping stage is introduced. Figure 12 This application provides a schematic diagram of the pre-offset stage during sampling of the lower electrode, as shown in the embodiment of the present application. Figure 12 As shown, a pre-offset process occurs, changing the reference voltage of a portion of ICs. Taking the charge of the positive capacitor array as an example: According to the law of charge conservation, Q1 = Q2. The voltage between the upper plate of the positive capacitor array and the positive input terminal of the comparator is: This is equivalent to a 0.25 LSB reduction in the input positive voltage. Right now, Output 1 at time. Output 0.

[0178] The analog-to-digital conversion method and successive approximation converter provided in this application have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

[0179] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. An analog-to-digital conversion method, characterized in that, A logic control circuit is applied to a successive approximation converter; the successive approximation converter includes a differential capacitor array, a comparator, and a logic control circuit; a corresponding analog voltage signal is applied to the power supply terminals of the positive and negative capacitor arrays of the differential capacitor array, the output ports of the positive and negative capacitor arrays are connected to the input terminals of the comparator, and the output terminals of the comparator are connected to the logic control circuit. The method includes: The weights of the weighted capacitors in the positive and negative capacitor array are weighted to obtain the offset control strategy corresponding to each weight processing. The first charge equation of the positive and negative capacitor arrays during the sampling phase and the second charge equation corresponding to each offset control strategy are obtained; the first charge equation and each of the second charge equations are then combined to obtain the voltage deviation signals corresponding to the positive and negative input terminals of the comparator, so as to determine the corresponding change reference signals. The final differential offset code is determined based on the quantization voltage formula of the differential capacitor array, the various changing reference signals, and the zero-point offset interval; and the positive and negative capacitor arrays are offset according to the final differential offset code to successively approximate the analog voltage signal to obtain the corresponding digital signal.

2. The analog-to-digital conversion method according to claim 1, characterized in that, When sampling the first plate of the positive and negative capacitor array, the weights of the weighted capacitors of the positive and negative capacitor array are weighted to obtain the offset control strategy corresponding to each weighted processing, including: Obtain the symmetrical weighted capacitors of the positive and negative capacitor array; In each symmetrical weighted capacitor, the weights of the first target symmetrical weighted capacitor are merged to obtain the corresponding first weight allocation strategy; wherein, the first target symmetrical weighted capacitor has at least one pair of symmetrical weighted capacitors. The weights of the weight capacitors in each first weight allocation strategy are pre-shifted to obtain the corresponding offset control strategy.

3. The analog-to-digital conversion method according to claim 2, characterized in that, The process of determining the second charge equation corresponding to each of the aforementioned offset control strategies includes: Obtain the first target symmetric weighted capacitor corresponding to the weight merging process of the positive and negative capacitor arrays and the first non-target symmetric weighted capacitor corresponding to the one that has not undergone weight merging process; Connect one of the weighted capacitors of the first non-target symmetrical weighted capacitor to the reference voltage signal, and connect the other weighted capacitor to the ground signal. The first target symmetrical weighted capacitor is connected to the ground signal for the weighted capacitor corresponding to the positive capacitor array, and the weighted capacitor corresponding to the negative capacitor array is connected to the reference voltage signal. The charge equations of the positive and negative capacitor arrays are determined based on the first target symmetric weighted capacitor and the first non-target symmetric weighted capacitor after each signal is received, and are used as the second charge equations.

4. The analog-to-digital conversion method according to claim 1, characterized in that, When sampling the second plate of the positive and negative capacitor array, the weights of the weighted capacitors of the positive and negative capacitor array are weighted to obtain the offset control strategy corresponding to each weighted processing, including: Acquire the symmetrical weighted capacitors of the positive and negative capacitor array during the sampling phase; Determine the second target symmetric weight capacitor among all symmetric weight capacitors; In each symmetrical weighted capacitor, the weights of the second non-target symmetrical weighted capacitor (excluding the second target symmetrical weighted capacitor) are frozen, and the weights of the second target symmetrical weighted capacitor are pre-offset to obtain the corresponding offset control strategy; wherein, the second target symmetrical weighted capacitor has at least one pair of symmetrical weighted capacitors.

5. The analog-to-digital conversion method according to claim 3, characterized in that, The process of determining the changing reference signal includes: The initial voltage deviation signal of the positive and negative capacitor array before weighting is obtained based on the law of charge conservation. The initial voltage deviation signal and each of the weighted voltage deviation signals are subtracted from each other to obtain the corresponding initial change reference signal; The initial change reference signals under each offset control strategy are summed to obtain the final change reference signal under each offset control strategy.

6. The analog-to-digital conversion method according to claim 5, characterized in that, The final differential offset code is determined based on the quantization voltage formula of the differential capacitor array, the aforementioned changing reference signals, and the zero-point offset interval, including: Substitute each of the aforementioned change reference signals into the quantization voltage formula to obtain the corresponding initial differential offset code; In each of the initial differential offset codes, the integer form of the initial differential offset code is excluded according to the zero-point offset interval to obtain the remaining initial differential offset code; The remaining initial differential offset code is used as the final differential offset code.

7. The analog-to-digital conversion method according to claim 6, characterized in that, Using the remaining initial differential offset code as the final differential offset code includes: When the number of remaining initial differential offset codes is one, the remaining initial differential offset code is used as the final differential offset code; When there are multiple remaining initial differential offset codes, the smallest remaining initial differential offset code is taken as the final differential offset code.

8. The analog-to-digital conversion method according to claim 2, characterized in that, In each symmetrically weighted capacitor, the first target symmetrically weighted capacitor is subjected to corresponding weight merging processing to obtain the corresponding first weight allocation strategy, including: When the first target symmetrical weighted capacitor is a pair of symmetrical weighted capacitors, the two weighted capacitors of the pair of symmetrical weighted capacitors are connected in parallel to obtain a single weighted capacitor, thereby completing the weight merging process of the first target symmetrical weighted capacitor. When the first target symmetrical weighted capacitor consists of multiple pairs of symmetrical weighted capacitors, all weighted capacitors of the multiple pairs of symmetrical weighted capacitors are connected in parallel to obtain a single weighted capacitor, thereby completing the weight merging process of the first target symmetrical weighted capacitor.

9. The analog-to-digital conversion method according to claim 3, characterized in that, In the process of successive approximation processing of the analog voltage signal, when the digital signals output by the comparator are all 1 in each successive decision, the method further includes: Obtain the symmetrical weighted capacitors of the positive and negative capacitor arrays when all digital signals are 1; The weighted capacitor corresponding to the first target symmetrical weighted capacitor in the positive capacitor array is flipped from the access ground signal to the access reference voltage signal; The first target symmetrical weighted capacitor is flipped from the reference voltage signal to the ground signal to achieve full-range symmetry of the differential capacitor array.

10. A successive approximation converter, characterized in that, It includes a differential capacitor array, a comparator, and a logic control circuit; the power supply terminals of the positive and negative capacitor arrays of the differential capacitor array are applied with corresponding analog voltage signals, the output ports of the positive and negative capacitor arrays are connected to the input terminals of the comparator, and the output terminals of the comparator are connected to the logic control circuit. The logic control circuit is used to execute the steps of the analog-to-digital conversion method according to any one of claims 1 to 9, and to complete the conversion process.

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