System and method for concurrent decoding of product-boosted low density parity check (LDPC) codes

Abstract

The invention relates to a system and a method for concurrent decoding of a product boosted low density parity check (LDPC) code. In some embodiments, an apparatus may include a receiver and one or more processors. The one or more processors may be configured to identify a low density parity check (LDPC) code corresponding to a bipartite graph including a set of edges connected between a first set of nodes and a second set of nodes. The one or more processors may be configured to generate a first set of messages and a second set of messages using the encoded data. The one or more processors may be configured to concurrently communicate the first set of messages with a first subset and the second set of messages with a second subset using the bipartite graph. The one or more processors may be configured to identify decoded data based at least on processing of the first set of messages and the second set of messages.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 705,874, filed October 10, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure generally relates to systems and methods for improving the decoding and / or coding processes of communication systems, including but not limited to systems and methods for concurrent decoding of product-enhanced low-density parity-check (LDPC) codes. Background Technology

[0004] Error correction codes enable the reliable exchange of information data between a transmitter communication system and a receiver communication system. The transmitter communication system encodes the information data to obtain codewords. A codeword is encoded information data. The transmitter communication system transmits the codeword to the receiver communication system. Due to noise in the communication channel, the transmission received by the receiver communication system may differ from the transmitted codeword. Encoding the information data allows the receiver communication system, with an appropriate decoding process, to recover the information data from the received transmission despite the presence of such noise. For example, the transmitter communication system transmits parity bits to the receiver communication system. Parity bits allow the receiver communication system to verify whether the received transmission is a valid codeword and to correct errors in the transmission if the received transmission is not a valid codeword. In one approach, generating parity bits involves a complex process. Summary of the Invention

[0005] On one hand, this disclosure provides an apparatus comprising: a receiver configured to receive encoded data; and one or more processors configured to: identify low-density parity-check (LDPC) codes corresponding to a bipartite graph including a set of edges connected between a first set of nodes and a second set of nodes, wherein the LDPC codes are generated using a first LDPC code associated with a first subset of the second set of nodes and a second LDPC code associated with a second subset of the second set of nodes; use the encoded data to generate a first set of messages and a second set of messages; use the bipartite graph to concurrently communicate the first set of messages with the first subset and the second set of messages with the second subset; and identify decoded data at least based on processing of the first set of messages and the second set of messages.

[0006] On the other hand, this disclosure provides a method comprising: receiving encoded data by a receiver; identifying by one or more processors a low-density parity-check (LDPC) code corresponding to a bipartite graph including a set of edges connecting a first set of nodes and a second set of nodes, wherein the LDPC code is generated using a first LDPC code associated with a first subset of the second set of nodes and a second LDPC code associated with a second subset of the second set of nodes; using the encoded data by the one or more processors to generate a first set of messages and a second set of messages; using the bipartite graph by the one or more processors to concurrently communicate the first set of messages with the first subset and the second set of messages with the second subset; and identifying decoded data by the one or more processors at least based on processing of the first set of messages and the second set of messages.

[0007] On the other hand, this disclosure provides an apparatus comprising: a receiver configured to receive encoded data; and one or more processors configured to: identify low-density parity-check (LDPC) codes corresponding to a bipartite graph including a first bipartite graph and a second bipartite graph sharing one or more edges, wherein the LDPC codes are generated using a first LDPC code associated with the first bipartite graph and a second LDPC code associated with the second bipartite graph; generate a first set of messages and a second set of messages using the encoded data; concurrently communicate the first set of messages using the first bipartite graph and communicate the second set of messages using the second bipartite graph; and identify decoded data at least based on processing of the first set of messages and the second set of messages. Attached Figure Description

[0008] The various objects, aspects, features, and advantages of this disclosure will become more apparent and better understood through reference to the detailed description taken in conjunction with the accompanying drawings, in which similar reference characters consistently identify corresponding elements. In the drawings, similar reference numerals generally indicate equivalent, functionally similar, and / or structurally similar elements.

[0009] Figure 1 It is a diagram depicting an instance communication environment having a communication system according to one or more embodiments.

[0010] Figure 2 This is a schematic block diagram of a computing system according to an embodiment.

[0011] Figure 3 It is a graph depicting an instance index matrix according to one or more embodiments.

[0012] Figure 4 It is a diagram depicting an instance shifted identity matrix according to one or more embodiments for generating a parity check matrix.

[0013] Figure 5It is a graph depicting an instance parity check matrix according to one or more embodiments.

[0014] Figure 6 It is a graph depicting an instance index matrix according to one or more embodiments.

[0015] Figures 7A to 7B Figure 700 depicts an instance bipartite graph and associated parity check matrix according to one or more embodiments.

[0016] Figures 8A to 8B It is a diagram depicting the processing of variables and verification nodes according to one or more embodiments.

[0017] Figure 9 It is a graph depicting the relationship between variable nodes and check nodes in a 2x LDPC graph according to one or more embodiments.

[0018] Figure 10 It is a diagram depicting the decomposition into parallel processes according to one or more embodiments.

[0019] Figures 11A to 11B It is a diagram depicting the parallel decomposition at the check node view according to one or more embodiments.

[0020] Figures 12A to 12B It is a graph depicting the decomposition of variables at the node view according to one or more embodiments in parallel.

[0021] Figure 13 This is a flowchart illustrating the concurrent decoding process used for product-enhanced LDPC codes.

[0022] Details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first feature communicating with or communicatively coupled to a second feature may include embodiments in which the first feature directly communicates with or is directly coupled to the second feature, and may also include embodiments in which an additional feature may intervene between the first and second features, such that the first feature indirectly communicates with or is indirectly coupled to the second feature. Additionally, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0024] The various embodiments disclosed herein relate to a device including a receiver and one or more processors. The one or more processors may be configured to recognize low-density parity-check (LDPC) codes corresponding to a bipartite graph comprising a set of edges connecting a first set of nodes and a second set of nodes. The LDPC codes may be generated using a first LDPC code associated with a first subset of the second set of nodes and a second LDPC code associated with a second subset of the second set of nodes. The one or more processors may be configured to use the encoded data to generate a first set of messages and a second set of messages. The one or more processors may be configured to concurrently communicate the first set of messages with the first subset and the second set of messages with the second subset using the bipartite graph. The one or more processors may be configured to recognize decoded data at least based on processing of the first set of messages and the second set of messages.

[0025] In some implementations, the LDPC code may be a product boosting code generated using the first LDPC code and the second LDPC code.

[0026] In some implementations, the first set of messages may be log-likelihood ratio (LLR) values. In these implementations, the second set of messages may also be LLR values.

[0027] In some implementations, the one or more processors may be configured such that nodes in the first group of nodes selectively receive messages from nodes in the first subset of the second group of nodes or from nodes in the second subset of the second group of nodes.

[0028] In some implementations, the first LDPC code may be associated with a first subset of the first group of nodes, and the second LDPC code may be associated with a second subset of the first group of nodes.

[0029] In some implementations, the one or more processors may be configured to process the first and second sets of messages at the second set of nodes in response to the communication of the first and second sets of messages to generate a third and a fourth set of messages. In some implementations, the one or more processors may be configured to use the bipartite graph to concurrently communicate the third set of messages with a first subset of the first set of nodes and the fourth set of messages with a second subset of the first set of nodes.

[0030] In some implementations, the one or more processors are configured such that nodes in the second group of nodes selectively receive messages from nodes in the first subset of the first group of nodes or from nodes in the second subset of the first group of nodes.

[0031] In one aspect, the parity check matrix defines a set of equations that any valid codeword satisfies. The parity check matrix can be used to encode low-density parity check (“LDPC”) codes, described by Richardson and Urbanke in the IEEE Transactions on Information Theory (Vol. 47, No. 2 (February 2001)). Generally, many wireless and wired communication systems use LDPC as a forward error correction write coding scheme. However, the longest block length (in bits) of write-coded data supported in the 802.11 standards (e.g., 802.11n-802.11be) is 1944. Using a block length of 1944 allows for finite gain in radio channels (e.g., 2x2 multiple-input multiple-output channels).

[0032] In one aspect, the base code can be product-enhanced. Product-enhanced LDPC codes can be constructed by copying and permuting smaller base codes, resulting in larger codes with enhanced error correction capabilities and efficient hardware implementations. For example, a 2x LDPC code can be constructed by copying and permuting a 1x LDPC code. However, product-enhanced codes can result in a code block length that is twice that of the original code. For example, enhancing the product of a base code with a block length of 1944 can result in a base code with a block length of 3888. A block length of 3888 is twice the block length of the longest code supported in the 802.11n-802.11be standard (e.g., a block length of 1944). While in some instances a 2x LDPC code can be decomposed into two 1x LDPC codes that can be processed in parallel using conventional methods, certain structures of 2x LDPC codes can pose significant challenges to decomposition due to node dependencies. For example, LDPC structures involving cross-connections between subgroups of variables and check nodes may not be decomposed for parallel processing using conventional methods.

[0033] To address this problem, embodiments of this disclosure, according to certain aspects, relate to a technique for supporting the decomposition of 2x LDPC codes with cross-connections for parallel processing. In some instances, a variable node may selectively receive messages from a first subgroup or a second subgroup of a check node. Similarly, a check node may selectively receive messages from a first subgroup or a second subgroup of a variable node. For example, a multiplexer (MUX) may select the node from which a variable node will receive messages by dynamically routing incoming signals based on predefined criteria or control signals. In this example, the MUX may select nodes from both the first and second subgroups of the check node for the variable node to receive messages (and vice versa). Thus, the LDPC structure involving cross-connections between the subgroups of the variable and check nodes can be decomposed for parallel processing. This allows a 2x LDPC code with cross-connections to be decomposed into two 1xLDPC codes that can be processed in parallel using existing hardware and / or methods.

[0034] The entire contents of the following IEEE standards (including any draft versions of such standards) are hereby incorporated by reference and form part of this disclosure for all purposes: WiFi Alliance standards and IEEE 802.11 standards, including but not limited to IEEE 802.11a™, IEEE 802.11b™, IEEE 802.11g™, IEEE P802.11n™; IEEE P802.11ac™; and IEEE P802.11be™ to IEEE P802.11bn™ standards. Although this disclosure may refer to aspects of these standards, it is in no way limited to these standards.

[0035] In one aspect, the parity check matrix defines a set of equations that any valid codeword satisfies. The parity check matrix can be used to encode low-density parity check (“LDPC”) codes, as described by Richardson and Urbanke in the IEEE Transactions on Information Theory (Vol. 47, No. 2 (February 2001)). Generally, many wireless and wired communication systems use LDPC as a forward error correction coding scheme.

[0036] In one aspect, LDPC codes have a quasi-cyclic (QC) structure, which facilitates efficient encoding and decoding. In some embodiments, QC-LDPC codes can be a type of structured LDPC code that can be used in many practical applications, including IEEE 802.11n, 802.11ac, 802.11ax, and 802.11be standards. In QC-LDPC codes, the parity check matrix has a cyclic structure that repeats itself in a quasi-cyclic manner, which simplifies the encoding and decoding process, thereby making QC-LDPC encoding more efficient. The block size (denoted by n) refers to the total number of write or transmit bits as a result of encoding data using error correction codes (e.g., LDPC). The number of information bits (denoted by k) refers to the number of bits carrying data to be encoded using error correction codes. The code rate (denoted by R) refers to the ratio of the number of information bits to the block size (R = k / n). In some embodiments, an LDPC encoder can acquire a block of k information bits and generate n write bits with a code rate of R = k / n. An LDPC decoder can operate on n received bits (the noisy version of them) and (ideally) recover k information bits. In some embodiments, an LDPC encoder can take a block of k information bits as input, encode the k-bit block to produce a block of n write bits with a code rate of R (=k / n).

[0037] Generally, the parity check matrix of a code represents an equation that determines whether an error has occurred during transmission. More formally, for all valid codewords (i.e., error-free bits generated by the encoder), the following equation may be true:

[0038] …………… (Equation 1)

[0039] In Equation 1, "H" is the parity check matrix, "c" is the codeword vector, and "0" is a vector of all zeros. The parity check matrix H is one way to describe a code.

[0040] The code generator matrix G satisfies the following equation:

[0041] …………… (Equation 2)

[0042] In Equation 2, “s” is a vector of information bits, “G” is the generator matrix, and “c” is the codeword corresponding to “s”. In some embodiments, the system (e.g., Figure 1 A communication system 108 containing a decoder 160 can use Equation 2 to decode codeword c to obtain decoded data s.

[0043] According to the matrix equations above, the parity check matrix of a code is related to its generator matrix. Generally, if the parity check matrix is ​​low-density, the corresponding generator matrix will be high-density, and vice versa. Therefore, LDPC codes are characterized by a low-density parity check matrix and a high-density generator matrix. The density of the matrix is ​​related to the number of operations that must be performed to implement one of the equations above. Although it was recognized in 1995 that LDPC codes could be used to transmit data with very few errors, i.e., an error rate as good as or better than turbo codes, one drawback of LDPC codes is that their generator matrix is ​​high-density, which makes the coding computationally intensive, thus rendering the codes impractical in many applications.

[0044] In some implementations, the parity check matrix may have a quasi-cyclic structure, such as the parity check matrix used for QC-LDPC codes. For example, given a boost size z, the parity check matrix may have multiple submatrices such that each submatrix is ​​a cyclically shifted version of an identity matrix of size (z x z), where z is an integer greater than 1. The parity check matrix can be represented in two equivalent forms: (1) the parity check matrix H and (2) the block matrix or exponential matrix P = E(H).

[0045] In some implementations, the parity check matrix H can be a binary matrix of size m x n (where each of m and n is an integer). The elements of the parity check matrix are binary values. Given a block length n and a code rate R, the LDPC code (or QC-LDPC code) LDPC(n, R) satisfies the following equation:

[0046] …………… (Equation 3)

[0047] …………… (Equation 4)

[0048] In some implementations, a block matrix or an exponential matrix (QC-LDPC exponential matrix) can be obtained. Given a lift size z, the exponential matrix P=E(H) can have a size of m / z x n / z. If n=24z, then the size of P=E(H) is 24(1-R) ​​x 24 (=n(1-R) / z x n / z). The elements of the exponential matrix can be integer values ​​corresponding to the cyclic shift values ​​of an identity matrix of size z x z. The parity matrix H can be a sparse binary matrix that can be derived from the exponential matrix P=E(H). The generator matrix G can have a size of n x k in binary form (e.g., the elements of the generator matrix G are binary values). The exponential matrix P=E(H) can have a structure containing multiple submatrices (e.g., A, B, C, D, E, T).

[0049] In some embodiments, a binary QC-LDPC code LDPC(n, R) may be characterized by the null space of an n(1 - R)×n parity-check matrix H. The parity-check matrix H may be a binary sparse matrix that includes a set of circulant matrices of size z x z. The parity-check array H of the QC-LDPC code may be equivalently represented by an exponent matrix P = E(H). This representation helps to illustrate the graphical structure of the underlying code together with the shift coefficients as a base graph.

[0050] In some embodiments, the parity-check matrix H may be generated from the exponent matrix P = E(H). The exponent matrix P = E(H) may include shift values d in the range 0 <= d < z and d = -1 (as an element). For example, if z = 7, then the shift values d may include -1, 0, 1, 2, 3, 4, 5, 6. The shift value d = 0 may correspond to (or map to) an identity matrix of size z x z, denoted by I(z). The shift value d = -1 may correspond to (or map to) a zero matrix of size z x z (all elements zero), denoted by . Any other integer value d in [1, z - 1] may correspond to (or map to) a matrix that is cyclically right-shifted from I(z). The parity-check matrix H may be obtained from the exponent matrix P = E(H) by expanding the exponent matrix P such that each element (as the shift value d) of the exponent matrix P is replaced by a matrix corresponding to the shift value.

[0051] In some embodiments, the exponent matrix P = E(H) may include multiple elements P1,1, P1,2, P1,3, …, P1,ń; P2,1, P2,2, P2,3, …, P2,ń; …, P1,1, P1,2, P1,3, …, P ,ń, which correspond to ( x ń) values, where and ń satisfy the following equations:

[0052] …………… (Equation 5)

[0053] …………… (Equation ⑥)

[0054] The exponent matrix (or permutation matrix) P = E(H) may be represented as follows:

[0055] …(Equation 7)

[0056] The corresponding parity-check matrix H may be obtained by replacing each element (as the shift value d) of the matrix with a matrix C(d) corresponding to the shift value as follows:

[0057] …(Equation 8)

[0058] For example, matrix C(1) can be represented as follows:

[0059] ... (Equation 9)

[0060] In some implementations, the encoder may use a generator matrix (e.g., using Equation 2) to generate codewords. In some embodiments, the encoder may use a parity check matrix (instead of a generator matrix) to generate codewords from a vector of information bits. After obtaining the parity check matrix H, the parity check matrix H may have submatrices A, B, C, D, T, and E. The upper region O of the submatrix T may correspond to a region in which the matrix contains all zeros, while other regions may represent positions that may contain one.

[0061] In some implementations, the codeword c can be obtained through the following expression:

[0062] ... (Equation 10),

[0063] Where “s” is the vector of information bits to be encoded, “p1” is the vector of the first g parity bits and “p2” is the vector of the remaining mg parity bits.

[0064] Vectors p1 and p2 can be obtained through the following equation:

[0065] ... (Equation 11);

[0066] ... (Equation 12); and

[0067] ………… (Equation 13).

[0068] Although the various embodiments disclosed herein describe the encoding of data for wireless communications (e.g., wireless local area networks (WLANs) conforming to any IEEE 802.11 standard), the principles disclosed herein are applicable to other types of communications (e.g., wired communications) or any process that performs LDPC code encoding.

[0069] In one area, Ultra High Reliability (UHR), or IEEE 802.11bn (also known as "Wi-Fi 8"), is a new research group within the IEEE 802.11 working group. Its aim is to research PHY (Physical Layer) and MAC (Media Access Control) technologies that can improve the reliability of WLAN (Wireless Local Area Network) connectivity. Depending on the complexity, several variations of the Wi-Fi 8 chip will be implemented for mobility and access.

[0070] In one aspect, IEEE 802.11bn proposes a new scheme for LDPC codes with a block length of 3888. These LDPC codes may have a product lifting structure. Since the block length (e.g., block size n=3888) is twice the current length (e.g., n=1944), the complexity of conventional decoders in decoding such codes may be much higher than the complexity in decoding existing codes.

[0071] To address this issue, according to certain aspects, embodiments of this disclosure relate to a technique for implementing and / or using concurrent and / or parallel decoding with two or more existing decoders. In some embodiments, the system may perform concurrent decoding of product-lifted LDPC codes.

[0072] In some embodiments, during the update process of iterative decoding of a product-lifted LDPC code (also referred to as "2xLDPC" when the lift size = 2), the graph can be appropriately divided into non-overlapping subgraphs identical to those of the base code (also referred to as "1xLDPC"). This allows two nodes (which contain, for example, two complementary check nodes and a pair of connection variable nodes) to process messages in parallel by applying the original message-passing algorithm for the 1xLDPC graph. Therefore, the decoding process can be split across multiple cores. A core can be an individual processing unit within a central processing unit (CPU). In some instances, the CPU can contain multiple cores capable of independently executing individual instruction sets. These individual instruction sets can be processed concurrently, allowing the CPU to split independent portions of operations (e.g., LDPC decoding operations) within its cores for parallel processing.

[0073] In some embodiments, for iterative decoding of 2xLDPC codes, the graph can be decomposed into two identical 1xLDPC code graphs and a 1x2 bipartite graph. The 1x2 bipartite graph can be a fixed-structure component determined by the lifting mode. This composite decomposition of the graph is applicable to any type of message-passing-based decoding algorithm.

[0074] In some embodiments, the rules used to update check nodes (referred to as "check node update rules") may be rules based on classical belief propagation. In some embodiments, check node update rules may be less complex versions (compared to rules based on classical belief propagation), such as minimum sums or offset minimum sums. In some embodiments, the metric may be performed on a linear logarithmic scale.

[0075] In some embodiments, the scheduling of updating variables and verification nodes can be arbitrarily chosen (e.g., scheduling of variable and verification node updates). In some embodiments, any scheduling method (such as flooding, hierarchical, permutation hierarchical, hybrid, etc.) can be used while still maintaining the inherent parallelism of the update process.

[0076] The systems and methods according to some embodiments are scalable to any higher-order elevated LDPC code. For example, a 4xLDPC can be considered as a 2x2xLDPC and the scheme is scalable to 4xLDPC. The systems and methods according to some embodiments are directly applicable to all types of LDPC codes (including QC-LDPC and Irregular Repeat Accumulation (IRA) codes). For example, the systems and methods according to some embodiments can be used to concurrently decode all 3888-block-length LDPC codes in IEEE 802.11bn / UHR.

[0077] The embodiments in this disclosure have at least the following advantages and benefits. The embodiments in this disclosure provide useful techniques for parallel decoding, which are faster than conventional decoding schemes and can be performed on two separate cores. The embodiments in this disclosure can also reuse existing circuit systems with 1xLDPC codes.

[0078] Details of various embodiments of the method and system are set forth in the accompanying drawings, appendices and the description below.

[0079] refer to Figure 1 The illustration depicts an example communication environment 100 including communication systems (or communication devices) 105, 108 according to one or more embodiments. In one embodiment, communication system 105 includes a baseband circuit system 110 and a transmitter circuit system 120, and communication system 108 includes a baseband circuit system 150 and a receiver circuit system 140. In one aspect, communication system 105 is considered a transmitter communication system, and communication system 108 is considered a receiver communication system. These components operate together to exchange data (e.g., messages or frames) over a wireless medium. In one or more embodiments, these components are embodied as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof. In some embodiments, compared to Figure 1 As shown, communication systems 105 and 108 may include more, fewer, or different components. For example, each of communication systems 105 and 108 includes a transceiver circuitry to allow bidirectional communication between or with other communication systems. In some embodiments, each of communication systems 105 and 108 may have similar characteristics to those shown in [examples of other systems]. Figure 2 The configuration of the computing system 2000 shown in the figure.

[0080] The baseband circuitry system 110 of the communication system 105 is a circuitry system that generates baseband data 115 for transmission. The baseband data 115 contains information data (e.g., signals) at the baseband frequency used for transmission. In one method, the baseband circuitry system 110 includes an encoder 130 that encodes the data and generates or outputs parity bits. In one aspect, the baseband circuitry system 110 (or encoder 130) obtains a generator matrix or a parity matrix, or uses a previously generated generator matrix or a previously generated parity matrix, and encodes the information data by applying the information data to the generator matrix or parity matrix to obtain codewords. In some embodiments, the baseband circuitry system 110 stores one or more generator matrices or one or more parity matrices conforming to any IEEE 802.11 standard for WLAN communication. The baseband circuitry system 110 retrieves the stored generator matrix or the stored parity matrix in response to detecting information data to be transmitted or in response to receiving an instruction to encode the information data. In one method, baseband circuitry 110 generates parity bits based on a portion of a generator matrix or using a parity check matrix, and appends the parity bits to information bits to form a codeword. Baseband circuitry 110 generates baseband data 115 containing the codeword for communication system 108, and provides baseband data 115 to transmitter circuitry 120.

[0081] The transmitter circuitry 120 (generally referred to as a transmitter) of the communication system 105 includes or corresponds to a circuitry that receives baseband data 115 from the baseband circuitry 110 and transmits a radio signal 125 based on the baseband data 115. In one configuration, the transmitter circuitry 120 is coupled between the baseband circuitry 110 and an antenna 122. In this configuration, the transmitter circuitry 120 up-converts the baseband data 115 from the baseband circuitry 110 to a carrier signal to generate a radio signal 125 at a radio frequency (RF) frequency (e.g., 10 MHz to 60 GHz), and transmits the radio signal 125 through the antenna 122. In some embodiments, the antenna 122 is a plurality of multiple-input multiple-output (MIMO) antennas, including transmit antennas 121-1, 122-2, ..., 122-N. T (For example, transmitting antenna N) T The number is an integer greater than 1.

[0082] The receiver circuitry 140 of the communication system 108 is a circuitry that receives radio signal 125 from the communication system 105 and obtains baseband data 145 from the received radio signal 125. In one configuration, the receiver circuitry 140 is coupled between the baseband circuitry 150 and the antenna 142. In this configuration, the receiver circuitry 140 receives the radio signal 125 through the antenna 142 and down-converts the radio signal 125 at an RF frequency according to a carrier signal to obtain baseband data 145 from the radio signal 125. The receiver circuitry 140 then provides the baseband data 145 to the baseband circuitry 150. In some embodiments, the antenna 142 is a plurality of multiple-input multiple-output (MIMO) antennas, including receiving antennas 142-1, 142-2, ..., 142-N. R (For example, receiving antenna N) R The number is an integer greater than 1.

[0083] The baseband circuitry system 150 of the communication system 108 includes or corresponds to a circuitry system that receives baseband data 145 from the receiver circuitry system 140 and obtains information data from the received baseband data 145. In one embodiment, the baseband circuitry system 150 includes a decoder 160 that extracts information and parity bits from the baseband data 145. The decoder 160 decodes the baseband data 145 to obtain information data generated by the baseband circuitry system 110 of the communication system 105.

[0084] In some implementations, each of the baseband circuit system 110 (including encoder 130), transmitter circuit system 120, receiver circuit system 140, and baseband circuit system 150 (including decoder 160) may be one or more processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof.

[0085] Figure 2 This is a schematic block diagram of a computing system according to an embodiment. The illustrated example computing system 2000 includes one or more processors 2010 that communicate directly or indirectly with memory 2060 via a communication system 2040 (e.g., a bus), at least one network interface controller 2030 having a network interface port for connecting to a network (not shown), and other components such as input / output (“I / O”) components 2050. Typically, the processors 2010 will execute instructions (or computer programs) received from memory. The illustrated processors 2010 are incorporated into or connected to cache memory 2020. In some examples, instructions are read from memory 2060 into cache memory 2020 and executed by processor 2010 from cache memory 2020. The computing system 2000 may not necessarily contain... Figure 2 All of these components shown, and may contain Figure 2 Other components not shown in the image.

[0086] More specifically, processor 2010 can be any logic circuit system that processes instructions, such as instructions fetched from memory 2060 or cache 2020. In many embodiments, processor 2010 is a microprocessor unit or a dedicated processor. Computing device 2000 can be based on any processor or processor group capable of operating as described herein. Processor 2010 can be a single-core or multi-core processor. Processor 2010 can be multiple dissimilar processors.

[0087] Memory 2060 may be any device suitable for storing computer-readable data. Memory 2060 may be a device with fixed storage or a device for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), non-volatile memory, media and storage devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic disks, magneto-optical disks, and optical disks (e.g., CD-ROM, DVD-ROM, or Blu-ray® optical disks). Computing system 2000 may have any number of memory devices 2060.

[0088] Cache memory 2020 is typically a form of computer memory placed close to processor 2010 for fast read times. In some implementations, cache memory 2020 is part of processor 2010 or on the same chip as processor 2010. In some implementations, there are multi-level caches 2020, such as L2 and L3 cache layers.

[0089] Network interface controller 2030 manages data exchange via a network interface (sometimes referred to as a network interface port). Network interface controller 2030 handles the physical and data link layers of the OSI model for network communication. In some embodiments, some of the tasks of the network interface controller are handled by one or more of the processors 2010. In some embodiments, network interface controller 2030 is part of processor 2010. In some embodiments, computing system 2000 has multiple network interfaces controlled by a single controller 2030. In some embodiments, computing system 2000 has multiple network interface controllers 2030. In some embodiments, each network interface is a connection point for a physical network link (e.g., a Cat-5 Ethernet link). In some embodiments, network interface controller 2030 supports wireless network connectivity, and the interface port is a wireless (e.g., radio) receiver or transmitter (e.g., for IEEE 802.11, Near Field Communication "NFC", Bluetooth, ANT, or any other wireless protocol). In some embodiments, network interface controller 2030 implements one or more network protocols, such as Ethernet. Typically, computing device 2000 exchanges data with other computing devices via a network interface through a physical or wireless link. The network interface may be directly linked to another device or linked to another device via an intermediary device, such as a network device that connects computing device 2000 to a data network (e.g., the Internet), such as a hub, bridge, switch, or router.

[0090] The computing system 2000 may include or provide interfaces to one or more input or output (“I / O”) devices. Input devices include, but are not limited to, keyboards, microphones, touchscreens, foot pedals, sensors, MIDI devices, and pointing devices such as mice or trackballs. Output devices include, but are not limited to, video displays, speakers, refreshable Braille terminals, indicator lights, MIDI devices, and 2-D or 3-D printers.

[0091] Other components may include I / O interfaces, external serial device ports, and any additional coprocessors. For example, computing system 2000 may include interfaces (e.g., a Universal Serial Bus (USB) interface) for connecting input devices, output devices, or additional memory devices (e.g., portable flash drives or external media drives). In some embodiments, computing device 2000 includes additional devices such as coprocessors; for example, a math coprocessor may assist processor 2010 in performing high-precision or complex calculations.

[0092] Component 2050 can be configured to connect to external media, display 2070, input device 2080, or any other component or combination thereof in computing system 2000. Display 2070 can be a liquid crystal display (LCD), organic light-emitting diode (OLED) display, flat panel display, solid-state display, cathode ray tube (CRT) display, projector, printer, or other display device now known or hereafter developed for outputting specific information. Display 2070 can act as an interface for a user to view the functions of processor 2010, or more specifically, as an interface to software stored in memory 2060.

[0093] Input device 2080 may be configured to allow a user to interact with any of the components of computing system 2000. Input device 2080 may be a plurality of tablets, a keyboard, a cursor control device such as a mouse or a joystick. Alternatively, input device 2080 may be a remote control, a touchscreen display (which may be a combination of display 2070 and input device 2080), or any other device operable to interact with computing system 2000, such as any device operable to act as an interface between the user and computing system 2000.

[0094] Figure 3 This is a diagram depicting an instance exponent matrix (QC-LDPC exponent matrix) 300 according to one or more embodiments. Given a lift size z, the exponent matrix 300 may have a size of m / z x n / z. If n = 24z, then the size of P = E(H) is 24(1-R) ​​x 24 (= n(1-R) / z x n / z). The elements of the exponent matrix may be integer values ​​corresponding to the cyclic shift values ​​of an identity matrix of size z x z. Parity check matrix H (see...) Figure 5 The generator matrix G can be a sparse binary matrix that can be derived from the exponential matrix P = E(H). The generator matrix G can have a size n x k in binary form (e.g., the elements of the generator matrix G are binary values). See reference. Figure 3 The exponential matrix P=E(H) can have a structure containing multiple submatrices (e.g., A 310, B 312, C 316, D 318, E 320, T 314).

[0095] Figure 4FIG. 400 depicts example shift identity matrices 409, 410, 411, 412, 413, 414, 415, 416 for generating a parity check matrix according to one or more embodiments. The parity check matrix H can be generated from an exponent matrix P = E(H) (e.g., exponent matrix 300) or can be identified using a codebook. As shown in Equation 7, the exponent matrix P = E(H) can include shift values d in the range 0 <= d < z and d = -1 (as an element). For example, if z = 7, the shift values d can include -1, 0, 1, 2, 3, 4, 5, 6 (see Figure 4 ). The shift value d = 0 can correspond to (or map to) an identity matrix of size z x z, denoted by I(z) (e.g., matrix 410). The shift value d = -1 can correspond to (or map to) a zero matrix of size z x z (all elements zero), denoted by 0*I(z) (e.g., matrix 409). Any other integer value d in [1, z - 1] can correspond to (or map to) a matrix that is circularly right-shifted from I(z) (e.g., matrices 411, 412, 413, 414, 415, 416). As shown in Equation 8, the parity check matrix H can be obtained from the exponent matrix P = E(H) by expanding the exponent matrix P such that each element (as a shift value d) of the exponent matrix P is replaced by a matrix corresponding to the shift value.

[0096] Figure 5 FIG. depicts an example parity check matrix 500 according to one or more embodiments. In some embodiments, an encoder (e.g., encoder 130) can use a generator matrix (e.g., using Equation 2) to generate a codeword. In some embodiments, an encoder (e.g., encoder 130) can use a parity check matrix (instead of a generator matrix) to generate a codeword from a vector of information bits. After obtaining the parity check matrix H (e.g., using a codebook), the parity check matrix H (e.g., parity check array 500) can have submatrices A 510, B 512, C 516, D 518, T 514, E 520. The upper region O 515 of the submatrix T 514 (e.g., Figure 5 the white region in) can correspond to a region where the matrix contains all zeros, while other regions (e.g., Figure 5 the gray region in) can represent positions that can contain ones. The size of the parity check matrix 500 can be m x n, where the size of the submatrix D 518 is g x g, and the size of the submatrix T is (m - g) x (m - g). In some embodiments, given a vector s of information bits to be encoded, the encoder can use Equation 10, Equation 11, Equation 12, and Equation 13 to obtain the codeword c.

[0097] Figure 6This is a diagram depicting an instance exponent matrix (QC-LDPC exponent matrix) 600 according to one or more embodiments. Given a lift size z, the exponent matrix 600 can have a size of m / z x n / z. If n = 48z, then for n... The size is 48(1-R) ​​x 48 (=n(1-R) / z x n / z). The elements of the exponent matrix can be integer values ​​corresponding to the cyclic shift values ​​of the identity matrix of size z x z. The parity check matrix H can be derived from the exponent matrix. The sparse binary matrix derived from [the original text]. The generator matrix G can have a size of n x k in binary form (e.g., the elements of the generator matrix G are binary values). [Reference] Figure 6 exponential matrix It can have multiple submatrices (e.g., 610、 612、 616、 618、 620 The structure of 614).

[0098] Figures 7A to 7B Figure 700 depicts an instance bipartite graph and associated parity check matrix according to one or more embodiments. In some instances, LDPC coding may be associated with a boost size. The boost size can define the degree to which the base code bipartite graph is expanded. For example, a 2x LDPC code can double the block length. For example, a double-boosted 1944 code can produce a block length of 3888.

[0099] Figure 7AThis is a graph of a basecode (e.g., "1x LDPC") bipartite graph 702 and a basecode parity matrix 704 according to one or more embodiments. The bipartite graph may represent a matrix (e.g., the basecode parity matrix 704) with two disjoint and independent sets of vertices (e.g., in the basecode bipartite graph 702, a set of left vertices indicated by circles and a set of right vertices indicated by rectangles). In some instances, the set of left vertices may be called variable nodes and may represent columns in the basecode parity matrix 704. In these instances, the set of right vertices may be called parity nodes and may represent rows in the basecode parity matrix 704. The basecode bipartite graph 702 may represent edge connections (e.g., relations) between variable nodes (e.g., columns) and parity nodes (e.g., rows) of the basecode parity matrix. In instances, codewords may be decoded based on operations along edge connections (e.g., XOR, minimum sum, offset minimum sum, belief propagation, and / or the like). After a certain number of iterations (e.g., determined by an iterative decoding algorithm and / or convergence criteria), the decoder can determine the values ​​of the decoded bits based on the basecode bipartite graph 702 and the basecode parity check matrix 704. The parity check nodes can receive the decoded bits (e.g., log-likelihood ratio (LLR) values) determined by the variable nodes via edge connections. Alternatively, the basecode parity check matrix 704 can also be used to determine the validity of the codeword. For example, the codeword can be multiplied by the transpose of the parity check matrix to determine its validity. In this example, if the operation results in a zero vector, then the codeword is considered valid.

[0100] Figure 7B This is a graph of a 2x LDPC (e.g., double product boost) bipartite graph 706 and a 2x LDPC parity matrix 708 according to one or more embodiments. In some instances, the base bipartite graph can be modified (e.g., edge connectivity changes, moves, shifts, migrations, and / or the like) to produce a 2x LDPC bipartite graph, such as 2x LDPC bipartite graph 706. In some instances, the 2x LDPC parity matrix 708 can be decomposed into two overlapping bipartite graphs (e.g., a 1x LDPC bipartite graph) with the same degree distribution. For example, the edge connectivity (e.g., v1) of a given node in the first bipartite graph may overlap with that of the second bipartite graph (e.g., v1). The edge connections of the nodes described in the diagram are identical. Variable nodes and / or check nodes can be grouped into two groups corresponding to two overlapping bipartite graphs of the same size. By decomposing the 2x LDPC bipartite graph, the resulting graph can be decoded in parallel. This allows the two bipartite graphs to be processed on a separate core, thereby reducing the need for dedicated hardware for 2x LDPC decoding and reducing processing time.

[0101] Figures 8A to 8BFigure 800 depicts variable and check node processing according to one or more embodiments. In some instances, encoded data can be received by a receiver. However, in some instances, the encoded data may contain errors. For example, the receiver may fail to correctly identify bits in the encoded data as 1 or 0 (e.g., due to interference, distortion, noise, and / or the like in the signal containing the encoded data). In this example, check node processing and variable node processing (e.g., ...) are used. Figure 8A and Figure 8B The iterative decoding process (including check node processing and variable node processing) shown in the diagram can be used to decode data and thereby correct misidentified values. In some instances, a log-likelihood ratio (LLR) value can be generated based on the received signal containing encoded data. The LLR value indicates the probability that a bit in the received signal is 1 or 0 and can be updated at each layer of the iterative decoding process using check node processing and variable node processing. Messages initialized based on variable nodes and encoded data can be iteratively modified (e.g., corrected) at check nodes and variable nodes during the decoding process to produce decoded data as a corrected version of the encoded data.

[0102] Figure 8A Figure 802 illustrates the processing of a verification node according to one or more embodiments. The operation at verification node "c" in Figure 802 can be represented by equation 804. In some instances, verification node "c" can be processed from its neighboring variable nodes (e.g., "... The check node receives LLR messages (e.g., encoded messages). For example, a check node may receive values ​​from an associated variable node based on values ​​in columns of a parity matrix associated with the variable node. As an example, a check node may receive values ​​from an LLR message based on the presence or absence of a 1 or 0 in the associated values ​​of columns of the parity matrix associated with the variable node. In some instances, neighboring nodes may be defined by edge connections in the associated bipartite graph (e.g., edge connections in, for example, the base code bipartite graph 702 of Figure 7). For example, a check node may receive a portion of an LLR message from each node with which it has an edge connection. In some instances, operations may be performed at the check node. For example, equation 804 may take all nodes except one node to which the check node “c” is connected as input and output the remaining variable nodes (e.g., “v”). jIn some instances, there may be more than one layer (e.g., "L"). A layer is a group of rows (or columns) in a parity check matrix that can be processed in parallel because there is only a single set of elements in the parity check matrix in the grouped columns (or rows). For example, a layer may be a subset of the parity check matrix that corresponds to a group of variables and check nodes that are updated together in a single parallel decoding step within a decoder iteration. In instances where there is more than one layer, Equation 804 can be performed on the check node (e.g., "c") at each layer. At each example of the equation (e.g., associated with a layer), the variable (e.g., "v") is updated. i ") may be the only value associated with that layer.

[0103] Figure 8B Figure 806 illustrates variable node processing according to one or more embodiments. The operation at variable node "v" in Figure 806 can be represented by equation 808. In some instances, variable node "v" may receive check node values ​​from associated check nodes. For example, a variable node may receive values ​​from check nodes based on which check nodes it has edge connections to in an associated bipartite graph. In some instances, operations may be performed at variable node "v". For example, equation 808 may take all check nodes connected to variable node "v" except for one check node as input and output the remaining check nodes (e.g., "c"). j Similar to check node processing, variable node processing can be performed on more than one layer. In these instances, the equation can contain values ​​from previous layers (e.g., "L"). prior The value of ''. This value may be from a previous function (e.g., "'') The value of (the calculation in the previous layer).

[0104] In some instances, decoding can be performed based on a schedule. Various scheduling methods can be used (e.g., flooding, hierarchical, permutation hierarchical, hybrid, and / or similar). Layers can define (e.g., schedule) the processing order of check nodes and variable nodes during decoding. The decoding process can begin by initializing all soft estimates with LLR-encoded message values. For example, the decoding process can be initialized as follows, where H is the parity check matrix:

[0105] …………… (Equation 14)

[0106] Output: …………… (Equation 15)

[0107] …………… (Equation 16)

[0108] Based on this initialization, the LLR encoded message can be decoded using a minimum sum-based algorithm. For all rows in the current layer of the iteration (e.g., ...), It can receive input from connected variable nodes and can calculate the verification output (e.g., minimum and offset) according to the following equation. ):

[0109] …………… (Equation 17)

[0110] …………… (Equation 18)

[0111] …………… (Equation 19)

[0112] Based on the output of these equations, the soft estimate can be determined by the following equation:

[0113] …………… (Equation 20)

[0114] Then, the layer index can be incremented, and The settings can be configured according to the following equation:

[0115] …………… (Equation 21)

[0116]

[0117]

[0118] After the layer index has been incremented, the process starting at Equation 17 can be repeated until all layers have been processed. After the layers have been processed, the decoded bits can be updated. Finally, this process can be repeated starting from Equation 17 until any checksum (e.g., the product of the message and the parity check matrix) is satisfied. For example, the process can be repeated until the checksum is a zero vector. This indicates a valid codeword, but a valid codeword may be the result of error correction. Alternatively, the process can be repeated until the maximum number of iterations is reached.

[0119] Figure 9 Figure 900 is a diagram depicting the relationship between variable nodes and check nodes in a 2x LDPC graph according to one or more embodiments. Figure 900 may represent a 2x LDPC, resulting in two sets of variable nodes (e.g., and ) and two sets of verification nodes (e.g., and The relationship between variable nodes and check nodes can be represented by a bipartite graph 902. For example, bipartite graph 902 can define edge connections (e.g., relationships) between variable nodes and check nodes. Relationship graph 904 can depict each individual connection between variables in two sets of variable nodes and check nodes in two sets of check nodes. As can be observed in Figure 900, the edge connections of the first set of variables and check nodes are mirror images of the edge connections of the second set of variables and check nodes. For example, With and The two edges, and With and The two edges.

[0120] In some instances, a 2x LDPC graph can be decomposed into two 1x LDPC graphs. This decomposition simplifies the decoding process, eliminating the need for dedicated hardware, reducing the computational cost of decoding, and / or improving scalability by allowing the process to be performed on two cores. Alternatively, decomposing a 2x LDPC code into two 1x LDPC codes can result in faster decoding times due to parallel processing of two relatively smaller codes, rather than linear processing of a single larger code. However, in some instances, such as the one illustrated in Figure 900, edge connectivity may not allow for conventional decomposition. For example, and The connection between and and Mirror connections between them may prevent the bipartite graph 902 from being decomposed using conventional methods. Similarly, and Between and and Edge connections between them may also prevent the bipartite graph 902 from being decomposed using conventional methods. As depicted in relation graph 904, these edge connections intersect, thus introducing structural complexity (e.g., cross connections), which may prevent the first set of variables and check nodes from being processed in parallel with the second set of variables and check nodes.

[0121] Figure 10 Figure 1000 depicts the parallel decomposition according to one or more embodiments. A first check node decomposition diagram 1004 is depicted for a first set of check nodes and a second check node decomposition diagram 1006 is depicted for a second set of check nodes. A first variable node decomposition diagram 1008 is also depicted for a first set of variable nodes and a second variable node decomposition diagram 1010 is depicted for a second set of variable nodes. Additionally, relational diagram 1002 illustrates how the first set of check nodes is processed separately from the second (e.g., prime number) check nodes.

[0122] The first check node decomposition diagram 1004 and the second check node decomposition diagram 1006 depict how the first and second sets of check nodes are decomposed into parallel operations. As depicted in the first check node decomposition diagram 1004 and the second check node decomposition diagram 1006, the first and second sets of check nodes may be associated with Figures 1004a and 1006a, respectively. For example, check node decomposition diagram 1004 may include Figure 1004a, and check node decomposition diagram 1006 may include Figure 1006a. During the check node update process, Figures 1004a and 1006a may share one or more edges and / or be identical. As an example, this may result in check nodes... and The same graph is seen during the check node update process. In the example, Figures 1004a and 1006a can be identical to the 1x LDPC graph, from which a 2x LDPC graph associated with relation graph 1002 is generated (e.g., Figure 9 The bipartite graph 902). Figure 1004a may contain node 1004b, which may be connected to a variable node in the first group of variable nodes or the second group of variable nodes. Similarly, Figure 1006a may contain node 1006b, which may be connected to a variable node in the first group of variable nodes or the second group of variable nodes. Node 1004b in Figure 1004a (e.g., represented by a circle) and node 1006b in Figure 1006a may represent update messages, which may be connected to the first group of variable nodes (e.g., ) in the variable nodes or the second group of variable nodes (e.g., The variable nodes in the () are linked to the variable nodes in the first or second group of variable nodes. In some instances, the node associated with the update message may be connected to the variable nodes in the first or second group of variable nodes based on a lifting structure. The lifting structure may be a fixed structure that transforms a basecode (e.g., 1x LDPC code) bipartite graph into a double-lifted (e.g., 2x LDPC code) bipartite graph by copying and replacing nodes and edges. As an example, the top node in node 1004b may be connected to the variable nodes in the first or second group of variable nodes based on a lifting structure. or This can be illustrated by relation diagram 1002. Relationship diagram 1002 will... Described as connected to Therefore, it can be determined that it should be connected to The top node in node 1004b. In some instances, and Both can be connected to the circle. For example, in the first check node decomposition diagram 1004, and Both can be based on and and The associated edge connection is connected to the bottom node in node 1004b.

[0123] Similarly, the first variable node decomposition diagram 1008 and the second variable node decomposition diagram 1010 depict how the first and second groups of variable nodes respectively contain diagrams 1008a and 1010a. For example, variable node decomposition diagram 1008 may contain diagram 1008a and variable node decomposition diagram 1010 may contain diagram 1010a. Similar to the check node decomposition, diagrams 1008a and 1010a may be the same diagram. Alternatively or additionally, diagrams 1008a and / or 1010a may be the same as the 1xLDPC diagram from which the 2x LDPC diagram associated with relation diagram 1002 is generated (e.g., and therefore the same diagram as diagrams 1004a and 1006a). Diagram 1008a may contain node 1008b, which may be connected to a check node in the first group of check nodes or the second group of check nodes. Similarly, diagram 1010a may contain node 1010b, which may be connected to a check node in the first group of check nodes or the second group of check nodes. Similar to the process described above, each node in node 1008b and node 1010b (e.g., represented by a square) can be connected to a check node (e.g., based on a fixed lifting structure) using a fixed lifting structure. or As an example, the top node in node 1008b can be connected to a lifting structure. or Relationship diagram 1002 will... Showing as a connection , and Therefore, the top node in node 1008b can be connected to The second node in node 1008b can be connected to And the third node in node 1008b can be connected to In some instances, and Both can be connected to a single node in node 1008b. For example, in the exploded graph 1008, and Both can be based on and Associated edge connections and with The associated edge connection is connected to the bottom node of node 1008b.

[0124] Figures 11A to 11B Figure 1100 depicts a parallel decomposition at the check node view according to one or more embodiments. For example, Figures 11A to 11B Operations at the check node of the descriptable code, such as those performed by... Figure 9 The double-lift code is represented. In this example, the check node (e.g., ) and variable nodes (e.g., ) can be divided into the first group (e.g., and ) and the second group (e.g., and As described herein, a check node can be considered cross-connected when it depends on variable nodes from both the first and second sets of variable nodes. As depicted in node diagrams 1102, 1104, 1106, and 1108, a check node verifies whether an operation performed on an input variable is equal to the output variable. In some instances, the operation may be an XOR function. In these instances, the check node may include an indication of whether the XOR of the input variable node should equal the value of the output variable node.

[0125] Figure 11A A first node diagram 1102 and a second node diagram 1104 are depicted according to one or more embodiments. In instances where there are no cross connections between the first set of variables and check nodes and the second set of variables and check nodes, check nodes can be computed in parallel. As an example, Can be with Parallel computation is depicted as shown in the first node diagram 1102 and the second node diagram 1104. The first node diagram 1102 depicts the verification node. The graph. Specifically, the graph has variable nodes. , and As input, and having nodes As output, the verification node depicted by the first node diagram 1102 and the second node diagram 1104 may involve a hierarchical scheduling decoding process, such as the process described by equations 14 to 21 in Figure 8. According to the process described by equations 14 to 21, " "It can be initialized through input or previous operation, while..." "It can be determined based on equations 17 to 19."

[0126] Figure 11B A first node diagram 1106 and a second node diagram 1108 are depicted according to one or more embodiments, wherein two variable nodes have been switched between diagrams. In some instances, the nodes may be switched by a multiplexer (MUX). For example, the MUX may control which variable nodes are provided as input to the verification node. In this example, the MUX may be used to switch between the first set of variable nodes and the second set of variable nodes (e.g., and The selection between these nodes allows for parallel processing of check nodes with cross-connections between the first group of variable nodes and the second group of variable nodes, such as the check nodes depicted in Figure 1106 (first node) and Figure 1108 (second node). In instances where the basecode contains cross-connections, at least some check nodes cannot be processed using conventional methods (e.g., by...). Figure 11A(As explained) Parallel processing. For example, this could be attributed to the check nodes that depend on both the first set of variable nodes and the second set of variable nodes. For example, Connected to , , and (For example, such as) Figure 9 (as depicted in bipartite graph 902), and therefore depends on the variable nodes from both the first set of variable nodes and the second set of variable nodes. To allow parallel processing, the check node can selectively receive variable nodes. For example, to process... and Exchange in the first node diagram 1106 and the second node diagram 1108 and Node. In the example, will Node switching A node can be considered as a... Connected to Figure 10 The bottom node in node 1004b.

[0127] Figures 12A to 12B Figure 1200 depicts a parallel decomposition at the check node view according to one or more embodiments. For example, Figures 12A to 12B Operations at the variable nodes of a describable code, such as those performed by... Figure 9 The double-lift code is represented. In this example, the check node (e.g., ) and variable nodes ( ) can be divided into the first group (e.g., and ) and the second group (e.g., and As described herein, a variable node can be considered to have cross-connections when it depends on a check node from both the first set of check nodes and the second set of check nodes. As depicted in node diagrams 1202, 1204, 1206, and 1208, a variable node (e.g., depicted by a circle with an equal sign in the middle) can represent variable node processing that has some relationship among multiple check nodes.

[0128] Figure 12A A first node diagram 1202 and a second node diagram 1204 are depicted according to one or more embodiments. In instances where there is no cross connection between the first set of variable and check nodes and the second set of variable and check nodes, variable node processing can be performed in parallel based on the first node diagram 1202 and the second node diagram 1204.

[0129] Figure 12BA first node diagram 1206 and a second node diagram 1208 are depicted according to one or more embodiments, wherein two variable nodes have been switched between diagrams. In some instances, the verification nodes may be switched by a multiplexer (MUX). For example, the MUX may control which variable nodes are provided as inputs to the variable nodes. In this example, the MUX may be used between the first set of verification nodes and the second set of verification nodes (e.g., and The choice is made between two groups of check nodes to allow parallel processing of variable nodes with cross-connections between the first group of check nodes and the second group of check nodes, such as the variable nodes depicted by the first node Figure 1106 and the second node Figure 1108. In instances where the basecode contains cross-connections, at least some variable nodes cannot be processed by conventional methods (e.g., by...). Figure 12A Parallel processing (as described). For example, this might be attributed to the check nodes depending on both the first set of variable nodes and the second set of variable nodes. For example, Connected to , and (For example, such as) Figure 9 (as depicted in the bipartite graph 902), and therefore depends on the check nodes from both the first set of check nodes and the second set of check nodes. However, as depicted in the first node graph 1106 and the second node graph 1108, nodes can be swapped to allow parallel processing. For example, in order to process and Exchange in the first node diagram 1106 and the second node diagram 1108 and node.

[0130] As such Figure 11B Exchange variable nodes as described in the document and / or as described in the document. Figure 12BAs described herein, by exchanging the results of the check nodes, the variable nodes and check nodes can be grouped into two groups, where the exchanged edges allow them to be processed in parallel, regardless of the scheduling algorithm used during decoding. This allows a double-lifted code with cross-connection (e.g., 3888 block length) to be decomposed into two base code (e.g., 1944 block length) graphs. Therefore, double-lifted codes with cross-connection can be processed using existing hardware and methods for decoding-based LDPC codes. This paper describes an example of parallel processing of 2x LDPC codes with cross-connection. However, the described system and method can also be used to process LDPC codes with cross-connection that have been multiplied by three times (e.g., 4x LDPC) or more in parallel. As an example, a 4x LDPC can be considered as two 2x LDPC codes, which, according to the method described herein, can each be considered as two 1x LDPC codes. Furthermore, the method and system described herein are applicable to all types of LDPC codes (e.g., quasi-cyclic low-density parity-check (QC-LDPC), irregular repeating accumulation (IRA), and / or similar).

[0131] Figure 13 This is a flowchart illustrating a concurrent decoding process 1300 for product-lifted LDPC codes. In some embodiments, process 1300 is executed by one or more processors (e.g., communication system 105, encoder 130, or processor 2010). In other embodiments, process 1300 is executed by other entities. In some embodiments, with Figure 13 Compared to the process shown in the diagram, process 1300 contains more, fewer, or different steps.

[0132] In some implementations, a receiver may be configured to receive encoded data. For example, a receiver may receive a transmission including encoded data. The term receiver may refer to an antenna, demodulator, RF front end, or any circuitry or apparatus configured to receive encoded data. The term encoded data may refer to a signal received by the receiver that has been encoded by a parity check matrix, binary digits (e.g., 1 or 0) identified from the received signal, an LLR value determined based on the received signal, or any other data representing information received by the receiver that has been encoded by a parity check matrix. As an example, encoded data may be a signal in which higher amplitude values ​​represent 1 and lower amplitude values ​​represent 0. In some instances, encoded data may be transmitted from a transmitter to a receiver. For example, a transmitter may encode communications representing information to be transmitted from the transmitter to the receiver. As an example, data bits of the communications may be arranged into a vector to generate a communications vector, the communications vector may be multiplied by a parity check matrix to generate parity bits, and the original data bits and the generated parity bits may be combined to form encoded data, which may include both data bits from the communications and parity bits.

[0133] At step 1302, one or more processors may identify a low-density parity-check (LDPC) code. For example, one or more processors may identify an LDPC code that can be used to decode encoded data received by a receiver. The term LDPC code refers to an error correction code, a decoding method, or any set of relationships between columns and rows in a parity check matrix that can be used to correct errors in a message encoded by the parity check matrix. For example, based on LDPC codes, iterative decoding algorithms, such as belief propagation, can be used to efficiently identify and correct errors in encoded data. In some instances, LDPC codes may correspond to bipartite graphs (e.g., such as...). Figure 9 A bipartite graph (902) includes a set of edges connecting a first set of nodes and a second set of nodes. The term bipartite graph refers to any other visual representation of the relationship between two sets of vertices, such as a graph, a Tanner graph, or the relationship between rows and columns of a parity check matrix defined by LDPC codes. For example, an LDPC code may correspond to a bipartite graph and an associated parity check matrix, where the first set of nodes are variable nodes corresponding to columns in the parity check matrix, and the second set of nodes are check nodes corresponding to rows in the parity check matrix. The bipartite graph can be a visual depiction of the relationship between the first set of nodes and the second set of nodes (e.g., the connected edges). In some instances, LDPC codes can be generated using a first LDPC code associated with a first subset of the second set of nodes and a second LDPC code associated with a second subset of the second set of nodes. For example, LDPC codes can be decomposed into a first LDPC code and a second LDPC code, each corresponding to a different subset of nodes, to facilitate a more efficient decoding and error correction process. In some instances, the first LDPC code and the second LDPC code can be used to decode encoded data in parallel.

[0134] In some implementations, the LDPC code may be product-enhanced. This document describes double-enhanced LDPC codes (e.g., those derived from...). Figure 9 The illustrated example is of an LDPC code, but in some instances, the LDPC code may be multiplied by a factor of three or more. In instances where the LDPC code is doubled, the first set of nodes (e.g., variable nodes) may contain a first subset (e.g., ... ) and the second subset (e.g., Similarly, the second set of nodes (e.g., check nodes) may contain the first subset (e.g., ) and the second subset (e.g., In some instances where the LDPC code is doubled, the LDPC code can be decomposed into a first LDPC code and a second LDPC code. For example, an LDPC code can be generated using a first LDPC code associated with a first subset of the second set of nodes, and a second LDPC code can be generated using a second subset of the second set of nodes.

[0135] In some implementations, one or more processors may enable nodes in a first group of nodes to selectively receive messages from a first or second subset of nodes in a second group. For example, one or more processors may include a multiplexer (MUX). The MUX may select nodes from the second group of nodes for reception by nodes in the first group. In an example, the multiplexer may enable nodes in the first group of nodes to selectively receive messages from a second subset of nodes in the second group (e.g., see reference...). Figure 12B , Selectively from (Message reception). Therefore, this allows for parallel processing of nodes in the first group of nodes that contain cross-connections between the first and second subsets of the second group of nodes. The nodes in the first group of nodes may contain cross-connections when they receive messages from both the first and second subsets of the second group of nodes based on LDPC codes. Using this method, the double-increase LDPC code can still be decomposed into two 1x LDPC codes that can be processed in parallel. This allows the double-increase LDPC code to be processed and / or processed more efficiently using existing methods without dedicated hardware.

[0136] In some implementations, the first LDPC code may be associated with a first subset of the first set of nodes (e.g., such as...). Figure 9 The description in In these implementations, the second LDPC code may be associated with a second subset of the first set of nodes (e.g., such as...). Figure 9 The description in (As an example, the first LDPC code can be associated with...) Figure 10 Figure 1008a shows that the second LDPC code can be represented by curve diagram 1010a. Similarly, the first LDPC code can be associated with a first subset of the second set of nodes (e.g., Similarly, the second LDPC code can be associated with a second subset of the second set of nodes (e.g., This is related to the first LDPC code and the second LDPC code. In some instances, the first LDPC code and the second LDPC code may be the same. In some instances, an LDPC code may be generated based on the first LDPC code and the second LDPC code. For example, see reference... Figure 10When the first LDPC code is associated with a first subset of the first group of nodes and the second LDPC code is associated with a second subset of the first group of nodes, the LDPC code can be generated based on which nodes in the second group of nodes are connected to nodes 1008b and 1010b. Return to Figure 13 Which nodes in the second group of nodes (e.g., check nodes) are connected to the nodes in the first LDPC code and the second LDPC code can be fixed and can be defined based on the lifting structure (e.g., a lifting structure that generates double-lifted LDPC codes from 1x LDPC-based codes).

[0137] At step 1304, one or more processors may generate a first set of messages and a second set of messages. The term "message" may refer to a bit value (e.g., (1 or 0)), a value indicating the probability of a bit value (e.g., an LLR value), a set of values ​​indicating a bit value or bit value probability, or any other set of information that can be used to characterize the transformation from encoded data to decoded data throughout the iterative decoding process. In some instances, messages may be initialized based on variable nodes and encoded data. During the iterative decoding process, message values ​​may be updated (e.g., when they are passed between variable nodes and check nodes). For example, in response to determining that a message value in a set of received messages is incorrect, one or more processors may correct the message value. In some instances, message values ​​may be the input and output of layers within the iterative decoding process. The iterative decoding process may be initialized with a set of initial messages containing encoded data. A set of update messages may be generated at each layer, and the output of the last layer may be the last set of messages containing decoded data. In some instances, this may allow for correction of the received encoded data. For example, due to various factors such as noise, interference, or signal degradation during transmission, the data received by the receiver may not always be correct. An iterative decoding process can allow one or more processors to identify incorrect message values ​​within the set of messages. In some instances, messages can be communicated between a first set of nodes and a second set of nodes. In these instances, communicating a set of messages may involve communicating message values ​​from a first node (e.g., within the first set of nodes) to a second node (e.g., within the second set of nodes) according to edge connections represented in a bipartite graph. As an example, a first subset of the nodes in the second set of nodes (e.g., ...) that communicate the first set of messages to the second set of nodes... ) can contain along bipartite graphs (e.g., Figure 10 The edge connection shown in Figure 1004a) conveys the first set of messages (e.g., node 1004b).

[0138] In some implementations, a message may be a log-likelihood (LLR) value. The term LLR value may refer to a value ranging from negative to positive, corresponding to the probability that a received bit is 1 or 0, where a higher absolute value indicates a higher confidence level in the determined bit value, or any other value representing the confidence level in the determined value of the received bit. In some instances, an LLR value may refer to a functional of LLR values, such as a correlation mapping between LLR values. For example, an LLR value may refer to an LLR value that has been multiplied by a value (e.g., -1) to map it to an index (e.g., a quantizer index). In an example, both the first set of messages and the second set of messages may be LLR values. LLR values ​​may be generated by a processor based on received encoded data. For example, the encoded data may be modulated and transmitted over a communication channel. In this example, a receiver may receive a modulated signal containing the encoded data. Based on the signal received by the receiver, one or more processors may demodulate the data. The demodulated data may contain data that has been converted from an analog signal (e.g., a wave of a sine wave) back to a digital signal (e.g., 1s and 0s). The LLR value can be a probability of a bit being 0 or 1 associated with a received signal (e.g., a signal containing encoded data received by a receiver). In some instances, the LLR value can incorporate the noise characteristics of the channel through which the receiver receives the encoded data. In some instances, the first and second sets of messages can each be associated with a set of bits (e.g., 8 bits). In these instances, the first and second sets of messages can be a set of 8 numbers, each representing the probability that each bit is 0 or 1. As an example, each number can represent the probability of each number being 0 or 1 in the range of -7.75 to 7.75, where 7.75 indicates a high probability of 0, and -7.75 indicates a high probability of 1. In some instances of iterative decoding, this LLR value can be updated at each layer to progressively refine the bit estimation and improve error correction.

[0139] At step 1306, one or more processors may concurrently communicate the first set of messages with a first subset of the second set of nodes and the second set of messages with a second subset of the second set of nodes. For example, the LDPC code may be a 2x LDPC code. As a result of decomposing the LDPC code into a first LDPC code and a second LDPC code (e.g., two 1x LDPC codes), the first LDPC code can be used to communicate the first set of messages to the first subset of the second set of nodes in parallel with the second LDPC code communicating the second set of messages to the second subset of the second set of nodes.

[0140] In some implementations, messages can be updated on a second set of nodes. For example, in response to delivering a first set of messages to a second set of nodes, the first set of messages can be processed (e.g., updated) to produce a third set of messages. The second set of messages can be processed similarly to produce a fourth set of messages. In some instances, one or more processors can deliver the third set of messages to a first subset of the first set of nodes. Similarly, one or more processors can deliver the fourth set of messages to a second subset of the first set of nodes. In some instances, messages can be delivered based on a bipartite graph. For example, one or more processors can deliver message values ​​from the third set of messages to specific nodes in the first subset of nodes based on a bipartite graph.

[0141] In some implementations, nodes in the second group of nodes can be configured to selectively receive messages from nodes in a first subset of the first group of nodes or from nodes in a second subset of the first group of nodes. For example, a MUX identical or similar to a MUX used to select nodes from the second group of nodes to transmit messages to nodes in the first group of nodes can be configured to determine which nodes in the second group of nodes should receive messages from. As an example, the MUX can enable nodes in the second group of nodes to selectively receive messages from nodes in a second subset of the first group of nodes (e.g., refer to...). Figure 11B , Selectively from the first group of nodes The second subset (Receive messages). As another example, MUX can enable nodes in a second group of nodes (e.g., Selectively from the first subset of the first set of nodes (e.g., from the first set of nodes) The first subset ) Receive messages. In some instances, the message may contain a first set of messages and a second set of messages. In these instances, the MUX can determine which nodes in the first subset of the second set of nodes receive the first set of messages and which nodes in the second subset of the second set of nodes receive the second set of messages.

[0142] At step 1308, one or more processors may identify the decoded data based on processing the first set of messages and the second set of messages. The term "decoded data" may refer to a set of bit values ​​corresponding to the encoded data (where one or more values ​​have been corrected during the LDPC decoding process), a set of modified (e.g., corrected) LLR values ​​corresponding to the encoded data, a set of bit values ​​derived from these modified LLR values, or any other data representing a modified version of the encoded data. For example, the first set of messages and the second set of messages may be processed at the second set of nodes to produce updated first set of messages and updated second set of messages. In an example, the decoded data may be identified as updated first set of messages and updated second set of messages. Alternatively, the first and second sets of messages may be iteratively passed and updated between the first and second set of nodes until a stopping condition is met, and the decoded data may be the first and second sets of messages when the stopping condition has been met. In an example, the stopping condition may be a threshold number of iterations. Additionally or alternatively, the stopping condition may be valid first and second sets of messages. For example, at each iteration (e.g., message update), the validity of the messages can be determined by multiplying the first and second sets of messages by a parity check matrix (e.g., concatenating the messages into a vector and multiplying it by the parity check matrix used to generate the encoded data). In this example, if this operation results in a zero vector, then the first and second sets of messages are considered valid. In instances where messages are represented by LLR values, the decoded data can be a series of 1s and 0s determined based on the likelihood indicated in each message.

[0143] A reference to “or” can be interpreted as inclusive, such that any term described using “or” can refer to any one, more than one, or all of the described items. A reference to at least one of a list of conjunctions for a term can be interpreted as inclusive or to refer to any one, more than one, or all of the described terms. For example, a reference to “at least one of 'A' and 'B'” includes only 'A', only 'B', and both 'A' and 'B'. Such references used in conjunction with “include” or other open terms can include additional items.

[0144] It should be noted that certain paragraphs of this disclosure may use terms such as "first" and "second" in conjunction with subsets of transmit space streams, probe frames, responses, and devices for the purpose of identifying or distinguishing them from one another or others. These terms are not intended to relate entities (e.g., first device and second device) temporally or sequentially, although in some cases these entities may contain such a relationship. These terms also do not limit the number of possible entities (e.g., STA, AP, beamformer, and / or beamformee) that may operate within the system or environment. It should be understood that the system described above may provide any or more of the components, and these components may be located on a standalone machine, or in some embodiments, on multiple machines in a distributed system. Furthermore, bit field positions may be changed, and multiple bit words may be used. Furthermore, the systems and methods described above can be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture, such as floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or magnetic tapes. The program can be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any bytecode language (e.g., JAVA). The software program or executable instructions can be stored as object code on or in one or more articles of manufacture.

[0145] While the foregoing written description of the methods and systems enables those skilled in the art to make and use embodiments thereof, those skilled in the art will understand and appreciate the existence of variations, combinations, and equivalents of the particular embodiments, methods, and examples described herein. Therefore, the methods and systems should not be limited to the embodiments, methods, and examples described above, but should be limited to all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. An apparatus comprising: A receiver configured to receive encoded data; and One or more processors, configured to: Identify a low-density parity-check LDPC code corresponding to a bipartite graph including a set of edges connecting a first set of nodes and a second set of nodes, wherein the LDPC code is generated using a first LDPC code associated with a first subset of the second set of nodes and a second LDPC code associated with a second subset of the second set of nodes; The encoded data is used to generate the first set of messages and the second set of messages; The bipartite graph is used to concurrently communicate the first set of messages with the first subset and the second set of messages with the second subset; and Decoded data is identified based at least on the processing of the first set of messages and the second set of messages.

2. The device according to claim 1, wherein the LDPC code is a product boosting code generated using the first LDPC code and the second LDPC code.

3. The device according to claim 1, wherein The first set of messages is the log-likelihood ratio (LLR) value, and The second set of messages is the LLR value.

4. The device of claim 1, wherein the one or more processors are configured to allow nodes in the first group of nodes to selectively receive messages from nodes in the first subset of the second group of nodes or from nodes in the second subset of the second group of nodes.

5. The device according to claim 1, wherein The first LDPC code is associated with a first subset of the first group of nodes, and the second LDPC code is associated with a second subset of the first group of nodes.

6. The device according to claim 5, wherein The one or more processors are configured to: In response to the transmission of the first set of messages and the second set of messages, the first set of messages and the second set of messages are processed at the second set of nodes to generate the third set of messages and the fourth set of messages; and The third set of messages is communicated concurrently with the first subset of the first group of nodes and the fourth set of messages with the second subset of the first group of nodes using the bipartite graph.

7. The device of claim 5, wherein the one or more processors are configured such that nodes in the second group of nodes selectively receive messages from nodes in the first subset of the first group of nodes or from nodes in the second subset of the first group of nodes.

8. A method comprising: Encoded data is received by the receiver; The low-density parity-check LDPC code corresponding to a bipartite graph including a set of edges connecting a first set of nodes and a second set of nodes is identified by one or more processors, wherein the LDPC code is generated using a first LDPC code associated with a first subset of the second set of nodes and a second LDPC code associated with a second subset of the second set of nodes; The one or more processors use the encoded data to generate a first set of messages and a second set of messages; The one or more processors use the bipartite graph to concurrently communicate the first set of messages with the first subset and the second set of messages with the second subset; and The decoded data is identified by one or more processors based at least on the processing of the first set of messages and the second set of messages.

9. The method according to claim 8, wherein the LDPC code is a product boosting code generated using the first LDPC code and the second LDPC code.

10. The method of claim 8, wherein The first set of messages is the log-likelihood ratio (LLR) value, and The second set of messages is the LLR value.

11. The method of claim 8, further comprising: This allows nodes in the first group of nodes to selectively receive messages from nodes in the first subset of the second group of nodes or nodes in the second subset of the second group of nodes.

12. The method of claim 8, wherein The first LDPC code is associated with a first subset of the first group of nodes, and the second LDPC code is associated with a second subset of the first group of nodes.

13. The method of claim 12, further comprising: In response to the transmission of the first group of messages and the second group of messages, the first group of messages and the second group of messages are processed at the second group of nodes to generate the third group of messages and the fourth group of messages; and The third set of messages is communicated concurrently with the first subset of the first group of nodes and the fourth set of messages with the second subset of the first group of nodes using the bipartite graph.

14. The method of claim 12, further comprising: This allows nodes in the second group of nodes to selectively receive messages from nodes in the first subset of the first group of nodes or from nodes in the second subset of the first group of nodes.

15. An apparatus comprising: A receiver configured to receive encoded data; and One or more processors, configured to: Identify a low-density parity-check LDPC code corresponding to a bipartite graph including a first bipartite graph and a second bipartite graph sharing one or more edges, wherein the LDPC code is generated using a first LDPC code associated with the first bipartite graph and a second LDPC code associated with the second bipartite graph; The encoded data is used to generate the first set of messages and the second set of messages; Concurrently use the first bipartite graph to convey the first group of messages and use the second bipartite graph to convey the second group of messages; and Decoded data is identified based at least on the processing of the first set of messages and the second set of messages.

16. The device according to claim 15, wherein The first set of messages is the log-likelihood ratio (LLR) value, and The second set of messages is the LLR value.

17. The device according to claim 15, wherein The LDPC code is a product-lift code generated using the first LDPC code and the second LDPC code.

18. The device according to claim 15, wherein The first bipartite graph includes a first set of edges connecting the first group of nodes and the second group of nodes, and The second bipartite graph includes a second set of edges connecting the third set of nodes and the fourth set of nodes.

19. The device of claim 18, wherein the one or more processors are configured to allow nodes in the first group of nodes to selectively receive messages from nodes in the second group of nodes or nodes in the fourth group of nodes.

20. The device of claim 18, wherein the one or more processors are configured to cause nodes in the second group of nodes to selectively receive messages from nodes in the first group of nodes or nodes in the third group of nodes.

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