Groove type silicon carbide MOSFET device and preparation method thereof

Abstract

The invention provides a groove type silicon carbide MOSFET device and a preparation method thereof, and the preparation method comprises the following steps: providing a silicon carbide substrate, and forming a silicon carbide epitaxial layer on the silicon carbide substrate; respectively forming a body region and a source region on the top of the silicon carbide epitaxial layer; forming a trench protection region, and forming an ONO hard mask layer on the silicon carbide epitaxial layer; patterning the ONO hard mask layer to etch the silicon carbide substrate, forming one or two gate trenches between two adjacent trench protection regions, forming gate oxide layers and filling polycrystalline silicon on the inner surfaces of the gate trenches, and back-etching or chemically and mechanically polishing the polycrystalline silicon layer until the upper surface of the top silicon dioxide layer is exposed; removing the top silicon dioxide layer to expose the lower silicon nitride layer; etching the residual polycrystalline silicon in the gate trench to enable the upper surface of the residual polycrystalline silicon to be lower than the upper surface of the silicon carbide substrate; removing the silicon nitride layer and the bottom silicon dioxide layer; depositing an interlayer dielectric layer; removing the interlayer dielectric layer outside the gate trench, and only retaining the interlayer dielectric layer in the gate trench; and forming a flat front metal layer.

Description

Technical Field

[0001] This invention relates to the technical field of trench silicon carbide MOSFET devices, and more specifically, to a trench silicon carbide MOSFET device and its fabrication method. Background Technology

[0002] Wide-bandgap semiconductor materials, represented by silicon carbide (SiC), have become the ideal foundation for fabricating next-generation high-voltage, high-temperature, high-efficiency, and high-frequency power electronic devices due to their superior physical properties, such as high critical breakdown electric field, high thermal conductivity, and high electron saturation drift velocity. Compared with traditional silicon-based devices, silicon carbide MOSFETs can significantly reduce device conduction and switching losses, while enabling more compact system designs, showing great application potential in key areas such as new energy vehicles, industrial motor drives, smart grids, and rail transportation.

[0003] The device structure of silicon carbide MOSFETs is undergoing technological evolution. Early products generally adopted a planar gate structure. While this structure is relatively simple to manufacture and its reliability is easy to guarantee, its channel mobility is limited, and it is difficult to further increase the cell density, resulting in room for optimization of the specific on-resistance of the device. To fully utilize the material advantages of silicon carbide, there is a trend of iterating from planar gate to trench gate structures. By embedding the gate inside the substrate, the trench gate structure can alleviate the JFET effect present in the planar structure, increase the channel density, and help to achieve higher channel mobility, thereby achieving lower on-resistance and better switching performance in the same chip area.

[0004] However, trench silicon carbide MOSFETs have extremely high technical barriers to entry. Their manufacturing process, especially the morphological control of trench etching, the quality and reliability of the gate oxide layer, and the optimization of the electric field at the bottom of the trench, constitute significant technical challenges. Providing an innovative trench silicon carbide MOSFET structure with a wide process window and high reliability, along with its manufacturing method, has become a key technical problem urgently needing to be solved by those skilled in the art.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To address the problems in the prior art, the present invention aims to provide a trench-type silicon carbide MOSFET device and its fabrication method. This fabrication method can effectively eliminate the difficulty in aligning contact holes and trenches in trench-type silicon carbide MOSFET devices with small cell pitch, thereby improving the parameter uniformity and reliability of the device.

[0007] Specifically, the first aspect of the present invention provides a method for fabricating a trench-type silicon carbide MOSFET, the method comprising the following steps: A silicon carbide substrate of a first doping type is provided, and a silicon carbide epitaxial layer of the first doping type is formed on the upper surface of the silicon carbide substrate; A second type of doped bulk region is formed on top of the silicon carbide epitaxial layer; A source region of the first doping type is formed within the body region; A second doping type trench protection zone is formed, the trench protection zone being between two adjacent body regions and having a depth greater than the body region; A bottom silicon dioxide layer, a silicon nitride layer, and a top silicon dioxide layer are sequentially deposited on the silicon carbide epitaxial layer to form an ONO hard mask layer. The ONO hard mask layer is patterned and used as a mask to etch a silicon carbide substrate, forming one or two gate trenches between two adjacent trench protection zones, and the bottom depth of the gate trench is greater than the lower interface depth of the body region. A gate oxide layer is formed on the inner surface of the gate trench, and a polysilicon layer is deposited on the gate oxide layer and the ONO hard mask layer to fill the gate trench. The polysilicon layer is etched back or chemically and mechanically polished until the upper surface of the top silicon dioxide layer is exposed. Remove the top silicon dioxide layer of the ONO hard mask layer to expose the underlying silicon nitride layer; The remaining polysilicon in the gate trench is etched so that its upper surface is lower than the upper surface of the silicon carbide substrate; Remove the silicon nitride layer and the underlying silicon dioxide layer; The interlayer medium is deposited and then subjected to high-temperature reflow densification treatment; The interlayer dielectric layer outside the gate trench is removed by planarization or dry etching, leaving only the interlayer dielectric layer inside the gate trench. A smooth front metal layer is formed.

[0008] According to a first aspect of the present invention, the preparation method further includes the following steps: A back metal layer is formed on the lower surface of the silicon carbide substrate.

[0009] According to a first aspect of the invention, the first doping type is N-type doping, and the second doping type is P-type doping; The second type of doped trench protection zone is formed using a high-energy aluminum ion implantation process, with a depth between 2.0 and 3.0 μm.

[0010] A second aspect of the present invention provides a trench-type silicon carbide MOSFET device, wherein the trench-type silicon carbide MOSFET device is fabricated using the fabrication method described in the first aspect, and the trench-type silicon carbide MOSFET device comprises: First type of doped silicon carbide substrate; The silicon carbide epitaxial layer of the first doped type on the upper surface of the silicon carbide substrate; A second type of doped trench protection zone is provided within the silicon carbide epitaxial layer; The body area is set between two adjacent trench protection zones; The source region, located within the body region, is discontinuous in the extension direction of the trench protection zone; One or two gate trenches are disposed between two adjacent trench protection zones. The gate trenches penetrate the body region. A gate oxide layer and polysilicon are disposed in the gate trenches. The upper surface of the polysilicon is lower than the upper surface of the silicon carbide substrate. An interlayer dielectric layer is disposed within the gate trench, and its upper surface is flush with the upper surface of the silicon carbide substrate; A front metal layer is disposed on the upper surface of the interlayer dielectric layer.

[0011] According to a second aspect of the invention, the thickness of the interlayer dielectric layer is greater than 0.2 μm; and / or

[0012] The lower surface of the interlayer dielectric layer is above the junction of the source region and the body region, and the distance between the lower surface of the interlayer dielectric layer and the junction is between 0.05 μm and 0.15 μm.

[0013] According to a second aspect of the invention, a grid trench is provided between two adjacent trench protection zones, and the grid trenches are distributed at equal intervals.

[0014] According to a second aspect of the invention, the gate trench is disposed on the center line of the source region.

[0015] According to a second aspect of the invention, the gate trench is disposed on one side of the source region.

[0016] According to a second aspect of the present invention, two grid trenches are provided between two adjacent trench protection zones, and the two grid trenches are respectively provided on both sides of the source zone.

[0017] According to a second aspect of the invention, two grid trenches are provided between two adjacent trench protection zones, and the distance between the two grid trenches is less than 0.3 μm.

[0018] The trench-type silicon carbide MOSFET fabrication method of this invention employs a high-energy aluminum ion implantation process to form a trench protection zone on the outer periphery of the bottom of the gate trench, effectively suppressing high electric field concentration at the bottom of the gate, thereby significantly improving the long-term reliability of the device. Simultaneously, through a non-equidistant gate trench arrangement design, combined with a new contact hole process, the cell pitch is further reduced while optimizing the electric field distribution, improving the consistency of device parameters and contributing to enhanced current density and switching performance. More importantly, based on the new contact hole process, the upper surface of the interlayer dielectric layer within the gate trench is made coplanar with the surface of the silicon carbide substrate, significantly improving the flatness of the front-side metal layer at this location. This characteristic has a critical impact on the packaging bonding quality: if the surface of the interlayer dielectric layer at the gate trench is uneven, it easily leads to uneven bonding contact area and increased contact resistance. Under high current density and high temperature operating conditions, this can cause local overheating and stress concentration, significantly weakening the bonding interface strength and making the device prone to bond point peeling or breakage during temperature cycling, becoming one of the main failure mechanisms affecting reliability. The trench-type silicon carbide MOSFET device of the present invention effectively suppresses this problem at the process level. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without inventive effort. Furthermore, the drawings are merely illustrative diagrams of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0020] Figure 1 A flowchart illustrating a method for fabricating a trench-type silicon carbide MOSFET according to an embodiment of the present invention; and

[0021] Figures 2 to 9 These are schematic diagrams of the silicon carbide substrate structure after each step of the trench-type silicon carbide MOSFET fabrication method according to an embodiment of the present invention. Figure 10 This is a schematic diagram of the structure of a trench-type silicon carbide MOSFET device according to another embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a trench-type silicon carbide MOSFET device according to another embodiment of the present invention. Detailed Implementation

[0022] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present invention can be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0023] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0024] In the representation of this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in one or two embodiments or examples of the invention. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate different embodiments or examples and features of different embodiments or examples represented in this invention without contradiction.

[0025] To clearly illustrate the present invention, components unrelated to the description are omitted, and the same or similar constituent elements throughout the specification are given the same reference numerals.

[0026] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0027] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.

[0028] Although the terms first, second, etc., are used in some instances herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0029] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the invention. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0030] Unless otherwise defined in this application, all terms, including technical and scientific terms as used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with relevant technical literature and the content of this present instruction, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0031] The trench-type silicon carbide MOSFET device and its fabrication method of the present invention are further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are not intended to limit the scope of protection of the present invention.

[0032] The first aspect of the present invention provides a method for fabricating a trench-type silicon carbide MOSFET. Figure 1 This is a flowchart of a method for fabricating a trench-type silicon carbide MOSFET according to an embodiment of the present invention. Specifically, the fabrication method includes the following steps: Step S1: Provide a silicon carbide substrate of the first doping type, and form a silicon carbide epitaxial layer of the first doping type on the upper surface of the silicon carbide substrate, see... Figure 2In this process, the first doping type can be N-type doping, in which case the second doping type is P-type doping; conversely, the first doping type can be P-type doping, in which case the second doping type is N-type doping. Taking the former as an example, the silicon carbide substrate is N-type doped, and the silicon carbide epitaxial layer 11 is also N-type doped. The doping concentration and thickness of the silicon carbide epitaxial layer 11 depend on parameters such as the voltage withstand requirement of the target silicon carbide MOSFET device.

[0033] Step S2: Form a second doped body region 2 on top of the silicon carbide epitaxial layer; Step S3: Form a source region 3 of the first doped type within the body region 2. Steps S2 and S3 can be formed by combining photolithography with ion implantation, the difference being the type of implanted ions. Body region 2 is implanted with P-type doping, such as Al ions. More specifically, photoresist is spin-coated onto the silicon carbide substrate after step S1, and then patterned using the photoresist. The openings of the patterned photoresist correspond to the positions of body region 2. Ion implantation is then performed, with the ion implantation energy between 40-900 keV and the implantation dose between 1e12-1e14 cm⁻¹. -2 The implantation angle is 0°, i.e., vertical implantation, and the implantation temperature can be ~500℃. Body region 2 can be completed by multiple implantations (3-8 times) to remove the photoresist layer. Preferably, the ion implantation depth of the obtained body region 2 is 0.7-1.0 μm.

[0034] Next, photoresist is spin-coated onto the silicon carbide substrate after step S2, and then patterned. The openings of the patterned photoresist correspond to the positions of source region 3. Then, step S3 is performed, which is an ion implantation process to implant N-type doping. The implanted ions can be nitrogen ions or phosphorus ions, and the implantation dose can be 25-250 keV, with an implantation dose of 1e14-1e16 cm⁻¹. -2 The implantation angle is 0°, and the implantation temperature can be 500°C. Source region 3 can be achieved through multiple implantations (3-5 times). Preferably, the ion implantation depth of the obtained source region 3 is between 0.4-0.6 μm. In one embodiment, the P-type doping concentration of the body region 2 at the boundary with the source region is controlled at 1e17-3e17 cm⁻¹. -3 .

[0035] Step S4: Form a second-type doped trench protection zone 4. The trench protection zone 4 is located between two adjacent bulk regions 2, and its depth is greater than that of the bulk region 2. See [link to relevant documentation]. Figure 2When the second doping type is P-type doping, the trench protection zone 4 of the second doping type is formed using a high-energy aluminum ion implantation process. More specifically, photoresist is spin-coated onto the silicon carbide substrate after step S3, and then patterned using the photoresist. After patterning, the openings of the photoresist correspond to the positions of the trench protection zone 4. An ion implantation process is then performed using a mask to form a deep P+ doped region (Al), i.e., the trench protection zone 4. The ion implantation energy can be between 60-3000 keV, and the implantation dose can be between 1e14-3e15 cm⁻¹. -2 The implantation angle is 0°, and the implantation temperature can be ~500℃. The trench protection zone 4 can be completed through multiple implantations (4-10 times). Preferably, the ion implantation depth of the trench protection zone 4 is between 2.0-3.0 μm. Of course, after ion implantation in steps S2 to S4, a carbon film can be deposited on the substrate surface, followed by furnace annealing. The annealing temperature can be between 1650℃ and 2000℃, and the annealing time is 5-30 minutes. After annealing, the carbon film is removed. Through the above process, doped ions can be activated and lattice defects caused by the ion implantation process can be repaired.

[0036] Step S5: On the silicon carbide epitaxial layer 11, i.e. on the silicon carbide substrate after step S4, a bottom silicon dioxide layer, a silicon nitride layer and a top silicon dioxide layer are deposited sequentially to form an ONO hard mask layer M1. In one embodiment, the ONO hard mask layer M1 includes a silicon dioxide layer of 20 angstroms to 100 angstroms, a silicon nitride layer of 500 angstroms to 1000 angstroms and a silicon dioxide layer of 1 to 2 μm.

[0037] Step S6: Etch the ONO hard mask layer M1 using patterned photoresist. After removing the photoresist, obtain the patterned ONO hard mask layer M1. Use the patterned ONO hard mask layer M1 as a mask to etch the silicon carbide substrate, forming one or two gate trenches C between two adjacent trench protection zones. See [link to relevant documentation]. Figure 3 The depth of the gate trench C can be between 1.2 and 1.5 μm, and the width w is between 0.3 and 0.7 μm. The sidewalls of the gate trench C are substantially perpendicular to the surface of the silicon carbide substrate, i.e., the included angle between them is between 88.5 and 90°, preferably 89.5°. The bottom depth of the gate trench C is greater than the lower interface depth of the body region 2. Preferably, the difference between the depth of the gate trench C and the depth of the body region 2 is between 0.2 and 0.4 μm.

[0038] Step S7: Form a gate oxide layer 51 on the inner surface of the gate trench, and deposit a polysilicon layer 5 on the gate oxide layer 51 and the ONO hard mask layer M1 to fill the gate trench. See [link to step S7]. Figure 4More specifically, in step S7, the sidewalls and bottomwalls of the gate trench C can be repaired using sacrificial oxygen and / or H2 repair processes, and then a gate oxide layer 51 can be formed by thermal oxidation, high-temperature CVD or atomic layer deposition (ALD) processes. The thickness of the gate oxide layer 51 can be between 500 angstroms and 800 angstroms. Then, an N-type doped polysilicon layer is deposited, and the thickness of the deposited polysilicon layer 5 is between 4000 angstroms and 8000 angstroms.

[0039] Step S8: Use back etching or chemical mechanical polishing (CMP) process to remove part of the polysilicon layer 5 until the upper surface of the top silicon dioxide layer is exposed. At this time, the polysilicon layer 5 is flush with the ONO hard mask layer M1.

[0040] Then perform step S9: Remove the top silicon dioxide layer of the ONO hard mask layer M1 to expose the underlying silicon nitride layer; and

[0041] Step S10: Etch the remaining polysilicon in the gate trench so that its upper surface is lower than the upper surface of the silicon carbide substrate. Preferably, the distance between the upper surface of the remaining polysilicon 5' in the gate trench and the upper surface of the silicon carbide substrate is greater than 0.2 μm, and the upper surface of the polysilicon 5' is 0.1 μm higher than the junction of the source region 3 and the body region 2.

[0042] Step S11: Remove the silicon nitride layer and the underlying silicon dioxide layer. The silicon carbide substrate after step S11 is shown below. Figure 5 As shown.

[0043] Step S12: Deposit an interlayer medium layer and perform high-temperature reflow densification treatment on this layer. The thickness of the deposited interlayer medium layer is between 6000 Å and 10000 Å. The high-temperature reflow temperature is 900-950℃, and after reflow for 20-40 minutes, a densified interlayer medium layer 6 is obtained. See [link to relevant documentation]. Figure 6 .

[0044] Step S13: Remove the interlayer dielectric layer outside the gate trench using a planarization process or a dry etching process, leaving only the interlayer dielectric layer 6' inside the gate trench. (See...) Figure 7 At this point, the upper surface of the interlayer dielectric layer 6' within the gate trench is flush with the surface of the silicon carbide substrate, or in other words, the upper surface of the interlayer dielectric layer 6' within the trench is flush with the upper surface of the adjacent source region 3, achieving coplanarization of the interlayer dielectric layer 6' within the gate trench and the substrate surface, thereby significantly improving the flatness of the front-side metal layer in this region. This characteristic has a critical impact on the packaging bonding quality: if the surface of the interlayer dielectric layer at the gate trench is not smooth, it can easily lead to uneven bonding contact area and increased contact resistance. Under high current density and high temperature operating conditions, this will cause local overheating and stress concentration, which will significantly weaken the bonding interface strength, making the device prone to bond point peeling or breakage during temperature cycling, becoming one of the main failure mechanisms affecting reliability.

[0045] Step S14: Form the front metal layer 7, see Figure 8 The front metal layer comprises multiple source metals, each electrically connected to a source region, not shown in the figure. The front metal layer is typically a Ti / TiN / AlCu composite layer. Contact resistance improvement processes may be included before the formation of the front metal layer, which will not be elaborated here.

[0046] Of course, the preparation method of the present invention may also include the following steps: Step S15: Form a back metal layer 8 on the lower surface of the silicon carbide substrate 1. A substrate thinning process may be included before the conventional back metal layer formation process. The back metal layer 8 is generally a Ti / Ni / Ag composite layer. A contact resistance improvement process may be included before the formation of the back metal layer, which will not be elaborated here.

[0047] The present invention also provides a trench-type silicon carbide MOSFET device, which is fabricated using the above-described method. In one embodiment, see... Figure 9 Trench-type silicon carbide MOSFET devices include: First doped type silicon carbide substrate 1; A first-doped silicon carbide epitaxial layer 11 on the upper surface of the silicon carbide substrate 1; The second type of trench protection zone 4 is disposed within the silicon carbide epitaxial layer 11; Body area 2 is located between two adjacent trench protection zones 4; Source region 3 is located within body region 2 and is discontinuous in the extension direction of trench protection zone 4; Two gate trenches are disposed between two adjacent trench protection zones 4, penetrating the body region 2. A gate oxide layer 51 and polysilicon 5' are disposed within the gate trenches, with the upper surface of the polysilicon 5' lower than the upper surface of the silicon carbide substrate. In this embodiment, the two gate trenches are respectively disposed on both sides of the source region 3 / body region 2, see... Figure 9 That is, two fence trenches are set between two adjacent trench protection zones 4, and the fence trenches are not evenly spaced.

[0048] An interlayer dielectric layer 6' is disposed within the gate trench, and its upper surface is flush with the upper surface of the silicon carbide substrate. In this case, when fabricating the source metal, it is no longer necessary to define contact holes between the gate trenches using photolithography, thus eliminating the problem of contact hole and gate trench overlay misalignment. That is, the trench-type silicon carbide MOSFET device of this invention has a novel contact hole structure. Preferably, the thickness of the interlayer dielectric layer 6' is greater than 0.2 μm, the lower surface of the interlayer dielectric layer 6' is above the boundary between the source region and the body region, and the distance between the lower surface of the interlayer dielectric layer 6' and the boundary is between 0.05 μm and 0.15 μm.

[0049] The front metal layer 7 is disposed on the upper surface of the interlayer dielectric layer 6'.

[0050] The non-equally spaced gate trenches of this invention, combined with a novel contact hole structure, can achieve a minimum spacing d between two adjacent gate trenches within the trench protection zone 4 of less than 0.3 μm. Optimally, this minimum spacing d is between 0.1 and 0.2 μm. The gate trench width w is between 0.3 and 0.7 μm. A trench protection zone 4 with a depth of 2.0-3.0 μm protects the gate oxide layer at the bottom of the gate trench. The overlap width between the trench protection zone 4 and the gate trench is between 0.15 μm and 0.4 μm. (See...) Figure 9 Within the red dashed box, the distance between the trench protection zone 4 and the other edge of the trench is greater than 0.2 μm. Figure 9 The blue dotted box indicates the area described. This structure optimizes the trade-off between current output capability and breakdown voltage in trench silicon carbide MOSFET devices.

[0051] Figure 10 This is a schematic diagram of a trench-type silicon carbide MOSFET device according to another embodiment of the present invention. In this embodiment, a gate trench is provided between two adjacent trench protection zones 4, and the gate trenches are evenly spaced. Similarly, the gate trench penetrates the body region 2, and a gate oxide layer 51B and polysilicon 5B are disposed within the gate trench. The upper surface of the polysilicon 5B is lower than the upper surface of the silicon carbide substrate. An interlayer dielectric layer 6B is disposed within the gate trench, and its upper surface is flush with the upper surface of the silicon carbide substrate. The gate trench is located on the center line of the source region 3 / body region 2. At this time, two vertical conductive channels are formed on both sides of the gate trench, which increases the device current density and significantly reduces the specific on-resistance Rsp,on of the trench-type silicon carbide MOSFET device, thus enhancing the output performance of the device. The evenly spaced gate trenches, combined with the new contact hole structure, can achieve a flat chip surface. When the trench width w is between 0.3 and 0.7 μm, a trench protection zone 4 with a depth of 2.0 to 3.0 μm is used to protect the gate oxide layer at the bottom of the trench. The spacing W between adjacent trench protection zones 4 is... B The range is between 0.5μm and 1.0μm, with 0.6-0.8μm being preferred.

[0052] Figure 11 This is a schematic diagram of a trench-type silicon carbide MOSFET device according to another embodiment of the present invention. In this embodiment, a gate trench is provided between two adjacent trench protection zones 4, and the gate trenches are evenly spaced. Similarly, the gate trench penetrates the body region 2, and a gate oxide layer 51C and a polysilicon 5C are disposed within the gate trench. The upper surface of the polysilicon 5C is lower than the upper surface of the silicon carbide substrate. An interlayer dielectric layer 6C is disposed within the gate trench, and its upper surface is flush with the upper surface of the silicon carbide substrate. The difference is that the gate trench is disposed on one side of the source region 3 / body region 2, that is, in this embodiment, the gate trench is based on... Figure 10 In this embodiment, the gate trench is offset to one side (left or right) of the source region 3 / body region 2, such that the trench protection zone 4 partially overlaps with the gate trench, and the overlap width is between 0.15μm and 0.4μm. Simultaneously, the distance between the trench protection zone 4 and the other edge of the gate trench is greater than 0.2μm. This structure optimizes the trade-off between current output capability and short-circuit withstand capability in trench-type silicon carbide MOSFET devices.

[0053] In summary, the trench-type silicon carbide MOSFET fabrication method of this invention employs a high-energy aluminum ion implantation process to form a trench protection zone on the outer periphery of the bottom of the gate trench, effectively suppressing high electric field concentration at the bottom of the gate, thereby significantly improving the long-term reliability of the device. Simultaneously, through a non-equidistant gate trench arrangement design, combined with a novel contact hole process, the electric field distribution is optimized while eliminating the difficulty in aligning contact holes and trenches in trench-type silicon carbide MOSFET devices with small cell pitches. This further reduces the cell pitch, improves the consistency of device parameters, and is beneficial for enhancing current density and switching performance. More importantly, based on the novel contact hole process, the upper surface of the interlayer dielectric layer within the gate trench is made coplanar with the surface of the silicon carbide substrate, thereby significantly improving the flatness of the front-side metal layer at that location. This characteristic has a critical impact on the bonding quality of the package: if the surface of the interlayer dielectric layer at the gate trench is uneven, it can easily lead to uneven bonding contact area and increased contact resistance. Under high current density and high temperature operating conditions, this can cause local overheating and stress concentration, which in turn significantly weakens the bonding interface strength. This makes the device prone to bond peeling or breakage during temperature cycling, becoming one of the main failure mechanisms affecting reliability. The trench-type silicon carbide MOSFET device and its fabrication method of this invention effectively suppress this problem at the process level.

[0054] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0055] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method of manufacturing a trench-type silicon carbide MOSFET, characterized by, The preparation method comprises the following steps: providing a silicon carbide substrate of a first doping type, forming a silicon carbide epitaxial layer of the first doping type on the upper surface of the silicon carbide substrate; forming a bulk region of a second doping type on the top of the silicon carbide epitaxial layer; forming a source region of the first doping type in the bulk region; forming a trench protection region of the second doping type between two adjacent bulk regions, and the depth of the trench protection region is greater than that of the bulk region; sequentially depositing a bottom silicon dioxide layer, a silicon nitride layer and a top silicon dioxide layer on the silicon carbide epitaxial layer to form an ONO hard mask layer; patterning the ONO hard mask layer and etching the silicon carbide substrate with the ONO hard mask layer as a mask to form one or two gate trenches between two adjacent trench protection regions, and the bottom depth of the gate trench is greater than the lower interface depth of the bulk region; forming a gate oxide layer on the inner surface of the gate trench, and depositing a polysilicon layer on the gate oxide layer and the ONO hard mask layer to fill the gate trench; etching back or chemical mechanical polishing the polysilicon layer until the upper surface of the top silicon dioxide layer is exposed; removing the top silicon dioxide layer to expose the underlying silicon nitride layer; etching the remaining polysilicon in the gate trench so that the upper surface of the polysilicon is lower than the upper surface of the silicon carbide substrate; removing the silicon nitride layer and the bottom silicon dioxide layer; depositing an interlayer dielectric layer and performing high-temperature reflow densification treatment; removing the interlayer dielectric layer outside the gate trench by a planarization process or a dry etching process, and only retaining the interlayer dielectric layer in the gate trench; forming a flat front metal layer.

2. The trench silicon carbide MOSFET fabrication method of claim 1, wherein The preparation method further comprises the following step: forming a back metal layer on the lower surface of the silicon carbide substrate.

3. The trench silicon carbide MOSFET fabrication method of claim 1, wherein, The first doping type is N-type doping, and the second doping type is P-type doping; The trench protection region of the second doping type is formed by a high-energy aluminum ion implantation process, and the depth is between 2.0-3.0 μm.

4. A trench silicon carbide MOSFET device, characterized by, The trench-type silicon carbide MOSFET device is prepared by the preparation method of any one of claims 1-3, and the trench-type silicon carbide MOSFET device comprises: a silicon carbide substrate of a first doping type; a silicon carbide epitaxial layer of the first doping type on the upper surface of the silicon carbide substrate; a trench protection region of a second doping type arranged in the silicon carbide epitaxial layer; a bulk region arranged between two adjacent trench protection regions; a source region arranged in the bulk region and discontinuous in the extension direction of the trench protection region; one or two gate trenches arranged between two adjacent trench protection regions, the gate trench penetrating the bulk region, and a gate oxide layer and a polysilicon being arranged in the gate trench, and the upper surface of the polysilicon being lower than the upper surface of the silicon carbide substrate; an interlayer dielectric layer arranged in the gate trench and having an upper surface flush with the upper surface of the silicon carbide substrate; a front metal layer arranged on the upper surface of the interlayer dielectric layer.

5. The trench silicon carbide MOSFET device of Claim 4, wherein, The thickness of the interlayer dielectric layer is greater than 0.2 μm; and / or The lower surface of the interlayer dielectric layer is above the junction of the source region and the body region, and the distance between the lower surface of the interlayer dielectric layer and the junction is between 0.05 μm and 0.15 μm.

6. The trench silicon carbide MOSFET device of Claim 4, wherein, Two adjacent trench protection regions are provided with one gate trench, and the gate trenches are equidistantly distributed.

7. The trench silicon carbide MOSFET device of Claim 6, wherein, The gate trench is arranged on the center line of the source region.

8. The trench silicon carbide MOSFET device of Claim 6, wherein, The gate trench is arranged on one side of the source region.

9. The trench silicon carbide MOSFET device of Claim 4, wherein, Two adjacent trench protection regions are provided with two gate trenches, and the two gate trenches are arranged on two sides of the source region, respectively.

10. The trench silicon carbide MOSFET device of Claim 4, wherein, Two adjacent trench protection regions are provided with two gate trenches, and the distance between the two gate trenches is less than 0.3 μm.

Images