Silicon carbide groove type grid power device, preparation method thereof and chip

Abstract

The invention belongs to the technical field of power devices, and provides a silicon carbide groove type gate power device with floating P-type rings, a preparation method of the silicon carbide groove type gate power device and a chip, a P-type shielding region is formed at the bottom of a groove of an N-type drift region, a gate dielectric layer is formed on the inner wall of the groove of the P-type shielding region, and a plurality of P-type floating ring regions are arranged in the N-type drift region. The widths of the plurality of P-type floating ring regions are gradually reduced from the P-type shielding region to the silicon carbide substrate, so that a linear floating PN junction is formed, an electric field extends downwards, the distribution range of a high electric field in a drift region can be expanded, the area of a space charge region is increased, the saturation current of the device is effectively reduced, and the endurance capability of the device under a short-circuit test is improved; and the reliability of the device is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power devices, and particularly relates to a silicon carbide trench gate power device and a preparation method and chip thereof. BACKGROUND

[0002] Based on the excellent material properties of silicon carbide, including a wide bandgap, high critical electric field, and good thermal conductivity, a silicon carbide (SiC) trench gate metal oxide semiconductor field effect transistor (TG-MOSFET) has a very high gate density without being limited by the parasitic JFET channel in a planar SiC MOSFET, thus reducing the contribution of channel resistance to the total on-resistance. Compared with a conventional planar SiC MOSFET, a TG-MOSFET can significantly reduce the specific on-resistance by accommodating more channels on a given chip area and completely eliminating the JFET effect.

[0003] However, in the preparation process of the SiC trench MOSFET, multiple layers of photoresist need to be used for photolithography and etching, which is not only high in cost but also long in process time. SUMMARY

[0004] To solve the above technical problems, the application provides a silicon carbide trench gate power device and a preparation method and chip thereof, aiming to improve the tolerance of the device under short circuit test and improve the reliability of the device.

[0005] The first aspect of the application provides a silicon carbide trench gate power device, comprising: A silicon carbide substrate, a buffer layer, and an N-type drift region are stacked; A first current expansion layer and a second current expansion layer are formed on the side of the N-type drift region; A first P-type well region is formed on the first current expansion layer, and a second P-type well region is formed on the second current expansion layer; the first P-type well region and the second P-type well region are in an L-shaped structure; A first N-type heavily doped region and a first P-type heavily doped region are formed on the horizontal part of the first P-type well region; a second N-type heavily doped region and a second P-type heavily doped region are formed on the horizontal part of the second P-type well region; the first P-type heavily doped region is formed between the first N-type heavily doped region and the vertical part of the first P-type well region; and the second P-type heavily doped region is formed between the second N-type heavily doped region and the vertical part of the first P-type well region; a gate dielectric layer, a gate layer, a P-type shielding region, a field oxide layer, the P-type shielding region is formed at the bottom of the recess of the N-type drift region and covers the bottom of the gate dielectric layer completely; the gate dielectric layer is formed on the inner wall of the recess of the P-type shielding region, and the gate dielectric layer is a inverted U-shaped structure; the horizontal part of the inverted U-shaped structure covers the vertical part of the first P-type well region, the vertical part of the second P-type well region, the first N-type heavily doped region, the second N-type heavily doped region and the second P-type heavily doped region; the gate layer is located in the recess of the inverted U-shaped structure and is flush with the horizontal part of the inverted U-shaped structure; the field oxide layer is located on the gate dielectric layer and forms a closed structure wrapping the gate layer with the gate dielectric layer; a plurality of P-type floating ring regions located in the central region of the N-type drift region, the width of the plurality of P-type floating ring regions decreases sequentially from the P-type shielding region to the silicon carbide substrate, and the spacing distance between the P-type floating ring regions and the P-type shielding region is greater than the thickness of the P-type shielding region; a source layer covering the gate dielectric layer and the field oxide layer; a drain layer formed on the back surface of the silicon carbide substrate.

[0006] In some embodiments, the width of the plurality of P-type floating ring regions is an arithmetic sequence.

[0007] In some embodiments, the doping concentration of the P-type floating ring regions in the plurality of P-type floating ring regions gradually increases from the drain layer to the source layer.

[0008] In some embodiments, the spacing distance between adjacent P-type floating ring regions in the plurality of P-type floating ring regions is the same.

[0009] In some embodiments, the width of the field oxide layer is greater than the width of the gate layer.

[0010] In some embodiments, the silicon carbide trench gate power device further comprises: a plurality of first P-type floating ring regions arranged in the first side region of the N-type drift region and arranged opposite to the first current spreading layer; a plurality of second P-type floating ring regions arranged in the second side region of the N-type drift region and arranged opposite to the second current spreading layer.

[0011] In some embodiments, the doping concentration of the plurality of first P-type floating ring regions gradually increases from the drain layer to the source layer; and / or, the doping concentration of the plurality of second P-type floating ring regions gradually increases from the drain layer to the source layer.

[0012] In some embodiments, the first P-type heavily doped region has a width greater than a vertical portion of the first P-type well region.

[0013] The second aspect of the embodiments of the present application further provides a preparation method of a silicon carbide trench gate power device, which is used for preparing the silicon carbide trench gate power device according to any one of the above-mentioned embodiments, and the preparation method comprises the following steps: A silicon carbide substrate is provided, and a buffer layer and an N-type drift region are sequentially formed on a front surface of the silicon carbide substrate. A plurality of P-type floating ring regions are formed in a central region of the N-type drift region by repeated oxide deposition, etching, ion implantation and epitaxy. The width of the plurality of P-type floating ring regions gradually increases upwards along the front surface of the silicon carbide substrate. The N-type drift region is continuously epitaxied, and a current spreading material layer, a P-type doped layer, an N-type heavily doped layer and a P-type heavily doped region are formed by N-type ion implantation and P-type ion implantation. The N-type heavily doped layer is provided with the P-type heavily doped region on both sides. An ion implantation trench reaching the N-type drift region is formed by etching a partial region of the N-type heavily doped layer under the protection of a first photoetching mask. The ion implantation trench divides the current spreading material layer into a first current spreading layer and a second current spreading layer, divides the P-type doped layer into a first P-type well region and a second P-type well region, and divides the N-type heavily doped layer into a first N-type heavily doped region and a second N-type heavily doped region. After a protection layer is formed along the inner surface of the ion implantation trench, an oxide hard film is deposited, a second photoetching mask is formed on the oxide hard film, and then the oxide hard film is etched under the protection of the second photoetching mask to expose a first region on the protection layer. After the second photoetching mask is removed, P-type doped ions are implanted along the first region, and annealing treatment is performed after the protection layer and the oxide hard film are removed, so as to form a P-type shielding region. After a gate dielectric layer in an inverted U-shaped structure is formed along the inner surface of the ion implantation trench on the P-type shielding region, a gate layer is formed in a groove of the gate dielectric layer, and a field oxide layer is formed on the gate layer. The gate dielectric layer and the field oxide layer form a closed structure wrapping the gate layer. The field oxide layer is etched, a source layer covering the gate dielectric layer and the field oxide layer is formed, and a drain layer is formed on the back surface of the silicon carbide substrate.

[0014] The third aspect of the embodiments of the present application further provides a chip comprising the silicon carbide trench gate power device prepared by the preparation method according to any one of the above-mentioned embodiments.

[0015] The beneficial effects of the embodiments of the present application are that the P-type shielding region is formed at the bottom of the groove of the N-type drift region, the gate dielectric layer is formed on the inner wall of the groove on the P-type shielding region, by setting multiple P-type floating ring regions in the N-type drift region, the width of the multiple P-type floating ring regions sequentially decreases along the P-type shielding region to the silicon carbide substrate, thus forming a floating PN junction, so that the electric field extends downward, the distribution range of the high electric field in the drift region can be expanded, the area of the space charge region is increased, the saturation current of the device is effectively reduced, the tolerance of the device under short circuit test is improved, and the reliability of the device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a structure schematic diagram of a silicon carbide trench gate power device provided by the embodiments of the present application; Figure 2 is a flow schematic diagram of a preparation method provided by the embodiments of the present application; Figure 3 is a schematic diagram of part of the preparation process of the preparation method provided by the embodiments of the present application; Figure 4 is a schematic diagram of part of the preparation process of the preparation method provided by the embodiments of the present application; Figure 5 is a schematic diagram of part of the preparation process of the preparation method provided by the embodiments of the present application; Figure 6 is a schematic diagram of part of the preparation process of the preparation method provided by the embodiments of the present application; Figure 7 is a schematic diagram of part of the preparation process of the preparation method provided by the embodiments of the present application; Figure 8 is a schematic diagram of part of the preparation process of the preparation method provided by the embodiments of the present application; Figure 9 is a schematic diagram of part of the preparation process of the preparation method provided by the embodiments of the present application. DETAILED DESCRIPTION

[0017] In order to make the technical problems, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0018] In order to solve the above technical problems, the embodiments of the present application provide a silicon carbide trench gate power device, as shown in Figure 1As shown, the silicon carbide trench gate power device in the embodiment includes a silicon carbide substrate 210, a buffer layer 220, an N-type drift region 230, a first current spreading layer 311, a second current spreading layer 312, a first P-type well region 321, a second P-type well region 322, a gate dielectric layer 431, a gate electrode layer 441, a P-type shielding region 370, a field oxide layer 451, a first N-type heavily doped region 341, a second N-type heavily doped region 342, a first P-type heavily doped region 331, a second P-type heavily doped region 332, a plurality of P-type floating ring regions 260, a source electrode layer 460, and a drain electrode layer 110.

[0019] The silicon carbide substrate 210, the buffer layer 220, and the N-type drift region 230 are stacked, the N-type drift region 230 is a concave structure, the first current spreading layer 311 and the second current spreading layer 312 are formed on the side of the N-type drift region 230, the first P-type well region 321 is formed on the first current spreading layer 311, the second P-type well region 322 is formed on the second current spreading layer 312, and the first P-type well region 321 and the second P-type well region 322 are L-shaped structures.

[0020] The first N-type heavily doped region 341 and the first P-type heavily doped region 331 are formed on the horizontal part of the first P-type well region 321, and the second N-type heavily doped region 342 and the second P-type heavily doped region 332 are formed on the horizontal part of the second P-type well region 322. The first P-type heavily doped region 331 is formed between the first N-type heavily doped region 341 and the vertical part of the first P-type well region 321, and the second P-type heavily doped region 332 is formed between the second N-type heavily doped region 342 and the vertical part of the first P-type well region 321.

[0021] The P-type shielding region 370 is formed on the bottom of the recess of the N-type drift region 230 and completely covers the bottom of the gate dielectric layer 431, the gate dielectric layer 431 is formed on the inner wall of the recess on the P-type shielding region 370, and the gate dielectric layer 431 is an inverted U-shaped structure. The horizontal part of the inverted U-shaped structure covers the vertical part of the first P-type well region 321, the vertical part of the second P-type well region 322, the first N-type heavily doped region 341, the second N-type heavily doped region 342, the first P-type heavily doped region 331, and the second P-type heavily doped region 332. The gate electrode layer 441 is located in the recess of the inverted U-shaped structure and is flush with the horizontal part of the inverted U-shaped structure. The field oxide layer 451 is located on the gate dielectric layer 431 and forms a closed structure wrapping the gate electrode layer 441 with the gate dielectric layer 431.

[0022] A plurality of P-type floating ring regions 260 are located in a central region of the N-type drift region 230, the widths of the plurality of P-type floating ring regions 260 gradually decrease in sequence from the P-type shielding region 370 to the silicon carbide substrate, and the spacing distance between the P-type floating ring regions and the P-type shielding region is greater than the thickness of the P-type shielding region; a source layer 460 covers the gate dielectric layer 431 and the field oxide layer 451; and a drain layer 110 is formed on the back surface of the silicon carbide substrate 210.

[0023] In the embodiments of the present application, the widths of the plurality of P-type floating ring regions 260 gradually increase in the front surface direction of the silicon carbide substrate 210, so that a higher doping concentration can be set for the entire N-type drift region. The higher the doping concentration of the N-type drift region, the greater the carrier density in the N-type drift region, and the smaller the specific on-resistance of the device. By setting the P-type floating ring regions close to the current spreading layer to have a wider width, the electric field borne by the gate dielectric layer can be shared more, the doping concentration of the N-type drift region and the width of the P-type floating ring region are balanced, and the electric field shielding effect at the bottom of the gate dielectric layer is enhanced. In the case of device turn-off, the PN junction formed by the P-type floating ring region and the N-type drift region can bear most of the voltage, transfer the high electric field from the fragile bottom region of the gate oxide, and reduce the risk of gate oxide breakdown.

[0024] In the embodiments of the present application, the P-type shielding region located in the N-type drift region can limit the instantaneous current when a short circuit occurs, prolong the short-circuit withstand time of the device, and improve the system robustness. Specifically, the P-type shielding region forms a PN junction with the N-type drift region in the blocking state. This PN junction can bear most of the applied blocking voltage, thereby attracting the electric field peak from the fragile gate oxide layer to the solid SiC bulk material, achieving electric field “redistribution”. Moreover, the presence of the plurality of floating P ring regions can further expand the high electric field distribution range in the drift region, increase the space charge area to improve the voltage withstand capability of the device, and increase the breakdown voltage. Although the presence of the floating P ring region will increase the on-resistance, in combination with the increase in the effective BV of the device, it is beneficial to optimize its static quality factor. Due to the introduction of the floating P ring region, the saturation current of the device is effectively reduced, the dynamic short-circuit withstand time (tsc) of the device under short-circuit test is improved, the short-circuit withstand capability of the device under short-circuit test is improved, and the reliability quality of the device is improved.

[0025] In some embodiments, the widths of the plurality of P-type floating ring regions 260 form an arithmetic sequence.

[0026] In the present embodiment, the plurality of P-type floating ring regions 260 are sequentially arranged along the P-type shielding region 370 towards the drain layer, and the width of the plurality of P-type floating ring regions 260 gradually decreases along the P-type shielding region 370 towards the silicon carbide substrate 210. In this way, a linear floating P ring region is formed. The presence of the linear floating P ring region effectively reduces the surface electric field intensity of the trench gate bottom oxide layer of the device, and improves the reliability quality of the operation of the device. Moreover, the presence of the linear floating P ring region can expand the distribution range of the high electric field in the drift region, increase the area of the space charge region, effectively reduce the saturation current of the device, improve the tolerance of the device under short circuit test, and improve the reliability of the device.

[0027] In some embodiments, the doping concentration of the P-type floating ring regions 260 in the plurality of P-type floating ring regions 260 gradually increases from the drain layer 110 towards the source layer 460.

[0028] In some embodiments, the spacing distance between adjacent P-type floating ring regions 260 in the plurality of P-type floating ring regions 260 is the same.

[0029] In the present embodiment, the doping concentration of the P-type floating ring regions 260 in the plurality of P-type floating ring regions 260 gradually increases from the drain layer 110 towards the source layer 460, and the width of the plurality of P-type floating ring regions 260 sequentially decreases along the P-type shielding region 370 towards the drain layer 110. The electric field in the N-type drift region 230 can be adjusted, the distribution range of the high electric field in the drift region is expanded, the area of the space charge region is increased, the saturation current of the device is effectively reduced, the tolerance of the device under short circuit test is improved, and the reliability of the device is improved.

[0030] In some embodiments, the doping concentration of the P-type shielding region 370 is gradiently distributed.

[0031] In the present embodiment, the P-type shielding region 370 can be formed by multiple aluminum ion implantations. The energy of each aluminum ion implantation is different, so that the doping concentration of the P-type shielding region 370 is gradiently distributed.

[0032] In some embodiments, N-type point-doped regions can be formed by implanting N-type dopants into the P-type shield region 370, forming at least two new PN junctions on both sides of the P-type shield region 370. A PN junction is formed between the P-type shield region 370 and the N-type drift region 230, and a PN junction is formed between the P-type shield region 370 and the N-type point-doped regions. The new structure in which N-type dopants are implanted into the region inside the P-type shield region 370 does not affect the JFET region and the N-type drift region in the original device structure, and thus does not affect the on-resistance of the device and the gate charge Qg generated during high-frequency operation of the device. In the off-state of the new structure in this embodiment, a reverse bias is applied to the drain when a positive voltage is applied to the drain. The PN junction formed in the region of the P-type shield region 370 provides a larger depletion region to increase the breakdown electric field that the device can withstand, thereby improving the voltage withstand capability and reliability of the device.

[0033] In some embodiments, N-type point-doped regions are formed in the central region of the P-type shield region 370, and the number of N-type point-doped regions is the same as the number of P-type floating ring regions 260.

[0034] In some embodiments, the width of the N-type point-doped regions in the central region of the P-type shield region 370 decreases sequentially from the P-type shield region to the silicon carbide substrate.

[0035] In some embodiments, the electrode mode of the grounded P-type shield region can also be used to reduce the gate-drain charge Qgd of the device, to optimize the device structure, and to improve the breakdown voltage of the device by changing the position of the linear P-type floating ring region in the N-type drift region 230, the width and concentration of the linear P-type floating ring region, and the number of linear P-type floating ring regions. The current spreading layer structure added to the N-type drift region 230 is beneficial for reducing the specific on-resistance Ron,sp of the device.

[0036] In some embodiments, the silicon carbide trench gate power device in this embodiment further includes a plurality of first P-type floating ring regions and a plurality of second P-type floating ring regions disposed in the regions on both sides of the N-type drift region 230. The plurality of first P-type floating ring regions are disposed in the first side region of the N-type drift region 230 and are disposed opposite to the first current spreading layer 311, and the plurality of second P-type floating ring regions 312 are disposed in the second side region of the N-type drift region 230 and are disposed opposite to the second current spreading layer 312.

[0037] In the embodiment, the P-type floating ring regions 260 of the first side region of the N-type drift region 230 are arranged opposite to the first current spreading layer 311, the P-type floating ring regions 260 of the second side region of the N-type drift region 230 are arranged opposite to the second current spreading layer 312, and the width of the P-type floating ring regions 260 of the two side regions of the N-type drift region 230 gradually decreases from the corresponding current spreading layer to the silicon carbide substrate 210, thereby forming an array of linear floating P ring regions in the N-type drift region 230. The presence of the array of linear floating P ring regions in the N-type drift region 230 effectively reduces the surface electric field intensity of the trench gate bottom oxide layer of the device, thereby improving the reliability of the device operation.

[0038] In some embodiments, the doping concentration of the plurality of first P-type floating ring regions gradually increases from the drain layer 110 to the source layer 460.

[0039] In some embodiments, the doping concentration of the plurality of second P-type floating ring regions gradually increases from the drain layer 110 to the source layer 460.

[0040] In some embodiments, the plurality of first P-type floating ring regions and the plurality of second P-type floating ring regions are arranged one-to-one.

[0041] In some embodiments, the first N-type heavily doped region 341 is formed between the first side of the gate dielectric layer 431 and the first P-type well region 321, the second N-type heavily doped region 342 is formed between the second side of the gate dielectric layer 431 and the second P-type well region 322, and the distance between the two sides of the gate dielectric layer 431 is the same. The height of the gate dielectric layer 431 is greater than the sum of the heights of the first current spreading layer 311, the first P-type well region 321, and the first N-type heavily doped region.

[0042] In some embodiments, in combination Figure 1 As shown, the width of the first N-type heavily doped region 341 is greater than the width of the first P-type heavily doped region 331, and the width of the second N-type heavily doped region 342 is greater than the width of the second P-type heavily doped region 332.

[0043] In some embodiments, the width of the first P-type heavily doped region is greater than the width of the vertical portion of the first P-type well region.

[0044] In some embodiments, the width of the field oxide layer 451 is greater than the width of the gate layer 441.

[0045] In some embodiments, the depth of the first P-type heavily doped region is the same as the depth of the first N-type heavily doped region. The depth of the first current spreading layer 311 is less than the depth of the first P-type well region 321, and the depth of the second current spreading layer 312 is less than the depth of the second P-type well region 322.

[0046] In some embodiments, the thickness of the gate dielectric layer 431 is less than the thickness of the P-type shield region 370.

[0047] In some embodiments, the gate dielectric layer 431 is a concave structure, the bottom of the gate dielectric layer 431 is arc-shaped, and the P-type shield region 370 is arc-shaped, and the P-type shield region 370 wraps the bottom of the gate dielectric layer 431.

[0048] In some embodiments, the gate dielectric layer 431 is a symmetric structure.

[0049] In some embodiments, the inner wall of the groove of the gate dielectric layer 431 is a sawtooth structure, which is used to increase the contact area between the gate and the channel, increase the on-current of the device, and facilitate local field dispersion, so that the channel is formed and disappears more quickly, and the working frequency of the device is improved.

[0050] The embodiment of the present application also provides a preparation method of a silicon carbide trench gate power device, which is applied to the silicon carbide trench gate power device of any one of the above-mentioned embodiments, and refers to Figure 2 The preparation method in the embodiment includes steps S100 to S700.

[0051] In step S100, a silicon carbide substrate 210 is provided, a buffer layer 220 and an N-type drift region 230 are sequentially formed on the front surface of the silicon carbide substrate 210, and a plurality of P-type floating ring regions 260 are formed in the N-type drift region 230 by repeated oxide deposition, etching, ion implantation, and epitaxy.

[0052] In the embodiment, the buffer layer 220 and the N-type drift region 230 can be sequentially formed on the silicon carbide substrate 210 by an epitaxy process, and the doping concentration of the N-type drift region 230 is greater than the doping concentration of the buffer layer 220, as shown in schematic structure (a) in Figure 3 The oxide hard film 240 is deposited, as shown in schematic structure (b) in Figure 3 The first photoresist 251 is formed on the oxide hard film 20, as shown in schematic structure (c) in Figure 3 Then, the oxide hard film 240 is etched according to the pattern of the first photoresist 251, as shown in schematic structure (d) in Figure 3

[0053] In combination with Figure 4 After the first photoresist 251 is removed, as shown in schematic structure (a) in Figure 4 The ion implantation area is exposed on both sides of the oxide hard film 240, and under the protection of the oxide hard film 240, the P-type doping ions are implanted to form the P-type floating ring region 260 in the central region of the N-type drift region 230, as shown in schematic structure (b) in Figure 4 ​The schematic structure (b) is shown in the diagram. Then, the oxide hard film 240 is removed, as shown in the diagram. Figure 4 The schematic structure (c) is shown in the diagram. An epitaxial N-type drift region 230 is formed, which covers a P-type floating ring region 260. Then, through repeated oxide deposition, etching, ion implantation, and epitaxy, multiple P-type floating ring regions 260 are formed within the N-type drift region 230. The width of the multiple P-type floating ring regions 260 gradually increases in the front direction of the silicon carbide substrate 210. The width of each repeated ion implantation is larger than the width of the previous ion implantation, as shown in the diagram. Figure 4 The schematic structure (d) is shown in the figure.

[0054] In step S200, the N-type drift region 230 is further epitaxially extended, and a current-extending material layer 310, a P-type doped layer 320, an N-type heavily doped layer 340, and a P-type heavily doped region (first P-type heavily doped region 331 and second P-type heavily doped region 332) are formed by N-type ion implantation and P-type ion implantation.

[0055] In this embodiment, the N-type drift region 230 is further extended, such as... Figure 5 The schematic structure (a) is shown in the diagram. A current-spreading material layer 310, a P-type doped layer 320, an N-type heavily doped layer 340, and heavily doped P-type regions (first heavily doped P-type region 331 and second heavily doped P-type region 332) are formed through N-type ion implantation and P-type ion implantation. The first heavily doped P-type region 331 and the second heavily doped P-type region 332 are respectively disposed on both sides of the N-type heavily doped layer 340, as shown in the diagram. Figure 5 The schematic structure (b) is shown in the figure.

[0056] In step S300, under the protection of the first photolithography mask 252, etching is performed along a portion of the N-type heavily doped layer 340 to form an ion implantation trench extending into the N-type drift region 230.

[0057] In this embodiment, a first photomask 252 is deposited, and ion implantation trenches are formed by photolithography according to the pattern of the first photomask 252, such as... Figure 5 The schematic structure (c) is shown in the diagram. The ion implantation trench divides the current spreading material layer 310 into a first current spreading layer 311 and a second current spreading layer 312, divides the P-type doped layer 320 into a first P-type well region 321 and a second P-type well region 322, and divides the N-type heavily doped layer 340 into a first N-type heavily doped region 341 and a second N-type heavily doped region 342, as shown in the diagram. Figure 5 The schematic structure (d) is shown in the figure.

[0058] In step S400, a protective layer 410 is formed along the inner surface of the ion implantation trench, such as... Figure 6 The schematic structure (a) is shown in the figure. A deposited oxide hard film 390, as... Figure 6As shown in the schematic structure (b) in FIG. 3B. A second photoresist mask 253 is formed on the oxide hard mask 390, as shown in the schematic structure (c) in FIG. 3C. Then the oxide hard mask 390 is etched under the protection of the second photoresist mask 253 to expose the first region on the protection layer 410, and a new oxide hard mask 391 is obtained, as shown in the schematic structure (d) in FIG. 3D. Figure 6 As shown in the schematic structure (b) in FIG. 3B. A second photoresist mask 253 is formed on the oxide hard mask 390, as shown in the schematic structure (c) in FIG. 3C. Then the oxide hard mask 390 is etched under the protection of the second photoresist mask 253 to expose the first region on the protection layer 410, and a new oxide hard mask 391 is obtained, as shown in the schematic structure (d) in FIG. 3D. Figure 6 As shown in the schematic structure (b) in FIG. 3B. A second photoresist mask 253 is formed on the oxide hard mask 390, as shown in the schematic structure (c) in FIG. 3C. Then the oxide hard mask 390 is etched under the protection of the second photoresist mask 253 to expose the first region on the protection layer 410, and a new oxide hard mask 391 is obtained, as shown in the schematic structure (d) in FIG. 3D.

[0059] As shown in the schematic structure (b) in FIG. 3B. A second photoresist mask 253 is formed on the oxide hard mask 390, as shown in the schematic structure (c) in FIG. 3C. Then the oxide hard mask 390 is etched under the protection of the second photoresist mask 253 to expose the first region on the protection layer 410, and a new oxide hard mask 391 is obtained, as shown in the schematic structure (d) in FIG. 3D. Figure 7 As shown in the schematic structure (b) in FIG. 3B. A second photoresist mask 253 is formed on the oxide hard mask 390, as shown in the schematic structure (c) in FIG. 3C. Then the oxide hard mask 390 is etched under the protection of the second photoresist mask 253 to expose the first region on the protection layer 410, and a new oxide hard mask 391 is obtained, as shown in the schematic structure (d) in FIG. 3D. Figure 7 As shown in the schematic structure (b) in FIG. 3B. A second photoresist mask 253 is formed on the oxide hard mask 390, as shown in the schematic structure (c) in FIG. 3C. Then the oxide hard mask 390 is etched under the protection of the second photoresist mask 253 to expose the first region on the protection layer 410, and a new oxide hard mask 391 is obtained, as shown in the schematic structure (d) in FIG. 3D.

[0060] In some embodiments, the P-type doping ions can include aluminum ions.

[0061] In the present embodiment, the P-type doping ions can be implanted into the first region at the bottom of the ion implantation trench to form the P-type shielding region 370 under the protection of the protection layer 410 and the oxide hard mask 391. The implantation process of the P-type doping ions can be performed in multiple times, so that the doping concentration of the P-type shielding region 370 presents a trapezoidal gradient. The doping concentration of the P-type shielding region gradually increases from the drain layer to the source layer.

[0062] In some embodiments, the position of the first region is defined by the initial gate structure of the device. The deposition of the silicon nitride material as the etching stop layer can ensure high-precision pattern transfer, control the critical dimension, and reduce process defects. Specifically, in the photoresist pattern transfer process, the etching stop layer utilizes the difference in etching rate with adjacent materials (such as silicon oxide and polysilicon) to accurately stop etching during pattern transfer, avoiding over-etching of the underlying structure. In addition, the etching stop layer can also prevent the loss of inner and outer stop layer height in the side wall, ensuring the uniformity of subsequent pattern transfer.

[0063] In some embodiments, the etching selectivity ratio of the etching stop layer to the adjacent material is greater than or equal to 10:1.

[0064] In some embodiments, by adjusting the nitrogen content in the silicon nitride material, the etching stop layer can include a multi-layer structure. Adjusting the etching speed of the etching stop layer can also facilitate the adjustment of the shape and size of the first region.

[0065] In step S600, after forming the inverted U-shaped gate dielectric layer 431 along the inner surface of the ion implantation trench on the P-type shielding region, as shown in the schematic structure (c) in FIG. 4C. The gate material 440 is deposited, as shown in the schematic structure (d) in FIG. 4D. Figure 7 In step S600, after forming the inverted U-shaped gate dielectric layer 431 along the inner surface of the ion implantation trench on the P-type shielding region, as shown in the schematic structure (c) in FIG. 4C. The gate material 440 is deposited, as shown in the schematic structure (d) in FIG. 4D. Figure 7As shown in the schematic structure (d) in FIG. 7. The gate layer 441 is formed in the recess of the gate dielectric layer 431, as shown in the schematic structure (e) in FIG. 7. Figure 8 As shown in the schematic structure (a) in FIG. 8. The field oxide material 450 is formed on the gate layer 441, as shown in the schematic structure (b) in FIG. 8. Figure 8 As shown in the schematic structure (b) in FIG. 8. The gate dielectric layer 431 and the field oxide material 450 form a closed structure wrapping the gate layer 441.

[0066] In some embodiments, the gate layer 441 can be a metal material. By setting a metal gate, the phenomenon of threshold voltage instability during the reliability operation of the device can be improved.

[0067] In some embodiments, the gate dielectric layer 431 can be composed of a high-K dielectric material. During the device conduction process, the channel resistance is the largest resistance in the conduction resistance. The channel size, device bias, oxide layer capacitance, channel electron mobility, and threshold voltage play an important role in reducing the conduction resistance. By using a high-K dielectric material and a metal gate material, the capacitance value of the oxide layer capacitance can be greatly increased at the same thickness of the dielectric layer, which is beneficial to the decrease of the threshold voltage and improves the oxide layer breakdown electric field, reduces the leakage current of the device, and improves the reliability of the device.

[0068] In some embodiments, the gate dielectric layer 431 can be a composite dielectric layer of silicon oxide and silicon nitride, which can be formed by alternately setting multiple layers of silicon oxide layers and silicon nitride layers.

[0069] In the same reaction chamber, by adjusting the reaction gas in the alternating time period, for example, gradually increasing the nitrogen and reducing the oxygen, the stage gradually deposits silicon nitride, if the oxygen is gradually increased and the nitrogen is gradually reduced, the stage gradually deposits silicon oxide. At the same time, the silicon-containing gas needs to be introduced, and the content of various gases in the mixed gas is matched to control the content of oxygen and nitrogen in the thin film, so as to alternately deposit the silicon oxide layer and the silicon nitride layer in the same reaction chamber to form the gate dielectric layer 431.

[0070] In step S700, the second photoresist 251 is formed on the field oxide material 450, as shown in the schematic structure (c) in FIG. 9. Figure 8 Then, the field oxide layer 451 is etched according to the pattern of the second photoresist 251 until the gate dielectric layer 431 is exposed, as shown in the schematic structure (d) in FIG. 9. Figure 8 The second photoresist 251 is removed, as shown in the schematic structure (a) in FIG. 10. Figure 9 The source layer 460 is formed in contact with the horizontal part of the gate dielectric layer 431 and the field oxide layer 451, as shown in the schematic structure (b) in FIG. 11. Figure 9 The drain layer 110 is formed on the back surface of the silicon carbide substrate 210, as shown in the schematic structure (c) in FIG. 11. Figure 1The source electrode material is deposited after etching the field oxide layer 451 to form the source layer 460.

[0071] In some embodiments, the coverage of the field oxide layer 451 is defined by photoresist, and the silicon oxide material is etched under the coverage of the photoresist to form the field oxide layer 451 on the gate dielectric layer 431 and the gate layer 441.

[0072] In the single-trench-gate lithography process in the embodiment, the P-type shielding region 370 is formed by injecting aluminum ions into the center of the bottom of the trench of the SiC trench-gate MOSFET using pattern lithography and high-concentration aluminum ion injection, to shield and reduce the high electric field of the oxide layer at the center of the bottom of the trench-gate, to avoid high electric field breakdown and reduce the gate leakage current, and to improve the operation reliability of the device.

[0073] In some embodiments, in the lithography pattern transfer process, the etching stop layer uses the difference in etching rate of adjacent materials (such as silicon oxide and polysilicon) to accurately stop etching during pattern transfer, to avoid over-etching of the underlying structure, and the etching stop layer can also prevent the loss of the height of the inner and outer sidewall stop layers, to ensure the uniformity of subsequent pattern transfer.

[0074] In some embodiments, the interface between the gate layer 441 and the field oxide layer 451 is arc-shaped or zigzag-shaped.

[0075] In some embodiments, the interface between the gate layer 441 and the field oxide layer 451 is arc-shaped, and the top of the arc is close to the P-type shielding region 370.

[0076] The embodiment of the present application also provides a chip comprising the SiC trench-gate power device according to any one of the above embodiments.

[0077] In the embodiment, the chip comprises a chip substrate, and one or more SiC trench-gate power devices are arranged on the substrate.

[0078] In a specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the SiC trench-gate power device according to any one of the above embodiments.

[0079] In a specific application embodiment, the chip can be a switching chip or a driving chip.

[0080] In the embodiment, the P-type shielding region 370 is formed at the bottom of the groove of the N-type drift region 230, the gate dielectric layer 431 is formed on the inner wall of the groove on the P-type shielding region 370, and the plurality of P-type floating ring regions 260 are arranged in the N-type drift region 230, the width of the plurality of P-type floating ring regions 260 gradually decreases from the P-type shielding region 370 to the silicon carbide substrate 210, which can effectively reduce the surface electric field intensity of the oxide layer at the bottom of the trench gate of the device, and improve the reliability quality of the device operation. On the other hand, the existence of the linear floating P ring region will expand the high electric field distribution range in the drift region, increase the space charge area to improve the withstand voltage capability of the device, and increase the breakdown voltage. Although the existence of the linear floating P ring region will cause the on-resistance to rise, however, combined with the increase of the effective BV of the device, it is beneficial to optimize its static quality factor. Due to the introduction of the linear floating P ring region, the saturation current of the device is effectively reduced, the dynamic short-circuit endurance time of the device under short-circuit test is improved, the endurance capability of the device under short-circuit test is improved, and the reliability quality of the device is improved.

[0081] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned various doped regions and devices are exemplified, and in actual application, the above-mentioned functions can be completed by different doped regions and devices according to needs, that is, the internal structure of the device is divided into different doped regions to complete all or part of the functions described above. The doped regions and devices in the embodiments can be integrated in one unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0082] In addition, the specific names of the doped regions and devices are only for the convenience of mutual differentiation, and are not used to limit the protection scope of the present application.

[0083] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in a certain embodiment can be referred to the related description of other embodiments.

[0084] In addition, the doped regions in each embodiment of the present application can be integrated in one unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0085] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A silicon carbide trench gate power device, characterized in that, include: A silicon carbide substrate, a buffer layer, and an N-type drift region are stacked together. The N-type drift region has a concave structure; A first current spreading layer and a second current spreading layer are formed on the side of the N-type drift region; The first P-type well region is formed on the first current spreading layer; The second P-type well region is formed on the second current spreading layer; the first P-type well region and the second P-type well region are L-shaped structures; The first N-type heavily doped region and the first P-type heavily doped region are formed on the horizontal portion of the first P-type well region; A second N-type heavily doped region and a second P-type heavily doped region are formed on the horizontal portion of the second P-type well region; a first P-type heavily doped region is formed between the vertical portions of the first N-type heavily doped region and the first P-type well region; and a second P-type heavily doped region is formed between the vertical portions of the second N-type heavily doped region and the first P-type well region. The system comprises a gate dielectric layer, a gate layer, a P-type shielding region, and a field oxide layer. The P-type shielding region is formed at the bottom of the groove of the N-type drift region and completely covers the bottom of the gate dielectric layer. The gate dielectric layer is formed on the inner wall of the groove on the P-type shielding region and has an inverted V-shaped structure. The horizontal portion of the inverted V-shaped structure covers the vertical portion of the first P-type well region, the vertical portion of the second P-type well region, the first heavily doped N-type region, the second heavily doped N-type region, and the second heavily doped P-type region. The gate layer is located within the groove of the inverted V-shaped structure and is flush with the horizontal portion of the inverted V-shaped structure. The field oxide layer is located on the gate dielectric layer and forms a closed structure that encloses the gate layer. Multiple P-type floating ring regions are located in the central region of the N-type drift region. The width of the multiple P-type floating ring regions decreases sequentially from the P-type shielding region toward the silicon carbide substrate. Furthermore, the spacing between the P-type floating ring regions and the P-type shielding region is greater than the thickness of the P-type shielding region. A source layer covers the gate dielectric layer and the field oxide layer; A drain layer is formed on the back side of the silicon carbide substrate.

2. The silicon carbide trench gate power device as described in claim 1, characterized in that, The widths of the multiple P-shaped floating ring zones form an arithmetic sequence.

3. The silicon carbide trench gate power device as described in claim 1, characterized in that, The doping concentration of the P-type floating ring regions in the plurality of P-type floating ring regions gradually increases from the drain layer to the source layer.

4. The silicon carbide trench gate power device as described in claim 1, characterized in that, The spacing between adjacent P-type floating ring zones in the plurality of P-type floating ring zones is the same.

5. The silicon carbide trench gate power device as described in claim 1, characterized in that, The width of the field oxide layer is greater than the width of the gate layer.

6. The silicon carbide trench gate power device as described in claim 1, characterized in that, The silicon carbide trench gate power device also includes: Multiple first P-type floating ring regions are disposed on the first side of the N-type drift region and are disposed opposite to the first current extension layer; Multiple second P-type floating ring regions are disposed on the second side of the N-type drift region and are disposed opposite to the second current extension layer.

7. The silicon carbide trench gate power device as described in claim 6, characterized in that, The doping concentration of the plurality of first P-type floating ring regions gradually increases from the drain layer to the source layer; and / or The doping concentration of the multiple second P-type floating ring regions gradually increases from the drain layer to the source layer.

8. The silicon carbide trench gate power device according to any one of claims 1-7, characterized in that, The width of the first heavily doped P-type region is greater than the width of the vertical portion of the first P-type well region.

9. A method for fabricating a silicon carbide trench gate power device, characterized in that, The preparation method is used to prepare the silicon carbide trench gate power device as described in any one of claims 1-8, and the preparation method includes: A silicon carbide substrate is provided, and a buffer layer and an N-type drift region are sequentially formed on the front side of the silicon carbide substrate. Multiple P-type floating ring regions are formed in the central region of the N-type drift region through repeated oxide deposition, etching, ion implantation, and epitaxy. The width of the multiple P-type floating ring regions gradually increases upward along the front side of the silicon carbide substrate. The N-type drift region is further extended, and a current-spreading material layer, a P-type doped layer, an N-type heavily doped layer, and a P-type heavily doped region are formed by N-type ion implantation and P-type ion implantation; the P-type heavily doped regions are provided on both sides of the N-type heavily doped layer. Under the protection of the first photolithography mask, etching is performed along a portion of the N-type heavily doped layer to form an ion implantation trench extending into the N-type drift region; the ion implantation trench divides the current spreading material layer into a first current spreading layer and a second current spreading layer, divides the P-type doped layer into a first P-type well region and a second P-type well region, and divides the N-type heavily doped layer into a first N-type heavily doped region and a second N-type heavily doped region; After forming a protective layer along the inner surface of the ion implantation trench, an oxide hard film is deposited, and a second photomask is formed on the oxide hard film. Then, the oxide hard film is etched under the protection of the second photomask to expose the first region on the protective layer. After removing the second photolithographic mask, P-type doped ions are implanted along the first region, and after removing the protective layer and the oxide hard film, annealing is performed to form a P-type shielding region; After forming an inverted V-shaped gate dielectric layer along the inner surface of the ion implantation trench on the P-type shielding region, a gate layer is formed in the groove of the gate dielectric layer, and a field oxide layer is formed on the gate layer; wherein, the gate dielectric layer and the field oxide layer form a closed structure that encloses the gate layer; The field oxide layer is etched to form a source layer covering the gate dielectric layer and the field oxide layer, and a drain layer is formed on the back side of the silicon carbide substrate.

10. A chip, characterized in that, Including the silicon carbide trench gate power device as described in any one of claims 1-8.

Images