Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle
By designing depletion-mode semiconductor devices and utilizing channel layer and split gate layer structures, the problems of high conduction loss and slow response speed of SiC MOSFETs are solved, achieving lower conduction loss and faster response speed, making them suitable for high-frequency circuits and switching circuits.
Patent Information
- Application Number
- CN202610038101.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-13
- Publication Date
- 2026-04-10
AI Technical Summary
Existing SiC MOSFETs are enhancement-mode devices with high conduction losses, slow response speed, and large capacitance between the gate and drain.
Design a depletion-type semiconductor device by forming a channel layer with the opposite conductivity type to the well region along the sidewall of the trench on the first surface, which can conduct without applying a voltage to the gate source, and by forming a separate gate layer in the insulating layer, increasing the thickness of the gate oxide layer at the bottom of the trench to reduce the gate and drain capacitance.
It reduces the conduction loss of semiconductor devices, improves the response speed, is suitable for high-frequency circuits and switching circuits, and reduces the capacitance of the gate and drain.
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Figure CN121843196A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. Background Technology
[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC), as representatives of third-generation semiconductor materials, have advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency scenarios.
[0003] The existing SiC metal-oxide-semiconductor field-effect transistor (MOSFET) is an enhancement-mode device. It is not normally turned on. If it is turned on, a positive voltage needs to be applied between the gate and the source to make the device form a channel and turn on.
[0004] However, enhancement-mode devices have higher conduction losses, slower response times, and larger capacitance between the gate and drain. Summary of the Invention
[0005] This application provides a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle to reduce the capacitance between the gate and drain, reduce the conduction loss of the semiconductor device, and improve the response speed.
[0006] According to one aspect of this application, a semiconductor device is provided, the semiconductor device comprising:
[0007] A semiconductor body, configured as a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, and a channel layer, the first region and the channel layer being in contact with each other, the first region being configured as a first conductivity type and located on the first surface, the well region being configured as a second conductivity type and located on the side of the first region away from the first surface; a trench is provided on the first surface; the channel layer is configured as a first conductivity type, the channel layer is located on the first surface and disposed along the sidewall of the trench; the first conductivity type and the second conductivity type are different;
[0008] An insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion; the first insulating portion is located on the bottom surface of the trench; the third insulating portion is located on the side wall of the trench; the first insulating portion is connected to both the second and third insulating portions.
[0009] A separation gate layer is located on the side of the first insulating portion away from the trench; a second insulating portion is located on the side of the separation gate layer away from the first insulating portion.
[0010] The gate is located on the side of the insulating layer in the trench away from the semiconductor body;
[0011] The source electrode is located on the first surface;
[0012] The drain electrode is located on the second surface.
[0013] Optionally, the ion concentration in the channel layer is lower than the ion concentration in the first region.
[0014] Optionally, the semiconductor body further includes a second region; the second region is configured with a second conductivity type and is located on the first surface; the second region and the first region are connected.
[0015] Optionally, the thickness of the second insulating portion is greater than or equal to 2000 angstroms and less than or equal to 3000 angstroms in the direction from the first surface to the second surface.
[0016] Optionally, along the direction from the first surface to the second surface, the distance between the side of the gate away from the second surface and the second surface is less than the distance between the first surface and the second surface.
[0017] Optionally, the semiconductor device further includes an interlayer insulating layer located on the first surface; the interlayer insulating layer is provided with a first via and a second via; the first via exposes a portion of the gate; the second via exposes a portion of the first region;
[0018] Semiconductor devices also include a gate electrode;
[0019] The gate electrode passes through the first via to reach the gate;
[0020] The source electrode passes through the second via to reach the first region.
[0021] Optionally, the semiconductor body may include a silicon carbide semiconductor body or a gallium nitride semiconductor body.
[0022] According to another aspect of this application, a method for manufacturing a semiconductor device is provided, the method comprising:
[0023] A semiconductor body is provided, the semiconductor body being configured with a first conductivity type, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region, a first region, and a channel layer, the first region and the channel layer being in contact with each other, the first region being configured with the first conductivity type and located on the first surface, the well region being configured with the second conductivity type and located on the side of the first region away from the first surface; a trench is provided on the first surface; the channel layer is configured with the first conductivity type, the channel layer being located on the first surface and disposed along the sidewall of the trench; the first conductivity type and the second conductivity type are different;
[0024] A first insulating part is formed on the bottom surface of the trench;
[0025] A separation gate layer is formed on the side of the first insulating portion away from the trench;
[0026] A second insulating portion is formed on the side of the separation gate layer away from the first insulating portion;
[0027] A third insulating part is formed on the sidewall of the trench; the first insulating part, the second insulating part, and the third insulating part together constitute an insulating layer;
[0028] A gate is formed on the side of the insulating layer away from the semiconductor body within the trench;
[0029] A source electrode is formed on the first surface;
[0030] A drain electrode is formed on the second surface.
[0031] Optionally, the semiconductor body includes:
[0032] A semiconductor body is provided, the semiconductor body is configured with a first conductivity type, and the semiconductor body includes a first surface and a second surface disposed opposite to each other;
[0033] A transition well region is formed on the first surface, and the transition well region is configured as a second conductivity type;
[0034] A first mask layer is formed on the first surface, and the first mask layer is provided with a third through hole;
[0035] A transition first region is formed on the first surface exposed by the third through hole, and the transition first region is set to a first conductivity type;
[0036] Remove the first mask layer;
[0037] A second mask layer is formed on the first surface, and the second mask layer is provided with a fourth through hole;
[0038] A third mask layer is formed at the bottom and sidewall of the fourth through hole, and the materials of the third mask layer and the second mask layer are different;
[0039] Remove the third mask layer at the bottom of the fourth through hole;
[0040] A trench is formed on the first surface, and the trench extends from the first surface into the semiconductor body;
[0041] A fourth mask layer is formed within the trench;
[0042] Remove the third mask layer;
[0043] A channel layer is formed on the first surface and along the sidewall of the trench; the channel layer is configured as a first conductivity type; the transition well region retained after the channel layer is formed is designated as a well region, and the retained transition first region is designated as a first region;
[0044] Remove the second and fourth mask layers.
[0045] Optionally, a first insulating portion is formed on the bottom surface of the trench, including:
[0046] A first gate oxide layer is formed on the bottom and sidewalls of the trench;
[0047] Remove the first gate oxide layer from the sidewall of the trench and use the first gate oxide layer on the bottom surface of the trench as the first insulating part.
[0048] A separation gate layer is formed on the side of the first insulating portion away from the trench, including:
[0049] A polysilicon layer is formed on the side of the first gate oxide layer away from the semiconductor body;
[0050] Part of the polysilicon layer is removed to form a detached gate layer;
[0051] A second insulating portion is formed on the side of the separation gate layer away from the first insulating portion, including:
[0052] A second gate oxide layer is formed on the side of the separated gate layer away from the first insulating portion;
[0053] A portion of the second gate oxide layer is removed to form a second insulating portion.
[0054] Optionally, the semiconductor body includes:
[0055] Provide a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.
[0056] According to another aspect of this application, a power module is provided, the power module including a substrate and at least one of the above-described semiconductor devices, the substrate being used to support the semiconductor devices.
[0057] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction;
[0058] The power conversion circuit includes a circuit board and at least one of the aforementioned semiconductor devices, which are electrically connected to the circuit board.
[0059] According to another aspect of this application, a vehicle is provided, the vehicle including a load and the aforementioned power conversion circuit, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.
[0060] The technical solution of this application embodiment provides a channel layer with the opposite conductivity type to the well region on the first surface and along the sidewall of the trench. This eliminates the need to apply a gate-source voltage to the semiconductor device. Under normal conditions, carriers of the first conductivity type are present, making the semiconductor device a depletion-type semiconductor device. It is normally in a conducting state, and a negative gate-source voltage is required to cut off the channel in the off state. Compared to enhancement-mode semiconductor devices, the technical solution provided in this application embodiment reduces the conduction loss of the semiconductor device, improves the response speed and the speed of current flow control, and is more suitable for high-frequency circuits and switching circuits. Simultaneously, by providing a separate gate layer within the insulating layer, the thickness of the gate oxide layer at the bottom of the trench is increased, reducing the strong electric field at the bottom of the trench. Furthermore, the separate gate layer connected to the source can shield the gate and drain areas, reducing the gate and drain capacitance and lowering the conduction loss of the semiconductor device.
[0061] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description
[0062] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0063] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application;
[0064] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application;
[0065] Figures 3-10 These are cross-sectional views corresponding to each step of a semiconductor device manufacturing method provided according to embodiments of this application;
[0066] Figure 11 Provided according to the embodiments of this application Figure 2 The flowchart included in S110;
[0067] Figures 12-21 Provided according to the embodiments of this application Figure 2 The cross-sectional views of each step included in S110. Detailed Implementation
[0068] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0069] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0070] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application. For example... Figure 1 As shown, the semiconductor device includes: a semiconductor body 100 configured with a first conductivity type, including a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 100 further includes a well region 103, a first region 104, and a channel layer 105, the first region 104 and the channel layer 105 being in contact with each other, the first region 104 being configured with the first conductivity type and located on the first surface 101, the well region 103 being configured with the second conductivity type and located on the side of the first region 104 away from the first surface 101; a trench 106 is provided on the first surface 101; the channel layer 105 is configured with the first conductivity type, the channel layer 105 being located on the first surface 101 and disposed along the sidewall of the trench 106; the first conductivity type... The second conductivity type is different; the insulating layer 50 includes a first insulating portion 501, a second insulating portion 502, and a third insulating portion 503; the first insulating portion 501 is located on the bottom surface of the trench 106; the third insulating portion 503 is located on the sidewall of the trench 106; the first insulating portion 501 is connected to both the second insulating portion 502 and the third insulating portion 503; the separation gate layer 60 is located on the side of the first insulating portion 501 away from the trench 106; the second insulating portion 502 is located on the side of the separation gate layer 60 away from the first insulating portion 501; the gate 200 is located on the side of the insulating layer 50 in the trench 106 away from the semiconductor body 100; the source 400 is located on the first surface 101; the drain 500 is located on the second surface 102.
[0071] In this embodiment, the semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.
[0072] For example, in an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type dopant ions in the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions; the channel layer 105 is an N-type channel layer. The well region 103 is a P-well region, and the P-type dopant ions in the P-well region can be aluminum (Al) ions or boron (B) ions. The first region 104 can be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or vapor deposition.
[0073] like Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by one or more epitaxial processes, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).
[0074] A trench 106 is formed on the first surface 101 of the semiconductor body 100. The trench 106 can be formed by photolithography and etching processes. The separation gate layer 60 is located within the insulating layer 50, increasing the thickness of the gate oxide layer at the bottom of the trench 106 and connecting the separation gate layer 60 to the source 400. This can shield the area of the gate 200 and drain 500, reduce the capacitance of the gate 200 and drain 500, and reduce the conduction loss of the semiconductor device.
[0075] The gate 200 can be made of polysilicon. The insulating layer 50 is used to insulate the semiconductor body 100 and the gate 200, and also to insulate the gate 200 and the separation gate layer 60. The source 400 can be formed by depositing metal on the first surface 101, and the drain 500 can be formed by depositing metal on the second surface 102. The deposited metal can be titanium (Ti), nickel (Ni), or silver (Ag).
[0076] The technical solution of this application embodiment provides a channel layer 105 with the opposite conductivity type to the well region 103, formed on the first surface 101 and along the sidewall of the trench 106. This eliminates the need to apply a gate-source voltage to the semiconductor device. Under normal conditions, carriers of the first conductivity type are present, making the semiconductor device a depletion-type semiconductor device. It is normally in a conducting state, and a negative gate-source voltage is required to cut off the channel in the off state. Compared to enhancement-mode semiconductor devices, the technical solution provided in this application embodiment reduces the conduction loss of the semiconductor device, improves the response speed and the speed of current flow control, and is more suitable for high-frequency circuits and switching circuits. Simultaneously, by providing a separation gate layer 60 within the insulating layer 50, the thickness of the gate oxide layer at the bottom of the trench 106 is increased, reducing the strong electric field at the bottom of the trench 106. Furthermore, the separation gate layer 60, connected to the source 400, can shield the areas of the gate 200 and drain 500, reducing the capacitance of the gate 200 and drain 500 and lowering the conduction loss of the semiconductor device.
[0077] For example, Figure 1 In this embodiment, the source electrode 400 is located on the first surface 101 and is a planar source electrode. In optional embodiments of this application, it may also include a trench type source electrode, that is, the first surface 101 may also be provided with a source electrode trench, and a source electrode insulating layer and a source electrode conductive filling layer are provided in the source electrode trench, with the source electrode 400 covering the source electrode insulating layer and the source electrode conductive filling layer.
[0078] In optional embodiments of this application, reference is made to Figure 1 The ion concentration in the channel layer 105 is lower than the ion concentration in the first region 104.
[0079] Specifically, the ion concentration of channel layer 105 is - Between these regions, the ion concentration in the channel layer 105 is lower than that in the first region 104, which can reduce the manufacturing cost of semiconductor devices.
[0080] In an optional embodiment of this application, the semiconductor body 100 further includes a second region 107; the second region 107 is configured with a second conductivity type and is located on the first surface 101; the second region 107 and the first region 104 are connected.
[0081] Specifically, for an N-type MOSFET, the second region 107 is a P+ doped region and the well region 103 is a P- well region. The doping concentration of the second region 107 is greater than that of the well region 103, which allows the second region 107 to form a good ohmic contact with the source 400.
[0082] In an optional embodiment of this application, the thickness of the second insulating portion 502 is greater than or equal to 2000 angstroms and less than or equal to 3000 angstroms along the direction X from the first surface 101 to the second surface 102.
[0083] Specifically, the thickness of the second insulating portion 502 is set to be greater than or equal to 2000 angstroms and less than or equal to 3000 angstroms. This can achieve both insulation isolation between the gate 200 and the separation gate layer 60 and increase the thickness of the insulating layer 50 at the bottom of the trench 106, thereby improving the reliability of the semiconductor device.
[0084] In optional embodiments of this application, reference is made to Figure 1 Along the direction X from the first surface 101 to the second surface 102, the distance L1 between the side of the gate 200 away from the second surface 102 and the second surface 102 is less than the distance L2 between the first surface 101 and the second surface 102.
[0085] Specifically, over-etching is required when forming the gate 200. If over-etching is not performed and the side of the gate 200 away from the second surface 102 is flush with the first surface 101, polysilicon residue will remain in the gate 200, leading to electrical failure. Setting the side of the gate 200 away from the second surface 102 to be lower than the first surface 101 can prevent electrical failure and improve the reliability of the semiconductor device.
[0086] In an optional embodiment of this application, the semiconductor device further includes an interlayer insulating layer 300 located on the first surface 101; the interlayer insulating layer 300 is provided with a first via CT1 and a second via CT2; the first via CT1 exposes a portion of the gate 200; the second via CT2 exposes a portion of the first region 104; the semiconductor device further includes a gate electrode 600; the gate electrode 600 passes through the first via CT1 to reach the gate 200; the source electrode 400 passes through the second via CT2 to reach the first region 104.
[0087] Specifically, the interlayer insulating layer 300 can be made of silicon dioxide. The interlayer insulating layer 300 provides electrical isolation, preventing electron migration between different metal layers and avoiding diffusion or penetration between substances. The interlayer insulating layer 300 can be formed by plasma-enhanced chemical vapor deposition. The gate electrode 600 can pass through the first via CT1 and connect to the gate 200 to provide an electrical signal to the gate 200. The source electrode 400 passes through the second via CT2 and contacts the first region 104.
[0088] In optional embodiments of this application, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.
[0089] The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 also includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.
[0090] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage withstand, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.
[0091] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 2 As shown, the method for manufacturing this semiconductor device includes:
[0092] S110. A semiconductor body is provided, the semiconductor body being configured with a first conductivity type, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region, a first region and a channel layer, the first region and the channel layer being in contact with each other, the first region being configured with the first conductivity type and located on the first surface, the well region being configured with the second conductivity type and located on the side of the first region away from the first surface; a trench is provided on the first surface; the channel layer is configured with the first conductivity type, the channel layer being located on the first surface and disposed along the sidewall of the trench; the first conductivity type and the second conductivity type are different.
[0093] refer to Figure 3 A semiconductor body 100 is provided, which is configured as a first conductivity type and includes a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body 100 also includes a well region 103, a first region 104 and a channel layer 105. The first region 104 and the channel layer 105 are in contact with each other. The first region 104 is configured as a first conductivity type and is located on the first surface 101. The well region 103 is configured as a second conductivity type and is located on the side of the first region 104 away from the first surface 101. The first surface 101 is provided with a trench 106. The channel layer 105 is configured as a first conductivity type and is located on the first surface 101 and disposed along the sidewall of the trench 106. The first conductivity type and the second conductivity type are different.
[0094] In this embodiment, the semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.
[0095] For example, in an N-type MOSFET, the first region 104 is an N+ doped region, where the N-type dopant ions can be phosphorus (P) ions or nitrogen (N) ions; the channel layer 105 is an N-type channel layer. The well region 103 is a P-well region, where the P-type dopant ions can be aluminum (Al) ions or boron (B) ions. The first region 104 can be formed on the first surface 101 of the semiconductor body 100 using processes such as ion implantation, ion diffusion, or vapor deposition. A trench 106 is provided on the first surface 101 of the semiconductor body 100. The trench 106 can be formed using photolithography and etching processes.
[0096] In an optional embodiment of this application, the semiconductor body 100 further includes a second region 107; the second region 107 is configured with a second conductivity type and is located on the first surface 101; the second region 107 and the first region 104 are connected.
[0097] Specifically, for an N-type MOSFET, the second region 107 is a P+ doped region and the well region 103 is a P- well region. The doping concentration of the second region 107 is greater than that of the well region 103, which allows the second region 107 to form a good ohmic contact with the source 400.
[0098] like Figure 3 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by one or more epitaxial processes, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).
[0099] S120, A first insulating part is formed on the bottom surface of the trench.
[0100] In an optional embodiment of this application, forming a first insulating portion on the bottom surface of the trench includes: forming a first gate oxide layer on the bottom surface and sidewalls of the trench; removing the first gate oxide layer on the sidewalls of the trench, and using the first gate oxide layer on the bottom surface of the trench as the first insulating portion.
[0101] refer to Figure 4 and Figure 1 Silicon oxide is deposited on the bottom surface, sidewalls, and first surface 101 of trench 106 to form a first gate oxide layer 201. The thickness of the first gate oxide layer 201 can be greater than or equal to 3000 angstroms and less than or equal to 5000 angstroms. Then, by etching the first gate oxide layer 201, a first insulating portion 501 is formed on the bottom surface of trench 106.
[0102] S130, a separation gate layer is formed on the side of the first insulating portion away from the trench.
[0103] In an optional embodiment of this application, forming a separation gate layer on the side of the first insulating portion away from the trench includes: forming a polysilicon layer on the side of the first gate oxide layer away from the semiconductor body; and removing a portion of the polysilicon layer to form the separation gate layer.
[0104] refer to Figure 4 A polysilicon layer 202 is deposited on the side of the first gate oxide layer 201 away from the semiconductor body 100 within the trench 106.
[0105] refer to Figure 5 Then, by etching the polysilicon layer 202, a separation gate layer 60 is formed on the side of the first insulating portion 501 away from the trench 106.
[0106] S140, A second insulating portion is formed on the side of the separation gate layer away from the first insulating portion.
[0107] In an optional embodiment of this application, forming a second insulating portion on the side of the separation gate layer away from the first insulating portion includes: forming a second gate oxide layer on the side of the separation gate layer away from the first insulating portion; and removing a portion of the second gate oxide layer to form the second insulating portion.
[0108] refer to Figure 5 Silicon oxide is deposited on the side of the separated gate layer 60 away from the first insulating portion 501 to form a second gate oxide layer 203.
[0109] refer to Figure 6 The second gate oxide layer 203 is chemically and mechanically polished along the first surface 101.
[0110] refer to Figure 7 A portion of the second gate oxide layer 203 is removed by wet etching, and a second insulating portion 502 is formed on the side of the separated gate layer 60 away from the first insulating portion 501.
[0111] S150, A third insulating part is formed on the sidewall of the trench; the first insulating part, the second insulating part and the third insulating part together constitute an insulating layer.
[0112] refer to Figure 8 A third insulating portion 503 is formed on the sidewall of the trench 106; the first insulating portion 501, the second insulating portion 502 and the third insulating layer 503 together constitute the insulating layer 50.
[0113] S160. A gate is formed on the side of the insulating layer away from the semiconductor body within the trench.
[0114] refer to Figure 9 Polysilicon is deposited on the side of the insulating layer 50 away from the semiconductor body 100 in the trench 106, and the gate 200 is formed by etching.
[0115] In an optional embodiment of this application, after forming the gate on the side of the insulating layer in the trench away from the semiconductor body in step S160, the method further includes:
[0116] S170. An interlayer insulating layer is formed on the first surface, and the interlayer insulating layer is provided with a first through-hole and a second through-hole; the first through-hole exposes a portion of the gate; the second through-hole exposes a portion of the first region.
[0117] refer to Figure 10 Silicon oxide is deposited on the first surface 101 to form an interlayer insulating layer 300. The interlayer insulating layer 300 has a first via CT1 and a second via CT2. The first via CT1 exposes a portion of the gate 200; the second via CT2 exposes a portion of the first region 104. The interlayer insulating layer 300 provides electrical isolation, preventing electron migration between different metal layers and avoiding diffusion or penetration between substances. The interlayer insulating layer 300 can be formed by plasma-enhanced chemical vapor deposition.
[0118] S180, the source electrode is formed on the first surface.
[0119] refer to Figure 1 Metal is deposited on the first surface 101 to form the source electrode 400. The deposited metal can be aluminum, titanium, nickel, or silver.
[0120] S190, a drain electrode is formed on the second surface.
[0121] refer to Figure 1 Metal is deposited on the second surface 102 to form the drain electrode 500. The deposited metal can be titanium, nickel, or silver.
[0122] Figure 11 Provided according to the embodiments of this application Figure 2 The flowchart included in S110 is as follows: Figure 11 As shown, S110, providing a semiconductor body includes:
[0123] S1101. Provide a semiconductor body, the semiconductor body is configured as a first conductivity type, the semiconductor body includes a first surface and a second surface disposed opposite to each other.
[0124] refer to Figure 12 A semiconductor body 100 is provided, the semiconductor body 100 is configured with a first conductivity type, and the semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other.
[0125] like Figure 12As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by one or more epitaxial processes.
[0126] S1102, A transition well region is formed on the first surface, and the transition well region is configured as a second conductivity type.
[0127] refer to Figure 13 A transition well region 1031 is formed on the first surface 101, and the transition well region 1031 is configured with a second conductivity type. The transition well region 1031 can be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion or vapor deposition.
[0128] S1103. A first mask layer is formed on the first surface, and the first mask layer is provided with a third through hole.
[0129] refer to Figure 14 A first mask layer 301 is formed on the first surface 101, and a third via CT3 is provided in the first mask layer 301. The first mask layer 301 is formed on the first surface 101 of the semiconductor body 100 using a hard mask (HM) process. Alternatively, silicon dioxide can be deposited to form the first mask layer 301 using plasma-enhanced chemical vapor deposition (PECVD). The first mask layer 301 is then patterned using a photolithography process to form the third via CT3.
[0130] S1104. A transition first region is formed on the first surface exposed by the third through hole, and the transition first region is set to a first conductivity type.
[0131] refer to Figure 14 A transition first region 1041 is formed on the first surface 101 exposed by the third via CT3, and the transition first region 1041 is configured as a first conductivity type. The transition first region 1041 can be formed on the first surface 101 exposed by the third via CT3 by an ion implantation process.
[0132] S1105, Remove the first mask layer.
[0133] refer to Figure 15 Hydrofluoric acid solution can be used to etch away the first mask layer 301 of the silicon dioxide material.
[0134] refer to Figure 16The same process used to form the first transition region 1041 is applied to form the second region 107 on the first surface 101.
[0135] S1106. A second mask layer is formed on the first surface, and the second mask layer is provided with a fourth through hole.
[0136] refer to Figure 17 A second mask layer 302 is formed on the first surface 101, and a fourth via CT4 is provided in the second mask layer 302. Silicon dioxide is deposited using HM process or PECVD to form the second mask layer 302. The second mask layer 302 is patterned using photolithography to form the fourth via CT4.
[0137] S1107. A third mask layer is formed at the bottom and sidewall of the fourth through hole. The materials of the third mask layer and the second mask layer are different.
[0138] In an optional embodiment of this application, forming a third mask layer at the bottom and sidewalls of the fourth via includes: forming a third mask layer comprising silicon nitride at the bottom and sidewalls of the fourth via.
[0139] refer to Figure 18 A third mask layer 303 comprising silicon nitride can be formed on the bottom and sidewalls of the fourth through-hole CT4. The third mask layer 303 is made of a different material than the second mask layer 302; for example, the second mask layer 302 is made of silicon dioxide, and the third mask layer 303 is made of silicon nitride. Distinguishing the materials of the third mask layer 303 and the second mask layer 302 prevents subsequent removal of the third mask layer 303 from affecting the second mask layer 302.
[0140] After forming a third mask layer at the bottom and sidewalls of the fourth through hole, the third mask layer at the bottom of the fourth through hole is removed.
[0141] refer to Figure 18 and Figure 19 After forming a third mask layer 303 comprising silicon nitride on the bottom and sidewalls of the fourth through hole CT4, and on the side of the second mask layer 302 away from the first surface 101, hot phosphoric acid can be applied to remove the third mask layer 303 on the bottom of the fourth through hole CT4 and on the side of the second mask layer 302 away from the first surface 101.
[0142] S1108. A trench is formed on the first surface, the trench extending from the first surface into the semiconductor body.
[0143] refer to Figure 19 A trench 106 is formed on the first surface 101 by etching, and the trench 106 extends from the first surface 101 into the semiconductor body 100. The third mask layer 303 is retained on the sidewall of the fourth via CT4 to facilitate the formation of the channel layer for ion implantation.
[0144] S1109. A fourth mask layer is formed in the trench.
[0145] refer to Figure 20 Polysilicon is deposited in trench 106 to form the fourth mask layer 304.
[0146] S1110, Remove the third mask layer.
[0147] refer to Figure 20 The third mask layer 303, which is made of silicon nitride, can be removed by applying thermal phosphoric acid.
[0148] S1111, A channel layer is formed on the first surface and along the sidewall of the trench; the channel layer is configured as a first conductivity type; the transition well region retained after the channel layer is formed is a well region, and the retained transition first region is a first region.
[0149] refer to Figure 21 After removing the third mask layer 303, a channel layer 105 is formed on the first surface 101 and along the sidewalls of the trench 106 by ion implantation. Exemplarily, the channel layer 105 is formed by implanting N-type doped ions. The transition well region retained after forming the channel layer 105 is designated as well region 103, and the retained transition first region is designated as first region 104. The ion implantation concentration of the channel layer 105 is lower than that of the first region 104, reducing the manufacturing cost of the semiconductor device.
[0150] S1112, Remove the second and fourth mask layers.
[0151] refer to Figure 3 Hydrofluoric acid and nitric acid can be used to remove the second mask layer 302 and the fourth mask layer 304. Here, the fourth mask layer 304 is first formed to fill the trench 106, and then the fourth mask layer 304 is removed to protect the bottom of the trench 106 from ion implantation.
[0152] In optional embodiments of this application, S110, providing a semiconductor body includes: providing a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.
[0153] For details, please refer to Figure 1 The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 also includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.
[0154] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage withstand, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.
[0155] This application provides a power module including a substrate and at least one semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of this power module including any semiconductor device as described in any embodiment of this application will not be elaborated further here.
[0156] This application provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, and the semiconductor device is electrically connected to the circuit board.
[0157] Therefore, the power conversion circuit incorporates the beneficial effects of any semiconductor device described in any embodiment of this application, which will not be elaborated further here.
[0158] This application embodiment also provides a vehicle, which includes a load and the aforementioned power conversion circuit. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.
[0159] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of this application will not be repeated here.
[0160] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.
[0161] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A semiconductor device, characterized in that, include: A semiconductor body, configured with a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, and a channel layer, the first region and the channel layer being in contact with each other, the first region being configured with the first conductivity type and located on the first surface, the well region being configured with the second conductivity type and located on the side of the first region away from the first surface; the first surface is provided with a trench; the channel layer is configured with the first conductivity type, the channel layer being located on the first surface and disposed along the sidewall of the trench; the first conductivity type and the second conductivity type are different; An insulating layer, comprising a first insulating portion, a second insulating portion, and a third insulating portion; The first insulating part is located on the bottom surface of the trench; the third insulating part is located on the side wall of the trench; the first insulating part is connected to both the second insulating part and the third insulating part; A separation gate layer is located on the side of the first insulating portion away from the trench; a second insulating portion is located on the side of the separation gate layer away from the first insulating portion; The gate is located on the side of the insulating layer in the trench away from the semiconductor body; The source electrode is located on the first surface; The drain electrode is located on the second surface.
2. The semiconductor device according to claim 1, characterized in that, The ion concentration in the channel layer is lower than that in the first region.
3. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a second region; the second region is configured with a second conductivity type and is located on the first surface; the second region and the first region are connected.
4. The semiconductor device according to claim 1, characterized in that, In the direction from the first surface to the second surface, the thickness of the second insulating portion is greater than or equal to 2000 angstroms and less than or equal to 3000 angstroms.
5. The semiconductor device according to claim 1, characterized in that, Along the direction from the first surface to the second surface, the distance between the side of the gate away from the second surface and the second surface is less than the distance between the first surface and the second surface.
6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes an interlayer insulating layer located on the first surface; the interlayer insulating layer is provided with a first via and a second via; the first via exposes a portion of the gate; the second via exposes a portion of the first region; The semiconductor device further includes a gate electrode; The gate electrode passes through the first through-hole to reach the gate; The source electrode passes through the second via to reach the first region.
7. The semiconductor device according to claim 1, characterized in that, The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.
8. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body being configured with a first conductivity type, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, and a channel layer, the first region and the channel layer being in contact with each other, the first region being configured with the first conductivity type and located on the first surface, the well region being configured with the second conductivity type and located on the side of the first region away from the first surface; the first surface is provided with a trench; the channel layer is configured with the first conductivity type, the channel layer being located on the first surface and disposed along the sidewall of the trench; the first conductivity type and the second conductivity type are different; A first insulating portion is formed on the bottom surface of the trench; A separation gate layer is formed on the side of the first insulating portion away from the trench; A second insulating portion is formed on the side of the separation gate layer away from the first insulating portion; A third insulating portion is formed on the sidewall of the trench; the first insulating portion, the second insulating portion, and the third insulating portion together constitute the insulating layer; A gate is formed on the side of the insulating layer away from the semiconductor body within the trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.
9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The semiconductor body includes: A semiconductor body is provided, the semiconductor body being configured with a first conductivity type, the semiconductor body including a first surface and a second surface disposed opposite to each other; A transition well region is formed on the first surface, and the transition well region is configured with a second conductivity type; A first mask layer is formed on the first surface, and the first mask layer is provided with a third through hole; A transition first region is formed on the first surface exposed by the third through hole, and the transition first region is configured as a first conductivity type; Remove the first mask layer; A second mask layer is formed on the first surface, and the second mask layer is provided with a fourth through hole; A third mask layer is formed at the bottom and sidewall of the fourth through hole, and the third mask layer is made of a different material than the second mask layer; Remove the third mask layer at the bottom of the fourth through hole; The trench is formed on the first surface and extends from the first surface into the semiconductor body; A fourth mask layer is formed within the trench; Remove the third mask layer; A channel layer is formed on the first surface and along the sidewall of the trench; the channel layer is configured with a first conductivity type; the transition well region retained after the formation of the channel layer is designated as a well region, and the retained transition first region is designated as a first region; Remove the second mask layer and the fourth mask layer.
10. The method for manufacturing a semiconductor device according to claim 8, characterized in that, A first insulating portion is formed on the bottom surface of the trench, comprising: A first gate oxide layer is formed on the bottom surface and sidewalls of the trench; Remove the first gate oxide layer from the sidewall of the trench and use the first gate oxide layer on the bottom surface of the trench as the first insulating part; A separation gate layer is formed on the side of the first insulating portion away from the trench, comprising: A polycrystalline silicon layer is formed on the side of the first gate oxide layer away from the semiconductor body; A portion of the polysilicon layer is removed to form a separation gate layer; A second insulating portion is formed on the side of the separation gate layer away from the first insulating portion, including: A second gate oxide layer is formed on the side of the separation gate layer away from the first insulating portion; A portion of the second gate oxide layer is removed to form a second insulating portion.
11. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The semiconductor body includes: Provide a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.
12. A power module, characterized in that, The device includes a substrate and the semiconductor device according to any one of claims 1-7, wherein the substrate is used to support the semiconductor device.
13. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-7, wherein the semiconductor device is electrically connected to the circuit board.
14. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 13, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.