Junction transistor device
By integrating a drain-source diode structure into the VJFET device, the current and heat distribution are optimized, solving the problem that the VJFET device cannot conduct in reverse when the gate is turned off. This reduces the gate-drain capacitance, improves the device's reliability and heat dissipation, and reduces switching losses.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-08
- Publication Date
- 2026-04-10
AI Technical Summary
Existing VJFET devices cannot achieve reverse conduction when the gate is turned off, making them unsuitable for use in third-quadrant power converters, and they also exhibit high gate-drain capacitance and switching losses.
Integrating a drain-source diode structure in a VJFET device creates an ohmic contact by placing gate and source contact electrodes within the cell trench and using a high dielectric constant material to isolate the gate and source, thus optimizing current and heat distribution.
This enables reverse conduction of the VJFET when the gate is turned off, reduces the gate-drain capacitance, evens out current and heat distribution, improves device reliability and heat dissipation, and reduces switching losses.
Smart Images
Figure CN121843201A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power semiconductor devices, and more particularly to a junction transistor device. Background Technology
[0002] In current silicon carbide (SiC) vertical junction field-effect transistor (VJFET) devices, the structure of a conventional VJFET is as follows: Figure 1 As shown, gate electrodes are located on both sides of the channel region. The width of the depletion region of the channel is controlled by adjusting the gate voltage, thereby controlling the current between the drain and source. Conventional VJFETs conduct naturally at zero gate voltage and require a negative gate voltage to turn off. However, this structure mainly relies on the gate-drain diode to withstand the drain-source voltage, resulting in a high gate-drain capacitance and thus significant switching losses.
[0003] Meanwhile, when the VJFET gate is on, the conduction mechanism of a conventional VJFET is the same in both forward and reverse conduction, so its forward and reverse conduction losses can be considered the same. When the VJFET gate is off, since the device does not have a drain-source body diode structure, there is only a very small leakage current in both forward and reverse directions, which can be approximated as no current conduction. Therefore, in applications involving third-quadrant reverse conduction (such as inverter circuits), conventional VJFETs cannot achieve reverse conduction due to the lack of a body diode structure, thus failing to provide a freewheeling and commutation path for the circuit.
[0004] Therefore, a device is needed that can reverse conduct when the VJFET gate is turned off, so that the VJFET can be used in power converter topologies and applications that need to operate in the third quadrant.
[0005] Currently, the common VJFET device structures that can achieve reverse conduction when the gate is turned off include the following: Cascode JFET, Direct-Driven JFET, and the dual-channel JFET proposed by SiCED / Infineon.
[0006] However, the above structures have the following problems: Although the common-source cascode structure and the dual-gate direct-drive structure can achieve reverse conduction of the device when the low-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) in series is in the gate-off state, the VJFET used in them is still a conventional VJFET structure. Therefore, its gate-drain capacitance is still high, which will still cause large switching losses.
[0007] The dual-channel structure, with both vertical and lateral channels, results in a longer channel length, leading to greater channel resistance and consequently, greater on-resistance, which limits device performance improvement.
[0008] Therefore, there is a need for a device that can achieve reverse conduction when the VJFET gate is turned off, while having a low gate-drain capacitance, so that the VJFET can be used in power converter topologies and applications that require operation in the third quadrant, and at the same time have better device performance.
[0009] Existing application CN118280987A proposes a feasible method to achieve the above function by integrating an anti-parallel drain-source diode. However, this structure requires converting part of the gate trench cell into an anti-parallel drain-source diode cell. When the VJFET is reverse-biased, the current and heat distribution are concentrated in the anti-parallel drain-source diode cell, which can easily lead to overheating and failure. Summary of the Invention
[0010] The present invention aims to solve or alleviate the above-mentioned technical problems and provides a VJFET device that can achieve reverse conduction when the VJFET gate is turned off, making the VJFET suitable for power converter topologies and applications.
[0011] This invention provides a junction transistor device, comprising: The drain metal located below the device, The substrate located above the drain metal. The drift layer located above the substrate, Cellular grooves located on the upper surface of the drift layer, The source region is located on the upper surface of the semiconductor between adjacent cell trenches. The first source contact electrode is located above the source region. A dielectric layer located above the device and filling downwards into the cell trenches; The feature is that a gate contact electrode is provided at the bottom corner of the first inner side of the cell trench, and a gate region is provided at the bottom of the first outer side, the corner connected to the first outer side, and a portion thereof, which forms an ohmic contact with the gate contact electrode. The bottom corner of the second inner side of the cell trench is provided with a second source contact electrode, and the bottom of the second outer side, the corner connected to the second outer side, and part of the bottom are provided with a first source region that forms an ohmic contact with the second source contact electrode. The channel region is located between the gate region and the source region on the sidewall of an adjacent cell trench.
[0012] Furthermore, the first source contact electrode and the second source contact electrode are connected along the second inner sidewall to form an integrated source contact electrode.
[0013] Furthermore, the bottom end of the integrated source contact electrode extends horizontally at the bottom of the cell trench, with an extension width less than 70% of the length of the trench bottom and not exceeding the bottom width of the source region at the bottom.
[0014] Furthermore, the cell trench includes a shallow trench located above and a deep trench located below the shallow trench, with the opening of the deep trench located at the middle of the bottom of the shallow trench.
[0015] Furthermore, the source region extends downward and inward along the second outer side of the deep trench to the bottom of the deep trench.
[0016] Furthermore, the opening of the deep trench is widened towards the second inner wall of the deep trench and coincides with the second inner wall, and the second source contact electrode is located at the bottom corner of the deep trench.
[0017] Compared with the prior art, the device has a lower gate-drain capacitance. The present invention integrates a drain-source diode structure in a single trench, which makes the current distribution and heat distribution more uniform when the device operates in the third quadrant, thereby enhancing heat dissipation, reducing device failure caused by heat generation, and thus improving the reliability of the device. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the cell trench structure of a portion of an existing vertical junction field-effect transistor (VJFET).
[0019] Figure 2 This is a schematic diagram of the cell trench structure of the integrated anti-parallel drain-source diode in the existing patent CN118280987A.
[0020] Figure 3 This is a cross-sectional schematic diagram of a portion of the cell trenches in the first embodiment of the present invention.
[0021] Figure 4 This is a cross-sectional schematic diagram of a portion of the cell trenches in the second embodiment of the present invention.
[0022] Figure 5 This is a cross-sectional schematic diagram of a portion of the cell trenches in the third embodiment of the present invention.
[0023] Figure 6 This is a cross-sectional schematic diagram of a portion of the cell trench in the fourth embodiment of the present invention.
[0024] Figure 7 This is a cross-sectional schematic diagram of a portion of the cell trench in the fifth embodiment of the present invention. Detailed Implementation
[0025] To facilitate understanding of the present invention, the present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments.
[0026] It should be noted that the devices in the accompanying drawings are not necessarily drawn to scale. The straight lines showing the boundaries of the doped regions and trenches in the drawings, as well as the sharp corners formed by these boundaries, are generally not straight lines or precise angles in practical applications.
[0027] It should be noted that the positional terms used in this document, such as "up," "down," "left," "right," "front," "back," "vertical," "horizontal," and "vertical," correspond to the relative positions shown in the reference illustrations. In practice, there is no fixed orientation. The terms "up," "down," "left," "right," "inner," "outer," and similar expressions used in this specification are for illustrative purposes only.
[0028] It should be noted that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and a second component may be referred to as a first component.
[0029] It should be noted that when a component is described as "connected" to another component, it may be directly connected to the other component, or there may be one or more intervening components.
[0030] The layers and / or regions described in this specification are characterized as having an conductivity type such as n-type or p-type, which refers to multiple carrier types in the layer and / or region. n-type materials include a balanced excess of electrons, while p-type materials include a balanced excess of holes. Some materials may be indicated with "+" or "-" (e.g., n+, n-, p+, p-) to indicate a relatively large (+) or small (-) carrier concentration compared to another layer or region; this notation does not represent a specific carrier concentration.
[0031] The term “and / or” as used in this specification includes any and all combinations of one or more of the associated listed items.
[0032] Unless otherwise specified, the N-type semiconductor layer described in this specification may be replaced with a P-type semiconductor layer, and vice versa.
[0033] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.
[0034] Example 1 like Figure 3 As shown, one embodiment of the VJFET device of the present invention includes: The drain metal 101 is located at the bottom. An N+ type substrate 102 is located above the drain metal 101; An N-type drift layer 103 is located above the N+ type substrate 102; Cellular grooves 110 located on the upper surface of the N-type drift layer 103; The N+ type source region 104 is located on the upper surface of the semiconductor between the cell trenches 110; The first source contact electrode 105a is located above the N+ type source region 104; Gate contact electrode 107 located at the bottom corner of the first inner side of the cell trench 110; The second source contact electrode 105b is located at the bottom corner of the second inner side of the cell trench 110; P+ type gate region 117 located at the bottom of the first outer side and part of the cell trench 110; The P+ type source region 115 is located at the bottom of the second outer side and part of the cell trench 110.
[0035] The gate contact electrode 107 and the second source contact electrode 105b are electrically isolated by a dielectric layer 109.
[0036] The P+ type gate region 117 and P+ type source region 115 extend downward from the lower surface of the N+ type source region 104 along the outer wall of the cell trench 110 to the bottom of the cell trench 110, and surround the trench corner. The P+ type gate region 117 and P+ type source region 115 are not connected at the bottom of the cell trench 110 and are spaced apart from each other by a gap 202.
[0037] The channel region 108 is located between the P+ type gate region 117 and the P+ type source region 115 on the sidewall of the adjacent cell trench 110.
[0038] The contact between the first source contact electrode 105a and the N+ type source region 104 is an ohmic contact.
[0039] The contact between the gate contact electrode 107 and the P+ type gate region 117 is an ohmic contact.
[0040] The contact between the second source contact electrode 105b and the P+ type source region 115 is an ohmic contact.
[0041] The doping concentration of the N+ type substrate 102, N+ type source region 104, P+ type gate region 117, and P+ type source region 115 is 1e17cm. -3 up to 1e21cm -3 .
[0042] The doping concentration of the N-type drift layer 103 is 1e14cm. -3up to 1e17cm -3 .
[0043] It should be noted that the doping concentration described above is merely an illustrative example, and the specific doping concentration can be flexibly adjusted according to the actual application scenario, device parameters, and process technology. Furthermore, the actual doping concentration is not necessarily uniform doping, and different concentration variations and distributions are permissible due to design requirements or process limitations.
[0044] It should be noted that although each diagram shows only a few trenches, it should be understood that the structure shown can be repeated multiple times in actual semiconductor devices.
[0045] Typically, the gate contact electrode 107, the first source contact electrode 105a, and the second source contact electrode 105b are formed of contact metal. The contact metal may be a metal including platinum (Pt), titanium (Ti), nickel (Ni), aluminum (Al), titanium nitride (TiN), tantalum (Ta), tungsten (W), etc., or it may be a semiconductor such as polycrystalline silicon or polycrystalline silicon carbide.
[0046] Typically, the dielectric layer 109 is an insulating material, such as silicon nitride (SiN), fluoride, borosilicate glass (BPSG), oxide, or a combination thereof. In some embodiments, the dielectric layer 109 may be a high dielectric constant material.
[0047] Typically, the drain metal 101 may be made of metals such as titanium (Ti), nickel (Ni), aluminum (Al), gold (Au), titanium nitride (TiN), palladium (Pd), and tungsten (W).
[0048] Example 2 In some embodiments, based on Embodiment 1, the first source contact electrode 105a extends downward along the second inner sidewall of the cell trench 110 to the bottom of the cell trench 110, and is connected together with the bottom second source contact electrode 105b to form an integrated source contact electrode 105. The integrated source contact electrode 105 is connected to the P+ type source region 115, as shown below. Figure 4 As shown.
[0049] When the above-mentioned device operates in the third quadrant, it can avoid connecting to the source at the chip edge and increase the contact area between the source and the metal. This helps to reduce contact resistance, reduce forward voltage drop, enhance heat dissipation, and thus improve the reliability of the device in the event of thermal failure.
[0050] Example 3 In some embodiments, based on Embodiment 2, the integrated source contact electrode 105 extends horizontally from the bottom of the cell trench 110 towards the middle of the bottom of the cell trench 110, and the extension width is less than 70% of the bottom length of the cell trench 110. Simultaneously, the extension width does not exceed the width of the P+ type source region 115 at the bottom of the cell trench 110, such as... Figure 5 As shown.
[0051] When the above-mentioned device operates in the third quadrant, it can increase the current path width of the P+ type source region 115 at the bottom of the cell trench 110, which can further increase the contact area of the source contact metal. Therefore, it is beneficial to reduce the contact resistance, reduce the forward conduction voltage drop, enhance the heat dissipation capacity, and thus improve the reliability of the device in the event of thermal failure.
[0052] Example 4 In some embodiments, based on Embodiment 1, the cell trench 110 may be formed by a combination of an upper shallow trench 110a and a lower deep trench 110b, wherein the opening of the deep trench 110b is located at the middle of the bottom of the shallow trench 110a. The P+ type source region 115 only surrounds the corner of the shallow trench 110a and does not extend downward to surround the deep trench 110b, as shown below. Figure 6 As shown.
[0053] This structure replaces the spacer 202 with a deep trench 110b. Previously, the source and gate were separated by the same material as the spacer 202, namely the N-type drift layer 103; now, the source and gate are separated by a dielectric layer 109. The dielectric layer 109 can be made of a high-dielectric-constant material, thus achieving the same gate-source breakdown voltage with a narrower spacing. This can help reduce cell size, thereby increasing device power density, or, at the same power, reducing chip size and cost. This structure can further reduce gate-drain capacitance, accelerate switching speed, and simultaneously shorten channel length, thereby reducing channel resistance. When operating in the third quadrant, the device can further increase the source contact area, thus helping to reduce contact resistance, lower forward voltage drop, enhance heat dissipation, and ultimately improve the device's reliability against thermal failure.
[0054] Example 5 In some embodiments, based on Embodiment 4, the opening of the deep trench 110b is located at the bottom of the second outer side of the shallow trench 110a, such as... Figure 7 As shown.
[0055] This structure increases the depth of the second source contact electrode 105b and the spacing between the gate and source electrodes, thus improving the gate-source breakdown voltage, enhancing device reliability, and reducing gate-source capacitance. Simultaneously, this structure removes the limitation of the spacing 202 between the gate and source electrodes, facilitating further reduction of cell size, increasing device power density, or reducing chip size and cost at the same power.
[0056] It should be noted that the source electrode shown in the schematic diagram is located on the second side of the cell trench 110 only as an example and does not limit the position of the source electrode. The relative positions of the source electrode and other electrodes on the first and second sides of the cell trench 110 can be interchanged. For example, in another embodiment, the second source electrode contact electrode 105b can be disposed on the first side of the cell trench 110, and the corresponding P+ type source region 115 is also formed on the first side of the cell trench 110.
[0057] Those skilled in the art should understand that the structural features and process details mentioned in the above embodiments can be combined to form more embodiment device structures and manufacturing processes.
[0058] It should be noted that the relevant process steps in the above embodiments can be appropriately increased or decreased to achieve the same effect. Those skilled in the art should recognize that the embodiments of the present invention described above are not limiting but exemplary, and the present invention can be implemented in a wider range than the above embodiments.
Claims
1. A junction transistor device, comprising: The drain metal located below the device, The substrate located above the drain metal. The drift layer located above the substrate, Cellular grooves located on the upper surface of the drift layer, The source region is located on the upper surface of the semiconductor between adjacent cell trenches. The first source contact electrode is located above the source region. A dielectric layer located above the device and filling downwards into the cell trenches; Its features are, The bottom corner of the first inner side of the cell trench is provided with a gate contact electrode, and the bottom of the first outer side, the corner connected to the first outer side, and part of the bottom are provided with a gate region that forms an ohmic contact with the gate contact electrode. The bottom corner of the second inner side of the cell trench is provided with a second source contact electrode, and the bottom of the second outer side, the corner connected to the second outer side, and part of the bottom are provided with a first source region that forms an ohmic contact with the second source contact electrode. The channel region is located between the gate region and the source region on the sidewall of an adjacent cell trench.
2. A junction transistor device as described in claim 1, characterized in that, The first source contact electrode and the second source contact electrode are connected along the second inner sidewall to form an integrated source contact electrode.
3. A junction transistor device as described in claim 2, characterized in that, The bottom end of the integrated source contact electrode extends horizontally at the bottom of the cell trench, with an extension width less than 70% of the length of the trench bottom and not exceeding the bottom width of the source region at the bottom.
4. A junction transistor device as described in any one of claims 1-3, characterized in that, Cellular trenches include a shallow trench located above and a deep trench located below the shallow trench, with the opening of the deep trench located at the middle of the bottom of the shallow trench.
5. A junction transistor device as described in claim 4, characterized in that, The source region extends downward and inward along the second outer side of the deep trench to the bottom of the deep trench.
6. A junction transistor device as described in claim 4, characterized in that, The opening of the deep trench is widened towards the second inner wall of the deep trench and coincides with the second inner wall. The second source contact electrode is located at the bottom corner of the deep trench.