Method for forming semiconductor device

Abstract

A method of forming a semiconductor device is provided. The method includes forming a stack on a substrate. The stack includes a plurality of semiconductor portions separated from each other by gaps. Next, the gap is filled with a dielectric oxide material. The end portion of the deposited dielectric oxide material is then laterally etched with an etching gas composition to form a lateral opening. The etching gas component includes a halogen-containing compound, ammonia, and an amine. After an inner spacer is formed in the lateral opening between adjacent semiconductor portions of the plurality of semiconductor portions, a remaining portion of the dielectric oxide material deposited in the gap is removed. A gate stack is then formed in the gap to surround a channel region of the stack.

Description

Technical Field

[0001] This disclosure relates to a method for forming a semiconductor device. Background Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have led to the production of several generations of ICs, each featuring smaller and more complex circuits than the previous generation. In the evolution of ICs, while geometric dimensions (i.e., the smallest element (or outline) that can be produced by a process) have decreased, functional density (i.e., the number of interconnects per unit wafer area) has generally increased. This scaling-up process typically benefits by increasing production efficiency and reducing associated costs. However, the reduction in size also increases the complexity of integrated circuit fabrication and manufacturing. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method for forming a semiconductor device includes the following operations: Forming a stack above a substrate, the stack including multiple semiconductor portions spaced apart from each other by multiple gaps. Filling the gaps with a dielectric oxide material. Laterally etching multiple end portions of the deposited dielectric oxide material using an etching gas composition including a halogen-containing compound, ammonia, and amine to form multiple lateral openings. Forming multiple inner spacers in the lateral openings between adjacent semiconductor portions. Removing multiple remaining portions of the dielectric oxide material deposited in the gaps. Forming a gate stack in the gaps to surround a channel region of the stack.

[0004] According to some embodiments of this disclosure, a method for forming a semiconductor device includes the following operations: Forming a fin structure over a substrate, the fin structure including a plurality of alternately stacked first semiconductor portions and a plurality of second semiconductor portions. Forming a dummy gate structure, the dummy gate structure including a dummy gate stack and a plurality of gate spacers located on a plurality of sidewalls of the dummy gate stack, the dummy gate stack spanning a channel region of the fin structure. Removing a plurality of portions of the fin structure not covered by the dummy gate structure to form a plurality of source / drain trenches. Selectively removing the first semiconductor portions to release the second semiconductor portions in the channel region. Forming a plurality of sacrificial oxide portions to fill a plurality of gaps located between the second semiconductor portions. Laterally recessing a plurality of end portions of the sacrificial oxide portions to form a plurality of lateral openings, wherein the lateral recessing is performed using an etching gas composition including a halogen-containing compound, ammonia, and amine. Forming a plurality of inner spacers in the lateral openings. Forming a plurality of source / drain features in the source / drain trenches. Removing the dummy gate stack to form gate trenches exposing a plurality of sidewalls of the second semiconductor portions and the sacrificial oxide portions. Removing the sacrificial oxide portions located in the gaps. A gate stack is formed to surround the second semiconductor portion, wherein the gate stack fills the gap.

[0005] According to some embodiments of this disclosure, a method for forming a semiconductor device includes the following operations: Forming a first stack and a second stack over a substrate, the first stack including a plurality of first semiconductor portions having a first width and spaced apart from each other by a plurality of first gaps, the second stack including a plurality of second semiconductor portions having a second width and spaced apart from each other by a plurality of second gaps, wherein the first width is smaller than the second width. Filling the first gaps and the second gaps with a dielectric oxide material. Forming a plurality of lateral openings by performing a plurality of cycles of lateral etching of a plurality of end portions of the deposited dielectric oxide material, the cycles including: exposing the deposited dielectric oxide material to an etching gas composition to modify a plurality of surfaces of the plurality of end portions of the deposited dielectric oxide material, the etching gas composition including a halogen-containing compound, ammonia, and an amine; and removing the modified surfaces of the deposited dielectric oxide material by heat treatment. Depositing dielectric material in the lateral openings to form a plurality of inner spacers, the inner spacers being located between adjacent first semiconductor portions of the first semiconductor portions and adjacent second semiconductor portions of the second semiconductor portions. Removing a plurality of remaining portions of the dielectric oxide material in the first gaps and the second gaps. Gates are stacked in the first gap and the second gap to surround the channel region of each of the first stack and the second stack. Attached Figure Description

[0006] The various embodiments disclosed herein can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a flowchart of a method for manufacturing a gate-all-around (GAA) device according to various embodiments of the present disclosure;

[0008] Figures 2 to 14 Various embodiments based on this disclosure are permitted. Figure 1 A cross-sectional view of the GAA device during the manufacturing process of the method;

[0009] Figure 15A and Figure 15B These are fin structures of different widths according to various embodiments of the present disclosure;

[0010] Figures 16A to 16C This is the etched outline of the sacrificial oxide portion according to various embodiments of this disclosure.

[0011] [Symbol Explanation]

[0012] 100: Method

[0013] 102: Operation

[0014] 104: Operation

[0015] 106: Operation

[0016] 108: Operation

[0017] 110: Operation

[0018] 112: Operation

[0019] 114: Operation

[0020] 116: Operation

[0021] 118: Operation

[0022] 120: Operation

[0023] 122: Operation

[0024] 124: Operation

[0025] 126: Operation

[0026] 200:GAA device

[0027] 202:Substrate

[0028] 204: Stacking

[0029] 206: Sacrificial Semiconductor Layer

[0030] 206P: Sacrificial Semiconductor Section

[0031] 208: Channel semiconductor layer

[0032] 208P: Channel Semiconductor Section

[0033] 210: Fin structure

[0034] 210B: Base portion

[0035] 210S: Fin stacking section

[0036] 212A: Fin structure

[0037] 212B: Fin structure

[0038] 216: Isolation Features

[0039] 220: Virtual gate structure

[0040] 222: Virtual gate dielectric

[0041] 224: Virtual gate electrode

[0042] 226: Gate spacer

[0043] 228: Source / Drain Trench

[0044] 230: Gap

[0045] 232P: Sacrificial oxide portion

[0046] 234: Horizontal opening

[0047] 240: Internal spacer

[0048] 250: Source / Drain Characteristics

[0049] 252: ILD layer

[0050] 254: Gate Trench

[0051] 256: Gap

[0052] 262: Channel Nanostructures

[0053] 270: Gate Stack

[0054] 272: Interface Layer

[0055] 274: Gate dielectric layer

[0056] 276: Work Function Layer

[0057] 278: Gate electrode layer

[0058] D1: Dimensions

[0059] D2: Lateral etching distance

[0060] D3: Lateral etching distance

[0061] L: Length

[0062] S1: Spacing

[0063] S2: Spacing

[0064] T1: Thickness

[0065] W1: Width

[0066] W2: Width

[0067] X: Direction

[0068] Y: direction

[0069] Z: Direction Detailed Implementation

[0070] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the implementation of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, embodiments of this disclosure may repeat element symbols or letters in various instances. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0071] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0072] Multi-gate devices, such as gate-all-around (GAA) transistors, have been introduced to improve gate control by increasing gate-channel coupling, minimizing off-state current, and mitigating the short-channel effect (SCE). The formation of a GAA transistor involves forming a stack comprising multiple channel layers interleaved with multiple sacrificial layers, wherein the sacrificial layers can be selectively removed to release the channel layers as channel nanosheets. A metal gate structure comprising multiple dielectric and conductive layers is then formed to encapsulate each channel nanosheet. The composition of the sacrificial layers is selected to ensure selective removal of the sacrificial layers without causing substantial damage to the channel layers. In the prior art, it is desirable for each channel nanosheet to have uniform dimensions along the gate length direction to ensure uniform gate control on each channel nanosheet.

[0073] Because the metal gates are interleaved between the channel nanosheets in a GAA transistor, internal spacers are placed between the sidewalls of the metal gates and portions of the epitaxial source / drain features adjacent to the metal gates to reduce capacitance and prevent leakage between the metal gates and the source / drain features. However, while internal spacers generally offer the advantage of reducing GAA transistor capacitance, their use introduces gate length variations and manufacturing difficulties for replacement metal gats (RMGs). For example, the gate lengths on the top and bottom surfaces of the channel nanosheets are determined by the respective dimensions of the top and bottom internal spacers. Therefore, the uniformity of the critical dimensions (CD) of the internal spacers from bottom to top affects device and yield performance. However, in the prior art, the lateral etching processes used to form internal spacers in stacked channel nanosheet structures often result in non-uniform critical dimensions for the internal spacers, whether within the same stack from top to bottom or between stacks with different channel widths.

[0074] Several embodiments disclosed herein provide methods for forming internal spacers with uniform critical dimension (CD) by controlling the etch rate from top to bottom within a single stack and between different stacks. This ensures that the gate lengths of all nanosheet channel surfaces in a GAA transistor are consistent, regardless of whether they have the same or different channel widths.

[0075] The GAA transistors described below can be patterned using any suitable method. For example, the structure can be patterned using one or more lithography processes, including dual or multiple patterning processes. Generally, dual or multiple patterning processes combine lithography and self-alignment processes to create patterns with smaller spacing than those obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor.

[0076] Figure 1 This is a flowchart of a method 100 for forming a GAA device 200 according to certain embodiments of the present disclosure. Figures 2 to 14 This is a cross-sectional view of the GAA device 200 at various stages of method 100 according to some embodiments. The following is in conjunction with... Figures 2 to 14Some embodiments of method 100 are described with reference to GAA device 200. Method 100 is merely an example and is not intended to limit the scope of the various embodiments disclosed herein beyond what is expressly stated in the claims. Additional operations may be provided before, during, and after method 100, and some of the described operations may be replaced, eliminated, or moved for additional embodiments of this method.

[0077] refer to Figure 1 and Figure 2 Method 100 includes operation 102, wherein an initial structure of GAA device 200 is provided. The initial structure includes a substrate 202 and a stack 204 of alternating epitaxial semiconductor layers above the substrate 202. Figure 2 This is a cross-sectional view of the GAA device 200 after alternating epitaxial semiconductor layer stacks 204 are formed on the substrate 202.

[0078] Substrate 202 can be any suitable substrate and can be processed to have various features. In some embodiments, substrate 202 can be a semiconductor substrate, such as a silicon substrate. In some embodiments, substrate 202 includes various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 202 can include various doping configurations. For example, different doping distributions (e.g., n-well, p-well) can be formed on substrate 202 in regions designed for different device types (e.g., n-type FET, p-type FET). Suitable doping can include ion implantation and / or diffusion processes of dopants. Substrate 202 typically has isolation features (e.g., shallow trench isolation (STI) features) inserted to provide regions for different device types. Substrate 202 includes other semiconductors, such as germanium or diamond. Optionally, substrate 202 includes compound semiconductors such as silicon carbide (SiC), gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, etc.; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP; and / or other suitable materials. In addition, the substrate 202 may optionally include an epitaxial layer, which may be strained to enhance performance, may include a silicon-on-insulator structure, and / or have other suitable enhancing features.

[0079] A stack 204 of alternating epitaxial semiconductor layers is fully deposited on a substrate 202. The stack 204 includes alternating sacrificial semiconductor layers 206 and channel semiconductor layers 208, wherein each channel semiconductor layer 208 is disposed between sacrificial semiconductor layers 206. In some embodiments, the sacrificial semiconductor layer 206 comprises a first semiconductor material, while the channel semiconductor layer 208 comprises a second semiconductor material different from the first semiconductor material. The materials of the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 can be selected to provide different etch selectivity. For example, in some embodiments, the first semiconductor material may comprise germanium (Ge) or silicon germanium (SiGe), while the second semiconductor material may comprise silicon (Si). In some embodiments, the germanium content in the first semiconductor material may be between about 15 wt% and about 40 wt%. In some alternative embodiments, the first semiconductor material comprises SiGe having a first Ge content, and the second semiconductor material comprises SiGe having a second Ge content lower than the first Ge content. In various embodiments, the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are substantially dopant-free (i.e., having less than about 1 × 10⁻⁶ dopants). 17 cm -3 (the concentration of intrinsic dopants).

[0080] In some embodiments, the sacrificial semiconductor layer 206 may be removed in a subsequent process, thereby leaving the channel nanostructure defining the GAA device 200 (e.g., Figure 13 The channel semiconductor layer 208 (262) is therefore the thickness of the sacrificial semiconductor layer 206, which determines the thickness of the adjacent channel nanostructures (e.g., Figure 12 The spacing between (262) is as follows. In some embodiments, the thickness of the sacrificial semiconductor layer 206 can be from about 8 nm to about 15 nm. The thickness of the channel semiconductor layer 208 is selected based on, for example, manufacturing considerations, transistor performance considerations, etc. In some embodiments, the thickness of the channel semiconductor layer 208 can be from about 4 nm to about 10 nm.

[0081] The number of sacrificial semiconductor layer 206 and channel semiconductor layer 208 depends on the channel nanostructure required in GAA device 200 (e.g., Figure 12 The number of channel semiconductor layers 208 is, for example, 2 to 10, to form a stack of 2 to 10 vertically separated channel nanostructures. In some embodiments, such as Figure 2 As shown, stack 204 includes four (4) sacrificial semiconductor layers 206 and four (4) channel semiconductor layers 208. However, it is understood that any number of sacrificial semiconductor layers 206 and channel semiconductor layers 208 can be formed in stack 204.

[0082] The sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are epitaxially grown layer by layer from the top surface of the substrate 202. In some embodiments, the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes such as metal-organic CVD (MOCVD), or other suitable epitaxial growth processes. The epitaxial growth results in the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 having the same crystal orientation as the substrate 202.

[0083] refer to Figure 1 and Figure 3 According to some embodiments, method 100 proceeds to operation 104, wherein at least one fin structure 210 is formed by stacking 204. Figure 3 This is a cross-sectional view of the GAA device 200 after at least one fin structure 210 has been formed.

[0084] In some embodiments, a portion of the stack 204 and the substrate 202 is patterned to form at least one fin junction 210. Each fin structure 210 extends perpendicularly from the substrate 202 along the Z direction and has a length dimension along the X direction and a width dimension along the Y direction. The width of each fin structure 210 ranges from approximately 1 nm to approximately 150 nm.

[0085] In some embodiments, operation 104 forms a plurality of fin structures, each fin structure having substantially the same width. For example, Figure 15A The fin structures 212A and 212B shown are formed to have the same width, denoted as W1. In other embodiments, at least two of the plurality of fin structures have different widths. Figure 15B As shown, the width W1 of fin structure 212A is smaller than the width W2 of fin structure 212B. The width W1 can be from about 3 nm to about 80 nm, while the width W2 can be from about 20 nm to about 150 nm.

[0086] The fin structures 212A and 212B are spaced apart by a distance S1. In some embodiments, the distance S1 ranges from about 5 nm to about 400 nm.

[0087] The fin structure 210 may include a substrate portion 210B and a fin stack portion 210S. The substrate portion 210B is formed by a substrate 202, while the fin stack portion 210S is formed by a stack 204 and includes a portion of a sacrificial semiconductor layer 206 (referred to herein as sacrificial semiconductor portion 206P) and a portion of a channel semiconductor layer 208 (referred to herein as channel semiconductor portion 208P).

[0088] In some embodiments, lithography and etching processes may be used to form the fin structure 210. During the lithography process, a hard mask layer (not shown) may first be formed above the top surface of the stack 204. In some embodiments, the hard mask layer comprises a dielectric material, such as silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbide nitride (SiOCN), or a combination thereof. In some embodiments, the hard mask layer is formed using chemical CVD, plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes. In some embodiments, the hard mask layer may have a bilayer structure, comprising a pad oxide layer and a pad nitride layer formed above the pad oxide layer. In some embodiments, the pad oxide layer comprises silicon oxide, which may be formed by thermal oxidation. The pad nitride layer comprises SiN, which may be formed by CVD, PECVD, PVD, ALD, or other suitable deposition processes.

[0089] Subsequently, a photoresist layer is applied to a hard mask layer, for example, by spin coating. The photoresist layer is then exposed to the mask according to a pattern and developed to form a pattern within the photoresist layer. The patterned photoresist layer can be used as an etching mask to pattern other layers. In some embodiments, the photoresist layer is patterned using extreme ultraviolet (EUV) lithography. The patterned photoresist layer is then used to protect areas of substrate 202 and the sacrificial semiconductor layer 206 and channel semiconductor layer 208 formed thereon, while an etching process forms the fin structure 210. In some embodiments, the etching process can be a dry etching process (e.g., plasma etching or reactive ion etching (RIE)), a wet etching process, or a combination thereof.

[0090] In various other embodiments, suitable processes, including dual-patterning or multi-patterning processes, can be used to form the fin structure 210. Generally, dual-patterning or multi-patterning processes combine lithography and self-alignment processes to create patterns with smaller spacing than those obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Using a self-alignment process, mandrels are formed alongside the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining mandrels are used as an etch mask to pattern the stack 204 and the substrate 202 to provide the fin structure 210.

[0091] Subsequently, an isolation feature 216 can be formed near and around the base 210B of the fin structure 210. The isolation feature 216 is disposed between the fin structures 212A and 212B, such as... Figure 15A and Figure 15B As shown. Isolation feature 216 can also be referred to as shallow trench isolation (STI) feature. In the exemplary process, a dielectric layer is first deposited over substrate 202, and the trench between fin structures 212A and 212B is filled with dielectric material. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric layer, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited using CVD processes, subatmospheric CVD (SACVD) processes, flowable CVD processes, atomic layer deposition (ALD) processes, physical vapor deposition (PVD) processes, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed using dry etching, wet etching, and / or combinations thereof to form isolation feature 216. In some embodiments, the top surface of isolation feature 216 is substantially coplanar with or below the bottom surface of the bottommost sacrificial semiconductor portion 206P.

[0092] Next, if the hard masking layer was not removed during the formation of the isolation feature 216, it is removed from the topmost surface of the fin structure 210. An anisotropic etching process can be used to remove the hard masking layer. The etching process can be a dry etching process (e.g., RIE), a wet etching process, or a combination of both.

[0093] refer to Figure 1 and Figure 4 According to some embodiments, method 100 proceeds to operation 106, wherein a virtual gate structure 220 is formed over fin structure 210. Figure 4 This is a cross-sectional view of the GAA device 200 after the virtual gate structure 220 is formed. The virtual gate structure 220 is formed on the fin structure 210, along the sidewalls and top surface of the fin structure 210.

[0094] The dummy gate structure 220 includes dummy gate stacks (222, 224) and gate spacers 226. According to several embodiments of this disclosure, the dummy gate stacks (222, 224) are replaced by metal gate stacks.

[0095] In some embodiments, the virtual gate stack (222, 224) includes a virtual gate dielectric 222 and a virtual gate electrode 224 on the virtual gate dielectric 222. In some embodiments, the virtual gate stack (222, 224) may further include a virtual gate cap (not shown) located on top of the virtual gate electrode 224.

[0096] In some embodiments, the virtual gate dielectric 222 may be made of silicon oxide, silicon nitride, or silicon oxynitride. The virtual gate electrode 224 may be made of silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the virtual gate stack (222, 224) may be formed by first conformally depositing a virtual gate dielectric layer over the fin structure 210 and the isolation feature 216. Then, a virtual gate electrode layer is deposited over the virtual gate dielectric layer such that the fin structure 210 is fully embedded in the virtual gate electrode layer. In some embodiments, the thickness of the virtual gate dielectric layer may range from about 1 nm to about 5 nm. In some embodiments, the thickness of the virtual gate electrode layer may range from about 100 nm to about 200 nm. In some embodiments, the virtual gate electrode layer is planarized, for example, by CMP. The virtual gate dielectric layer and the virtual gate electrode layer may be deposited using CVD, PECVD, PVD, ALD, or other suitable deposition processes. Subsequently, the virtual gate dielectric layer and the virtual gate electrode layer are patterned using lithography and etching processes. For example, a photoresist layer (not shown) is applied over the dummy gate electrode layer and patterned by photolithography exposure and development. The pattern in the photoresist layer is sequentially transferred to the dummy gate electrode layer and the dummy gate dielectric layer by at least one anisotropic etching process, thereby forming a dummy gate stack (222, 224), which includes the remaining portions of the dummy gate dielectric layer and the dummy gate electrode layer. The anisotropic etching process can be a dry etching process, such as RIE, a wet etching process, or a combination thereof. If not completely consumed, the remaining photoresist layer after forming the dummy gate stack (222, 224) is removed by, for example, ashing.

[0097] Gate spacers 226 are disposed on the sidewalls of the dummy gate stacks (222, 224). In some embodiments, gate spacers 226 may comprise a dielectric material, such as an oxide, nitride, oxynitride, or a combination thereof. In some embodiments, gate spacers 226 are made of silicon nitride. In some embodiments, gate spacers 226 may be formed by first depositing a conformal gate spacer material layer on the exposed surfaces of the dummy gate stacks (222, 224), the fin structure 210, and the isolation feature 216, and then etching the gate spacer material layer to remove horizontal portions of the gate spacer material layer. In some embodiments, the gate spacer material layer may be deposited, for example, by CVD, PECVD, or ALD. In some embodiments, the gate spacer material layer may be etched by dry etching (e.g., plasma etching or RIE). Vertical portions of the gate spacer material layer on the sidewalls of the dummy gate stacks (222, 224) constitute gate spacers 226.

[0098] refer to Figure 1 and Figure 5 According to some embodiments, method 100 proceeds to operation 108, wherein a source / drain trench 228 is formed in the fin structure 210. Figure 5 This is a cross-sectional view of the GAA device 200 after the source / drain trench 228 is formed.

[0099] In some embodiments, a virtual gate structure 220 is used as an etching mask to etch portions of the fin structure 210 in the source / drain regions to form source / drain trenches 228. Etching can be performed using a dry etching process (e.g., plasma etching or RIE). Exemplary dry etching processes may employ oxygen-containing gases, hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases (e.g., CF3I), other suitable gases, and / or combinations thereof. Alternatively, etching can be performed using a wet etching process that uses an etchant such as ammonium hydroxide, a mixture of hydrogen peroxide and water (APM), tetramethylammonium hydroxide (TMAH), or ammonium hydroxide (NH4OH). After etching, the sidewalls of the channel semiconductor portion 208P and the sacrificial semiconductor portion 206P are exposed in the source / drain trench 228. In some embodiments, the substrate 202 may also be partially etched. Therefore, the bottom surface of the source / drain trench 228 can be flush with the top surface of the substrate portion 210B (e.g., Figure 5 (as shown) or the top surface below the base portion 210B (not shown).

[0100] refer to Figure 1 and Figure 6 According to some embodiments, method 100 continues to operation 110, in which the sacrificial semiconductor portion 206P is removed. Figure 6 This is a cross-sectional view of the GAA device 200 after the sacrificial semiconductor portion 206P has been removed.

[0101] Selectively removing the sacrificial semiconductor portion 206P releases the channel semiconductor portion 208P, thereby forming a gap 230 between adjacent channel semiconductor portions 208P and between the bottommost channel semiconductor portion 208P and the substrate portion 210B in the fin structure 210.

[0102] In some embodiments, the sacrificial semiconductor portion 206P can be removed by a selective etching process, wherein the etchant is selective for the material of the sacrificial semiconductor portion 206P, such that the sacrificial semiconductor portion 206P is removed without substantially eroding the channel semiconductor portion 208P. In some embodiments, the etching process is an isotropic etching process, which may be a dry etching process or a wet etching process. In some embodiments, the selective etching process may include oxidizing the sacrificial semiconductor portion 206P using a suitable oxidant (e.g., ozone). Thereafter, the oxidized sacrificial semiconductor portion 206P can be selectively removed. In some embodiments, when the channel semiconductor portion 208P comprises Si and the sacrificial semiconductor portion 206P comprises SiGe, the sacrificial semiconductor portion 206P can be selectively removed by applying HCl gas at a temperature of about 500°C to about 700°C, or by applying a mixed gas of CF4, SF6, and CHF3.

[0103] refer to Figure 1 and Figure 7 According to some embodiments, method 100 continues to operation 112, wherein a sacrificial oxide portion 232P is formed to fill gap 230. Figure 7 This is a cross-sectional view of the GAA device 200 after the sacrificial oxide portion 232P is formed to fill the gap 230.

[0104] A sacrificial oxide layer is conformally deposited on the channel semiconductor portion 208P, the substrate portion 210B, and the dummy gate structure 220 to fill the gap 230 (i.e., the space between adjacent channel semiconductor portions 208P). In some embodiments, the sacrificial oxide layer comprises a dielectric oxide, such as silicon oxide, silicon dioxide, or silicon-rich oxynitride. The sacrificial oxide layer can be formed by a conformal deposition process (e.g., CVD or ALD). In some embodiments, the thickness of the sacrificial oxide layer is controlled such that the sacrificial dielectric layer is offset from the gap 230. In some embodiments, the sacrificial dielectric layer completely fills the gap 230.

[0105] Next, an etching process (e.g., an anisotropic etching process) is performed to remove a portion of the sacrificial oxide layer located outside the gap 230 from the structure. In some embodiments, wet etching or dilute hydrofluoric acid (dHF) cleaning is performed. The remaining portion of the sacrificial oxide layer in the gap 230 forms the sacrificial oxide portion 232P. In some embodiments, the sidewalls of the end portion of the sacrificial oxide portion 232P are aligned with the sidewalls of the end portion of the channel semiconductor portion 208P.

[0106] refer to Figure 1 and Figure 8 According to some embodiments, method 100 continues to operation 114, wherein the sacrificial oxide portion 232P is recessed to form a lateral opening 234. Figure 8 This is a cross-sectional view of the GAA device 200 after the sacrificial oxide portion 232P is recessed to form a transverse opening 234.

[0107] The end portions of the exposed sacrificial oxide portions 232P in the source / drain trench 228 are selectively laterally recessed to form lateral openings 234, while the exposed channel semiconductor portions 208P are substantially unetched. In some embodiments, the amount of etched sacrificial oxide portions 232P is precisely controlled to maintain sufficient channel length for the metal gate stack formed in subsequent processing steps. This ensures high conductivity while maintaining good yield. In some embodiments, the lateral etch distance is no greater than the width of the gate spacer 226. In some embodiments, after the selective recess in operation 114, the dimension D1 of each lateral opening 234 in the X direction is approximately 4 nm to approximately 8 nm, such that the inner spacer (240, as shown) to be formed... Figure 9 (As shown) Thick enough to protect the source / drain characteristics (250, such as) Figure 10 (As shown) to prevent damage in subsequent processes. In some embodiments, the length L of the sacrificial oxide portion 232P determines the metal gate stack (e.g., gate stack 270, as shown) Figure 14 The key dimensions (as shown) range from 12nm to 18nm.

[0108] In some embodiments, selective recessing of the sacrificial oxide portion 232P can be achieved by an isotropic dry etching process, wherein the etching gas composition comprises a halogen-containing compound, ammonia (NH3), and amine. In some embodiments, the halogen-containing compound is a hydrohalide, including hydrofluoride, hydrochloride, hydrobromide, hydroiodide, or a combination thereof. In some embodiments, the halogen-containing compound is a fluorine-containing compound. In some embodiments, the fluorine-containing compound may include, but is not limited to, hydrogen fluoride (HF), carbon tetrafluoride (CF4), trifluoromethane (CHF3), sulfur hexafluoride difluoromethane (CH2F2), and hexafluoroethane (C2F6). In some embodiments, the amine may include, but is not limited to, methylamine, dimethylamine, trimethylamine, ethylamine, diethylamine, triethylamine, methylethylamine, N,N-diethylmethylamine, N,N-dimethylethylamine, isopropylamine, N-ethyldiisopropylamine, and tert-butylamine. In some embodiments, the etching gas composition includes hydrogen fluoride, ammonia, and trimethylamine.

[0109] In some embodiments, the etching gas composition may further include a carrier gas, such as argon, nitrogen, helium, or a combination thereof.

[0110] Ammonia and amine gases act as catalysts during halide oxide etching. In some embodiments, the flow rate ratio of the halogen-containing compound to the mixture of ammonia and amine can be from approximately 1:1 to approximately 1:2. Adjusting the ammonia to amine flow rate controls the etching rate from top to bottom of the sacrificial oxide portion 232P stack, ensuring a uniform lateral etching depth. By precisely controlling the critical dimension (CD) of the oxide from top to bottom, a metal gate with an improved CD can be formed after replacing the sacrificial oxide portion 232P in subsequent processes, thereby improving device performance. In some embodiments, the ammonia to amine flow rate ratio in the etchant composition is from 1:5 to 5:1. If the ammonia to amine flow rate ratio is too low, the etching rate may become too slow, resulting in the inner spacer 240 becoming too thin to adequately protect the source / drain features 250, leading to poor yield. Conversely, if the ammonia to amine flow rate ratio is too high, the etching rate may be difficult to control, resulting in over-etching or substantially uneven etching of the sacrificial oxide portion 232P from top to bottom, leading to poor device performance. In some embodiments, the flow rate ratio of ammonia to amine is 1:3 to 3:1. In some embodiments, the flow rate ratio of ammonia to amine is 1:1.

[0111] The selective etching process is cyclic, with each cycle comprising two steps: a reaction step and a byproduct removal step. In the reaction step, a gaseous reactant comprising a halogen-containing compound, ammonia, and amine is introduced into the processing chamber to selectively etch the sacrificial oxide portion 232P. Reaction conditions may include a gas pressure within the processing chamber ranging from approximately 100 mTorr to approximately 3,000 mTorr, a temperature ranging from approximately 20°C to 70°C, and a duration ranging from approximately 50 seconds to approximately 5 minutes. In some embodiments, the etching reaction is carried out at a low-temperature process environment. The low voltage may range from 100 mTorr to 600 mTorr, for example, 400 mTorr. The flow rate of the halogen-containing compound may range from approximately 50 standard cubic centimeters per minute (sccm) to approximately 500 sccm, while the total flow rate of the ammonia and amine may vary from approximately 50 sccm to approximately 500 sccm. If a carrier gas is present, the flow rate may range from approximately 20 sccm to 100 sccm. Plasma may be generated during the reaction step; alternatively, the plasma may not be activated.

[0112] when Figure 7When the GAA device 200 is exposed to the etching gas composition under these conditions, halogenated compounds, ammonia, and amine etching gases adsorb onto the surface of the sacrificial oxide portion 232P, thereby initiating surface etching. Amines tend to adsorb more readily on top of the sacrificial oxide stack, while ammonia is more readily adsorbed at the bottom. By controlling the flow rates of ammonia and amine within a specified range, a uniform etching rate from top to bottom on the sacrificial oxide portion 232P can be achieved. During the reaction step, a solid byproduct is formed on the surface of the sacrificial oxide portion 232P, comprising ammonium fluorosilicate ((NH4)2SiF6) and alkylated derivatives of (NH4)2SiF6.

[0113] The byproduct removal step includes breaking down the solid byproducts into volatile substances, and then evacuating or removing them from the treatment chamber. In some embodiments, a carrier gas may also be used as a purge gas. In some embodiments, heat treatment may be performed to thermally decompose the solid byproducts. In some embodiments, the heat treatment may be performed at a temperature ranging from about 80°C to about 200°C.

[0114] In some embodiments, the selective etching process may be a single cycle, involving only one reaction operation and one removal operation. In other embodiments, multiple cycles may be used to achieve the desired etching effect.

[0115] As is well known, when features of different widths are etched simultaneously, the aspect ratio-dependent etching (ARDE) effect causes wider features to be etched at a faster rate, resulting in a larger lateral etch distance. For example... Figure 15A and Figure 15B As shown, under the same etching conditions, the narrower fin structure 212A ( Figure 16A The 232P sacrificial oxide portion of the fin structure 212B has a wider etching rate than the 232P sacrificial oxide portion. Figure 16B The wider sacrificial oxide portion 232P in the fin structure 210 is etched at a slower rate. Therefore, the lateral etch distance D2 of the lateral opening 234 in the fin structure 210 is smaller than the lateral etch distance D3 of the lateral opening 234 in the fin structure 212B.

[0116] To achieve a uniform etch distance in the sacrificial oxide portions 232P of varying widths on substrate 202, the etch cycle is repeated at least six (6) times to ensure that the etch distance (defined as the thickness of the sacrificial oxide portion 232P removed after each cycle) does not exceed 1.5 nm / cycle. In some embodiments, the etch cycle may be repeated 7, 8, 10, 15, 20, 30, 40, 50, or even 100 times to remove the desired amount of oxide. By utilizing multiple etch cycles to maintain a low etch rate during each cycle, a uniform lateral etch distance can be achieved in the sacrificial oxide portions 232P of varying widths on substrate 202. Figure 16C ).

[0117] refer to Figure 1 and Figure 9 According to some embodiments, method 100 continues to operation 116, wherein an inner spacer 240 is formed in the transverse opening 234. Figure 9 This is a cross-sectional view of the GAA device 200 after the inner spacer 240 is formed.

[0118] An inner spacer material layer is deposited over the structure including the lateral opening 234. The inner spacer material may include a dielectric nitride, such as silicon nitride, silicon carbonitride, or any suitable dielectric material having a different etch selectivity than the dielectric oxide constituting the sacrificial oxide portion 232P. The inner spacer material layer may be formed by CVD, ALD, or any other suitable conformal deposition process. In some embodiments, the inner spacer material layer may be formed to a thickness such that the lateral opening 234 is completely filled by the inner spacer material layer.

[0119] An etching process (e.g., anisotropic etching) is then performed to remove a portion of the inner spacer material layer located outside the lateral opening 234. The remaining portion of the inner spacer material layer (i.e., the portion located within the inner spacer recess) forms the inner spacer 240. In some embodiments, the anisotropic etching process may be a wet etching process, including the use of an etchant such as buffered hydrofluoric acid (BHF), hydrofluoric acid (HF), hydrofluoric nitric acid (HNA), phosphoric acid, HF diluted by ethylene glycol (HFEG), hydrochloric acid (HCl), or any combination thereof. In some embodiments, the anisotropic etching process may be a dry etching process, including the use of oxygen-containing gases, hydrogen, nitrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases (e.g., CF3I), other suitable gases and / or combinations thereof.

[0120] refer to Figure 1 and Figure 10 Method 100 continues to operation 118, in which, according to some embodiments, source / drain features 250 are formed in source / drain trench 228. Figure 10 This is a cross-sectional view of the GAA device 200 after the source / drain feature 250 is formed. The source / drain feature 250 is disposed on the opposite side of the virtual gate structure 220, the channel semiconductor portion 208P, and the sacrificial oxide portion 232P, such that the source / drain feature 250 is in contact with the channel semiconductor portion 208P, but is separated from the sacrificial oxide portion 232P by the inner spacer 240.

[0121] Source / drain features 250 are epitaxially grown in source / drain trenches 228. Epitaxial processes may include CVD deposition (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), molecular beam epitaxy (MBE), other suitable selective epitaxial growth (SEG) processes, or combinations thereof). Because the substrate 202 in the source / drain trenches 228 is covered by isolation features 216, no nucleation sites are formed at the bottom during source / drain epitaxial growth. As a result, source / drain features 250 grow laterally from the exposed sidewalls (if exposed by isolation features 216) of the channel semiconductor portion 208P and the substrate portion 210B.

[0122] The source / drain feature 250 can include any material suitable for an n-type or p-type FET device. For example, when forming an n-type FET device, the source / drain feature 250 can include a material to which tensile strain is applied in the channel region, such as Si, SiC, SiCP, SiP, etc., and can be in-situ doped in an epitaxial process by introducing n-type dopants (e.g., phosphorus (P), arsenic (As)) or out-of-situ doped using a implantation process (i.e., junction implantation). Similarly, when forming a p-type FET device, the source / drain feature 250 can include a material to which compressive strain is applied in the channel region, such as Si, SiGe, SiGeB, Ge, GeSn, etc., and can be in-situ doped in an epitaxial process by introducing p-type dopants, such as boron (B), aluminum (Al), gallium (Ga), and indium (In), or out-of-situ doped using a implantation process (i.e., junction implantation). The source / drain feature 250 may have a surface protruding from a corresponding surface of the channel semiconductor portion 208P and may have facets. In some embodiments, the source / drain feature 250 is a p-type source / drain feature and comprises boron-doped SiGe. In some embodiments, the source / drain feature 250 is an n-type source / drain feature and comprises phosphorus-doped Si.

[0123] In some embodiments, a thermal annealing process is performed after the epitaxial growth and doping of the source / drain feature 250. This process results in the implantation of dopant into portions of the channel semiconductor portion 208P that contact the source / drain feature 250. This annealing process effectively extends the source / drain feature 250 to the end portions of the channel semiconductor portion 208P, thereby reducing the parasitic resistance of the nanosheet transistor. In other embodiments, the thermal annealing process is performed in a subsequent process (e.g., after the formation of a high-k gate dielectric layer), so that the same annealing process can simultaneously achieve two objectives: introducing dopant into the channel semiconductor portion 208P and improving the reliability of the high-k gate dielectric. In some embodiments (not shown), after annealing, the sidewalls of the source / drain feature 250 are aligned with the inner sidewalls of the gate spacer 226. In some other embodiments, the thermal annealing process is omitted, and the sidewalls of the source / drain feature 250 are aligned with the outer sidewalls of the gate spacer 226. Figure 10 ).

[0124] refer to Figure 1 and Figure 11 Method 100 continues to operation 120, in which, according to some embodiments, an interlayer dielectric (ILD) layer 252 is formed over the source / drain feature 250 and the isolation feature 216. Figure 11 This is a cross-sectional view of the GAA device 200 after the formation of the ILD layer 252.

[0125] In some embodiments, the ILD layer 252 may include a low-k dielectric material with a dielectric constant lower than that of silicon dioxide (approximately 3.9). Low-k dielectric materials may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), and silicon oxycarbide (SiO₂). x C yThe ILD layer 252 may be a multilayer structure having a variety of dielectric materials and may be formed by CVD, flowable CVD (FCVD), spin coating, or other suitable deposition processes. In some embodiments, forming the ILD layer 252 also includes performing a CMP process to planarize the top surface of the ILD layer 252, thereby exposing the dummy gate electrode 224. The top surface of the ILD layer 252 may be coplanar with the top surfaces of the dummy gate electrode 224 and the gate spacer 226.

[0126] refer to Figure 1 and Figure 12 According to some embodiments, method 100 proceeds to operation 122, in which the virtual gate stack including virtual gate dielectric 222 and virtual gate electrode 224 is removed. Figure 12 This is a cross-sectional view of the GAA device 200 after the virtual gate stacks (222, 224) have been removed.

[0127] The etching process selectively removes the dummy gate dielectric 222 and the dummy gate electrode 224 to form a gate trench 254 that exposes the channel semiconductor portion 208P and the sacrificial oxide portion 232P in the channel region of the GAA device 200. The ILD layer 252 protects the source / drain features 250 during the etching process. The etching process can be a dry etching process, a wet etching process, or a combination thereof. The etching process can be adapted to remove the dummy gate dielectric 222 and the dummy gate electrode 224 without etching (or with minimal etching) other elements in the GAA device 200, including the ILD layer 252, the source / drain features 250, and the gate spacer 226. For example, when the dummy gate electrode 224 is made of polysilicon and the ILD layer 252 is made of silicon oxide, a wet etchant (e.g., a TMAH solution) can be used to selectively remove the dummy gate electrode 224. Subsequently, plasma dry etching and / or wet etching are used to remove the dummy gate dielectric 222.

[0128] refer to Figure 1 and Figure 13 According to some embodiments, method 100 continues to operation 124, in which the sacrificial oxide portion 232P is removed. Figure 13 This is a cross-sectional view of the GAA device 200 after the sacrificial oxide portion 232P has been removed.

[0129] Selective removal of the sacrificial oxide portion 232P releases the channel semiconductor portion 208P to form the channel nanostructure 262. In some embodiments, the channel nanostructure 262 is a nanosheet. In some embodiments, the sacrificial oxide portion 232P can be removed by a selective etching process, wherein the etchant is selective to the material of the sacrificial oxide portion 232P, such that the sacrificial oxide portion 232P is removed without substantially eroding the channel semiconductor portion 208P, gate spacer 226, inner spacer 240, and ILD layer 252. In some embodiments, the etching process is an isotropic etching process, which can be a dry etching process or a wet etching process. The inner spacer 240 serves as an etch stop layer to protect the source / drain features 250 during the removal of the sacrificial oxide portion 232P.

[0130] In some embodiments, after exposing the channel nanostructure 262 by removing the sacrificial oxide portion 232P, a trimming operation can be performed to reduce the thickness of the channel nanostructure 262, thereby improving the gate fill window. The trimming operation can utilize any suitable etching process, such as dry etching, wet etching, or a combination of both. The resulting channel nanostructure 262 has a thickness T1 ranging from 3 nm to 6 nm.

[0131] like Figure 13 As shown, due to the removal of the sacrificial oxide portion 232P and the trimming of the nanosheets, gaps 256 (e.g., blank spaces) are formed between adjacent channel nanostructures 262 and between the bottommost channel nanostructure 262 and the substrate portion 210B. Gap 256 defines the spacing S2 between adjacent channel nanostructures 262. In some embodiments, the spacing S2 between adjacent channel nanostructures 262 (also referred to as inter-sheet spacing) can be approximately 8 nm to approximately 15 nm.

[0132] refer to Figure 1 and Figure 14 Method 100 continues to operation 124, in which, according to some embodiments, a gate stack 270 is formed in the gate trench 254 and the gap 256. Figure 14 This is a cross-sectional view of the GAA device 200 after the gate stack 270 has been formed. In some embodiments, the gate stack 270 includes an interface layer 272, a gate dielectric layer 274, a work function layer 276, and a gate electrode layer 278.

[0133] An interface layer 272 is formed on the exposed surfaces of the channel nanostructure 262 and the substrate portion 210B. The interface layer 272 facilitates the adhesion of the gate dielectric layer 274 to the channel nanostructure 262. In some embodiments, the interface layer 272 may comprise a dielectric material such as silicon oxide. In some embodiments, the interface layer 272 may be formed by chemically or thermally oxidizing the surface portions of the channel nanostructure 262 and the substrate portion 210B. For example, in some embodiments, the interface layer 272 is formed using ozonated deionized water containing ozone. The thickness of the interface layer 272 ranges from about 0.5 nm to about 1.5 nm. In some embodiments, the interface layer 272 has a thickness of about 1 nm, achieved by oxidizing the channel nanostructure 262 to about 1 nm.

[0134] Subsequently, a gate dielectric layer 274 is conformally deposited over the interface layer 272. The gate dielectric layer 274 covers the channel nanostructure 262 and is located on the sidewall of the gate trench 254. In some embodiments, the gate dielectric layer 274 may comprise a high-k dielectric material with a dielectric constant greater than that of silicon dioxide. Examples of high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and hafnium oxide-aluminum oxide (HfO2-Al2O3) alloys. The gate dielectric layer 274 may be formed using CVD, ALD, or other suitable conformal deposition methods. In some embodiments, the gate dielectric layer 274 is formed using a conformal deposition process (e.g., ALD) to ensure that the high-k gate dielectric layer 274 has a uniform thickness around each channel nanostructure 262. The gate dielectric layer 274 may be formed to have a thickness ranging from about 1 nm to about 2.5 nm. In some embodiments, the gate dielectric layer 274 may be formed to have a thickness of about 1.5 nm.

[0135] Subsequently, a work function layer 276 is deposited over the gate dielectric layer 274. For an n-type FET, the work function layer 276 may include an n-type work function layer suitable for adjusting the threshold voltage of the n-type FET. Suitable n-type work function materials include, but are not limited to, aluminum (Al), aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), aluminum tantalum carbide (TaAlC), aluminum tantalum silicide (TaSiAl), silicon tantalum carbide (TaSiC), tantalum silicide (TaSi), hafnium carbide (HfC), and combinations thereof. For a p-type FET, the work function layer 276 may include a p-type work function layer suitable for adjusting the threshold voltage of the p-type FET. In some embodiments, the p-type work function layer includes tungsten (W), molybdenum (Mo), tungsten nitride (WN), tungsten carbonitride (WCN), tantalum silicon nitride (TaSiN), or tantalum nitride (TaN). The work function layer may be formed by conformal deposition processes (e.g., ALD or CVD). In some embodiments, the work function layer 276 may be formed to have a thickness ranging from about 1.5 nm to about 2.5 nm.

[0136] Subsequently, a gate electrode layer 278 is formed on the work function layer 276 to fill any remaining volume in the gate trench 254 and gap 256. The gate electrode layer 278 may comprise a conductive material, such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. The gate electrode layer 278 may be formed by any suitable deposition process, such as CVD, PECVD, PVD, or electrochemical plating.

[0137] Next, a planarization process (e.g., CMP process) is used to remove excess portions of the gate dielectric layer 274, work function layer 276, and gate electrode layer 278 deposited on the top surface of the ILD layer 252 and gate spacer 226 to form a gate stack 270. The top surface of the gate stack 270 may be coplanar with the top surface of the ILD layer 252 and gate spacer 226.

[0138] The gate stack 270 thus formed surrounds the channel nanostructures 262 and fills the gaps 256 between the channel nanostructures 262 and between the bottommost channel nanostructure 262 and the substrate portion 210B. Between the channel nanostructures 262, the gate electrode layer 278 is surrounded circumferentially by the work function layer 276 (in the cross-sectional view), and the work function layer 276 is in turn surrounded circumferentially by the gate dielectric layer 274. In the portion of the gate stack 270 formed above the topmost channel nanostructure 262, the gate electrode layer 278 is formed above the work function layer 276, and the work function layer 276 surrounds the gate electrode layer 278, and the gate dielectric layer 274 surrounds the work function layer 276.

[0139] Additional processing can be performed to complete the fabrication of the GAA device 200. For example, gate contacts (not shown for simplicity) and source / drain contacts can be formed to be electrically coupled to the gate stack 270 and the source / drain feature 250, respectively. Interconnect structures can then be formed over the source / drain contacts and the gate contacts. The interconnect structures may include multiple dielectric layers surrounding the metal features, including conductive traces and conductive vias, which form electrical connections between devices (e.g., the GAA device 200) on the substrate 202.

[0140] In several embodiments disclosed herein, by adjusting the flow ratio of ammonia to amine gas and the number of etching cycles, a uniform lateral etching rate is achieved from top to bottom in the GAA device, ensuring the formation of internal spacers with uniform width. This control over the critical dimension (CD) of the metal gate can be effectively applied to GAA devices with the same and different channel widths, thereby improving device performance.

[0141] Several embodiments disclosed herein relate to a method of forming a semiconductor device. The method includes forming a stack over a substrate. The stack includes multiple semiconductor portions spaced apart from each other by multiple gaps. The gaps are then filled with a dielectric oxide material. Next, multiple end portions of the deposited dielectric oxide material are laterally etched using an etching gas composition to form multiple lateral openings. The etching gas composition includes a halogen-containing compound, ammonia, and an amine. Next, multiple inner spacers are formed in the lateral openings between adjacent semiconductor portions. Next, multiple remaining portions of the dielectric oxide material deposited in the gaps are removed. Next, a gate stack is formed in the gaps to surround a channel region of the stack.

[0142] In some embodiments, the halogen-containing compound includes hydrogen fluoride (HF), carbon tetrafluoride (CF4), trifluoromethane (CHF3), sulfur hexafluoride difluoromethane (CH2F2), or hexafluoroethane (C2F6). In some embodiments, the amine includes methylamine, dimethylamine, trimethylamine, ethylamine, diethylamine, triethylamine, methylethylamine, N,N-diethylmethylamine, N,N-dimethylethylamine, isopropylamine, N-ethyldiisopropylamine, or tert-butylamine. In some embodiments, the etching gas composition includes hydrogen fluoride, ammonia, and trimethylamine. In some embodiments, the flow rate ratio of ammonia to amine is 1:3 to 3:1. In some embodiments, the etching gas composition further includes a carrier gas. In some embodiments, the flow rate ratio of the halogen-containing compound to the mixture of ammonia and amine is 1:1 to 1:2. In some embodiments, filling the gap with a dielectric oxide material includes: conformally depositing an oxide layer comprising silicon oxide to pinch off the gap; and removing multiple portions of the oxide layer outside the gap. In some embodiments, the critical dimension of the gate stack within each gap is 12 nm to 18 nm. In some embodiments, forming an inner spacer in a lateral opening includes depositing a dielectric nitride material in the lateral opening.

[0143] Several embodiments disclosed herein relate to a method of forming a semiconductor device. The method includes forming a fin structure over a substrate, the fin structure including a plurality of alternately stacked first semiconductor portions and a plurality of second semiconductor portions. A dummy gate structure is formed, the dummy gate structure including a dummy gate stack and a plurality of gate spacers located on a plurality of sidewalls of the dummy gate stack. The dummy gate stack spans a channel region of the fin structure. Next, a plurality of portions of the fin structure not covered by the dummy gate structure are removed to form a plurality of source / drain trenches. Next, the first semiconductor portions are selectively removed to release the second semiconductor portions in the channel region. Next, a plurality of sacrificial oxide portions are formed to fill a plurality of gaps located between the second semiconductor portions. Next, a plurality of end portions of the sacrificial oxide portions are laterally recessed to form a plurality of lateral openings. The lateral recessing is performed using an etching gas composition including a halogen-containing compound, ammonia, and amine. Next, a plurality of inner spacers are formed in the lateral openings, and a plurality of source / drain features are formed in the source / drain trenches. Next, the dummy gate stack is removed to form gate trenches exposing the second semiconductor portions and the plurality of sidewalls of the sacrificial oxide portions. After removing the sacrificial oxide portion located in the gap, a gate stack is formed to surround the second semiconductor portion, wherein the gate stack fills the gap.

[0144] In some embodiments, the halogen-containing compound includes hydrogen fluoride (HF), carbon tetrafluoride (CF4), trifluoromethane (CHF3), sulfur hexafluoride difluoromethane (CH2F2), or hexafluoroethane (C2F6). In some embodiments, the amine includes methylamine, dimethylamine, trimethylamine, ethylamine, diethylamine, triethylamine, methylethylamine, N,N-diethylmethylamine, N,N-dimethylethylamine, isopropylamine, N-ethyldiisopropylamine, or tert-butylamine. In some embodiments, the etching gas composition includes hydrogen fluoride, ammonia, and trimethylamine. In some embodiments, the flow rate ratio of ammonia to amine is 1:3 to 3:1. In some embodiments, the flow rate ratio of the halogen-containing compound to the mixture of ammonia and amine is 1:1 to 1:2.

[0145] Several embodiments disclosed herein relate to a method of forming a semiconductor device. The method includes forming a first stack and a second stack over a substrate. The first stack includes a plurality of first semiconductor portions having a first width and spaced apart from each other by a first gap, and the second stack includes a plurality of second semiconductor portions having a second width and spaced apart from each other by a second gap. The first width is smaller than the second width. After filling the first and second gaps with a dielectric oxide material, a plurality of end portions of the deposited dielectric oxide material are laterally etched in multiple cycles to form a plurality of lateral openings. These cycles include exposing the deposited dielectric oxide material to an etching gas composition to modify a plurality of surfaces of the plurality of end portions of the deposited dielectric oxide material. The etching gas composition includes a halogen-containing compound, ammonia, and an amine, and removing the modified surfaces of the deposited dielectric oxide material by heat treatment. Next, dielectric material is deposited in the lateral openings to form a plurality of inner spacers located between adjacent first semiconductor portions of the first semiconductor portions and adjacent second semiconductor portions of the second semiconductor portions. After removing a plurality of remaining portions of the dielectric oxide material in the first and second gaps, gate stacks are formed in the first and second gaps to surround channel regions of each of the first and second stacks.

[0146] In some embodiments, the halogenated compound includes hydrogen fluoride (HF), carbon tetrafluoride (CF4), trifluoromethane (CHF3), sulfur hexafluoride difluoromethane (CH2F2), or hexafluoroethane (C2F6). In some embodiments, the amine includes methylamine, dimethylamine, trimethylamine, ethylamine, diethylamine, triethylamine, methylethylamine, N,N-diethylmethylamine, N,N-dimethylethylamine, isopropylamine, N-ethyldiisopropylamine, or tert-butylamine. In some embodiments, the etch distance per cycle in each of the plurality of cycles is less than 1.5 nm / cycle.

[0147] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0148] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, this disclosure is intended to cover any modifications and variations falling within the scope of the appended claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A stack is formed on a substrate, the stack comprising a plurality of semiconductor portions spaced apart from each other by a plurality of gaps; The plurality of gaps are filled with a dielectric oxide material; Multiple end portions of the deposited dielectric oxide material are laterally etched by an etching gas composition comprising a halogen-containing compound, an ammonia, and an amine to form multiple lateral openings. Multiple inner spacers are formed in the multiple lateral openings between adjacent semiconductor portions; Remove any remaining portions of the dielectric oxide material deposited in the plurality of gaps; as well as A gate is formed in the plurality of gaps to surround a channel region of the stack.

2. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The halogenated compounds include hydrogen fluoride, carbon tetrafluoride, trifluoromethane, sulfur hexafluoride, difluoromethane, or hexafluoroethane.

3. The method for forming a semiconductor device as claimed in claim 2, characterized in that, The amine includes methylamine, dimethylamine, trimethylamine, ethylamine, diethylamine, triethylamine, methylethylamine, N,N-diethylmethylamine, N,N-dimethylethylamine, isopropylamine, N-ethyldiisopropylamine, or tert-butylamine.

4. The method for forming a semiconductor device as claimed in claim 3, characterized in that, The etching gas composition includes hydrogen fluoride, ammonia, and trimethylamine.

5. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The flow rate ratio of the ammonia to the amine is 1:3 to 3:

1.

6. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The flow rate ratio of the halogenated compound to a mixture of the ammonia and the amine is 1:1 to 1:

2.

7. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The use of the dielectric oxide material to fill the plurality of gaps includes: Conformal deposition includes an oxide layer of silicon oxide to clamp the plurality of gaps; and Remove multiple portions of the oxide layer outside the multiple gaps.

8. A method for forming a semiconductor device, characterized in that, include: A fin structure is formed on a substrate, the fin structure comprising a plurality of alternatingly stacked first semiconductor portions and a plurality of second semiconductor portions; A virtual gate structure is formed, the virtual gate structure including a virtual gate stack and a plurality of gate spacers located on a plurality of sidewalls of the virtual gate stack, the virtual gate stack spanning a channel region of the fin structure; Remove multiple portions of the fin structure that are not covered by the virtual gate structure to form multiple source / drain trenches; Selectively remove the plurality of first semiconductor portions to release the plurality of second semiconductor portions in the channel region; Multiple sacrificial oxide portions are formed to fill multiple gaps located between the multiple second semiconductor portions; The multiple end portions of the plurality of sacrificial oxide portions are laterally recessed to form a plurality of lateral openings, wherein an etching gas composition comprising a halogen-containing compound, an ammonia and an amine is used to perform the lateral recessing; Multiple internal spacers are formed in the multiple transverse openings; Multiple source / drain features are formed in the multiple source / drain trenches; Remove the dummy gate stack to form a gate trench that exposes the sidewalls of the plurality of second semiconductor portions and the plurality of sacrificial oxide portions; Remove the plurality of sacrificial oxidized portions located in the plurality of gaps; as well as A gate stack is formed to surround the plurality of second semiconductor portions, wherein the gate stack fills the plurality of gaps.

9. A method for forming a semiconductor device, characterized in that, include: A first stack and a second stack are formed on a substrate. The first stack includes a plurality of first semiconductor portions having a first width and being spaced apart from each other by a plurality of first gaps. The second stack includes a plurality of second semiconductor portions having a second width and being spaced apart from each other by a plurality of second gaps, wherein the first width is smaller than the second width. The plurality of first gaps and the plurality of second gaps are filled with a dielectric oxide material; Multiple end portions of the deposited dielectric oxide material are laterally etched through multiple cycles to form multiple lateral openings, the multiple cycles including: The deposited dielectric oxide material is exposed to an etching gas composition to modify multiple surfaces of multiple end portions of the deposited dielectric oxide material, the etching gas composition comprising a halogen-containing compound, an ammonia, and an amine; and The deposited dielectric oxide material is removed from the modified plurality of surfaces by heat treatment; A dielectric material is deposited in the plurality of lateral openings to form a plurality of inner spacers, the plurality of inner spacers being located between adjacent plurality of first semiconductor portions and adjacent plurality of second semiconductor portions; Remove multiple remaining portions of the dielectric oxide material from the plurality of first gaps and the plurality of second gaps; and A gate is formed in the plurality of first gaps and the plurality of second gaps to surround a channel region of each of the first stack and the second stack.

10. The method for forming a semiconductor device as claimed in claim 9, characterized in that, The etching distance for each of the plurality of cycles is less than 1.5 nanometers per cycle.

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