Decoupling capacitor unit, preparation method thereof and electronic equipment

Abstract

The invention provides a decoupling capacitor unit, a preparation method thereof and electronic equipment. The decoupling capacitor unit comprises a transistor group which comprises a first transistor and a second transistor which are arranged along the horizontal direction; a power supply metal wire in the front interconnection layer is respectively connected with the first source electrode structure and the second source electrode structure; the back interconnection layer is located below the transistor group in the vertical direction, the back interconnection layer comprises a signal metal wire, and the signal metal wire is electrically connected with the first gate structure and the second gate structure; the metal interconnection structure is located between the back interconnection layer and the transistor group, one end of the metal interconnection structure is connected with the first drain electrode structure, and the other end of the metal interconnection structure extends towards the second transistor in the horizontal direction and is connected with a signal metal wire connected with the second gate structure; one end of the metal interconnection structure is connected with the second drain electrode structure, and the other end of the metal interconnection structure extends towards the first transistor in the horizontal direction and is connected with a signal metal wire connected with the first grid electrode structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor chip manufacturing, and in particular to a decoupling capacitor unit, a preparation method thereof, and an electronic device. BACKGROUND

[0002] In the context of Moore's Law deepening, further improving the integration density of semiconductor devices has become one of the important technologies to continue the size miniaturization of integrated circuits.

[0003] In related technologies, in the process of forming a decoupling capacitor (DECAP) unit, the internal wiring of the transistor is complex, the preparation difficulty is extremely great, and it is not conducive to the size miniaturization of integrated circuits. SUMMARY

[0004] Embodiments of the present application provide a decoupling capacitor unit, a preparation method thereof, and an electronic device, which can effectively balance the wiring resources of the front and back surfaces of the wafer, and further improve the integration performance of the decoupling capacitor unit.

[0005] The technical solutions of the embodiments of the present application are implemented as follows:

[0006] The embodiments of the present application provide a decoupling capacitor unit, comprising: a transistor group comprising a first transistor and a second transistor arranged along a horizontal direction, the first transistor comprising a first source structure, a first drain structure and a first gate structure; the second transistor comprising a second source structure, a second drain structure and a second gate structure; a front interconnection layer located above the transistor group along a vertical direction; wherein the power supply metal lines in the front interconnection layer are connected to the first source structure and the second source structure respectively; a back interconnection layer located below the transistor group along the vertical direction, wherein the back interconnection layer comprises a signal metal line, the signal metal line being electrically connected to the first gate structure and the second gate structure; a metal interconnection structure located between the back interconnection layer and the transistor group, one end of the metal interconnection structure being connected to the first drain structure, the other end of the metal interconnection structure extending towards the second transistor along the horizontal direction and being connected to the signal metal line connected to the second gate structure; and one end of the metal interconnection structure being connected to the second drain structure, the other end of the metal interconnection structure extending towards the first transistor along the horizontal direction and being connected to the signal metal line connected to the first gate structure.

[0007] The embodiments of the present application provide a preparation method of a decoupling capacitor unit, for preparing the decoupling capacitor unit as described above, comprising: forming a transistor group above a semiconductor substrate; forming a front interconnection layer above the transistor group; reversing the film, and removing the semiconductor substrate; sequentially forming a metal interconnection structure and a back interconnection layer above the transistor group.

[0008] The embodiments of the present application provide an electronic device, comprising: a circuit board and the decoupling capacitor unit described above, the decoupling capacitor unit being arranged on the circuit board.

[0009] The technical scheme provided by the embodiment of the present application can include the following beneficial effects:

[0010] In the present application, the first transistor and the second transistor in the transistor group are arranged along a first direction, and a front interconnection layer and a back interconnection layer are respectively arranged above and below the transistor group in a vertical direction. The front interconnection layer is connected to a power supply end, and the back interconnection layer is connected to a gate signal line. The metal interconnection structure on the back is used to realize cross-coupling of a drain and an opposite gate, thereby forming a decoupling capacitor unit. In the decoupling capacitor unit, the front and back double-layer interconnection layers are used, and the gate cross-connection line is transferred to the back interconnection layer, which significantly releases the wafer front wiring resources, realizes the reduction of the unit area, and improves the integration density. At the same time, the parasitic capacitance and signal interference of the front interconnection layer are reduced, and the synergistic optimization of the capacitor performance and the chip area utilization rate is realized without increasing the process cost.

[0011] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application.

[0013] Figure 1 is a structural schematic of a back interconnection structure according to an exemplary embodiment Figure 1 ;

[0014] Figure 2 is a structural schematic of a back interconnection structure according to an exemplary embodiment Figure 2 ;

[0015] Figure 3 is a structural schematic of a decoupling capacitor unit according to an exemplary embodiment Figure 1 ;

[0016] Figure 4 is an equivalent circuit schematic of a decoupling capacitor unit according to an exemplary embodiment Figure 1 ;

[0017] Figure 5 is an equivalent circuit schematic of a decoupling capacitor unit according to an exemplary embodiment Figure 2 ;

[0018] Figure 6 is a structural schematic of a decoupling capacitor unit according to an exemplary embodiment Figure 2 ;

[0019] Figure 7is a flow chart of a preparation method of a decoupling capacitor unit according to an exemplary embodiment;

[0020] Figures 8 to 16 is a flow chart of a preparation of a decoupling capacitor unit according to an exemplary embodiment;

[0021] Figure 17 is a top view schematic of a decoupling capacitor unit according to an exemplary embodiment Figure 1 ;

[0022] Figure 18 is a top view schematic of a decoupling capacitor unit according to an exemplary embodiment Figure 2 ;

[0023] Figure 19 is a top view schematic of a decoupling capacitor unit according to an exemplary embodiment Figure 3 ;

[0024] Figure 20 is a top view schematic of a decoupling capacitor unit according to an exemplary embodiment Figure 4 .

[0025] The reference signs and names in the drawings are as follows:

[0026] 1, placeholder structure; 2, self-aligned backside direct contact structure; 3, buried oxygen layer; 4, trench structure; 5, insulating structure; 11, first drain structure; 12, first source structure; 13, second source structure; 14, second drain structure; 15, metal contact structure; 16, backside source / drain metal; 171, first gate structure; 172, second gate structure; 18, source / drain direct metal; 19, gate direct metal; 20, decoupling capacitor unit; 21, transistor group; 211, first transistor; 212, second transistor; 22, frontside interconnect layer; 221, first power rail; 222, second power rail; 223, dielectric structure; 23, backside interconnect layer; 232, signal metal line; 24, carrier wafer; 25, dummy gate structure; 26, sidewall structure; 27, shallow trench isolation structure; 28, frontside source / drain metal; 29, metal via; 30, semiconductor substrate. DETAILED DESCRIPTION

[0027] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be described in further detail below with reference to the drawings, and the described embodiments should not be regarded as limiting the present application. All other embodiments obtained by those of ordinary skill in the art without making creative labor fall within the scope of protection of the present application.

[0028] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but which can be understood as possibly being the same or different subsets of all possible embodiments, and which can be combined with each other, without conflict, in the description.

[0029] In the following description, the terms "first / second / third" are merely used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that the "first / second / third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.

[0030] In related technologies, there are space and wiring challenges in designing decoupling capacitor cells. For example, in a decoupling capacitor cell composed of a Gate-All-Around Field-Effect Transistor (GAAFET), without wasting cell area and without using M1 metal in the metal interconnection layer, since there is only a wafer front surface active drain metal (MD) structure, the winding resource in the cell is severely limited. When trying to connect the drain of an N-type transistor (NMOS) to the gate of a corresponding P-type transistor (PMOS) (or vice versa), the design space is limited and short circuits are easily caused, forcing the need to increase the spacing of NMOS and PMOS in the Y direction of the layout, thereby increasing the cell area. If M1 metal wiring is used, although the winding pressure can be alleviated, at least 4 M0 signal lines need to be placed in the standard cell, and at least 2 M1 signal lines need to be placed in the 2 contact gaps (CPP) in the Y direction. This will cause a design violation of the minimum spacing of the metal via (such as the metal via V1 corresponding to the M1 metal). At the same time, the requirement for the number of signal lines is not conducive to further scaling of the standard cell height. Figure X

[0031] To overcome the above technical problems, the embodiments of the present application provide a decoupling capacitor cell and a preparation method thereof, and an electronic device. By using a double-sided wiring scheme and a back interconnection technology, the wiring resources of the wafer front surface and the back surface are effectively balanced, and the integration performance of the decoupling capacitor cell is further improved. The double-sided wiring scheme expands the wiring freedom degree by utilizing the double-sided resources of the wafer, and the back interconnection technology avoids the front winding bottleneck by means of the back metal layer. Both of them can effectively avoid short circuit risks, reduce spacing constraints, and support efficient scaling of the cell height, thereby improving the overall performance and integration of the decoupling capacitor cell.

[0032] In a first aspect, the embodiments of the present application provide a decoupling capacitor cell.

[0033] ​In some embodiments, implementing double-sided interconnection on the back of a wafer is a future research hotspot and trend in the integrated circuit industry. In order to connect the source and drain of the front transistor to the power line and signal line on the back, while minimizing the significant overlay error when performing photolithography on the back of the wafer, a self-aligned backside contact (SADBC) scheme based on a placeholder is proposed. The scheme forms a placeholder structure around the target circuit area (such as the transistor source / drain) on the front of the wafer (active area) through photolithography and etching processes. Then the wafer is thinned to the target thickness by mechanical grinding or chemical mechanical polishing (CMP), and then the placeholder structure is used as a positioning reference to form a contact hole pattern on the back through photolithography or electron beam exposure. Since the placeholder structure is precisely defined on the front, the back etching does not require additional alignment marks, achieving self-alignment.

[0034] An exemplary, Figure 1 is a structural diagram of a backside interconnection structure according to an exemplary embodiment Figure 1 . Referring to Figure 1 (a), a placeholder structure 1 can be formed on the back of the wafer, which is located below the source / drain. Referring to Figure 2 (b), based on the placeholder structure 1 on the back of the wafer, a self-aligned backside contact structure 2 can be formed.

[0035] In some embodiments, a backside interconnection scheme based on self-aligned backside contact and backside metalized drain (BSMD) is proposed. Based on the formation of the placeholder structure, the original substrate is completely removed by extreme thinning of the original wafer to directly fabricate the backside metalized drain on the back of the wafer through photolithography process, achieving self-alignment.

[0036] An exemplary, Figure 2 is a structural diagram of a backside interconnection structure according to an exemplary embodiment Figure 2 . Referring to Figure 3, shows the specific process of forming back side source-drain metal on the back side of the wafer. The first process of preparing back side source-drain metal can include: (a) thinning the substrate; (b) thinning the buried oxygen layer 3; (c) forming a via at the buried oxygen layer 3 to expose the placeholder structure 1 by using a patterning process; (d) forming a sidewall structure 26 on the sidewall of the via; (e) filling the via with metal to form back side source-drain metal 16. The second process of preparing back side source-drain metal can include: (f) thinning the substrate; (g) removing the buried oxygen layer 3; (h) forming a trench structure 4 by etching process; (i) filling the trench structure 4 with insulating structure 5; (j) forming a via at the insulating structure 5 by using a patterning process, the bottom of the via is composed of the placeholder structure 1; (k) filling the via with metal to form back side source-drain metal 16.

[0037] In some embodiments, Figure 1 is a structural diagram of a decoupling capacitor unit according to an exemplary embodiment Figure 3 . Figure 3 (a) in FIG. 1 shows a back view of the layout of the decoupling capacitor unit, Figure 3 (b) in FIG. 1 shows a front view of the layout of the decoupling capacitor unit. The back view and the front view show fin structures, gate structures, source-drain structures, signal metal lines and power supply metal lines. Among them, the A-A' section is the section of the decoupling capacitor unit along the length direction of the gate region (the direction perpendicular to the channel direction); the B-B' section is the section of the decoupling capacitor unit along the length direction of the source-drain region (the direction perpendicular to the channel direction); the C-C' section is the section of the decoupling capacitor unit along the length direction of the source-drain region (the direction perpendicular to the channel direction); the D-D' section is the section of the decoupling capacitor unit along the third direction (the channel direction). Figure 3 (c) to (f) in FIG. 1 respectively show the sectional view of the decoupling capacitor unit along the A-A' section, along the B-B' section, along the C-C' section and along the D-D' section.

[0038] As shown in Figure 3 , the decoupling capacitor unit 20 in the embodiments of the present application can include a transistor group 21, a front interconnection layer 22 and a back interconnection layer 23. Here, the transistor group 21 can include a first transistor 211 and a second transistor 212 arranged along a horizontal direction. In an embodiment, the horizontal direction can be any direction in the plane parallel to the wafer surface. In some embodiments, the first transistor 211 can include a first drain structure 11, a first source structure 12 and a first gate structure 171. The second transistor 212 can include a second source structure 13, a second drain structure 14 and a second gate structure 172.

[0039] In some embodiments, the horizontal direction can be the length direction of the source-drain region, i.e., in the B-B' section, the horizontal direction can be the direction of proceeding from the left to the right. For example, the transistor group 21 can include a first transistor 211 and a second transistor 212 arranged along the horizontal direction. Among them, the arrangement direction between the first drain structure 11, the first gate structure 171 and the first source structure 12 is perpendicular to the horizontal direction. In an embodiment, the arrangement direction between the second source structure 13, the second gate structure 172 and the second drain structure 14 is perpendicular to the horizontal direction.

[0040] In some embodiments, the first transistor 211 in the transistor group 21 can be a P-type transistor, and the second transistor 212 can be an N-type transistor. In some embodiments, the second transistor 212 in the transistor group 21 can be a P-type transistor, and the first transistor 211 can be an N-type transistor.

[0041] In some embodiments, the first transistor 211 and / or the second transistor 212 can be a planar transistor, a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor or a fork sheet field-effect transistor (Forksheet FET), etc.

[0042] In some embodiments, the type of the first transistor 211 and / or the second transistor 212 can be set according to actual needs, which is not limited in the embodiments of the present application. In an example, the first transistor 211 and the second transistor 212 can be planar transistors. In an example, the first transistor 211 can be a planar transistor, and the second transistor 212 can be a fin field-effect transistor. In an example, the first transistor 211 can be a gate-all-around field-effect transistor, and the second transistor 212 can be a fork sheet field-effect transistor. Referring to FIG. 1, the first transistor 211 and the second transistor 212 can be gate-all-around field-effect transistors. Figure 4

[0043] In some embodiments, the front interconnection layer 22 and the back interconnection layer 23 are respectively located above and below the transistor group 21 along the vertical direction. The vertical direction is perpendicular to the horizontal direction, and the vertical direction is the direction perpendicular to the wafer surface. When the front interconnection layer 22 is located above the transistor group 21 along the vertical direction, the front interconnection layer 22 is located on the front surface of the wafer; when the back interconnection layer 23 is located below the transistor group 21 along the vertical direction, the back interconnection layer 23 is located on the back surface of the wafer. In this way, the front interconnection layer 22 and the back interconnection layer 23 are respectively located on the front and back surfaces of the wafer, balancing the distribution of the wire winding resources on both sides of the transistor group 21 (single-layer transistor).​

[0044] In some embodiments, the front interconnection layer 22 can be a film layer formed by BEOL (back-end-of-line) on the front side of the wafer. In some embodiments, the front interconnection layer 22 can include a first power rail 221 and a second power rail 222. The first power rail 221 and the second power rail 222 can be power supply lines arranged in the front interconnection layer 22, i.e., the first power rail 221 and the second power rail 222 can be front power supply metal lines. The first power rail 221 and the first source structure 12 in the first transistor 211 are electrically connected through a via or an interconnection structure. The second power rail 222 and the second source structure 13 in the second transistor 212 are electrically connected through a via or an interconnection structure.

[0045] In an example, the first power rail 221 is connected to the first source structure 12 in the first transistor 211 through a vertical interconnection structure (such as a copper pillar), thereby realizing the function of supplying power to the first transistor 211 from the front side. In an example, the second power rail 222 is connected to the second source structure 13 in the second transistor 212 through a vertical interconnection structure (such as a copper pillar), thereby realizing the function of supplying power to the second transistor 212 from the front side.

[0046] In some embodiments, the voltage of the first power rail 221 is different from the voltage of the second power rail 222, i.e., the voltage provided by the first power rail 221 to the first transistor 211 is different from the voltage provided by the second power rail 222 to the second transistor 212. In some embodiments, the first power rail 221 can be a positive power supply (Voltage Drain Drain, VDD), and the second power rail 222 can be a ground (Voltage Source Source, VSS). Alternatively, the first power rail 221 can be VSS, and the second power rail 222 can be VDD.

[0047] In some embodiments, the first power rail 221 and the second power rail 222 do not overlap. In this way, the power supply of the power rail is more stable, and the signal integrity is better. At the same time, the non-overlapping of the power rails can make different power rails close to different transistors, thereby meeting the differentiated power supply needs between different transistors.

[0048] In some embodiments, the first transistor 211 is a P-type transistor, and the second transistor 212 is an N-type transistor; wherein the voltage of the first power rail 221 is greater than the voltage of the second power rail 222.

[0049] It can be understood that when the first power rail 221 is electrically connected with the first transistor 211, the first transistor 211 can be a P-type transistor, and the first power rail 221 can be VDD. When the second power rail 222 is electrically connected with the second transistor 212, the second transistor 212 can be an N-type transistor, and the second power rail 222 can be VSS. The voltage of the first power rail 221 is greater than the voltage of the second power rail 222. In this way, VDD is arranged on the side close to the P-type transistor, and VSS is arranged on the side close to the N-type transistor, which can improve the proximity of the P-type transistor to VDD and the proximity of the N-type transistor to VSS, and meet the wiring requirements of the decoupling capacitor unit 20.

[0050] In some embodiments, the front interconnection layer 22 further includes a front metal line. The front metal line can be a signal line arranged in the front interconnection layer 22, i.e., the front metal line can be a front signal metal line. The front metal line can be electrically connected with the transistors in the transistor group 21 through a via or an interconnection structure.

[0051] In some embodiments, the front interconnection layer 22 can include a plurality of metal layers. For example, the front interconnection layer 22 can have 18 metal layers, i.e., M0 metal to M17 metal. Here, the first power rail 221, the second power rail 222 and the front metal line are all included in the plurality of metal layers.

[0052] In some embodiments, the front interconnection layer 22 can include a dielectric structure 223. The dielectric structure 223 can be formed by depositing a dielectric material. The dielectric structure 223 is used to wrap the first power rail 221 and / or the second power rail 222 to electrically isolate the first power rail 221 and / or the second power rail 222 from other structures. In some embodiments, the dielectric material can include silicon oxide, silicon nitride, silicon carbide, diamond-like carbon, polymer-based low dielectric constant material, porous silicon dioxide, spin-on glass, polyimide, benzocyclobutene (BCB), or any combination thereof.

[0053] In some embodiments, the back interconnection layer 23 can be a film layer formed by BEOL on the back of the wafer. In some embodiments, the back interconnection layer 23 can include a signal metal line 232 and a dielectric structure 223. The signal metal line 232 can be a signal line arranged in the back interconnection layer 23. The signal metal line 232 can be electrically connected with the transistors in the transistor group 21 through a via or an interconnection structure.

[0054] In some embodiments, the signal metal line 232 can have a plurality of lines, one of which can be connected with the first gate structure 171 in the first transistor 211, and the other of which can be connected with the second gate structure 172 in the second transistor 212.

[0055] In some embodiments, the back interconnect layer 23 can include multiple metal levels. For example, the back interconnect layer 23 can have 18 metal layers, namely M0 metal to M17 metal. Here, the signal metal line 232 is included in the multiple metal levels.

[0056] In some embodiments, the dielectric structure 223 in the back interconnect layer 23 can refer to the dielectric structure 223 in the front interconnect layer 22, which will not be repeated here for the sake of brevity of the description.

[0057] In some embodiments, a metal interconnect structure is formed between the transistor group 21 and the back interconnect layer 23, which is used to connect the drain in the transistor and the opposite gate, so as to form an interleaved coupling circuit, and obtain the decoupling capacitor unit 20.

[0058] In some embodiments, one end of the metal interconnect structure is connected to the first drain structure 11 of the first transistor 211, and the other end extends in the horizontal direction towards the second transistor 212 and is connected to the signal metal line 232 connected to the second gate structure 172; and one end of the metal interconnect structure is connected to the second drain structure 14, and the other end extends in the horizontal direction towards the first transistor 211 and is connected to the signal metal line 232 connected to the first gate structure 171.

[0059] It can be understood that before the back interconnect layer 23 is formed, a film layer can be formed above the transistor group 21. The film layer can include a metal interconnect structure. By connecting the first drain structure 11 and the second gate structure 172, and connecting the second drain structure 14 and the first gate structure 171 through the metal interconnect structure, the circuit interconnection inside the decoupling capacitor unit can be completed on the back of the wafer. In this way, after the back interconnect layer 23 is prepared, the decoupling capacitor unit 20 can be prepared.

[0060] In some embodiments, the metal interconnect structure can be a multi-layer metallization structure. The multi-layer metallization structure can use a stack of metal layers such as copper or aluminum, and connect different layers through vias and contact holes to support high-density interconnection. In some embodiments, the metal interconnect structure can be a structure formed by a combination of metal leads and through-silicon vias (TSV) structure. Among them, the metal lead is used to realize horizontal interconnection, and the through-silicon via is used to realize vertical stacked interconnection. The interconnection of structures at different positions can be completed through the metal lead and the through-silicon via.

[0061] In some embodiments, the metal interconnect structure can include a metal contact structure 15 and a back source-drain metal 16. In some embodiments, the metal interconnect structure located between the first drain structure 11 and the back interconnect layer 23 can include the metal contact structure 15 and the back source-drain metal 16; and / or the metal interconnect structure located between the second drain structure 14 and the back interconnect layer 23 can include the metal contact structure 15 and the back source-drain metal 16.

[0062] It can be understood that the metal contact structure 15 is used to connect the active region of the transistor and the back source-drain metal 16, and the back source-drain metal 16 is used to connect the metal contact structure 15 and the back interconnection layer 23. In this way, the connection between the active region of the transistor and the back interconnection layer 23 is achieved.

[0063] In some embodiments, the metal contact structure 15 can extend in the vertical direction, and the back source-drain metal 16 can extend in the horizontal direction. Through the combination of the metal contact structure 15 and the back source-drain metal 16, the connection of the structures at any two positions can be achieved.

[0064] In some embodiments, one end of the metal contact structure 15 is connected to the first drain structure 11, and the other end extends in the vertical direction towards the back interconnection layer 23. One end of the back source-drain metal 16 is connected to the metal contact structure 15 connected to the first drain structure 11, and the other end extends in the horizontal direction towards the second transistor 212 and is connected to the signal metal line 232 connected to the second gate structure 172.

[0065] It can be understood that one end of the metal contact structure 15 is connected to the first drain structure 11, and the other end extends in the vertical direction to achieve vertical electrical signal transmission. One end of the back source-drain metal 16 is connected to the metal contact structure 15, and the other end extends horizontally to the second transistor 212 and is interconnected with the signal metal line 232 connected to the second gate structure 172 to complete the horizontal signal transmission.

[0066] In some embodiments, one end of the metal contact structure 15 is connected to the second drain structure 14, and the other end extends in the vertical direction towards the back interconnection layer 23. One end of the back source-drain metal 16 is connected to the metal contact structure 15 connected to the second drain structure 14, and the other end extends in the horizontal direction towards the first transistor 211 and is connected to the signal metal line 232 connected to the first gate structure 171.

[0067] It can be understood that one end of the metal contact structure 15 is connected to the second drain structure 14, and the other end extends in the vertical direction to achieve vertical electrical signal transmission. One end of the back source-drain metal 16 is connected to the metal contact structure 15, and the other end extends horizontally to the first transistor 211 and is interconnected with the signal metal line 232 connected to the first gate structure 171 to complete the horizontal signal transmission.

[0068] An exemplary, Figure 1 is an equivalent circuit schematic of a decoupling capacitor unit according to an exemplary embodiment Figure 3 , in combination Figure 4 and Figure 3As shown, the first transistor 211 and the second transistor 212 can constitute a decoupling capacitor unit 20. The first transistor 211 is a P-type transistor, and the second transistor 212 is an N-type transistor. The first transistor 211 and the second transistor 212 are arranged along a horizontal direction. The first transistor 211 is located at the left side of (c) in Figure 3 , and the second transistor 212 is located at the right side of (c) in Figure 3 . The first source structure 12 of the first transistor 211 is electrically connected to the first power rail 221 through the front side source / drain metal 28 and the metal via 29, and the second source structure 13 of the second transistor 212 is electrically connected to the second power rail 222 through the front side source / drain metal 28 and the metal via 29. The first gate structure 171 of the first transistor 211 is connected to the signal metal line 232 in the back side interconnection layer 23, and the second gate structure 172 of the second transistor 212 is connected to the signal metal line 232 in the back side interconnection layer 23. Referring to (d) in Figure 3 , the first drain structure 11 of the first transistor 211 is connected to the signal metal line 232 in the back side interconnection layer 23 connected to the second gate structure 172 through the metal contact structure 15 and the back side source / drain metal 16. Here, the extension direction of the back side source / drain metal 16 is from the left side of the figure to the right side of the figure, until it is connected to the signal metal line 232 at the left 4 in the figure. Referring to (e) in Figure 5 , the second drain structure 14 of the second transistor 212 is connected to the signal metal line 232 in the back side interconnection layer 23 connected to the first gate structure 171 through the metal contact structure 15 and the back side source / drain metal 16. Here, the extension direction of the back side source / drain metal 16 is from the right side of the figure to the left side of the figure, until it is connected to the signal metal line 232 at the left 2 in the figure.

[0069] In some embodiments, the metal contact structure 15 is located below the first drain structure 11 and / or the second drain structure 14 in the vertical direction. It can be understood that the metal contact structure 15 can be located between the first drain structure 11 and the back side interconnection layer 23, and / or between the second drain structure 14 and the back side interconnection layer 23. In the embodiments of the present application, the metal contact structure 15 can be in direct contact with the first drain structure 11 and located below the first drain structure 11 (i.e., the back side of the wafer); and / or the metal contact structure 15 can be in direct contact with the second drain structure 14 and located below the second drain structure 14.

[0070] In some embodiments, the metal contact structure 15 can be formed by removing the placeholder structure 1 and filling a metal material at the position where the placeholder structure 1 is removed. It can be understood that the placeholder structure 1 is used to provide space for forming the metal contact structure 15 below the transistor group. The placeholder structure 1 can be formed before the transistor group is formed. This preparation process method can realize high-density interconnection, improve chip performance and reliability.

[0071] In some embodiments, the placeholder structure 1 can be formed by forming a trench in the active region and filling the trench with a specific material. In some embodiments, the material forming the placeholder structure 1 can be an insulating material. In some embodiments, the material forming the placeholder structure 1 can be a material having etching selectivity with respect to the semiconductor substrate. In this way, the placeholder structure 1 can be selectively removed before the metal contact structure 15 is formed.

[0072] It can be appreciated that when the metal contact structure 15 connected with the first drain structure 11 is needed to be formed, the placeholder structure 1 can be first formed under the position where the first source structure is located, then the first source structure is formed on the placeholder structure 1, and finally the placeholder structure 1 is removed and the metal material is filled in the position where the placeholder structure 1 is removed, so that the metal contact structure 15 connected with the first drain structure 11 can be formed. When the metal contact structure 15 connected with the second drain structure 14 is needed to be formed, the placeholder structure 1 can be first formed under the position where the second source structure is located, then the second source structure is formed on the placeholder structure 1, and finally the placeholder structure 1 is removed and the metal material is filled in the position where the placeholder structure 1 is removed, so that the metal contact structure 15 connected with the second drain structure 14 can be formed.

[0073] In some embodiments, the transistor group 21 includes a plurality of transistors, and the plurality of transistors constitute a plurality of decoupling capacitor units 20. The plurality of decoupling capacitor units 20 can be connected. In some embodiments, the plurality of decoupling capacitor units 20 can be connected through the metal interconnection structure and / or the back interconnection layer.

[0074] An exemplary structure of a decoupling capacitor unit is shown in FIG. 2. Figure 2 An equivalent circuit schematic of a decoupling capacitor unit is shown in FIG. 3 according to an exemplary embodiment. Figure 6 An equivalent circuit schematic of a decoupling capacitor unit is shown in FIG. 3 according to an exemplary embodiment. Figure 2 An equivalent circuit schematic of a decoupling capacitor unit is shown in FIG. 3 according to an exemplary embodiment. Figures 5 to 6 As shown in FIG. 2, the dashed line schematically represents that the structures at both ends of the line segment are connected through the back source-drain metal in the decoupling capacitor unit, and the solid line schematically represents that the structures at both ends of the line segment are connected through the signal metal line in the back interconnection layer. Figure 5 The nodes with the same letter number in FIG. 2 and FIG. 3 correspond in sequence. Figure 6 The nodes with the same letter number in FIG. 2 and FIG. 3 correspond in sequence. Figure 3 It should be noted that, for the convenience of description, the source-drain metal mentioned in the embodiments of the present application is a short name, which specifically refers to the source metal and / or the drain metal. Similarly, the source-drain structure is also a short name, which specifically refers to the source structure and / or the drain structure. The “connection” mentioned in the embodiments of the present application all refers to electrical connection (i.e. electrical conduction or signal transmission relationship between conductors).

[0075] It should be noted that, for the convenience of description, the source-drain metal mentioned in the embodiments of the present application is a short name, which specifically refers to the source metal and / or the drain metal. Similarly, the source-drain structure is also a short name, which specifically refers to the source structure and / or the drain structure. The “connection” mentioned in the embodiments of the present application all refers to electrical connection (i.e. electrical conduction or signal transmission relationship between conductors).

[0076] In the embodiments of the present application, the first transistor and the second transistor in the transistor group are arranged along a first direction, and a front interconnection layer and a back interconnection layer are respectively arranged above and below the transistor group in a vertical direction. The front interconnection layer is connected to a power supply terminal, and the back interconnection layer is connected to a gate signal line. The metal interconnection structure on the back surface is used to realize the cross coupling of the drain and the opposite gate, so as to form a decoupling capacitor unit. In the decoupling capacitor unit, the front and back double-layer interconnection layers are used, and the gate cross connection line is transferred to the back interconnection layer, so as to significantly release the wafer front surface wiring resource, realize the reduction of the unit area, and improve the integration density. At the same time, the parasitic capacitance and signal interference of the front interconnection layer are reduced, and the synergistic optimization of the capacitor performance and the chip area utilization rate is realized without increasing the process cost.

[0077] In some embodiments, the decoupling capacitor unit 20 further comprises a source-drain direct metal 18 (BSVD) and a gate direct metal 19 (BSVG). It can be understood that the source-drain direct metal 18 can be a metal conductive structure connected to the transistor source-drain structure, used to realize the electrical connection between the source-drain region and the external circuit. The gate direct metal 19 can be a metal conductive structure directly connected to the transistor gate structure, used for the lead-out and interconnection of the gate signal.

[0078] In some embodiments, the source-drain direct metal 18 can be a metal via, a metal lead, or the like. In some embodiments, the gate direct metal 19 can be a metal via, a metal lead, or the like.

[0079] In some embodiments, the source-drain direct metal 18 and the gate direct metal 19 can be used together to connect the first drain structure and the second gate structure; and / or, used together to connect the second drain structure and the first gate structure.

[0080] In some embodiments, when the source-drain direct metal 18 and the gate direct metal 19 are used together to connect the first drain structure and the second gate structure, the source-drain direct metal 18 can be located between the metal interconnection structure connected to the first drain structure and the signal metal line connected to the second gate structure; and the gate direct metal 19 can be located between the signal metal line connected to the second gate structure and the second gate structure.

[0081] In some embodiments, when the source-drain direct metal 18 and the gate direct metal 19 are used together to connect the second drain structure and the first gate structure, the source-drain direct metal 18 can be located between the metal interconnection structure connected to the second drain structure and the signal metal line connected to the first gate structure; and the gate direct metal 19 can be located between the signal metal line connected to the first gate structure and the first gate structure.

[0082] For example, referring to Figure 3In diagram (d), the first drain structure 11 of the first transistor 211 is connected to the signal metal line 232, which is connected to the second gate structure 172 in the back interconnect layer 23, via the metal contact structure 15, the back source-drain metal 16, and the source-drain direct connection metal 18. Furthermore, the second gate structure 172 is connected to the signal metal line 232 via the gate direct connection metal 19. Here, the back source-drain metal 16 extends from the left side of the diagram to the right side, until it connects to the signal metal line 232 (left 4) in the diagram. See also... Figure 7 In (e), the second drain structure 14 of the second transistor 212 is connected to the signal metal line 232 connected to the first gate structure 171 in the back interconnect layer 23 via the metal contact structure 15, the back source-drain metal 16, and the source-drain direct connection metal 18. Furthermore, the first gate structure 171 is connected to the signal metal line 232 via the gate direct connection metal 19. Here, the back source-drain metal 16 extends from the right side of the figure to the left side until it connects to the signal metal line 232 on the left (second from the left) in the figure.

[0083] In some embodiments, the decoupling capacitor unit 20 further includes an intermediate interconnect structure; wherein the intermediate interconnect structure is located between the source-drain direct-connect metal 18 and the gate-direct-connect metal 19, and is used to connect the source-drain direct-connect metal 18 and the gate-direct-connect metal 19.

[0084] Understandably, the intermediate interconnect structure can be a metal conductive structure that connects the source / drain direct-connect metal 18 and the gate direct-connect metal 19 to realize the electrical connection between the source / drain structure and the gate structure.

[0085] In some embodiments, the intermediate interconnect structure, the source-drain direct-connect metal 18, and the gate direct-connect metal 19 are formed using the same semiconductor fabrication process.

[0086] Understandably, after forming a dielectric layer through a deposition process, etching is used to etch the dielectric layer, which can form source / drain direct connection metal vias, gate direct connection metal vias, and intermediate interconnect structure trenches within the dielectric layer. The intermediate interconnect structure trenches are located between the source / drain direct connection metal vias and the gate direct connection metal vias, and are connected to both. Subsequently, by depositing metal within the source / drain direct connection metal vias, gate direct connection metal vias, and intermediate interconnect structure trenches, source / drain direct connection metal 18, gate direct connection metal 19, and intermediate interconnect structures can be formed simultaneously. Specifically, source / drain direct connection metal 18 is formed by directly filling the source / drain direct connection metal vias with metal material, gate direct connection metal 19 is formed by directly filling the gate direct connection metal vias with metal material, and the intermediate interconnect structure is formed by directly filling the intermediate interconnect structure trenches with metal material.

[0087] It can be understood that the source-drain direct connection metal 18 and the gate direct connection metal 19 can be connected through the intermediate interconnection structure. Thus, the cross-coupling of the drain and the opposite gate can be realized by using the intermediate interconnection structure before the back interconnection layer is prepared, and greater flexibility and wiring space are provided for the design of the subsequent back interconnection layer, thereby simplifying the process complexity, reducing the cost and improving the overall yield.

[0088] In a second aspect, the embodiments of the present application provide a preparation method of a decoupling capacitor unit. Figure 7 FIG. 1 is a flow diagram of a preparation method of a decoupling capacitor unit according to an exemplary embodiment. As shown in FIG. 1, the preparation method of the decoupling capacitor unit in the embodiments of the present application is used to prepare the decoupling capacitor unit 20 in any one of the embodiments of the first aspect. The preparation method of the decoupling capacitor unit 20 can include: Figures 8 to 16

[0089] Step 701: forming a transistor group above a semiconductor substrate.

[0090] Step 702: forming a front interconnection layer above the transistor group.

[0091] Step 703: peeling off and removing the semiconductor substrate.

[0092] Step 704: sequentially forming a metal interconnection structure and a back interconnection layer above the transistor group.

[0093] In the embodiments of the present application, first, the transistor group 21 is made on the semiconductor substrate, then the front interconnection layer 22 is formed above the transistor group 21 through deposition, photolithography and etching processes, the front interconnection layer 22 includes the first power rail 221 and the second power rail 222, the first power rail 221 is electrically connected to the first source structure 12 of the first transistor 211 in the transistor group 21, and the second power rail 222 is electrically connected to the second source structure 13 of the second transistor 212 in the transistor group 21. Then, the original semiconductor substrate is peeled off and removed. After the original semiconductor substrate is removed, the transistor group 21 can be re-exposed, and the metal interconnection structure is formed according to the positions of the first drain structure 11 and the second gate structure 172, and the metal interconnection structure is formed according to the positions of the second drain structure 14 and the first gate structure 171. After the metal interconnection structure is formed, the back interconnection layer is formed above the metal interconnection structure. Thus, the first drain structure 11 and the second gate structure 172, and the second drain structure 14 and the first gate structure 171 can be connected through the metal interconnection structure and the back interconnection layer.

[0094] It can be understood that the specific structure of the decoupling capacitor unit 20 can be referred to the description in any one of the embodiments of the first aspect, and will not be described here for the sake of brevity of the description.

[0095] ​In some embodiments, the method for manufacturing the transistor group 21 can be implemented according to a standard semiconductor manufacturing process corresponding to the specific type of the transistor. For example, for a fin field effect transistor, the standard semiconductor manufacturing process can include the following key steps: first, a three-dimensional fin structure is created on a semiconductor substrate (e.g., a silicon wafer) through deposition and etching processes. Second, a gate dielectric layer and a polysilicon gate layer are sequentially deposited above the fin. Third, ion implantation is performed to form source and drain regions on both sides of the fin, and annealing is performed to activate the dopant atoms.

[0096] In some embodiments, the front interconnection layer 22 and the back interconnection layer 23 can be implemented using a standard semiconductor back-end manufacturing process. The connection between the front interconnection layer 22 and the transistor can be implemented through the front source / drain metal 28. The connection between the back interconnection layer 23 and the transistor can be implemented through the metal interconnection structure.

[0097] In some embodiments, the metal interconnection structure trench can be formed by depositing a dielectric layer on the back of the transistor group, and then etching the dielectric layer using an etching process. Here, the metal interconnection structure trench extends in the horizontal direction, and one end of the metal interconnection structure trench is connected to the first drain structure 11 and / or the second drain structure 14. Then, by depositing metal in the metal interconnection structure trench, the metal interconnection structure can be formed. For example, when the metal interconnection structure trench is connected to the first drain structure 11, after depositing metal in the metal interconnection structure trench, the obtained metal interconnection structure trench can be connected to the first drain structure 11 at one end, and extend in the horizontal direction towards the second transistor 212 at the other end, and be connected to the signal metal line 232 connected to the second gate structure 172.

[0098] In some embodiments, the metal interconnection structure includes the metal contact structure 15 and the back source / drain metal 16. The metal contact structure 15 is used to connect the active region of the transistor to the back source / drain metal 16, and the back source / drain metal 16 is used to connect the metal contact structure 15 to the back interconnection layer 23. The metal contact structure 15 can extend in the vertical direction, and the back source / drain metal 16 can extend in the horizontal direction.

[0099] In some embodiments, the via that exposes the first drain structure 11 and / or the second drain structure 14 can be formed by etching the dielectric layer using an etching process. Then, by depositing a metal material in the via, the metal contact structure 15 can be formed. In some embodiments, by depositing a metal material above the dielectric layer containing the metal contact structure 15, the back source / drain metal 16 extending in the horizontal direction can be formed.

[0100] In some embodiments, step 701 can include: etching the semiconductor substrate to form a plurality of fin structures, wherein a trench is formed between adjacent fin structures, and the bottom of the trench is filled with a shallow trench isolation structure 27; forming a dummy gate structure 25 above the shallow trench isolation structure 27, the dummy gate structure 25 spanning the plurality of fin structures; removing portions of the plurality of fin structures that are not covered by the dummy gate structure 25; removing the semiconductor substrate wrapped by the shallow trench isolation structure 27 to form a first recess; forming a placeholder structure 1 in the first recess; and forming a transistor group 21 above the placeholder structure 1 based on the plurality of fin structures.

[0101] It can be understood that by etching the semiconductor substrate to form the fin structures and the shallow trench isolation structure 27, and then defining the protection area using the dummy gate structure 25, the unprotected fin structures and the substrate thereunder are selectively removed to form a recess, and the placeholder structure 1 is filled as a support, and finally the transistor group 21 is constructed above the placeholder structure 1. The core role of the placeholder structure 1 can be to act as a sacrificial structure to provide spatial support and self-alignment definition for the precise formation of the metal contact structure 15, and finally to achieve high-performance metal interconnection.

[0102] In some embodiments, step 704 can include: removing the placeholder structure 1 to form a second recess, wherein the bottom of the second recess is composed of the first drain structure and / or the second drain structure; forming a metal contact structure 15 in the second recess; forming a back source-drain metal 16 above the metal contact structure 15; and forming a back interconnection layer 23 above the back source-drain metal 16.

[0103] It can be understood that after the film is developed, the placeholder structure 1 is removed from the back of the wafer to obtain the second recess with the bottom composed of the first drain structure and / or the second drain structure, and then the metal is deposited in the second recess to form the metal contact structure 15, and then the back source-drain metal 16 and the back interconnection layer 23 are sequentially stacked, which can complete the construction of the back power supply network.

[0104] Here, the placeholder structure 1 defines the second recess (i.e., the via for forming the metal contact structure 15) at one time, simplifying the process and tending to zero overlay error; and the second recess is self-aligned with the drain, which has low interface resistance and high uniformity.

[0105] In some embodiments, step 704 can include: simultaneously forming a source-drain direct metal 18 and a gate direct metal 19 above the metal interconnection structure using the same semiconductor manufacturing process.

[0106] It can be understood that, after the metal interconnection structure is completed, the via holes respectively aligned with the lower metal interconnection structure and the gate structure can be etched at one time. Then, the metal is deposited in the via holes, and the source-drain direct metal 18 and the gate direct metal 19 are formed at the same time. The source-drain direct metal 18 is connected to the first drain structure through the metal interconnection structure, and the gate direct metal 19 is connected to the second gate structure directly; and / or, the source-drain direct metal 18 is connected to the second drain structure through the metal interconnection structure, and the gate direct metal 19 is connected to the first gate structure directly.

[0107] In some embodiments, when the decoupling capacitor unit further comprises the intermediate interconnection structure, the step 704 can comprise: simultaneously forming the source-drain direct metal 18, the intermediate interconnection structure and the gate direct metal 19 above the metal interconnection structure by using the same semiconductor manufacturing process.

[0108] It can be understood that, after the metal interconnection structure is completed, the via holes respectively aligned with the lower metal interconnection structure and the gate structure, and the intermediate interconnection structure groove can be etched at one time. Then, the metal is deposited in the via holes and the intermediate interconnection structure groove, and the source-drain direct metal 18, the intermediate interconnection structure and the gate direct metal 19 are formed at the same time.

[0109] In some embodiments, the step 702 can comprise: electrically connecting the first power rail 221 in the front interconnection layer 22 to the first transistor 211, and electrically connecting the second power rail 222 in the front interconnection layer 22 to the second transistor 212.

[0110] It can be understood that the connection mode of the first power rail 221 to the first transistor 211 and the connection mode of the second power rail 222 to the second transistor 212 can refer to the description in any one of the embodiments of the first aspect, and will not be described here for the sake of brevity of the description.

[0111] In some embodiments, the first power rail 221 and / or the second power rail 222 are located in the M0 metal layer in the front interconnection layer, which facilitates the electrical connection with the transistor.

[0112] In the following, the decoupling capacitor unit and the preparation method thereof in the embodiments of the present application are described with specific examples.

[0113] Figures 8 to 16 is a preparation flow diagram of the decoupling capacitor unit according to an exemplary embodiment. In which, Figure 3 (a) in (a) of the decoupling capacitor unit along Figures 8 to 16 the cross-sectional view of the A-A' section shown in; Figure 3 (b) in (b) of the decoupling capacitor unit along Figures 8 to 16 the cross-sectional view of the B-B' section shown in; Figure 3 (c) in (c) of the decoupling capacitor unit along Figures 8 to 16A cross-sectional view of the C-C' plane shown; Figure 3 (d) in FIG. 1C shows the decoupling capacitor unit along Figure 8 A cross-sectional view of the D-D' plane shown. See Figure 9 to form Figure 10 As shown in the decoupling capacitor unit, the preparation method of the decoupling capacitor unit can include the following steps.

[0114] The first step, using the semiconductor substrate 30, according to the standard GAA process, until the side wall structure 26 in the transistor is formed, as shown in the structure of Figure 11 .

[0115] Here, the standard GAA process can include etching the semiconductor substrate 30 to form fin structures, forming shallow trench isolation structures 27 between adjacent fin structures, forming a pseudo gate structure 25 spanning multiple fin structures above the shallow trench isolation structures 27, and removing portions of the multiple fin structures not covered by the pseudo gate structure 25.

[0116] The second step, etching the semiconductor substrate 30 below the removed fin structure to form a first recess, and depositing and etching back the corresponding material in the first recess to form a placeholder structure 1, as shown in the structure of Figure 12 .

[0117] In some embodiments, the lower surface of the first recess can be flush with the lower surface of the shallow trench isolation structure 27. In some embodiments, the material forming the placeholder structure 1 can be selected according to actual needs, which is not limited in the embodiments of the present application.

[0118] The third step, according to the standard GAA process, on the placeholder structure 1, continue to complete the front-end process (FEOL) and middle process (MOL) of the transistor, until the front M0 metal is formed, as shown in the structure of Figure 17 .

[0119] Here, the front M0 metal is included in the front interconnection layer 22. The front M0 metal includes a first power rail 221 and a second power rail 222. The first power rail 221 can be connected to the first source structure 12 through the front source-drain metal 28, and the second power rail 222 can be connected to the second source structure 13 through the front source-drain metal 28.

[0120] The fourth step, using BEOL to form a front high layer metal layer in the front interconnection layer 22, as shown in the structure of Figure 1 .

[0121] Here, the front high layer metal layer can be a metal layer above the front M1 metal layer, such as the M1 metal layer, the M2 metal layer, etc. Only the M1 metal layer is shown in the figure.

[0122] Fifth step, after bonding the wafer 24 and the front interconnection layer 22, the semiconductor substrate 30 is thinned by CMP, and the structure as shown in Fig. 8 is obtained. Figure 17

[0123] Here, the CMP removes the semiconductor substrate 30 under the placeholder structure 1, and stops at the lower surface of the shallow trench isolation structure 27.

[0124] An exemplary, Figure 13 is a top view of a decoupling capacitor unit according to an exemplary embodiment Figure 18 . Referring to Figure 2 , the placeholder structure 1 in PMOS and NMOS is located in the source-drain region.

[0125] Sixth step, through a photolithography process, the area where the placeholder structure 1 needs to be selectively removed and replaced by the metal contact structure 15 is exposed, and then a high-selectivity etching process is used to remove the placeholder structure 1 in the area and fill metal at the position where the placeholder structure 1 is removed to form the metal contact structure 15, and the structure as shown in Fig. 9 is obtained. Figure 14

[0126] Here, the formation of the metal contact structure 15 can form a connection path with the transistor source-drain structure from the back of the wafer.

[0127] An exemplary, Figure 19 is a top view of a decoupling capacitor unit according to an exemplary embodiment Figure 3 . Referring to Figure 19 , the area inside the dashed box is exposed by photolithography. The placeholder structure 1 has good self-alignment characteristics in the x and y directions of the layout during this process. By removing the placeholder structure 1 inside the dashed box, the metal contact structure 15 can be formed self-aligned.

[0128] Seventh step, on the metal contact structure 15, the back source-drain metal 16, the source-drain direct connection metal 18 and the gate direct connection metal 19 are formed in sequence, and the structure as shown in Fig. 10 is obtained. Figure 15

[0129] ​​​Here, one end of the back-side source-drain metal 16 can be connected with the metal contact structure 15 connecting the first drain structure 11, and the other end can be connected with one end of the source-drain direct metal 18; the other end of the source-drain direct metal 18 is connected with the signal metal line 232 of the back-side interconnection layer 23, and the signal metal line 232 is connected with the second gate structure 172 through the gate direct metal 19. And / or, one end of the back-side source-drain metal 16 can be connected with the metal contact structure 15 connecting the second drain structure 14, and the other end can be connected with one end of the source-drain direct metal 18; the other end of the source-drain direct metal 18 is connected with the signal metal line 232 of the back-side interconnection layer 23, and the signal metal line 232 is connected with the first gate structure 171 through the gate direct metal 19.

[0130] Exemplarily, Figure 20 is a top view of a decoupling capacitor unit according to an exemplary embodiment Figure 4 . Referring to Figure 20 , the back-side source-drain metal 16 extending horizontally to the NMOS can be formed above the metal contact structure 15 of the PMOS. The back-side source-drain metal 16 extending horizontally to the PMOS can be formed above the metal contact structure 15 of the NMOS. Meanwhile, the source-drain direct metal 18 is formed between the back-side source-drain metal 16 and the signal metal line 232, and the gate direct metal 19 is formed between the gate structure and the signal metal line 232.

[0131] In the eighth step, the MOL is continued to be completed according to the standard GAA process until the M0 metal of the back side is formed, and a structure as shown in Figure 16 is obtained.

[0132] Here, the M0 metal of the back side is included in the back-side interconnection layer 23. The M0 metal of the back side includes the signal metal line 232. The signal metal line 232 can be connected with the gate direct metal 19 connecting the first gate structure 171 and the source-drain direct metal 18 connecting the second drain structure 14 at the same time; and / or, the signal metal line 232 can be connected with the gate direct metal 19 connecting the second gate structure 172 and the source-drain direct metal 18 connecting the first drain structure 11 at the same time.

[0133] Exemplarily, ​ is a top view of a decoupling capacitor unit according to an exemplary embodiment ​ . Referring to ​ , the signal metal line (such as the back-side M0 metal (BSM0)) connects the source-drain direct metal 18 and the gate direct metal 19, realizing the connection of the first gate structure 171 to the second drain structure 14 and the connection of the second gate structure 172 to the first drain structure 11.

[0134] The ninth step is to form a back high layer metal layer in the back interconnection layer 23 by BEOL to obtain a structure as shown in FIG. 8. ​

[0135] Here, the back high layer metal layer can be a metal layer above the back M1 metal layer, such as the M1 metal layer, the M2 metal layer, etc. Only the M1 metal layer is schematically shown in the figure.

[0136] The tenth step is to flip the structure prepared in the ninth step so that the wafer front surface is on top and the wafer back surface is on the bottom. In this way, the front interconnection layer 22 is above the transistor group 21 in the vertical direction, and the back interconnection layer 23 is below the transistor group 21 in the vertical direction.

[0137] Up to now, the preparation of the decoupling capacitor unit is completed.

[0138] In the embodiments of the present application, a single transistor design with a power rail arranged on the wafer front surface and a back interconnection implemented by a placeholder structure is used to implement a decoupling capacitor unit circuit that requires both NMOS and PMOS. The focus is to remove the placeholder structure by adding one step of photolithography to achieve partial removal of the placeholder structure, thereby increasing the degree of freedom of design; the wafer front surface mainly completes the connection of NMOS and PMOS with the power rail, while the wafer back surface uses BSM0 to implement the remaining connection, which can also be implemented by a cross-coupling (Cross Couple) structure (i.e., when BSVD and BSVG are made on BSMD, the through holes of the two are directly connected by etching process, thereby realizing the direct connection of BSMD and the metal gate without using M0 metal).

[0139] In addition, the semiconductor preparation method in the embodiments of the present application can be applied to the next generation of integrated circuit processes, especially to single transistor with double-sided interconnection. The interconnection scheme of the back signal line and the transistor (such as using Placeholder, using Placeholder and BSMD at the same time, using only BSMD, etc.) does not affect the implementation of the present patent.

[0140] Further, the decoupling capacitor unit 20 provided by the embodiments of the present application can be detected by detection analysis instruments, such as a scanning electron microscope (scanning electron microscope, SEM), a transmission electron microscope (transmission electron microscope, TEM), a scanning transmission electron microscope (scanning transmission electron microscopy, STEM), etc.

[0141] ​Taking TEM as an example, the embodiment of the present application can adopt the TEM slice mode to detect the decoupling capacitor unit. On the cross section of the height of the layout and the placeholder structure, it can be seen that not all placeholder structures are removed, and the placeholder structure connection replaced by metal within a standard decoupling capacitor unit height is zigzag. On the cross section of the height of the layout and BSMD, BSVD, BSVG and BSM0, it can be seen that on the back of the wafer, the drain of the PMOS is connected to the gate of the corresponding NMOS through the back metal interconnection structure, and the drain of the NMOS is connected to the gate of the corresponding PMOS. The connection of the source of the corresponding NMOS and PMOS to the power rail is realized on the front of the wafer.

[0142] In a third aspect, the embodiment of the present application provides an electronic device, comprising a circuit board and a chip as described in the above embodiments, and the decoupling capacitor unit 20 is arranged on the circuit board.

[0143] The above is only an embodiment of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement and improvement within the spirit and scope of the present application are included in the protection scope of the present application.

Claims

1. A decoupling capacitor unit, characterized in that, include: A transistor array includes a first transistor and a second transistor arranged in a horizontal direction. The first transistor includes a first source structure, a first drain structure, and a first gate structure. The second transistor includes a second source structure, a second drain structure, and a second gate structure. A front interconnect layer is located vertically above the transistor group; wherein the power metal lines in the front interconnect layer are respectively connected to the first source structure and the second source structure; A back interconnect layer is located vertically below the transistor group, wherein the back interconnect layer includes signal metal lines that electrically connect the first gate structure and the second gate structure; A metal interconnect structure located between the back interconnect layer and the transistor group, wherein one end of the metal interconnect structure is connected to the first drain structure, and the other end extends along the horizontal direction toward the second transistor and is connected to a signal metal line connected to the second gate structure; and one end of the metal interconnect structure is connected to the second drain structure, and the other end extends along the horizontal direction toward the first transistor and is connected to a signal metal line connected to the first gate structure.

2. The decoupling capacitor unit according to claim 1, characterized in that, The metal interconnect structure includes: a metal contact structure and a back-side source / drain metal; Wherein, one end of the metal contact structure is connected to the first drain structure, and the other end extends along the vertical direction toward the back interconnect layer; one end of the back source / drain metal is connected to the metal contact structure connected to the first drain structure, and the other end extends along the horizontal direction toward the second transistor and is connected to the signal metal line connected to the second gate structure; and / or, One end of the metal contact structure is connected to the second drain structure, and the other end extends toward the back interconnect layer along the vertical direction; one end of the back source / drain metal is connected to the metal contact structure connected to the second drain structure, and the other end extends toward the first transistor along the horizontal direction and is connected to the signal metal line connected to the first gate structure.

3. The decoupling capacitor unit according to claim 2, characterized in that, The metal contact structure is located below the first drain structure and / or the second drain structure in the vertical direction; The metal contact structure is formed by removing the occupant structure and filling the location where the occupant structure was removed with metal material.

4. The decoupling capacitor unit according to claim 1 or 2, characterized in that, The decoupling capacitor unit further includes: source-drain direct-connect metal and gate direct-connect metal; Wherein, the source-drain direct connection metal is located between the metal interconnect structure connecting the first drain structure and the signal metal line connecting the second gate structure; the gate direct connection metal is located between the signal metal line connecting the second gate structure and the second gate structure; and / or, The source-drain direct connection metal is located between the metal interconnect structure connecting the second drain structure and the signal metal line connecting the first gate structure; the gate direct connection metal is located between the signal metal line connecting the first gate structure and the first gate structure.

5. The decoupling capacitor unit according to claim 4, characterized in that, The decoupling capacitor unit further includes: an intermediate interconnection structure; The intermediate interconnect structure is located between the source / drain direct-connect metal and the gate direct-connect metal, and is used to connect the source / drain direct-connect metal and the gate direct-connect metal; The intermediate interconnect structure, the source-drain direct-connect metal, and the gate direct-connect metal are formed using the same semiconductor fabrication process.

6. A method for fabricating a decoupling capacitor unit, characterized in that, Used to prepare the decoupling capacitor unit according to any one of claims 1 to 5; The preparation method includes: A transistor array is formed above a semiconductor substrate; A front interconnect layer is formed above the transistor group; The wafer is flipped and the semiconductor substrate is removed; A metal interconnect structure and a back interconnect layer are sequentially formed above the transistor group.

7. The preparation method according to claim 6, characterized in that, The formation of a transistor array over a semiconductor substrate includes: A semiconductor substrate is etched to form multiple fin structures, wherein trenches are formed between adjacent fin structures and the bottom of the trenches is filled with shallow trench isolation structures. A pseudo-gate structure is formed above the shallow trench isolation structure, spanning the plurality of fin structures; Remove the portions of the plurality of fin structures that are not covered by the pseudo-gate structure; Remove the semiconductor substrate enclosed by the shallow trench isolation structure to form the first groove; A spacer structure is formed within the first groove; The transistor array is formed on the spacer structure based on the plurality of fin structures.

8. The preparation method according to claim 7, characterized in that, The formation of a metal interconnect structure and a back interconnect layer above the transistor group includes: Remove the occupier structure to form a second groove, wherein the bottom of the second groove is formed by a first drain structure and / or a second drain structure; A metal contact structure is formed within the second groove; A back-side source / drain metal is formed above the metal contact structure; The back interconnect layer is formed above the back source / drain metal.

9. The preparation method according to claim 6 or 7, characterized in that, When the decoupling capacitor unit further includes source-drain direct-connect metal and gate-direct-connect metal, a metal interconnect structure and a back-side interconnect layer are formed above the transistor group, including: Using the same semiconductor fabrication process, source-drain direct-connect metal and gate direct-connect metal are simultaneously formed above the metal interconnect structure.

10. An electronic device, characterized in that, Includes a circuit board and a decoupling capacitor unit as described in any one of claims 1 to 5.

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