Design and preparation method of low dark count semiconductor single-photon detector

Abstract

The invention provides a design and preparation method of a low-dark-count semiconductor single-photon detector, and belongs to the technical field of detectors, and the low-dark-count semiconductor single-photon detector comprises a substrate; the first P-type doped well is positioned in the central active region of the substrate; the first N-type doped well is positioned in the central active region and is partially overlapped with the first P-type doped well in the vertical direction so as to form an avalanche PN junction; the second N-type doped well is arranged in the first N-type doped well and is used for forming a cathode; the second P-type doped well is positioned on the periphery of the central active region and is used for forming an anode; and the third P-type doped well is positioned on the periphery of the central active region, and the second P-type doped well is positioned above the third P-type doped well in the vertical direction. According to the semiconductor single-photon detector, a high-electric-field avalanche region is mainly distributed in the first P-type doped well HVPW by using a refined design, a peak electric field is suppressed, tunneling dark count is reduced, and thus the semiconductor single-photon detector can perform single-photon detection under low dark count.

Description

Technical Field

[0001] This invention relates to the field of detector technology, and in particular to a design and fabrication method for a low-darkness-count semiconductor single-photon detector. Background Technology

[0002] With the development of quantum information science and technology and the popularization of lidar and ranging technologies, the demand for extremely weak light detection is increasing. Single photon detection is an important technical means to meet these needs.

[0003] Among them, semiconductor single-photon detectors, such as single-photon avalanche diodes (SPADs), are the core components of their optical receiving modules and play an important role in single-photon detection systems.

[0004] Dark count is a core parameter in the field of single-photon detection that characterizes the noise level of a detector. It is defined as the number of false trigger pulses caused by thermal fluctuations, electrical noise, or stray light when no photons are incident.

[0005] The semiconductor single-photon detectors in the relevant technical solutions have a relatively high dark count, which cannot meet the requirements for single-photon detection under low dark count conditions. Summary of the Invention

[0006] This invention provides a design and fabrication method for a low dark count semiconductor single-photon detector, which solves the problem that the dark count ratio of semiconductor single-photon detectors in related technical solutions is too high to meet the requirements of single-photon detection under low dark count conditions.

[0007] This invention provides a low-darkness-count semiconductor single-photon detector, comprising: Substrate; The first P-type doped well is located in the central active region of the substrate; The first N-type doped well is located in the central active region and partially overlaps with the first P-type doped well in the vertical direction to form an avalanche PN junction. The vertical direction refers to the direction extending from the substrate surface to the interior of the substrate. The second N-type doped well is disposed inside the first N-type doped well and is used to form a cathode; The second P-type doped well is located on the periphery of the central active region and is used to form the anode; The third P-type doped well is located on the periphery of the central active region, and in the vertical direction, the second P-type doped well is located above the third P-type doped well; The diameter of the first N-type doped well is larger than the diameter of the first P-type doped well, and the doping concentration of the first N-type doped well is larger than the doping concentration of the first P-type doped well.

[0008] In the low-darkness counting semiconductor single-photon detector provided by this invention, the doping concentration of the second N-type doped well is greater than the doping concentration of the first N-type doped well; and / or The doping concentration of the second P-type doped well is greater than that of the first P-type doped well and the third P-type doped well.

[0009] In the low-dark-count semiconductor single-photon detector provided by the present invention, in the vertical direction, the bottom of the first P-type doped well is deeper than the bottom of the first N-type doped well.

[0010] In the low-darkness counting semiconductor single-photon detector provided by the present invention, the ring width of the second P-type doped well is smaller than the ring width of the third P-type doped well; and / or The bottom of the third P-type doped well is deeper than the bottom of the second P-type doped well.

[0011] The low-darkness counting semiconductor single-photon detector provided by the present invention further includes: A first isolation layer is formed with the third P-type doped well to create a receiving trench, and the second P-type doped well is located within the receiving trench.

[0012] The low-darkness counting semiconductor single-photon detector provided by the present invention further includes: The second isolation layer is in contact with the back of the substrate and is located on the periphery of the central active region; The structural depth of the second isolation layer is greater than that of the first isolation layer.

[0013] The low-darkness counting semiconductor single-photon detector provided by the present invention further includes: A back-illuminated metal grid, in contact with the second isolation layer, is located on the periphery of the central active region and on the opposite side to the third P-type doped well.

[0014] This invention provides a method for fabricating a low-darkness-count semiconductor single-photon detector as described in any of the above-described methods, the method comprising: A base substrate is provided, wherein the base substrate has undergone pretreatment; Photolithography and ion implantation are performed on the base substrate to form a first P-type doped well, a first N-type doped well, and a second N-type doped well in the central active region of the base substrate, and a second P-type doped well and a third P-type doped well are formed around the central active region to obtain a doped substrate. The first N-type doped well and the first P-type doped well partially overlap in the vertical direction to form an avalanche PN junction. The second N-type doped well is disposed inside the first N-type doped well. The third P-type doped well and the second P-type doped well partially overlap in the vertical direction. The diameter of the first N-type doped well is larger than the diameter of the first P-type doped well, and the doping concentration of the first N-type doped well is larger than the doping concentration of the first P-type doped well. The doped substrate is subjected to at least one photolithography process to form an anode and a cathode on the doped substrate.

[0015] The preparation method provided by this invention includes the following pretreatment steps: Etching is performed on the substrate to form etching trenches on the substrate; The etched trenches are passivated. After passivation, the etched trenches are filled with silicon dioxide, and the filled substrate is planarized to form a first isolation layer on the substrate.

[0016] In the preparation method provided by the present invention, after forming the anode and cathode on the doped substrate, the preparation method further includes: The doped substrate is bonded to a support wafer; Thinning is performed from the back side of the doped substrate; A second isolation layer and a back-illuminated metal grid are formed on the back of the thinned doped substrate.

[0017] The present invention provides a design and fabrication method for a low dark count semiconductor single-photon detector, wherein a first N-type doped well and a first P-type doped well partially overlap in the vertical direction to form an avalanche PN junction. Since the doping concentration of the first N-type doped well is greater than that of the first P-type doped well, the avalanche region can be moved away from the surface, reducing the surface dark count assisted by surface defects. Furthermore, the diameter of the first N-type doped well is greater than that of the first P-type doped well, which can suppress the peak electric field and reduce the tunneling dark count, thereby enabling the semiconductor single-photon detector to perform single-photon detection under low dark count conditions. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is one of the structural schematic diagrams of the low-darkness counting semiconductor single-photon detector provided by the present invention; Figure 2 This is the second schematic diagram of the structure of the low-darkness counting semiconductor single-photon detector provided by the present invention; Figure 3 This is one of the schematic flowcharts of the preparation method provided by the present invention; Figure 4 This is a schematic diagram of the preprocessing process provided by the present invention; Figure 5 This is the second schematic diagram of the preparation method provided by the present invention; Figure 6 A schematic diagram illustrating the doping distribution of different traps within a pixel is shown. Figure 7 The current-voltage characteristic curves of the tested single-photon detector are schematically shown. The three curves in the figure are the dark current, photocurrent, and dark current of the external quenching resistor, respectively. Figure 8 The diagram illustrates the dark count of a single-photon detector under different overbias voltages and a schematic diagram of the dark count per unit area. Figure 9 The diagram illustrates the detection efficiency of a single-photon detector for 905 nm and 940 nm light under different overbias conditions. Figure 10 The diagram illustrates the detection efficiency of a single-photon detector for wavelengths from 300 nm to 1100 nm under a tested over-biased voltage of 2V.

[0020] Figure label: 101. Substrate; 102. Dielectric layer; 103. Back passivation SiO2 layer; 104. Back passivation High K layer; HVPW, first P-type doped well; Nwell, first N-type doped well; N++, second N-type doped well; P++, second P-type doped well; DPW, third P-type doped well; STI, first isolation layer; DTI, second isolation layer; BMG, back-illuminated metal grid; Anode, anode; Cathode, cathode. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0022] It should be noted that in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The terms "upper," "lower," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0023] The terms "first," "second," etc., used in this invention are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0024] The following is combined with Figures 1-10 The present invention describes the design and fabrication method of a low dark count semiconductor single-photon detector, which aims to solve the problem that the dark count ratio of semiconductor single-photon detectors in related technical solutions is too high to meet the requirements of single-photon detection under low dark count conditions.

[0025] Figure 1 This is one of the structural schematic diagrams of the low-darkness counting semiconductor single-photon detector provided by the present invention. Figure 2 This is the second schematic diagram of the structure of the low-darkness counting semiconductor single-photon detector provided by the present invention, as shown below. Figure 1 and Figure 2 As shown, it includes: Substrate 101; The first P-type doped well HVPW is located in the central active region of substrate 101; The first N-type doped well, Nwell, is located in the central active region and partially overlaps with the first P-type doped well, HVPW, in the vertical direction to form an avalanche PN junction. The vertical direction refers to the direction extending from the substrate surface to the interior of the substrate. The second N-type doped well N++ is located inside the first N-type doped well Nwell and is used to form a cathode. The second P-type doped well, P++, is located on the periphery of the central active region and is used to form the anode. The third P-type doped well DPW is located on the periphery of the central active region. In the vertical direction, the second P-type doped well P++ is located above the third P-type doped well DPW. The diameter of the first N-type doped well (Nwell) is larger than the diameter of the first P-type doped well (HVPW), and the doping concentration of the first N-type doped well (Nwell) is greater than the doping concentration of the first P-type doped well (HVPW).

[0026] Specifically, such as Figure 2 As shown, the diameter W of the first N-type doped well (Nwell) LGN The diameter W is greater than that of the first P-type doped well HVPW. LGP The diameter W of the second N-type doped well N++ NPP The diameter W is greater than that of the first P-type doped well HVPW. LGP And smaller than the diameter W of the first N-type doped well Nwell LGN .

[0027] In this embodiment, the first N-type doped well (Nwell) and the first P-type doped well (HVPW) partially overlap in the vertical direction to form an avalanche PN junction. Since the doping concentration of the first N-type doped well (Nwell) is greater than that of the first P-type doped well (HVPW), the avalanche region can be moved away from the surface, reducing the surface dark count assisted by surface defects. Furthermore, the diameter of the first N-type doped well (Nwell) is greater than that of the first P-type doped well (HVPW), which can suppress the peak electric field and reduce the tunneling dark count, thereby enabling the semiconductor single-photon detector to perform single-photon detection at low dark counts.

[0028] Specifically, since the doping concentration of the first N-type doped well (Nwell) is greater than that of the first P-type doped well (HVPW), under over-bias, the depletion region of the avalanche PN junction expands to form the main high-electric-field working region. The depletion region mainly expands towards the low-doped side, so that the high-electric-field avalanche region is mainly distributed in the first P-type doped well (HVPW), far away from the silicon wafer surface, which usually contains a large number of defects and traps.

[0029] The diameter of the first N-type doped well (Nwell) is larger than that of the first P-type doped well (HVPW), resulting in a negative curvature in the junction edge region. Furthermore, due to the lower substrate 101 concentration, the depletion region of the guard ring expands faster, thus confining the electric field peak to a flat central region. This avoids the spike electric field generated at the junction edge due to electric field concentration, effectively suppressing the tunneling effect related to the electric field intensity and reducing the tunneling dark count.

[0030] In the above embodiments, by setting a third P-type doped well (DPW) in the vertical direction around the central active region, electric field isolation between different pixels can be achieved, thereby suppressing crosstalk between different pixels. The pixel is also the low dark count semiconductor single-photon detector in this invention.

[0031] In the low-darkness counting semiconductor single-photon detector provided by this invention, the doping concentration of the second N-type doped well N++ is greater than the doping concentration of the first N-type doped well Nwell; and / or The doping concentration of the second P-type doped well P++ is greater than that of the first P-type doped well HVPW and the third P-type doped well DPW.

[0032] In this embodiment, the second N-type doped well N++ and the second P-type doped well P++ are used to form the cathode and anode, respectively. Since both are highly doped wells with relatively high doping concentrations, they can form good ohmic contacts.

[0033] Specifically, to ensure a low-resistance, high-efficiency electrical connection—that is, a good ohmic contact—is formed between the external electrode (e.g., a metal electrode) and the semiconductor region, a heavily doped region is typically created at the interface between the electrode and the semiconductor. A good ohmic contact avoids the formation of undesirable barriers (such as Schottky barriers) at the contact point, thereby reducing parasitic resistance and ensuring that the signal can be extracted efficiently and without distortion. This embodiment is based on this principle, and the doping concentrations of the second N-type doped well N++ and the second P-type doped well P++ are specifically designed.

[0034] In some embodiments, the first N-type doped well (Nwell) is the main N-type region constituting the PN junction, and its doping concentration needs to be precisely controlled to optimize the electric field distribution. The second N-type doped well (N++) serves as the contact region of the cathode, and its core function is to achieve low contact resistance. By employing, for example, a high-dose, low-energy ion implantation process, a region shallower but with a much higher doping concentration than the first N-type doped well (Nwell) can be formed.

[0035] As a specific, non-limiting example, the peak doping concentration of the first N-type doped well (Nwell) can be set to 1e-1. 18 cm -3 The order of magnitude, while the peak doping concentration of the second N-type doped well N++ can be set to be no less than 1e 20 cm -3 This ensures excellent ohmic contact between the electrode and the subsequently formed cathode metal electrode.

[0036] Similar to the function of the second N-type doped well N++, the second P-type doped well P++ serves as the contact region for the anode. The first P-type doped well HVPW, as a major component of the avalanche region, is designed with a low doping concentration (e.g., 1e). 17 cm -3 The first P-type doped well (P++) is used to control the broadening of the depletion region; the second P-type doped well (DPW) serves as an isolation well, with a moderate doping concentration to achieve isolation without excessively affecting the electrical characteristics of the central active region. Therefore, to provide a low-resistance contact point for the anode, the doping concentration of the second P-type doped well (P++) needs to be much higher than the first two. For example, its peak doping concentration can also be set to be no less than 1e-1. 20 cm -3 .

[0037] In some embodiments, the depths of the second N-type doped well N++ and the second P-type doped well P++ are between 100 nm and 200 nm.

[0038] In some embodiments, the doping concentration of the second N-type doped well N++ and the second P-type doped well P++ is higher than 1e. 20 cm -3 .

[0039] In this process, by heavily doping the second N-type doped well N++ and the second P-type doped well P++ used for ohmic contacts, the solution provided in this embodiment can significantly reduce the contact resistance of the cathode and anode, and reduce the parasitic series resistance of the device. This not only ensures the accurate application of the device operating voltage and the efficient extraction of avalanche signals, but also improves the overall electrical performance of the device. For example, when used in conjunction with a quenching circuit, it can achieve faster quenching and recovery speeds, thereby increasing the maximum count rate of the detector.

[0040] In the low-dark-count semiconductor single-photon detector provided by the present invention, in the vertical direction, the bottom of the first P-type doped well HVPW is deeper than the bottom of the first N-type doped well Nwell.

[0041] The vertical direction refers to the direction extending from the surface of substrate 101 into the interior of substrate 101.

[0042] In this embodiment, in order to further optimize the electric field distribution of the avalanche PN junction and ensure that the avalanche multiplication process occurs stably and efficiently in the preset region, this embodiment has made a specific design on the relative depth relationship of the first P-type doped well HVPW and the first N-type doped well Nwell in the vertical direction.

[0043] Here, "bottom" refers to the deepest position of the doping concentration profile distribution of the doped well in the direction perpendicular to the surface of substrate 101.

[0044] First, as described in the previous embodiment, the first N-type doped well (Nwell) and the first P-type doped well (HVPW) form an avalanche PN junction through partial overlap. Since the first P-type doped well (HVPW) has a lower doping concentration, the depletion region under reverse bias primarily extends inwards. By designing the first P-type doped well (HVPW) to be deeper, sufficient space can be provided for the expansion of the depletion region. This ensures that even under high overbias, the depletion region can be completely contained within the first P-type doped well (HVPW) without touching the underlying epitaxial layer or substrate 101. This is crucial for avoiding the punch-through effect caused by the depletion region touching the substrate 101, thereby ensuring the stability and reliability of the device operation.

[0045] Secondly, this combination of shallow N-well and deep P-well structure firmly establishes the physical location of the avalanche PN junction at the boundary between the bottom of the first N-type doped well (Nwell) and the upper half of the first P-type doped well (HVPW). When photons are incident, photogenerated carriers (electron-hole pairs) generated throughout the epitaxial layer, especially those generated at deeper locations, will be guided by the electric field to drift to the avalanche region. The deeper design of the first P-type doped well (HVPW) helps to increase the carrier collection volume, thereby improving the detection efficiency for long-wavelength photons (such as red and near-infrared light) because these long-wavelength photons have a greater penetration depth in silicon.

[0046] In this embodiment, by designing the bottom of the first P-type doped well (HVPW) to be deeper than the first N-type doped well (Nwell), the solution provided by this embodiment not only provides sufficient space for the stable expansion of the depletion region and avoids device punch-through, but also optimizes the collection efficiency of photogenerated carriers, which helps to improve the overall photon detection efficiency of the device, especially in the long wavelength range. This design, combined with the aforementioned concentration and diameter design, works together to achieve a comprehensive performance of low dark count and high detection efficiency.

[0047] In the low-darkness counting semiconductor single-photon detector provided by this invention, such as Figure 2 As shown, the ring width W of the second P-type doped well P++ is... PPP The ring width W is smaller than that of the third P-type doped well DPW. PLG ; and / or The bottom of the third P-type doped well DPW is deeper than the bottom of the second P-type doped well P++.

[0048] In this embodiment, the relative geometric dimensions of the second P-type doped well P++ and the third P-type doped well DPW located on the periphery of the central active region were further optimized and defined.

[0049] The second P-type doped well P++ primarily serves as the ohmic contact region of the anode, while the third P-type doped well DPW mainly undertakes the task of electrical isolation between pixels. To enable these two functionally different doped wells to work together and achieve optimal results, this embodiment features a specific design for their relative ring width and depth.

[0050] In an alternative implementation, the ring width of the second P-type doped well P++ is designed to be smaller than the ring width of the third P-type doped well DPW. Here, the ring width refers to the radial width of the two ring-shaped doped wells on the substrate 101 plane. The second P-type doped well P++, acting as a contact region, only needs a ring width sufficient to meet the alignment and connection requirements in subsequent anode electrode fabrication processes; an excessively large ring width is unnecessary and may even increase parasitic capacitance. The third P-type doped well DPW, acting as an isolation wall, needs a sufficiently large ring width to form a sufficiently wide and effective P-type isolation band within the bulk silicon of the device, blocking lateral carrier drift between adjacent pixels and thus more effectively suppressing electrical crosstalk. Therefore, designing the ring width of the second P-type doped well P++ to be narrower than that of the third P-type doped well DPW below it is an optimized design that matches function and structure.

[0051] In another alternative implementation, or in combination with the above, the bottom of the third P-type doped well (DPW) is designed to be deeper than the bottom of the second P-type doped well (P++). This depth relationship is also a direct reflection of their different functions. The second P-type doped well (P++) only needs to form a heavily doped region on the outermost layer of substrate 101 to achieve good ohmic contact, and is therefore typically designed as a very shallow well, for example, with a depth of only 100 to 200 nanometers. In contrast, the mission of the third P-type doped well (DPW) is to block electrical crosstalk paths that may occur deep in bulk silicon, and therefore it must be designed as a well deep enough to intercept these crosstalk paths to the maximum extent. For example, this deep P-well can be formed by one or more high-energy ion implantation processes, ensuring that its depth is much greater than that of a shallow contact well.

[0052] In one implementation, the two geometric relationships described above are used simultaneously, forming a narrow-ring, shallow second P-type doped well P++, which sits on a wide-ring, deep third P-type doped well DPW, and the two are typically designed to be concentric.

[0053] By employing such a specific synergistic design of the ring width and depth of the second P-type doped well P++ and the third P-type doped well DPW, the solution provided in this embodiment ensures a low-resistance ohmic contact for the anode while also constructing a more robust and effective deep electrical isolation structure. This layout maximizes the crosstalk suppression capability of the isolation wells while reducing the parasitic effects that contact wells may introduce, which is of great significance for improving the signal-to-noise ratio and signal independence of the entire detector array.

[0054] The low-darkness counting semiconductor single-photon detector provided by this invention further includes: The first isolation layer STI forms a receiving trench with the third P-type doped well DPW, and the second P-type doped well P++ is located in the receiving trench.

[0055] In this embodiment, although electrical isolation is constructed within the bulk silicon of the device using a third P-type doped well (DPW), carriers may still form unwanted leakage current paths along the surface of the semiconductor device due to the possible presence of surface states, contaminants, or inversion layers. This surface leakage not only increases dark current but may also create surface crosstalk between adjacent pixels or between the anode and cathode of the same pixel, thereby degrading the detector's performance.

[0056] To address this issue, the low dark count semiconductor single-photon detector provided in this embodiment further includes a first isolation layer (STI). In the semiconductor manufacturing process, this structure is commonly referred to as Shallow Trench Isolation (STI). Its basic principle is to etch trenches of a predetermined shape onto the surface of the substrate 101 and fill the trenches with an insulating dielectric, thereby physically forming an insulating barrier to block any possible surface conductive pathways.

[0057] In this specific layout, the first isolation layer STI and the third P-type doped well DPW work together to form a receiving groove, within which the second P-type doped well P++ is located. Specifically, two annular shallow groove isolation structures can be provided: one inside the ring formed by the third P-type doped well DPW, and the other outside. Thus, the inner first isolation layer STI effectively isolates the second P-type doped well P++, which serves as the anode contact area, from the central active region (containing the cathode contact area, the second N-type doped well N++), suppressing surface leakage between the anode and cathode; while the outer first isolation layer STI isolates the entire pixel from adjacent pixels, effectively suppressing surface crosstalk between pixels. Therefore, the receiving groove here can be understood as an annular region defined by the inner and outer first isolation layers STI for housing the second P-type doped well P++.

[0058] In one approach, the trenches of the first insulating layer (STI) are filled with silicon dioxide, a material with excellent electrical insulation properties. The trench etching depth is typically 200 to 300 nanometers.

[0059] One important point to note is that the location and depth of the first isolation layer (STI) should be carefully designed to ensure that its bottom and sidewalls avoid direct contact with the depletion region of the avalanche PN junction. This is because the etching process of shallow trench isolation inevitably introduces lattice damage to the trench sidewalls. If these defective regions overlap with the high-electric-field depletion region, they will become strong dark current generation centers, which will severely degrade the dark counting performance of the device.

[0060] By introducing a first isolation layer (STI), this embodiment adds a robust surface isolation barrier to the bulk isolation (provided by a third P-type doped well (DPW)). This combined bulk and surface isolation scheme can more comprehensively and effectively suppress various leakage and crosstalk paths within and between devices, further significantly reducing the overall dark count of the detector and improving the signal-to-noise ratio and imaging quality of the detector array.

[0061] The low-darkness counting semiconductor single-photon detector provided by this invention further includes: The second isolation layer DTI is in contact with the back of the substrate 101 and is located on the periphery of the central active region; The structural depth of the second isolation layer DTI is greater than that of the first isolation layer STI.

[0062] To overcome the limitations on photon detection efficiency caused by the obstruction of the incident light path by the front-side metal wiring in traditional front-side illumination (FSI) devices, this invention employs a back-illuminated process. In this process, after the fabrication of the front-side structure (including various doped wells and the first isolation layer STI, etc.) of the device substrate 101, it is flipped, bonded to a support wafer, and thinned from its back side. Photons will then be incident from this thinned, unobstructed back side. However, this process also introduces new technical challenges, namely, optoelectronic crosstalk from the back side becomes a new problem that needs to be addressed, especially in high-density detector arrays. Secondary photons or drifting carriers generated during pixel avalanche may enter adjacent pixels through the back path, causing false counting.

[0063] To address this back-side crosstalk issue, the low-dark-count semiconductor single-photon detector provided in this embodiment further includes a second isolation layer (DTI). This structure is commonly referred to as Deep Trench Isolation (DTI). As the name suggests, the second isolation layer (DTI) is an isolation structure with a significantly greater depth than the first isolation layer (STI).

[0064] Specifically, the second isolation layer DTI is in contact with the back of the substrate 101 and is located on the periphery of the central active region.

[0065] In one embodiment, the second isolation layer DTI is positioned on the top-view projection at the same location as the first isolation layer STI on the front periphery, thus forming a vertically aligned isolation wall. The structural depth of the second isolation layer DTI is greater than that of the first isolation layer STI. For example, the depth of the first isolation layer STI may be several hundred nanometers, while the depth of the second isolation layer DTI can reach 400 nm or even deeper, such as 2000 nm, which is sufficient to penetrate most of the regions where photogenerated carriers may drift.

[0066] The second isolation layer DTI is formed by etching deep trenches on the back of the thinned substrate 101 and then filling them with appropriate isolation material.

[0067] In one embodiment, the trench is filled with a metal, such as tungsten (W). The metal-filled trench effectively suppresses photons from tilted incident light angles from entering other pixels, or photons generated during avalanches from entering other pixels, physically isolating back-side optical crosstalk. Before filling with metal, the sidewalls of the trench are typically passivated, for example, by growing a thin passivation medium (such as aluminum oxide, Al2O3) using atomic layer deposition (ALD) to repair etching damage and reduce interface states.

[0068] By adding a second isolation layer (DTI), this embodiment constructs a more complete and three-dimensional isolation system. It combines shallow trench isolation on the front surface, deep P-well isolation within the bulk, and deep trench metal isolation on the back, forming an isolation box that almost completely encloses each pixel. This structure can extremely effectively suppress electrical and optical crosstalk from the surface, bulk, and back simultaneously, thereby reducing the overall dark count level and crosstalk probability of the array to a much lower level, which is crucial for achieving high signal-to-noise ratio and high-resolution single-photon imaging.

[0069] The low-darkness counting semiconductor single-photon detector provided by this invention further includes: The back-illuminated metal grid BMG is in contact with the second isolation layer DTI and is located on the periphery of the central active region, opposite to the third P-type doped well DPW.

[0070] In this embodiment, optical crosstalk is a particularly critical and important issue to address in high-density single-photon detector arrays employing back-illuminated technology. Specifically, due to the tilt of the incident angle, photons that should have been incident on other pixels are instead incident on the current pixel.

[0071] The back-illuminated metal grid (BMG) is positioned on the back of the detector and contacts the second isolation layer (DTI). Its location is also on the periphery of the central active region, typically coinciding with the positions of the second isolation layer (DTI) and the front isolation structures (such as the first isolation layer (STI) and the third P-type doped well (DPW)) in a top-view projection.

[0072] In this specific structure, the back-illuminated metal grid (BMG) is located on the side opposite to the second isolation layer (DTI) and the third P-type doped well (DPW). To put it more clearly, if we define the front side of the device (the side containing the third P-type doped well DPW) as "top" and the back side as "bottom," then the back-illuminated metal grid (BMG) is located below the second isolation layer (DTI), i.e., closer to the back incident surface of the device. Typically, the width of the back-illuminated metal grid (BMG) is designed to be slightly wider than the underlying second isolation layer (DTI) to provide better coverage and shielding.

[0073] The essence of a back-illuminated metal grid (BMG) is to form a mesh-like metal structure on the back surface of the substrate 101 at the boundary of each pixel. This metal mesh is opaque, and its main function is to act as a physical barrier to block photons that should be incident on other pixels from entering the current pixel, thereby reducing optical crosstalk. This is equivalent to setting up a light-blocking curtain between each pixel at the photon entrance.

[0074] By further adding a back-illuminated metal grid (BMG), a dual back-side optical isolation system was constructed. The deep second isolation layer (DTI) (especially when metal-filled) works synergistically with the shallow BMG to form a continuous optical barrier extending from the back surface to the depths of the bulk silicon. This isolation design can more thoroughly suppress back-side optical crosstalk, which is of paramount value for applications requiring extremely low crosstalk probabilities, such as quantum imaging and long-range lidar, significantly improving the system's detection accuracy and reliability.

[0075] In some embodiments, the substrate 101 is a P-type doped substrate, and a weakly P-type doped epitaxial layer is epitaxially grown thereon, wherein the doping concentration of the P-type doped substrate is less than the doping concentration of the first P-type doped well HVPW.

[0076] This invention provides a method for fabricating a low-dark-count semiconductor single-photon detector as described in any of the above embodiments, such as... Figure 3 As shown, the preparation method includes: Step 301, provide a base substrate, which is a pretreated substrate; Step 302: Photolithography and ion implantation are performed on the base substrate to form a first P-type doped well, a first N-type doped well, and a second N-type doped well in the central active region of the base substrate, and a second P-type doped well and a third P-type doped well are formed in the periphery of the central active region to obtain a doped substrate.

[0077] The first N-type doped well and the first P-type doped well partially overlap in the vertical direction to form an avalanche PN junction. The second N-type doped well is located inside the first N-type doped well. The third P-type doped well and the second P-type doped well partially overlap in the vertical direction. The diameter of the first N-type doped well is larger than the diameter of the first P-type doped well. The doping concentration of the first N-type doped well is greater than the doping concentration of the first P-type doped well.

[0078] Step 303: Perform at least one photolithography on the doped substrate to form an anode and a cathode on the doped substrate.

[0079] Photolithography and ion implantation are performed on the pretreated substrate to form various doped wells. This step allows for the precise definition of regions within the substrate with specific doping types, concentrations, depths, and lateral dimensions. Specifically, this step includes sequentially forming a first P-type doped well, a first N-type doped well, a second N-type doped well, a second P-type doped well, and a third P-type doped well.

[0080] The formation process is typically an iterative cycle. Five independent photolithography steps and five independent ion implantations can be used to form the five doped wells. For each doped well, the process includes: first, spin-coating a layer of photoresist onto a base substrate; then, using a patterned photomask, exposing only the doped well region to be implanted; after exposure, removing the exposed (or unexposed, depending on the photoresist type) photoresist by development, leaving only the target doped region exposed on the base substrate; next, feeding the patterned photoresist mask into an ion implanter, selecting specific ion types (e.g., boron ions for P-type wells, phosphorus or arsenic ions for N-type wells), implantation energy (determining implantation depth), and implantation dose (determining doping concentration) according to the doped well design requirements, and performing ion implantation. After implantation, the remaining photoresist is removed. This "photolithography-implantation-removal" cycle is repeated until all five doped wells are fabricated according to the design requirements.

[0081] In this way, independent and precise control of the parameters of each doped well can be achieved. For example, the diameter of the first N-type doped well is larger than that of the first P-type doped well, and its doping concentration is also greater than that of the first P-type doped well. After this step is completed, a doped substrate containing all the core doped structures is obtained.

[0082] Step 303 typically includes multiple sub-steps. For example, a dielectric isolation layer can first be deposited across the entire wafer surface. Then, contact holes are etched into this isolation layer using a single photolithography and etching process, precisely aligning them with the underlying second N-type and second P-type doped wells. Next, these contact holes are filled using a metal deposition process (such as Physical Vapor Deposition, PVD, or Chemical Vapor Deposition, CVD), for example, by filling with tungsten (W), and excess metal is removed using chemical-mechanical polishing (CMP) to flush the top of the filled contact holes with the isolation layer. After this, at least one more photolithography and metal deposition / etching process (such as damascus etching) is used to fabricate the final anode and cathode metal interconnect pattern on the isolation layer and connected to the corresponding contact holes. The anode is connected to the second P-type doped well through contact holes, and the cathode is connected to the second N-type doped well through contact holes.

[0083] By performing the above-described fabrication method, semiconductor single-photon detectors with optimized electric field distribution and isolation structures can be precisely fabricated using a series of customized photolithography and ion implantation steps. This process allows for a high degree of design freedom, enabling significant optimization of device performance, particularly dark count performance, through fine-tuning of the doped wells, ultimately achieving the beneficial effect of low dark count.

[0084] In the preparation method provided by this invention, such as Figure 4 As shown, step 301 includes the following steps: Step 401: Etching is performed on the substrate to form etch trenches on the substrate.

[0085] This step aims to reserve physical space for subsequent filling of the insulating dielectric. The process is not a simple single-step etching, but a multi-step precision patterning process. In some embodiments, this step may specifically include: First, a thin pre-oxide layer is grown on a clean substrate (e.g., a substrate with an epitaxial layer already grown) using furnace tube thermal oxidation. This layer serves to buffer the stress on the substrate silicon from subsequent deposition layers. Next, a dense silicon nitride layer is deposited on the pre-oxide layer using a low-pressure chemical vapor deposition (LPCVD) process. This silicon nitride layer will act as a critical stop layer in subsequent CMP steps. Subsequently, a silicon oxynitride layer can be deposited as an anti-reflection layer using plasma-enhanced chemical vapor deposition (PECVD) to improve the accuracy of subsequent photolithography. After the above thin film deposition is completed, the pattern of the first isolation layer is transferred onto the photoresist using a photolithography process (spin-coating photoresist, exposure, development). Finally, using patterned photoresist as a mask, dry etching is employed to sequentially etch the underlying silicon oxynitride layer and silicon nitride layer until the preceding oxide layer is exposed. Then, using the remaining silicon nitride layer as a hard mask, dry etching continues downwards onto the silicon substrate to form an etch trench with a predetermined depth (e.g., 200 nm to 300 nm).

[0086] Step 402: Passivate the etched trenches.

[0087] In this step, the preceding dry etching is a high-energy physical process that inevitably introduces lattice damage and dangling bonds into the sidewalls and bottom of the etched trenches. If left untreated, these defects will become a strong source of leakage current. Therefore, the purpose of passivation is to repair these damages and stabilize the surface. In this embodiment, the passivation process may include: first, performing a thorough chemical cleaning (e.g., Radio Corporation of America, RCA cleaning) on ​​the etched wafer to remove etching residues. Then, the wafer is placed in a furnace tube and subjected to high-quality thermal oxidation of the exposed trench surface using an in-situ steam generation (ISSG) process. This thermal oxidation process has a dual effect: firstly, it effectively repairs lattice damage caused by etching and reduces interface state density; secondly, it rounds off the sharp corners of the trenches, which is crucial for avoiding additional leakage current caused by electric field concentration at the corners during device operation.

[0088] Step 403: Fill the passivated etched trench with silicon dioxide and perform surface planarization on the filled substrate to form a first isolation layer on the substrate.

[0089] In some embodiments, this step aims to complete the construction of the isolation structure and restore a flat surface for subsequent processes. Specifically, this step may include: First, using a high-density plasma chemical vapor deposition (PDCVD) process, filling the passivated etched trenches with silicon dioxide (SiO2). PDCVD is chosen because of its simultaneous sputtering and deposition characteristics, which can effectively fill trenches with high aspect ratios while avoiding voids. During filling, the deposited silicon dioxide thickness exceeds the trench depth, covering the entire wafer surface. Next, using a CMP process, the entire wafer surface is polished. During this process, the previously deposited silicon nitride layer acts as a stop layer. CMP preferentially removes the softer silicon dioxide, and the polishing rate significantly decreases when polishing reaches the silicon nitride layer, thereby achieving precise planarization. This ensures that the silicon dioxide outside the trench is completely removed, leaving only the portion filling the trench. After planarization, the silicon nitride layer serving as the stop layer and the underlying thin pre-oxide layer are removed by methods such as wet etching. Thus, the first isolation layer embedded in the substrate is formed. To protect the newly formed device surface, a new pre-oxide layer is usually regrown.

[0090] By performing the detailed preprocessing steps described above, a high-quality, structurally complete first isolation layer can be pre-constructed on the substrate before the actual doped well implantation. This first isolation layer provides a solid foundation for the subsequent surface electrical isolation of the device and is one of the key prerequisites for suppressing surface leakage current and surface crosstalk, thereby achieving low dark count performance of the device.

[0091] In the preparation method provided by this invention, after the anode and cathode are formed on the doped substrate, that is, after step 303, as follows: Figure 5 As shown, the preparation method also includes: Step 501: Bond the doped substrate to a support wafer.

[0092] In this step, the doped substrate refers to the device wafer that has completed all front-side processes. Because the back side of this wafer needs to be significantly thinned subsequently, the thinned wafer becomes very fragile and cannot be processed independently. Therefore, it needs to be bonded face down to another flat, robust wafer (called the support wafer or carrier wafer). This bonding process can be achieved using wafer-to-wafer bonding technology. For example, an oxide layer can be deposited on each of the two wafers to be bonded, and then plasma activation and annealing can be used to firmly bond the two wafers together through the oxide layers.

[0093] Step 502: Thinning is performed from the back side of the doped substrate.

[0094] In this step, after the device wafer is securely mounted on the support wafer, its exposed back side can be processed. Thinning is a crucial step in this process. The initial substrate wafer is typically hundreds of micrometers thick, while the effective absorption depth of photons in silicon is usually only a few to tens of micrometers. An excessively thick substrate not only absorbs photons but also causes photogenerated carriers to recombine due to long-distance drift before reaching the avalanche region, thus reducing detection efficiency and increasing timing jitter. Therefore, a thinning process is needed to reduce the substrate thickness to the optimal range for photon and carrier transport. This thinning process can be achieved using a multi-step process, such as using wet etching or CMP for fine thinning and surface planarization.

[0095] In some embodiments, an optional final thickness is 3.5 micrometers.

[0096] Step 503: A second isolation layer and a back-illuminated metal grid are formed on the back side of the thinned doped substrate.

[0097] In this step, after the doped substrate is thinned to the target thickness and a flat, clean back surface is obtained, the fabrication of the back structure can begin, constructing an isolation structure to suppress back optoelectronic crosstalk.

[0098] In some embodiments, the fabrication method employs a deep submicron BSI process, which is divided into a front-end process and a back-end process. The front-end process includes STI etching, ion implantation to control doping distribution, and contact hole etching, thereby forming a pretreated substrate. The back-end process includes via etching, electrode extraction, and bonding.

[0099] Specifically, in the front-end process, STI etching is performed first, with an etching depth of 200nm~300nm. The STI is then passivated using ISSG process. High-density plasma chemical vapor deposition (HDPCVD) is used to fill the STI with SiO2 and CMP is used for surface planarization. At this point, the STI process is complete.

[0100] The specific manufacturing process of STI is as follows: 1. STI etching.

[0101] 1.1 RCA cleaning.

[0102] 1.2 A pre-oxide layer is grown using a furnace tube. The pre-oxide layer is used to alleviate the stress on the substrate caused by the subsequent growth of Si3N4.

[0103] 1.3 Si3N4 was grown using LPCVD. LPCVD can grow very dense Si3N4, which can be used as a stop layer for CMP.

[0104] 1.4 SiON was deposited using PECVD for the anti-reflection layer on the bottom of the photolithography.

[0105] 1.5 Active area photolithography to etch the STI position.

[0106] 1.6 Using photoresist as a mask, dry etch SiON and Si3N4 on STI, with etching stopping at the preceding oxide layer.

[0107] 1.7 Remove photoresist.

[0108] 1.8 Using SiON and Si3N4 as masks, etch Si to form the trenches required for STI.

[0109] 2. STI filling.

[0110] 2.1 RCA cleaning.

[0111] 2.2 The STI is thermally oxidized using an ISSG process via a furnace tube to repair etching damage and passivate the surface, while also rounding the corners of the bottom grooves of the STI.

[0112] 2.3 HDPCVD is used to deposit SiO2 to fill the isolation trench and is higher than Si3N4. HDPCVD uses high-density plasma bombardment sputtering deposition to prevent the opening from closing too early during filling and creating voids, which can effectively fill the voids of STI.

[0113] 2.4 STI CMP planarization process, using Si3N4 as the stop layer. Considering the process margin, the oxide on the nitride must be completely removed to prevent the oxide from covering the nitride and affecting the etching of the nitride in subsequent steps. When the endpoint detector detects the signal of the nitride, it is necessary to grind for a period of time. This period of time has no significant impact on the nitride and will make the oxide slightly lower than the nitride.

[0114] 2.5 Annealing of furnace tubes to repair the STI structure.

[0115] 2.6 Wet etching to remove Si3N4.

[0116] 2.7 Remove the pre-oxidation layer.

[0117] 2.8 Regrowing a pre-oxide layer: The surface of the Si wafer cannot be directly exposed or in direct contact with the photoresist. The pre-oxide layer can isolate the substrate silicon from contact with air and photoresist, preventing organic matter in the photoresist from contacting and contaminating the substrate Si. In electronic-grade Si wafers, oxygen and carbon elements in the photoresist cannot migrate. These impurities will exist in the form of trap centers, thereby degrading the performance of SPAD.

[0118] After STI etching, a pre-oxide layer is grown using the ISSG process. Then, using i-line photoresist as a mask, photolithography is performed on the LGN, LGP, and PLD regions. Deep ultraviolet lithography (DUV) is used to lithographically depict the NPP and PPP regions. The diameters of the LGN, LGP, and NPP regions are W... LGN W LGP W NPP The ring widths of the PLG and PPP regions are W respectively. PLG W PPP After photolithography, ion implantation was performed in five regions to form Nwell, HVPW, DPW, N++, and P++, respectively. Following ion implantation, the front-end process was completed, and the back-end process was executed. This involved removing the pre-oxide layer, regrowing a new pre-oxide layer, and then growing a SiO2 layer as an electrical isolation layer. After etching contact holes, Ta2O5 / Ta was grown as the isolation and contact layers, followed by electroplating with metal W to fill the contact holes. CMP was then used for planarization. The cathode and leads were then grown using a damascus process. Based on this, SiO2 was regrown as the electrical isolation layer, also known as the surface passivation dielectric layer (dielectric layer 102). Through-holes were etched and filled with TiO2 / Ti as the isolation and contact layers, followed by filling with metal Cu. The anode was then grown using a damascus process. The main body of the SPAD and the front-side illumination (FSI) process were then completed.

[0119] To achieve back incidence, a BSI process is required. The substrate after the FSI process is bonded to another substrate wafer. After etching the DTI on the back side, a thin layer of Al2O3 is grown using ALD for passivation. Then, metal W is filled into the DTI for isolation. After etching the BMG, a back passivation High K layer 104, which is the High K passivation layer Al2O3, and a back passivation SiO2 layer 103, which is the SiO2 & Ta2O5 passivation layer, are grown. The BSI process is then completed, and a SPAD based on a customized deep submicron BSI process is fabricated.

[0120] DTI and BMG are deep trench isolation and metal isolation on the back of the pixel, respectively. Due to the BSI process, light enters from the back, and DTI and BMG can suppress photoelectric crosstalk on the back to a certain extent. The DTI is located in the same position as the STI on the front perimeter, but is deeper than the STI. The internal metal filling (W) effectively isolates optical crosstalk between pixels and also physically isolates electrical crosstalk between pixels. The BMG is located in the same position as the DTI, but is wider than the DTI. DTI and BMG are standard components of the BSI process and require no customization.

[0121] During the BSI process, since there is already metal on the front side, it is not possible to use furnace tubes for hot oxygen and low-pressure vapor deposition. The back side needs to be passivated by growing Al2O3 using ALD. ALD is atomic layer deposition, and its passivation effect is better than other deposition methods, but its passivation effect is worse than hot oxygen. Therefore, when designing the ion implantation trap, it is necessary to avoid direct contact between the depletion region and the bottom of the pixel. Since ALD growth is extremely slow, only a very thin passivation layer can be grown. Subsequently, Ta2O5 and SiO2 need to be grown for supplementary passivation.

[0122] Among them, the N-well is the main N-type well for forming the PN junction. This well is formed by two medium-current ion implantations. In order to keep the avalanche region away from the detector surface and reduce the influence of surface defects on dark counting, the N-well needs to be deep enough to make the depletion region difficult to approach the substrate surface. The implantation energy is between 50 keV and 300 keV, and the doping concentration for forming the well is higher than 1 eV. 18 cm -3 The depletion region hardly widens within the N-well, but instead widens into the inner HVPW. The diameter of this well needs to be larger than the diameters of the HVPW and N++, and the distance from W... PLD At least 700nm distance.

[0123] HVPW is a lightly doped, medium-depth, high-voltage-resistant P-type well formed by several medium-to-high current ion implantations. To effectively control the breakdown voltage and depletion region width, the implantation energy is between 100 keV and 600 keV, and the well doping concentration needs to be controlled at 1 eV. 17 cm -3 Nearby, this well is the main P-type well forming the PN junction. Due to the low doping concentration, under high voltage, the depletion region mainly widens in the HVPW, causing the high electric field to mainly fall inside the detector, shielding surface defects, and controlling the peak electric field intensity to not exceed 0.7 MV / cm, thereby controlling the tunneling probability and further reducing the volume dark count. The diameter of the HVPW needs to be smaller than the diameter of the Nwell.

[0124] The Nwell and HVPW together form the main region of the PN junction. The region between the Nwell and HVPW is the guard ring of the single-photon detector, used to suppress edge breakdown. Since the doping concentration of the substrate is much lower than that of the HVPW, the guard ring broadens much faster than the central active region during the depletion region broadening process of the PN junction. This causes the high electric field to be concentrated in the central active region. There is no electric field intensity around the central active region that can generate collisional ionization. Collisional ionization is concentrated only in the central active region, avoiding the spike electric field generated by electric field accumulation, reducing the probability of tunneling, significantly reducing dark count during operation, and improving detection efficiency.

[0125] A deep, moderately doped p-well (DPW) is formed by several medium-to-high current ion implantations and is used for inter-pixel isolation. To achieve the desired effect, the doping concentration of the DPW should not be too high to avoid affecting the main pixel region, and the doping depth needs to be deep enough to maximize the isolation of the electric field between pixels. The ring width of the DPW is slightly greater than N++ and is located at the outermost edge of the pixel.

[0126] N++ and P++ are two wells used for ohmic contacts, and their doping concentration must be at least greater than 1e. 20 cm -3 This results in a good ohmic contact, formed through two low-current, high-dose ion implantations. The diameter of N++ is smaller than that of Nwell, and it is concentric with both Nwell and HVPW. The ring width of P++ is slightly smaller than that of DPW, and it is concentric with DPW.

[0127] Shallow trench isolation (STI) is a method of isolating pixels to suppress surface crosstalk. It is commonly found in submicron and below Complementary Metal Oxide Semiconductor (CMOS) processes and is considered the optimal method for device isolation. The STI process has a crucial impact on performance. On one hand, STI effectively suppresses surface crosstalk between pixels through physical isolation, preventing charge carriers from reaching nearby pixels through surface channels. On the other hand, the etching process of STI inevitably introduces some surface damage, which, if not handled properly, can drastically degrade pixel performance. STI should avoid direct contact with the depletion region. Placing two STIs, one inside and one outside the DPW, can isolate both crosstalk between pixels and the electric field between the anode and cathode, significantly reducing dark counts.

[0128] Figure 6 This schematic diagram illustrates the doping distribution of different wells within a pixel, such as... Figure 6 As shown, different doping concentrations are represented by different gray levels.

[0129] During performance testing, a 0 V potential is applied to the Anode electrode, and a potential ranging from 0 to 20 V is applied to the Cathode in 0.2 V scanning steps. The potential difference between the two is the voltage that the single-photon detector can withstand. Simultaneously, the current at a fixed voltage is extracted during the scanning process. As the voltage increases, the point where the current rises to 10 μA is considered the breakdown point. Voltages exceeding the breakdown point are considered over-biased. The over-biased voltage is used as a performance metric for the single-photon detector. During operation, a quenching circuit is required for a single-photon detector. Quenching circuits are divided into passive quenching, active quenching, and gated quenching. Here, we take passive quenching as an example. The single-photon detector is connected in series with a large resistor (typically 100 kΩ) to form a closed loop with the power supply. Initially, an overbias voltage higher than the avalanche voltage is applied to the SPAD. When an external stimulus (such as photon incidence) causes the single-photon detector to generate an avalanche current and triggers counting, the resistor rapidly divides the voltage, reducing the voltage across the single-photon detector to below the avalanche voltage, preventing the avalanche from continuing. The current magnitude quickly returns to its pre-avalanche state. As the current in the loop decreases, the voltage across the resistor also gradually decreases, and the voltage across the SPAD gradually returns to its pre-counting state, waiting for the next avalanche. This completes one full count.

[0130] Figure 7 The current-voltage characteristic curves of the tested single-photon detector are schematically shown. The three curves in the figure represent the dark current, photocurrent, and dark current of the external quenching resistor, respectively.

[0131] Figure 8 The diagram illustrates the dark count of a single-photon detector under different overbias voltages and a schematic diagram of the dark count per unit area.

[0132] Figure 9 The diagram illustrates the detection efficiency of a single-photon detector for 905 nm and 940 nm light under different overbias.

[0133] Figure 10 The diagram illustrates the detection efficiency of a single-photon detector for wavelengths from 300 nm to 1100 nm under a tested over-biased voltage of 2V.

[0134] like Figure 7 , Figure 8 , Figure 9 and Figure 10 As shown, the low-dark-count semiconductor single-photon detector performs excellently in different scenarios and can achieve low-dark-count single-photon detection.

[0135] This invention achieves a low-dark-count single-photon detector by adjusting the depth of the ion implantation trap to reduce the volume dark count and surface dark count, and by using structures such as STI and DTI to isolate pixels and reduce crosstalk dark count.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-darkness-count semiconductor single-photon detector, characterized in that, include: Substrate; The first P-type doped well is located in the central active region of the substrate; The first N-type doped well is located in the central active region and partially overlaps with the first P-type doped well in the vertical direction to form an avalanche PN junction. The vertical direction refers to the direction extending from the substrate surface to the interior of the substrate. The second N-type doped well is disposed inside the first N-type doped well and is used to form a cathode; The second P-type doped well is located on the periphery of the central active region and is used to form the anode; The third P-type doped well is located on the periphery of the central active region, and in the vertical direction, the second P-type doped well is located above the third P-type doped well; The diameter of the first N-type doped well is larger than the diameter of the first P-type doped well, and the doping concentration of the first N-type doped well is larger than the doping concentration of the first P-type doped well.

2. The low-darkness counting semiconductor single-photon detector according to claim 1, characterized in that, The doping concentration of the second N-type doped well is greater than the doping concentration of the first N-type doped well; and / or The doping concentration of the second P-type doped well is greater than that of the first P-type doped well and the third P-type doped well.

3. The low-darkness-count semiconductor single-photon detector according to claim 1, characterized in that, In the vertical direction, the bottom of the first P-type doped well is deeper than the bottom of the first N-type doped well.

4. The low-darkness-count semiconductor single-photon detector according to claim 1, characterized in that, The ring width of the second P-type doped well is smaller than the ring width of the third P-type doped well; and / or The bottom of the third P-type doped well is deeper than the bottom of the second P-type doped well.

5. The low-dark-count semiconductor single-photon detector according to any one of claims 1 to 4, characterized in that, The low-dark-count semiconductor single-photon detector also includes: A first isolation layer is formed with the third P-type doped well to create a receiving trench, and the second P-type doped well is located within the receiving trench.

6. The low-darkness-count semiconductor single-photon detector according to claim 5, characterized in that, The low-dark-count semiconductor single-photon detector also includes: The second isolation layer is in contact with the back of the substrate and is located on the periphery of the central active region; The structural depth of the second isolation layer is greater than that of the first isolation layer.

7. The low-darkness-count semiconductor single-photon detector according to claim 6, characterized in that, The low-dark-count semiconductor single-photon detector also includes: A back-illuminated metal grid, in contact with the second isolation layer, is located on the periphery of the central active region and on the opposite side to the third P-type doped well.

8. A method for fabricating a low-dark-count semiconductor single-photon detector as described in any one of claims 1 to 7, characterized in that, The preparation method includes: A base substrate is provided, wherein the base substrate has undergone pretreatment; Photolithography and ion implantation are performed on the base substrate to form a first P-type doped well, a first N-type doped well, and a second N-type doped well in the central active region of the base substrate, and a second P-type doped well and a third P-type doped well are formed around the central active region to obtain a doped substrate. The first N-type doped well and the first P-type doped well partially overlap in the vertical direction to form an avalanche PN junction. The second N-type doped well is disposed inside the first N-type doped well. The third P-type doped well and the second P-type doped well partially overlap in the vertical direction. The diameter of the first N-type doped well is larger than the diameter of the first P-type doped well, and the doping concentration of the first N-type doped well is larger than the doping concentration of the first P-type doped well. The doped substrate is subjected to at least one photolithography process to form an anode and a cathode on the doped substrate.

9. The preparation method according to claim 8, characterized in that, The preprocessing includes the following steps: Etching is performed on the substrate to form etching trenches on the substrate; The etched trenches are passivated. After passivation, the etched trenches are filled with silicon dioxide, and the filled substrate is planarized to form a first isolation layer on the substrate.

10. The preparation method according to claim 8, characterized in that, After forming the anode and cathode on the doped substrate, the fabrication method further includes: The doped substrate is bonded to a support wafer; Thinning is performed from the back side of the doped substrate; A second isolation layer and a back-illuminated metal grid are formed on the back of the thinned doped substrate.

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