LED packaging structure and light-emitting device

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an LED packaging structure and a light-emitting device. The LED packaging structure comprises a substrate, a spacing layer, an IC chip, at least one heightening layer and at least one LED chip, wherein the spacing layer, the IC chip, the at least one heightening layer and the at least one LED chip are located on the substrate; the IC chip is located on the surface, deviating from the substrate, of the spacing layer; the heightening layer is located on the surface, deviating from the substrate, of the spacing layer, and is spaced from the IC chip; the LED chip is located on the surface, away from the spacing layer, of the heightening layer; wherein the absolute value of the vertical height difference H between the upper surface of the LED chip and the upper surface of the IC chip is not greater than 2 microns. Through the above design, the transfer yield of integrated packaging of the active driving IC and the Micro LED can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an LED packaging structure and a light emitting device. BACKGROUND

[0002] In the display screen market, AMiP (Active Matrix integrated Package) technology is one of the core development directions of the current LED display field, which marks the key leap of LED display technology to high integration and high pixel experience, and occupies an increasingly important position in the display screen market. This technology integrates active drive IC and Micro LED in the same package, realizes the structure design of "lamp drive integration", can significantly improve the pixel performance and display effect of the display screen, and can simplify the subsequent assembly process, which is an important breakthrough to promote the upgrading of LED display technology.

[0003] However, in the actual industrialization process of AMiP technology, the integrated packaging of active drive IC and Micro LED faces the key problem of poor yield in large quantity transfer. This problem directly restricts the large-scale production efficiency and cost control of AMiP products, and becomes the core technical bottleneck that needs to be broken through in the current AMiP field. SUMMARY

[0004] The embodiments of the present application provide an LED packaging structure, which can solve at least one problem in the background art to effectively improve the transfer yield of the integrated packaging of active drive IC and Micro LED.

[0005] In a first aspect, the embodiments of the present application provide an LED packaging structure, comprising a substrate, a spacer layer, an IC chip, at least one heightening layer, and at least a plurality of LED chips; the spacer layer is located on the substrate; the IC chip is located on the surface of the spacer layer away from the substrate; the at least one heightening layer is located on the surface of the spacer layer away from the substrate, and is spaced apart from the IC chip; the at least one LED chip is located on the surface of the heightening layer away from the spacer layer; wherein the absolute value of the vertical height difference H between the upper surface of the LED chip and the upper surface of the IC chip is not greater than 2 μm.

[0006] In a second aspect, the embodiments of the present application provide an LED packaging structure, comprising a substrate, a spacer layer, an IC chip, and at least a plurality of LED chips; the spacer layer is located on the substrate; a local thinning area is provided on the side of the spacer layer away from the substrate; the IC chip is arranged in the local thinning area; the at least one LED chip is located on the surface of the spacer layer away from the substrate, and is spaced apart from the IC chip; wherein the absolute value of the vertical height difference H between the upper surface of the LED chip and the upper surface of the IC chip is not greater than 2 μm.

[0007] In a third aspect, the embodiments of the present application provide a light emitting device comprising the LED packaging structure as described in the first aspect or the second aspect.

[0008] The LED packaging structure provided by the present application can make the upper surface of the LED chip close to the upper surface of the IC chip by designing the heightening layer and / or the local thinning area, thereby effectively improving the transfer yield.

[0009] Other features and advantages of the present application will be described in the following description and, in part, will become apparent to those skilled in the art, and will, in part, be learned from the practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0011] Figures 1-4 is a cross-sectional schematic view of the LED packaging structure provided by each embodiment in embodiment one; Figure 5 、 Figure 6 is a top view schematic view of the LED packaging structure provided by different variants in embodiment one; Figure 7 、 Figure 8 is a cross-sectional schematic view of the LED packaging structure provided by each embodiment in embodiment two; Figure 9 is a top view schematic view of the LED packaging structure provided by one embodiment in embodiment two; Figure 10 、 Figure 11 is a cross-sectional schematic view of the LED packaging structure provided by each embodiment in embodiment three; Figure 12 is a top view schematic view of the LED packaging structure provided by one embodiment in embodiment three.

[0012] Reference signs: 10, substrate; 20, spacer layer; 21, local thinning area; 30, IC chip; 40, LED chip; 50, heightening layer; 60, chip covering layer; 70, insulating protective layer. DETAILED DESCRIPTION

[0013] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. The technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0014] It should also be noted that the structural schematic diagram provided by the embodiments of the present application is to more clearly express the structural features of the LED packaging structure, but is not made in proportion.

[0015] The embodiments of the present application provide an LED packaging structure, comprising: a substrate 10, a spacing layer 20, an IC chip 30, at least one elevation layer 50, and at least a plurality of LED chips 40; the spacing layer 20 is located on the substrate 10; the IC chip 30 is located on the surface of the spacing layer 20 away from the substrate 10; the elevation layer 50 is located on the surface of the spacing layer 20 away from the substrate 10 and is spaced apart from the IC chip 30; the LED chip 40 is located on the surface of the elevation layer 50 away from the spacing layer 20; wherein the absolute value of the vertical height difference H between the upper surface of the LED chip 40 and the upper surface of the IC chip 30 is not greater than 2 μm. Through the above design of the elevation layer 50 and the limitation of the vertical height difference H, the transfer yield of the active drive IC and the Micro LED integrated packaging can be effectively improved.

[0016] In an embodiment, the elevation layer 50 comprises a plurality of transparent layers with a layer number greater than 2; the refractive index of each transparent layer gradually decreases from the LED chip 40 towards the direction close to the spacing layer 20. Through the design of the refractive index of the multi-layer transparent layer of the elevation layer 50, not only the mass transfer yield can be improved, but also the light extraction efficiency can be effectively matched with the light emitting angle of the LED chip 40.

[0017] In an embodiment, the thickness h1 of the elevation layer 50 is between 0.5 μm and 3 μm or between 3 μm and 5 μm.

[0018] In an embodiment, the spacing W1 between the elevation layer 50 and the IC chip 30 and the spacing W2 between the LED chip 40 and the IC chip 30 satisfy: W1≥1 / 5W2, so as to avoid signal interference or physical contact between the IC chip 30 and the elevation layer 50.

[0019] In an embodiment, the spacing W1 between the elevation layer 50 and the IC chip 30 satisfies: W1≥3 μm. Through this setting, the IC chip 30 can be effectively prevented from being pressed to the elevation layer 50 during the process, so as to cause damage to the IC chip 30 or affect the structural quality.

[0020] In an embodiment, the thickness h3 of the IC chip 30 satisfies: 10 μm≤h3≤20 μm, and the minimum size of one side of the IC chip 30 is 1 μm~110 μm; the thickness h2 of the LED chip 40 satisfies: 2 μm≤h2≤12 μm, and the minimum size of one side of the LED chip 40 is 1 μm~100 μm.

[0021] In an embodiment, the thickness h1 of the spacer layer 50 satisfies: h3-h2-2 μm≤h1≤h3-h2+2 μm, in relation to the thickness h2 of the LED chip 40 and the thickness h3 of the IC chip 30.

[0022] In an embodiment, the ratio of the thickness h2 of the LED chip 40 to the thickness h3 of the IC chip 30 is less than or equal to 50%.

[0023] In an embodiment, the spacer layer 20 comprises a transfer layer made of transparent material.

[0024] In an embodiment, a chip covering layer 60 is further included, which covers at least part of the sidewall of the LED chip 40, the chip covering layer 60 comprises black glue, and the light transmittance of the chip covering layer 60 in the wavelength range of 380 nm~760 nm visible light is less than or equal to 10%, thereby effectively suppressing the sidewall stray light of the LED chip 40. Further, the LED chip 40 comprises electrodes, at least part of which is exposed from the chip covering layer.

[0025] In an embodiment, an insulating protective layer 70 is further included, which is located on the side of the spacer layer 20 away from the substrate 10, and covers at least part of the surface of the IC chip 30 and / or part of the surface of the LED chip 40.

[0026] In an embodiment, the LED chip 40 and the IC chip 30 are provided with a metal interconnection structure on the side away from the substrate 10, so as to electrically connect the IC chip 30 and the LED chip 40; the metal interconnection structure comprises a wiring layer, which electrically contacts the IC chip 30 and the LED chip 40 respectively.

[0027] In an embodiment, the LED chip 40 comprises one or more of a red light chip, a blue light chip and a green light chip, and the LED chip 40 is transferred onto the substrate 10 via a mass transfer process; a plurality of the LED chips 40 are provided with a common spacer layer 50 thereunder, or a plurality of corresponding independent spacer layers 50.

[0028] In an embodiment, the substrate 10 is a transparent substrate, and the light transmittance of the transparent substrate in the wavelength range of 380 nm~760 nm visible light is not less than 90%.

[0029] In an embodiment, the spacer layer 20 is provided with a local thinning area 21 on a side away from the substrate 10, and the IC chip 30 is arranged in the local thinning area 21. Through the design of the local thinning area 21, a larger range of chip thickness differences can be effectively adapted, and the disadvantages caused by the design of the cushion layer 50 being too thick when the chip thickness difference is too large can be compensated.

[0030] In an embodiment, the distance W3 between the edge of the local thinning area 21 and the IC chip 30 satisfies: W3≥5μm and W3≤20μm. Through the limitation of W3≥5μm, not only can mechanical interference be avoided when the IC chip 30 is embedded, but also the problem of interface thermal stress concentration caused by too small W3 can be alleviated; at the same time, through the limitation of W3≤20μm, the size ratio of the local thinning area 21 can be prevented from being too large to affect the chip layout and structural strength, effectively balancing the improvement of transfer yield while ensuring the reliability and heat dissipation effect of the device structure.

[0031] The embodiment of the present application also provides an LED packaging structure, which comprises a substrate 10, a spacer layer 20, an IC chip 30, and at least a plurality of LED chips 40; the spacer layer 20 is located on the substrate 10; the spacer layer 20 is provided with a local thinning area 21 on a side away from the substrate 10; the IC chip 30 is arranged in the local thinning area 21; the LED chips 40 are located on a surface of the spacer layer 20 away from the substrate 10 and are spaced apart from the IC chip 30; wherein the absolute value of the vertical height difference H between the upper surface of the LED chip 40 and the upper surface of the IC chip 30 is not greater than 2μm. Through the design of the local thinning area 21, the height difference can be eliminated without additionally setting the cushion layer 50, thereby effectively improving the mass transfer yield of the IC chip 30 and the LED chip 40.

[0032] In an embodiment, the distance W3 between the edge of the local thinning area 21 and the IC chip 30 satisfies: W3≥5μm and W3≤20μm.

[0033] In an embodiment, the depth d1 of the local thinning area 21 and the thickness d2 of the spacer layer 20 satisfy: d1

[0034] In an embodiment, at least one cushion layer 50 is further included, and the cushion layer 50 is located between the spacer layer 20 and the LED chip 40.

[0035] In an embodiment, the cushion layer 50 comprises a plurality of transparent layers with a layer number greater than 2; and the refractive index of each transparent layer gradually decreases from the LED chip 40 towards the direction close to the spacer layer 20.

[0036] In an embodiment, the distance W1 between the elevation layer 50 and the IC chip 30 and the distance W2 between the LED chip 40 and the IC chip 30 satisfy: W1≥1 / 5W2; or the distance W1 between the elevation layer 50 and the IC chip 30 satisfies: W1≥3μm.

[0037] The embodiment of the present application also provides a light emitting device comprising the LED packaging structure according to any one of the above embodiments.

[0038] Next, the technical solutions of the present application will be described and explained in detail through various specific embodiments in combination with the accompanying drawings.

[0039] Embodiment one Please refer to Figure 1 , Figure 1 is a cross-sectional view of the LED packaging structure provided by the embodiment one of the present application. The LED packaging structure provided by the embodiment one of the present application comprises at least a substrate 10, a spacer layer 20, an IC chip 30, at least one elevation layer 50, and at least a plurality of LED chips 40.

[0040] In the embodiment, the substrate 10 is a transparent substrate to meet the light transmission requirement of the packaging structure. Specifically, the light transmission rate of the transparent substrate in the visible light wavelength range of 380nm~760nm is not less than 90%. The material of the transparent substrate can be flexibly selected according to the actual application scenario, including but not limited to sapphire, glass, epoxy, silicone, etc. Further, the thickness of the transparent substrate can be set to 50μm~200μm according to the structural strength requirement, for example, the thickness of the sapphire substrate can be selected to 50μm~150μm to balance the strength and light weight, and the thickness of the glass substrate can be selected to 70μm~200μm to balance the light transmission and processability; preferably, the side of the transparent substrate facing the spacer layer 20 can be subjected to plasma treatment or film coating (such as SiO2 film) to improve the interface bonding force with the spacer layer 20 and avoid delamination.

[0041] The spacing layer 20 is located on the substrate 10. The spacing layer 20 can be made of insulating materials such as epoxy, polyimide (PI), silicon nitride (Si3N4), or silicon oxide (SiO2) to achieve electrical isolation between the substrate 10 and the upper layer components. The combination of the spacing layer 20 and the substrate 10 can be achieved by coating and curing, sputter deposition, or bonding process. The preferred embodiment of the spacing layer 20 includes a transfer layer made of transparent material, which can stably support the LED chip 40 during mass transfer, avoid chip displacement or damage, and the transparent property does not block the light radiation path from the chip to the spacing layer 20 side, ensuring the overall light efficiency of the package. Of course, according to actual needs, the spacing layer 20 can also include other functional layer structures, which are not limited in the present embodiment. As an example, the thickness of the spacing layer 20 is between 1 μm and 4 μm.

[0042] The IC chip 30 is located on the surface of the spacing layer 20 away from the substrate 10; the IC chip 30 is internally designed with a special circuit for LED driving control to drive and control the LED chip 40, and the specific circuit design is reasonably set according to actual needs, which is not limited in the present embodiment. The IC chip 30 is fixed on the surface of the spacing layer 20 by welding or conductive adhesive. As an example, the minimum single side size of the IC chip 30 is 1 μm to 120 μm, and the thickness h3 of the IC chip 30 satisfies: 10 μm ≤ h3 ≤ 20 μm, more preferably less than 12 μm, for example 10 μm, 11 μm, 12 μm, which is reasonably set according to actual functional needs.

[0043] Similarly, the LED chip 40 is located on the side of the spacing layer 20 away from the substrate 10. The LED chip 40 includes one or more of red, blue, and green light chips, and the LED chip 40 is transferred to the substrate 10 by a mass transfer process. As an example, the minimum single side size of the LED chip 40 is 1 μm to 100 μm. The thickness h2 of the LED chip 40 satisfies: 2 μm ≤ h2 ≤ 12 μm, such as 2 μm, 4 μm, 5 μm, 6 μm, 8 μm, 10 μm, 12 μm; more preferably less than 10 μm.

[0044] In the prior art, in order to ensure the functionality of the IC chip 30, the IC chip 30 on the market currently has a certain thickness, for example, the thickness h3 of the IC chip 30 satisfies: h3 ≥ 10 μm. That is, when the IC chip 30 and the LED chip 40 are both arranged on the spacing layer 20, the IC chip 30 will be higher than the LED chip 40. However, the height difference between the two will easily lead to a significant decrease in the overall yield of mass transfer, increasing the difficulty of transfer. Based on this, the present embodiment sets a height-adjustable pad layer 50 between the LED chip 40 and the spacing layer 20 to offset the difference between the thickness of the LED chip 40 itself and the IC chip 30.

[0045] Specifically, please continue to refer to Figure 1 , the elevation layer 50 is located on the surface of the spacer layer 20 away from the substrate 10, and is spaced apart from the IC chip 30, and the LED chip 40 is located on the surface of the elevation layer 50 away from the spacer layer 20. That is, a space is formed between the elevation layer 50 and the IC chip 30. When the number of the LED chip 40 is one, the number of the elevation layer 50 is also one, and preferably the orthographic projection of the LED chip 40 on the spacer layer 20 is located within the orthographic projection range of the elevation layer 50 on the spacer layer 20. When the number of the LED chip 40 is multiple, a common elevation layer is provided below the multiple LED chips 40, or multiple independent elevation layers 50 corresponding to the multiple LED chips 40 are provided. For example, one or more independent elevation layers 50 can be provided below the same LED chip 40, and / or one or more LED chips 40 can be provided above the same elevation layer 50. For example Figure 5 three LED chips 40 are located on one elevation layer 50, and for example Figure 6 three LED chips 40 are located on three independent elevation layers 50. The specific number and positional relationship can be reasonably designed according to actual needs, which is not limited in the embodiment.

[0046] Further, by designing the elevation layer 50, the absolute value of the vertical height difference H between the upper surface of the LED chip 40 and the upper surface of the IC chip 30 is not greater than 2 μm, thereby offsetting the height difference between the upper surface of the IC chip 30 and the upper surface of the LED chip 40, improving the yield of the mass transfer, and avoiding affecting the process due to the large difference between the two.

[0047] The thickness h1 of the elevation layer 50 should depend on the thickness h2 of the LED chip 40 and the thickness h3 of the IC chip 30. In the embodiment, the thickness h1 of the elevation layer 50 is preferably related to the thickness h2 of the LED chip 40 and the thickness h3 of the IC chip 30, and satisfies: h3-h2-2 μm≤h1≤h3-h2+2 μm. As an example, the thickness h1 of the elevation layer 50 is between 0.5 μm and 3 μm or between 3 μm and 5 μm.

[0048] Further, in the embodiment, the ratio of the thickness h2 of the LED chip 40 to the thickness h3 of the IC chip 30 is less than or equal to 60%, and more preferably the ratio is less than 50%. That is, when the ratio of h2 and h3 is less than or equal to 60%, the thickness difference between the two is large, for example, h2 is 8 μm and h3 is 15 μm, at this time, the yield of mass transfer is significantly reduced due to the thickness difference. Therefore, within this ratio range, the design of the elevation layer 50 can effectively improve the yield of mass transfer, and further improve the preparation yield of the device.

[0049] Preferably, referring to Figure 2 , the cushion layer 50 is a single transparent layer or a multi-layer transparent layer. The material of the transparent layer includes, but is not limited to, silica gel, epoxy resin, UV curing glue, etc., and the materials between different layers of the transparent layer can be the same or different, which is not limited in the embodiment. The embodiment preferably uses a multi-layer transparent layer with more than two layers, and when the cushion layer 50 includes a multi-layer transparent layer, the refractive index of each transparent layer gradually decreases from the LED chip 40 towards the direction close to the spacer layer 20.

[0050] The gradual decrease can be continuous and / or stepwise. The continuous gradient is achieved by gradient doping of the material composition or continuous adjustment of the process parameters, and the refractive index changes linearly or nonlinearly along the direction from the LED chip 40 towards the direction close to the spacer layer 20. The stepwise gradient is achieved by sequentially stacking 3-6 transparent layers with different refractive indexes, and the refractive index difference between adjacent layers is controllable and decreases along the direction from the LED chip 40 towards the direction close to the spacer layer 20. For example, the cushion layer 50 includes n layers of transparent layers (n>2), and the refractive index of the transparent layers from the LED chip 40 towards the direction close to the spacer layer 20 is K1, K2, …, Kn in turn; then K1<K2<…<Kn, which decreases as a whole along the direction close to the spacer layer 20. The refractive index difference between adjacent layers can be controlled within the range of 0.1-0.5 to match the light emitting angle of the LED chip 40 and reduce the total reflection probability of light at the interface.

[0051] Meanwhile, the surface of the cushion layer 50 towards the LED chip 40 can be designed with a rough structure (not shown in the figure), which can further improve the light extraction efficiency compared to a flat surface. In addition, the thickness of each layer of the transparent layer in the cushion layer 50 can be reasonably designed according to the actual light emitting or light reflection requirements, for example, the thickness of each transparent layer is distributed in a continuous gradient or stepwise gradient, to balance the structural stability and light path optimization.

[0052] In an embodiment, referring to Figure 1 , Figure 5 , Figure 6The interval W1 between the cushion layer 50 and the IC chip 30 and the interval W2 between the LED chip 40 and the IC chip 30 satisfy: W1≥1 / 5W2. Through the above limitation, the IC chip 30 can be effectively prevented from being pressed to the cushion layer 50 during the process, so as to avoid damage to the IC chip 30 or affect the structural quality. In the embodiment, the interval W1 between the cushion layer 50 and the IC chip 30 preferably satisfies: W1≥3μm, so as to avoid signal interference or physical contact between the IC chip 30 and the cushion layer 50. Of course, according to the requirement, an insulating medium (such as transparent silicone or epoxy resin, and the filling thickness is flush with the surface of the interval layer 20) can be filled between the cushion layer 50 and the IC chip 30, so as to further avoid the interference between the two.

[0053] Optionally, referring to Figure 3 The LED packaging structure further comprises a chip covering layer 60, the chip covering layer 60 covers at least part of the sidewall of the LED chip 40, and the light transmittance of the chip covering layer 60 in the visible light wavelength range of 380nm-760nm is less than or equal to 10%, that is, the chip covering layer 60 is a material with no light transmittance or very small light transmittance, which can effectively suppress the stray light of the sidewall of the LED chip 40 to avoid the interference of the light leakage of specific wavelength. The chip covering layer 60 covers the sidewall of the LED chip 40 in a local wrapping or full wrapping manner, and the coverage range can be adjusted according to the light shielding requirement. For example, the coverage height extends from the sidewall of the non-light surface end of the LED chip 40 to the sidewall of the light surface end of the LED chip 40 to more than 1 / 5-1 of the thickness of the LED chip 40. In the embodiment, the chip covering layer 60 preferably comprises a black substance (such as black glue), so as to effectively shield the light of the sidewall of the LED chip 40.

[0054] Through the above design of the chip covering layer 60, the front light intensity of the LED chip 40 can be ensured, and the problem of adjacent pixel crosstalk can be reduced, so as to effectively improve the contrast and color purity of the display screen.

[0055] In addition, the LED chip 40 comprises an electrode (not shown in the figure), and at least part of the electrode is exposed from the chip covering layer 60. That is, the electrode extends to the sidewall of the LED chip 40, and the chip covering layer 60 is provided with a avoiding hole at the position corresponding to the electrode, so as to ensure that at least part of the electrode is exposed, thereby facilitating the electrical connection of the LED chip 40 through the electrode.

[0056] In other embodiments, referring to Figure 4 The LED packaging structure further comprises an insulating protective layer 70, the insulating protective layer 70 is located on the side of the interval layer 20 away from the substrate 10, and covers at least part of the surface of the IC chip 30 and / or part of the surface of the LED chip 40.

[0057] Specifically, the insulation protective layer 70 is arranged on the side of the spacing layer 20 away from the substrate 10 in a manner of overall covering or selective covering, and covers at least part of the surface of the IC chip 30 (for example, at least part of the top surface and / or at least part of the side wall of the IC chip 30), at least part of the surface of the LED chip 40 (for example, at least part of the top surface and / or at least part of the side wall of the LED chip 40), and the exposed area of the spacing layer 20 not occupied by the chips, thereby forming an effective protective interface to achieve electrical isolation, block the intrusion of external water vapor and dust, and protect the chips. The material of the insulation protective layer 70 can be an organic insulating material such as transparent polyimide (PI), epoxy modified acrylic resin, or silica gel; or an inorganic insulating material such as silicon nitride (Si3N4), silicon oxide (SiO2), or aluminum oxide (Al2O3); or a composite insulating material. The specific material and covering thickness can be reasonably designed according to actual protection requirements. The present embodiment is not limited herein.

[0058] Further, the LED packaging structure further comprises a metal interconnection structure (not shown in the figure) located on the side of the LED chip 40 and the IC chip 30 away from the substrate 10 to electrically connect the IC chip 30 and the LED chip 40. That is, according to actual requirements, the metal interconnection structure is designed on the non-light-emitting side of the LED chip 40.

[0059] The metal interconnection structure can be in electrical contact with the pins or pads of the LED chip 40 and the IC chip 30 through the structure of the wiring layer or the wire to achieve electrical connection. For example, when the metal interconnection structure is located on the side of the spacing layer 20 away from the substrate 10, surface wiring and metal bump bonding are used to achieve electrical connection of the chips. Of course, according to actual requirements, the metal interconnection structure can also be located on the side of the spacing layer 20 close to the substrate 10; when the metal interconnection structure is located on the side of the spacing layer 20 close to the substrate 10, via hole interconnection and back surface wiring are used to achieve electrical connection of the chips. The present embodiment preferably comprises a wiring layer in electrical contact with the IC chip 30 and the LED chip 40.

[0060] Embodiment Two Different from Embodiment One, Embodiment Two does not use the heightening layer 50, but uses a scheme of arranging a local thinning area 21 in the spacing layer 20 under the IC chip 30 to reduce the vertical height difference between the LED chip 40 and the IC chip 30.

[0061] For specific implementation, please refer to Figure 7The interval layer 20 is provided with a local thinning area 21 on the side away from the substrate 10, which is arranged below the IC chip 30 and enables the IC chip 30 to be embedded into the local thinning area 21. The local thinning area 21 is a recess structure on the side of the interval layer 20 away from the substrate 10, which has a planar shape matching the projection outline of the IC chip 30 (such as a rectangle, a square or a special-shaped one), so as to ensure the accurate embedding of the IC chip 30.

[0062] The thinning depth of the local thinning area 21 is determined according to the thickness difference between the IC chip 30 and the LED chip 40 and the thickness of the interval layer 20 itself. In the embodiment, the thinning depth of the interval layer 20 should be such that the absolute value of the vertical height difference H between the upper surface of the LED chip 40 and the upper surface of the IC chip 30 is not greater than 2 μm. That is, the depth d1 of the local thinning area 21 and the thickness h2 of the LED chip 40 and the thickness h3 of the IC chip 30 satisfy: h3-h2-2 μm≤d1≤h3-h2+2 μm. Preferably, the depth d1 of the local thinning area 21 and the thickness d2 of the interval layer 20 satisfy: d1

[0063] In an optional embodiment, please continue to refer to Figure 7 、 Figure 9 The distance W3 between the edge of the local thinning area 21 and the IC chip 30 satisfies: W3≥5 μm and W3≤20 μm. That is, the distance W3 refers to the horizontal distance between the edge of the local thinning area 21 (i.e. the inner wall edge of the recess structure) and the peripheral edge of the IC chip 30. By limiting W3≥5 μm, not only the mechanical interference during the embedding of the IC chip 30 is avoided, but also sufficient buffer space is provided to prevent the collision or scratching of the chip edge with the right-angle edge of the thinning area; meanwhile, the thermal stress concentration at the interface of the IC chip 30 and the interval layer 20 caused by the difference in the material coefficient of thermal expansion (CTE) is also alleviated. By limiting W3≤20 μm, the size ratio of the local thinning area 21 is prevented from being too large to affect the chip layout and the structural strength, effectively balancing the improvement of the transfer yield while ensuring the reliability and heat dissipation effect of the device structure.

[0064] In another optional embodiment, please refer to Figure 8 The edge of the local thinning area 21 is designed with a slope transition, with a slope angle of 20°~80° (preferably 45°) and a slope width of 2 μm~5 μm, which can avoid the stress concentration caused by the right-angle edge during the embedding of the IC chip 30, and facilitate the accurate grabbing of the chip by the suction nozzle during the transfer process (reducing the edge interference).

[0065] In other alternative embodiments, after the IC chip 30 is embedded in the partially thinned region 21 of the spacer layer 20, the gap between its sidewall and the thinned region can be filled with an insulating material (such as silicone) to further improve structural stability.

[0066] This second embodiment uses an "embedded" design with localized thinning to eliminate height differences without the need for an additional padding layer 50, thereby effectively improving the mass transfer yield of IC chip 30 and LED chip 40.

[0067] Example 3 Based on Embodiments 1 and 2, Embodiment 3 further reduces the vertical height difference between the LED chip 40 and the IC chip 30 by simultaneously setting a padding layer 50 between the LED chip 40 and the spacer layer 20, and by setting a locally thinned region 21 in the spacer layer 20 below the IC chip 30. In other words, the vertical height difference between the LED chip 40 and the IC chip 30 is reduced synergistically through the combination of the "padding layer 50 + locally thinned region 21".

[0068] For specific implementation details, please refer to [link / reference]. Figure 10 , Figure 11 When the two work together, the height of the padding layer 50 is increased from the LED chip 40 side, while the height of the locally thinned area 21 is decreased from the IC chip 30 side. Through bidirectional compensation, the absolute value of the vertical height difference H between the upper surfaces of the LED chip 40 and the IC chip 30 is controlled to ≤2μm. This combined solution can effectively adapt to a wider range of chip thickness differences and effectively reduce the impact of a single process error on the height difference. At the same time, it compensates for the drawbacks caused by an excessively thick padding layer 50 when the chip thickness difference is too large (for example, an excessively thick padding layer 50 will affect performance such as light output and heat dissipation).

[0069] Preferably, please refer to Figure 12 Viewed from above, the orthographic projection of the padding layer 50 on the substrate 10 falls outside the orthographic projection range of the local thinning region 21 on the substrate 10, to ensure that the two processes do not interfere with each other.

[0070] The specific structure, function, and role of the padding layer 50 and the local thinning area 21 can be referred to the contents of the aforementioned Embodiment 1 and Embodiment 2, and will not be repeated here.

[0071] Example 4 Based on the above, Embodiment 4 of the present invention also provides a light-emitting device, which adopts the LED packaging structure described in the above embodiments to effectively improve the yield of mass transfer and improve the reliability of the light-emitting device.

[0072] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An LED packaging structure, characterized in that, include: substrate; A spacer layer is located on the substrate; The IC chip is located on the surface of the spacer layer opposite to the substrate. At least one pad layer is located on the surface of the spacer layer opposite to the substrate and is spaced apart from the IC chip; At least a plurality of LED chips are located on the surface of the padding layer opposite to the spacer layer; The absolute value of the vertical height difference H between the upper surface of the LED chip and the upper surface of the IC chip is no greater than 2μm.

2. The LED packaging structure according to claim 1, characterized in that: The padding layer comprises multiple transparent layers with more than two layers; the refractive index of each transparent layer gradually decreases from the LED chip toward the spacer layer.

3. The LED packaging structure according to claim 1, characterized in that: The thickness h1 of the pad layer is between 0.5μm and 3μm or between 3μm and 5μm.

4. The LED packaging structure according to claim 1, characterized in that: The distance W1 between the padding layer and the IC chip and the distance W2 between the LED chip and the IC chip satisfy the following condition: W1 ≥ 1 / 5W2.

5. The LED packaging structure according to claim 1, characterized in that: The spacing W1 between the padding layer and the IC chip satisfies: W1≥3μm.

6. The LED packaging structure according to claim 1, characterized in that: The thickness h3 of the IC chip satisfies: 10μm≤h3≤20μm, and the minimum single-sided dimension of the IC chip is 1μm~120μm; the thickness h2 of the LED chip satisfies: 2μm≤h2≤12μm, and the minimum single-sided dimension of the LED chip is 1μm~100μm.

7. The LED packaging structure according to claim 1, characterized in that: The relationship between the thickness h1 of the padding layer, the thickness h2 of the LED chip, and the thickness h3 of the IC chip satisfies: h3-h2-2μm≤h1≤h3-h2+2μm.

8. The LED packaging structure according to claim 1, characterized in that: The ratio of the thickness h2 of the LED chip to the thickness h3 of the IC chip is less than or equal to 60%.

9. The LED packaging structure according to claim 1, characterized in that: The spacer layer includes a transfer layer made of a transparent material.

10. The LED packaging structure according to claim 1, characterized in that: It also includes a chip cover layer, which at least covers a portion of the sidewalls of the LED chip. The chip cover layer includes black adhesive and has a transmittance of ≤10% in the visible light wavelength range of 380nm to 760nm. The LED chip includes electrodes, and at least a portion of the electrodes are exposed from the chip cover layer.

11. The LED packaging structure according to claim 1, characterized in that: It also includes an insulating protective layer located on the side of the spacer layer opposite to the substrate, and at least covering a portion of the surface of the IC chip and / or a portion of the surface of the LED chip.

12. The LED packaging structure according to claim 1, characterized in that: The LED chip and the IC chip have a metal interconnect structure on the side away from the substrate to electrically connect the IC chip and the LED chip; the metal interconnect structure includes a wiring layer, which is in electrical contact with the IC chip and the LED chip respectively.

13. The LED packaging structure according to claim 1, characterized in that: The LED chip includes one or more of red, blue and green chips, and the LED chip is transferred onto the substrate via a mass transfer process; a common pad layer is provided under the multiple LED chips, or multiple independent pad layers are provided respectively.

14. The LED packaging structure according to claim 1, characterized in that: The substrate is a transparent substrate, and the transmittance of the transparent substrate in the visible light band of 380nm~760nm is not less than 90%.

15. The LED packaging structure according to any one of claims 1 to 14, characterized in that: The spacer layer has a partially thinned area on the side opposite to the substrate, and the IC chip is disposed within the partially thinned area.

16. The LED packaging structure according to claim 15, characterized in that: The distance W3 between the edge of the locally thinned region and the IC chip satisfies: W3≥5μm and W3≤20μm.

17. An LED packaging structure, characterized in that, include: substrate; A spacer layer is located on the substrate; The spacer layer has a locally thinned area on the side opposite to the substrate; An IC chip is disposed within the localized thinning area; At least a plurality of LED chips are located on the surface of the spacer layer opposite to the substrate and are spaced apart from the IC chip; The absolute value of the vertical height difference H between the upper surface of the LED chip and the upper surface of the IC chip is no greater than 2μm.

18. The LED packaging structure according to claim 17, characterized in that: The distance W3 between the edge of the locally thinned region and the IC chip satisfies: W3≥5μm and W3≤20μm.

19. The LED packaging structure according to claim 17, characterized in that: The relationship between the depth d1 of the locally thinned region and the thickness d2 of the spacer layer satisfies: d1 < d2; and / or, the depth d1 of the locally thinned region satisfies: d1 ≤ 2 μm.

20. The LED packaging structure according to any one of claims 17 to 19, characterized in that: It also includes at least one padding layer, which is located between the spacer layer and the LED chip.

21. The LED packaging structure according to claim 20, characterized in that: The padding layer comprises multiple transparent layers with more than two layers; the refractive index of each transparent layer gradually decreases from the LED chip toward the spacer layer.

22. The LED packaging structure according to claim 20, characterized in that: The distance W1 between the padding layer and the IC chip and the distance W2 between the LED chip and the IC chip satisfy: W1 ≥ 1 / 5W2; or the distance W1 between the padding layer and the IC chip satisfies: W1≥3μm.

23. A light-emitting device, characterized in that: This includes using the LED packaging structure as described in any one of claims 1 to 22.

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