Display panel and electronic device including the same

Abstract

The invention provides a display panel and electronic equipment comprising the display panel. The display panel includes: a base layer; a pixel defining layer on the base layer and including a first light emitting opening and a second light emitting opening; and a light emitting element layer including a first light emitting element overlapping the first light emitting opening and a second light emitting element overlapping the second light emitting opening. The pixel defining layer includes a valley pattern disposed between the first light emitting opening and the second light emitting opening, and recessed from an upper surface of the pixel defining layer in a thickness direction of the pixel defining layer, and the valley pattern includes a first valley pattern between the first light emitting opening and the second light emitting opening, and a second valley pattern between the first valley pattern and the second valley pattern. The second light-emitting opening is disposed closer to the first light-emitting opening than to the second light-emitting opening.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0137927, filed on October 10, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a display panel and an electronic device including the same. More particularly, the present disclosure relates to a display panel having improved display characteristics and an electronic device including the same. BACKGROUND

[0003] Electronic devices such as a smart phone, a tablet computer, a digital camera, a notebook computer, a navigation device, or a television, etc. that provide an image to a user include a display panel to display the image.

[0004] The display panel includes red, green, and blue pixels to display colors, and a light emitting layer that emits light having a color of a corresponding pixel is formed in each pixel. Generally, the light emitting layer is formed by a deposition method using a shadow mask. However, due to defects such as a mask sag, a process of forming a light emitting layer and other organic layers commonly throughout the pixels through an open mask has been developed.

[0005] However, in the case of commonly forming the organic layers, a lateral leakage current can occur due to the organic layer commonly provided between adjacent pixels, thereby causing color mixing and poor brightness between the adjacent pixels.

[0006] The lateral leakage current is blocked by placing a valley pattern between pixels adjacent to each other. However, in the case where the height or slope of the valley pattern is excessively increased, the thickness of the organic layer becomes non-uniform in a region adjacent to the pixel, and thus, an overshoot occurs due to the presence of accumulated excess charge. In the case of switching frames, the overshoot causes a specific pixel to appear brighter than a set brightness, thereby causing a decrease in image quality. SUMMARY

[0007] The present disclosure provides a display panel capable of reducing charge imbalance in a region adjacent to a pixel and preventing a lateral leakage current from occurring between adjacent pixels to prevent color mixing between the adjacent pixels and improve poor image quality, and an electronic device including the same.

[0008] However, embodiments are not limited to those set forth herein. The above and other embodiments will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0009] Embodiments of the present invention provide a display panel including: a substrate layer; a pixel definition layer disposed on the substrate layer and including a first light emission opening and a second light emission opening; and a light emission element layer including a first light emission element overlapping the first light emission opening and a second light emission element overlapping the second light emission opening. The pixel definition layer includes a valley pattern disposed between the first light emission opening and the second light emission opening and recessed from an upper surface of the pixel definition layer in a thickness direction of the pixel definition layer. The valley pattern includes a first valley pattern disposed between the first light emission opening and the second light emission opening and disposed closer to the first light emission opening than to the second light emission opening. The first valley pattern includes a first-first side surface, a first-second side surface disposed closer to the second light emission opening than the first-first side surface, and a lower surface disposed between the first-first side surface and the first-second side surface, and the first-first side surface has a smaller inclination angle than an inclination angle of the first-second side surface.

[0010] The inclination angle of the first-first side surface can be less than about 74 degrees, and the inclination angle of the first-second side surface can be greater than or equal to about 74 degrees and less than or equal to about 90 degrees.

[0011] The first light emission element can include a first electrode partially exposed through the first light emission opening, and a distance from a boundary between the first electrode and the first light emission opening to the first-second side surface can be greater than or equal to about 8 micrometers.

[0012] The first valley pattern can have a depth less than or equal to about 650 nm.

[0013] The valley pattern can further include a second valley pattern disposed between the first light emission opening and the second light emission opening and disposed closer to the second light emission opening than to the first light emission opening. The second valley pattern can include a second-first side surface, a second-second side surface disposed closer to the first light emission opening than the second-first side surface, and a lower surface disposed between the second-first side surface and the second-second side surface, and the second-first side surface can have a smaller inclination angle than an inclination angle of the second-second side surface.

[0014] The first valley pattern can include a first-first valley pattern and a first-second valley pattern arranged to surround a portion of the first light emission opening, and an area of the first-first valley pattern at which the first-first valley pattern is spaced apart from the first-second valley pattern can face the second valley pattern.

[0015] The first light emitting element can include a first electrode partially exposed through the first light emitting opening, a first-first light emitting layer disposed on the first electrode, a charge generation layer disposed on the first-first light emitting layer, a second-first light emitting layer overlapping the first-first light emitting layer and disposed on the charge generation layer, and a second electrode disposed on the second-first light emitting layer and the charge generation layer.

[0016] The first-first light emitting layer and the second-first light emitting layer can emit light having the same wavelength.

[0017] The second light emitting element can include a first electrode partially exposed through the second light emitting opening, a first-second light emitting layer disposed on the first electrode of the second light emitting element, a charge generation layer disposed on the first-second light emitting layer, a second-second light emitting layer overlapping the first-second light emitting layer and disposed on the charge generation layer, and a second electrode disposed on the second-second light emitting layer and the charge generation layer. The charge generation layer of the first light emitting element and the charge generation layer of the second light emitting element can have a single unitary shape, and the second electrode of the first light emitting element and the second electrode of the second light emitting element can have a single unitary shape.

[0018] The first-first light emitting layer and the second-first light emitting layer can emit light having the same wavelength, and the first-first light emitting layer and the first-second light emitting layer can emit light having wavelengths different from each other.

[0019] The charge generation layer can overlap the valley pattern, the charge generation layer can include an n-type charge generation layer and a p-type charge generation layer disposed on the n-type charge generation layer, and the n-type charge generation layer can be broken on the first-second side surface of the first valley pattern.

[0020] A thickness of a portion of the charge generation layer overlapping the first-first side surface of the first valley pattern can be greater than a thickness of a portion of the charge generation layer overlapping the first-second side surface of the first valley pattern.

[0021] A lower surface of the first valley pattern can include a first region, and a second region disposed between the first region and the first-second side surface and recessed deeper than the first region.

[0022] The first valley pattern can include first through nth valley patterns, where n can be an integer greater than 1, and the first through nth valley patterns can be continuously arranged from the first light emitting opening toward the second light emitting opening.

[0023] The first light emitting element can include a first electrode partially exposed through the first light emitting opening, and a distance from a boundary between the first electrode and the first light emitting opening to the first valley pattern can be greater than or equal to about 8 micrometers.

[0024] An embodiment provides a display panel including: a base layer including a first light emitting area, a second light emitting area adjacent to the first light emitting area, and a non-light emitting area adjacent to the first light emitting area and the second light emitting area; a pixel definition layer disposed on the base layer and including a first light emitting opening and a second light emitting opening overlapping the first light emitting area and the second light emitting area, respectively; and a light emitting element layer at least a portion of which is disposed in the first light emitting opening and the second light emitting opening. The pixel definition layer includes a valley pattern overlapping the non-light emitting area and recessed from an upper surface of the pixel definition layer in a thickness direction of the pixel definition layer, and the valley pattern includes a first valley pattern disposed closer to the first light emitting opening than to the second light emitting opening and a second valley pattern disposed closer to the second light emitting opening than to the first light emitting opening. The first valley pattern includes a first-first side surface surrounding a portion of the first light emitting area, a first-second side surface disposed closer to the second light emitting opening than to the first-first side surface, and a lower surface disposed between the first-first side surface and the first-second side surface, and the first-first side surface has a smaller inclination angle than an inclination angle of the first-second side surface.

[0025] The light emitting element layer can include: a first anode partially exposed through the first light emitting opening; a second anode partially exposed through the second light emitting opening; a first-first light emitting layer disposed on the first anode; a first-second light emitting layer disposed on the second anode; an organic layer commonly disposed on the first anode and the second anode; a second-first light emitting layer disposed on the first-first light emitting layer; a second-second light emitting layer disposed on the first-second light emitting layer; and a cathode commonly disposed on the second-first light emitting layer and the second-second light emitting layer.

[0026] Each of the first-first light emitting layer and the second-first light emitting layer can emit first light, and each of the first-second light emitting layer and the second-second light emitting layer can emit second light having a wavelength different from a wavelength of the first light.

[0027] A thickness of the organic layer on the first-first side surface can be greater than a thickness of the organic layer on the first-second side surface.

[0028] An electronic device according to an embodiment is provided. The electronic device includes a display module; a window disposed on the display module; and a housing disposed below the display module. The display module includes a base layer; a pixel definition layer disposed on the base layer and including a first light emission opening and a second light emission opening; and a light emission element layer including a first light emission element overlapping the first light emission opening and a second light emission element overlapping the second light emission opening. The pixel definition layer includes a valley pattern disposed between the first light emission opening and the second light emission opening and recessed from an upper surface of the pixel definition layer in a thickness direction of the pixel definition layer, and the valley pattern includes a first valley pattern disposed between the first light emission opening and the second light emission opening and disposed closer to the first light emission opening than to the second light emission opening. The first valley pattern includes a first-first side surface, a first-second side surface disposed closer to the second light emission opening than the first-first side surface, and a lower surface disposed between the first-first side surface and the first-second side surface, and the first-first side surface has a smaller inclination angle than an inclination angle of the first-second side surface.

[0029] According to the above, the valley pattern can include one side surface adjacent to one of the light emission openings and another side surface adjacent to another of the light emission openings, and can have an asymmetric shape in which an inclination of the one side surface is gentler than an inclination of the other side surface. Since an organic layer that can be disposed on the one side surface of the valley pattern closer to the one opening is formed more uniformly, charge imbalance in a region adjacent to the one opening can be improved. Accordingly, a response speed and an image quality characteristic of the display panel can be improved.

[0030] Further, a lateral leakage current is prevented by the other side surface of the valley pattern. As a result, the display panel provides a luminance corresponding to a gray value. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a schematic combined perspective view of an electronic device according to an embodiment;

[0032] Figure 2 is a schematic exploded perspective view of an electronic device according to an embodiment;

[0033] Figure 3 is a schematic cross-sectional view of a display module according to an embodiment;

[0034] Figure 4 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0035] Figure 5A is an enlarged schematic plan view of a portion of a display panel according to an embodiment;

[0036] Figure 5B is a schematic cross-sectional view of a display panel according to an embodiment;

[0037] Figure 5C is an enlarged schematic cross-sectional view of a portion of a light-emitting element according to an embodiment;

[0038] Figure 6 is a schematic cross-sectional view of a display panel according to an embodiment; Figure 5B is an enlarged schematic cross-sectional view of a region BB' of the display panel of

[0039] Figure 7 , Figure 8 , Figure 9A and Figure 9B is an enlarged schematic cross-sectional view of a portion of a display panel according to an embodiment. DETAILED DESCRIPTION

[0040] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable terms that refer to non-limiting examples of the apparatus or methods disclosed herein. It will be apparent, however, that various embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the concepts of various embodiments. It will be apparent to one of ordinary skill in the art, in view of this disclosure, that the various embodiments can include a variety of other features and alternatives.

[0041] The illustrated embodiments are to be understood as providing features of the present invention. Thus, unless otherwise noted, features, components, modules, layers, films, panels, regions, and / or aspects of the various embodiments (hereinafter referred to collectively as "elements") can be combined with each other in any manner possible by those of skill in the art, along with other present or currently

[0042] The use of cross-hatching and / or shading in the attached figures is generally provided to illustrate the boundaries of regions or areas in a single figure. As the skilled artisan will appreciate, the absence of cross-hatching and / or shading from a region in a figure should not be construed to mean that the region is void of the attribute it is in common with other regions in the same figure. Further, unless otherwise indicated, the size, proportions, and / or relative placement of the various elements in the attached figures can be exaggerated or otherwise not drawn to scale for the sake of illustration. When an embodiment can be implemented differently, the specific order or hierarchy of processing steps can be performed differently, or other processing steps can be performed in place of or in addition to the described processing steps. For example, two described processing steps can be executed substantially concurrently or in reverse order, or additional processing steps can be executed between described processing steps. Additionally, the same reference numerals are generally used to refer to the same elements throughout the description.

[0043] When an element or layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected, or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, or “directly coupled to” another element or layer, then there are no intervening elements or layers present. In this regard, the term “connected” can refer to physical or electrical and / or fluid connection, with or without wiring. Further, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to directions corresponding to three axes (e.g., X-axis, Y-axis, and Z-axis) of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. In terms of the present disclosure, “at least one of A and B” can be understood to mean only A, only B, or any combination of A and B. Also, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0044] Although the terms “first”, “second”, etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0045] Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper”, “on”, “over”, “side” (e.g., as in “sidewall”), and the like, can be used herein for descriptive purposes, and, thereby, to describe one element’s relationship to another element(s) as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and, as such, the spatially relative descriptors used herein are to be interpreted in the context as described.

[0046] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "with," or "contains," "containing," are used in the detailed description and / or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional term in a claim. Also, it is to be noted that the term "substantially" and the like are used herein as terms of approximation and not as terms of degree, unless otherwise indicated, and therefore such terms are utilized to account for minor variations from the intended exemplary design as would be recognized by one skilled in the art. For example, "substantially" can mean within one or more standard deviations of a stated value, or within ±20%, ±15%, ±10%, or ±5% of a stated value.

[0047] Various embodiments are described herein with reference to cross-sectional and / or exploded illustrations of schematic illustrations of embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, embodiments disclosed herein are not to be construed as being limited to the particular shapes of regions illustrated in the drawings as such regions can not be perfectly shaped. In this manner, the regions illustrated in the drawings can be schematic in nature and the shapes of the regions illustrated in the figures can not reflect the actual shapes of the regions of devices being described and, as such, are not intended to limit the scope of embodiments described herein.

[0048] As is conventional in the art, some embodiments are described in terms of functional blocks, units, and / or modules, and are illustrated in the attached figures as block diagrams. Those skilled in the art will recognize that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and / or a combination thereof designed to perform the various functions described herein. In this regard, each block, unit, and / or module can be, for example, a software module executing on one or more microprocessors, hardware circuits (e.g., integrated circuits), or a combination thereof. Those skilled in the art should appreciate that the functions described herein, which are the subject of this disclosure, can be implemented in a variety of ways. For example, the functions can be implemented in hardware (e.g., analog or digital), in software or by a combination of hardware and software. As is conventional in the art, some embodiments are described in terms of functional blocks, units, and / or modules, and are illustrated in the attached figures as block diagrams. Those skilled in the art will recognize that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and / or a combination thereof designed to perform the various functions described herein. In this regard, each block, unit, and / or module can be, for example, a software module executing on one or more microprocessors, hardware circuits (e.g., integrated circuits), or a combination thereof. Those skilled in the art should appreciate that the functions described herein, which are the subject of this disclosure, can be implemented in a variety of ways. For example, the functions can be implemented in hardware (e.g., analog or digital), in software or by a combination of hardware and software. As is conventional in the art, some embodiments are described in terms of functional blocks, units, and / or modules, and are illustrated in the attached figures as block diagrams. Those skilled in the art will recognize that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and / or a combination thereof designed to perform the various functions described herein. In this regard, each block, unit, and / or module can be, for example, a software module executing on one or more microprocessors, hardware circuits (e.g., integrated circuits), or a combination thereof. Those skilled in the art should appreciate that the functions described herein, which are the subject of this disclosure, can be implemented in a variety of ways. For example, the functions can be implemented in hardware (e.g., analog or digital), in software or by a combination of hardware and software. As is conventional in the art, some embodiments are described in terms of functional blocks, units, and / or modules, and are illustrated in the attached figures as block diagrams. Those skilled in the art will recognize that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and / or a combination thereof designed to perform the various functions described herein. In this regard, each block, unit, and / or module can be, for example, a software module executing on one or more microprocessors, hardware circuits (e.g., integrated circuits), or a combination thereof. Those skilled in the art should appreciate that the functions described herein, which are the subject of this disclosure, can be implemented in a variety of ways. For example, the functions can be implemented in hardware (e.g., analog or digital), in software or by a combination of hardware and software.

[0049] In the following, embodiments will be described with reference to the attached figures.

[0050] Figure 1 is a schematic combined perspective view of an electronic device ED according to an embodiment. Figure 2 is a schematic exploded perspective view of an electronic device ED according to an embodiment.

[0051] With reference to Figure 1 The electronic device ED can be activated in response to an electrical signal. The electronic device ED can display an image IM and can sense an external input. The electronic device ED can be implemented according to various embodiments. For example, the electronic device ED can be a computer such as a tablet computer or a notebook computer, a smart phone, or a television, etc. In the present embodiment, a tablet computer is shown as an example of the electronic device ED, however, the present disclosure should not be limited thereto or thereby. The electronic device ED can be a smart phone, a notebook computer, or a large-sized display apparatus such as a monitor or a television.

[0052] The electronic device ED can display the image IM toward a third direction DR3 through a display surface DS substantially parallel to each of the first direction DR1 and the second direction DR2. The display surface DS through which the image IM is displayed can correspond to a front surface of the electronic device ED and a front surface of a window described later. The image IM can include still images and videos. Figure 1 An application icon is shown as a representative example of the image IM.

[0053] In the present embodiment, a front (or upper) surface and a rear (or lower) surface of each member of the electronic device ED can be defined with respect to a direction in which the image IM is displayed. The front surface and the rear surface can be opposite to each other in the third direction DR3, and a normal direction of each of the front surface and the rear surface can be substantially parallel to the third direction DR3. A separation distance between the front surface and the rear surface in the third direction DR3 can correspond to a thickness of the electronic device ED in the third direction DR3. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be relative to each other, and can be changed to other directions. In the following description, the expression "when viewed in a plane" or "in a plan view" can mean a state of viewing a plane defined by the first direction DR1 and the second direction DR2 in the third direction DR3.

[0054] The electronic device ED can sense a user input applied thereto from the outside. The user input can include various types of external inputs such as a part of a user's body, light, heat, or pressure. The user input can be provided in various ways, and the electronic device ED can sense a user input applied to a side surface or a rear surface of the electronic device ED according to its structure, however, the present disclosure should not be limited thereto.

[0055] As shown in FIG. 1A, the electronic device ED can include a window WM, a display module DM, and a housing EDC. In the present embodiment, the window WM can be coupled to the housing EDC to form an appearance of the electronic device ED. In the present embodiment, the housing EDC, the display module DM, and the window WM can be sequentially stacked in the third direction DR3. Figure 2

[0056] The window WM can include an optically transparent material. The window WM can include an insulating plate. As an example, the window WM can include glass, plastic, or a combination thereof.

[0057] As described above, a front surface of the window WM can define a front surface of the electronic device ED.

[0058] The window WM can include a bezel area and a transmissive area. The transmissive area can be an optically transparent area. For example, the transmissive area can have a transmittance of about 90% or more with respect to visible light.

[0059] ​The bezel area can have a relatively lower light transmittance than the light transmittance of the transmissive area. The bezel area can define a shape of the transmissive area. The bezel area can be defined adjacent to the transmissive area and can surround the transmissive area. The bezel area can have a color. The bezel area can overlap the non-display area DP-NDA of the display panel DP described later. The bezel area can cover the non-display area DP-NDA of the display panel DP to prevent the non-display area DP-NDA from being seen from the outside, however, this is an example. According to an embodiment, the bezel area can be omitted from the window WM.

[0060] The display module DM can include at least the display panel DP. The display module DM can further include components disposed above and below the display panel DP in addition to the display panel DP. A detailed stack structure of the display module DM will be described later.

[0061] The display panel DP can include a display area DP-DA and a non-display area DP-NDA corresponding to the display area DA (refer to Figure 1 ) and the non-display area NDA (refer to Figure 1 ) of the electronic device ED, respectively. In the present disclosure, the expression "an area / portion corresponds to another area / portion" means "an area / portion overlaps another area / portion", however, "areas and portions" should not be limited to having the same size as each other. The display module DM can further include a driving chip DIC disposed in the non-display area DP-NDA. The display module DM can further include a printed circuit board PCB coupled to the non-display area DP-NDA. The printed circuit board PCB can be electrically connected to a pad disposed in the non-display area DP-NDA of the display panel DP through an anisotropic adhesive layer.

[0062] The driving chip DIC can include a driving element to drive a pixel of the display panel DP. As an example, the driving chip DIC can include a data driving circuit. Figure 2 A structure in which the driving chip DIC is mounted on the display panel DP is illustrated, however, the present disclosure should not be limited to or by this. As an example, the driving chip DIC can be mounted on the printed circuit board PCB.

[0063] The housing EDC can accommodate the display module DM and can be coupled to the window WM. The housing EDC can protect components such as the display module DM accommodated therein from external impact.

[0064] Figure 3 FIG. 1 is a schematic cross-sectional view of a display module DM according to an embodiment, and Figure 4 FIG. 2 is a schematic cross-sectional view of a portion of a display panel DP according to an embodiment. Figure 4 An organic light emitting element OLED and a transistor TR included in a pixel of the display panel DP are illustrated.

[0065] Referring to Figure 3 , the display module DM can include a display panel DP and an input sensing unit ISU. The display panel DP can have a configuration to generate an image IM (refer to Figure 1 ). A user can see the image IM (refer to Figure 1 ) generated by the display panel DP from the outside through a display area DA (refer to Figure 1 ).

[0066] The display panel DP can be a light emitting type display panel, however, should not be limited thereto. For example, the display panel DP can be an organic light emitting display panel or an inorganic light emitting display panel. The light emitting layer of the organic light emitting display panel can include an organic light emitting material. The inorganic light emitting display panel can be a display panel including a light emitting layer including quantum dots and / or quantum rods or including micro-LEDs.

[0067] The input sensing unit ISU can be disposed on the display panel DP. The input sensing unit ISU can sense an external input received from the outside. The external input can include various inputs provided from the outside of the electronic device ED (refer to Figure 1 ). As an example, the external input can include a proximity input (e.g., hovering) applied when approaching or being adjacent to the electronic device ED at a certain distance and a touch input by a part of a user's body (e.g., a user's hand). For example, the external input can be provided in the form of force, pressure, light, etc., and should not be limited thereto.

[0068] The input sensing unit ISU can be formed on the display panel DP through a continuous process. For example, the input sensing unit ISU can be disposed on (e.g., directly disposed on) the display panel DP. In the following description, the expression "a component A is directly disposed on a component B" means that there is no intervening element between the component A and the component B. For example, a separate adhesive layer can not be disposed between the input sensing unit ISU and the display panel DP.

[0069] The display panel DP can include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a top insulating layer TFL disposed on the display element layer DP-OLED.

[0070] The base layer BL can provide a base surface on which the circuit element layer DP-CL, the display element layer DP-OLED, and the upper insulating layer TFL are stacked. The base layer BL can be a rigid substrate, or a flexible substrate that is bendable, foldable, or rollable. The base layer BL can be a glass substrate, a metal substrate, or a polymer substrate, however, it should not be limited thereto or thereby. According to an embodiment, the base layer BL can include an inorganic layer, an organic layer, or a composite layer.

[0071] The base layer BL can have a multi-layer structure. For example, the base layer BL can include a first synthetic resin layer, an inorganic layer having a single-layer structure or a multi-layer structure, and a second synthetic resin layer disposed on the inorganic layer having a single-layer structure or a multi-layer structure. Each of the first synthetic resin layer and the second synthetic resin layer can include a polyimide-based resin, however, it should not be limited thereto.

[0072] The circuit element layer DP-CL can be disposed on the base layer BL. The circuit element layer DP-CL can include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The conductive layer of the circuit element layer DP-CL can form a signal line or a control circuit of a pixel.

[0073] The display element layer DP-OLED can be disposed on the circuit element layer DP-CL. The display element layer DP-OLED can include a light emitting element OLED (refer to Figure 4 ). The display element layer DP-OLED can include, for example, an organic light emitting element, however, this is an example. The display element layer DP-OLED can include an inorganic light emitting element, an organic-inorganic light emitting element, or a liquid crystal layer. In the present disclosure, a layer of the display element layer DP-OLED for forming the light emitting element OLED (refer to Figure 4 ) can be referred to as a light emitting element layer.

[0074] The upper insulating layer TFL can include a later-described encapsulation layer and a packaging layer (e.g., a thin film encapsulation layer). The upper insulating layer TFL can include an organic layer and a plurality of inorganic layers that encapsulate the organic layer.

[0075] The upper insulating layer TFL can be disposed on the display element layer DP-OLED, and can protect the display element layer DP-OLED from moisture, oxygen, and foreign substances such as dust particles. The upper insulating layer TFL can encapsulate the display element layer DP-OLED to prevent moisture, oxygen, and foreign substances such as dust particles from entering the display element layer DP-OLED. The upper insulating layer TFL can include at least one inorganic layer. The upper insulating layer TFL can include an organic layer and inorganic layers that encapsulate the organic layer. The upper insulating layer TFL can include a stacked structure of inorganic layers / organic layers / inorganic layers.

[0076] The input sensing unit (ISU) can be disposed on the upper insulating layer (TFL). The input sensing unit (ISU) can be formed on the upper insulating layer (TFL) through a continuous process. The input sensing unit (ISU) can be disposed on (e.g., directly disposed on) the display panel (DP). For example, no separate adhesive member may be provided between the input sensing unit (ISU) and the display panel (DP). The input sensing unit (ISU) can be configured to contact the inorganic layer disposed at the topmost position of the upper insulating layer (TFL).

[0077] For example, the display module DM according to an embodiment may further include a protective member disposed on the lower surface of the display panel DP and an anti-reflective member disposed on the upper surface of the input sensing unit ISU. The anti-reflective member can reduce the reflectivity of the display module DM relative to external light. The anti-reflective member can be disposed on the input sensing unit ISU through a continuous process (e.g., directly disposed on it).

[0078] The anti-reflective member may include a light-shielding pattern that overlaps with a reflective structure disposed below the anti-reflective member. The anti-reflective member may further include color filters. The color filters may be disposed between these light-shielding patterns and may include a first color filter, a second color filter, and a third color filter corresponding to a first color pixel, a second color pixel, and a third color pixel, respectively.

[0079] like Figure 3 As shown in the diagram, in a plan view, the display panel DP may include a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP may be the area where the image IM is displayed, and the non-display area DP-NDA may be the area where driving circuitry and driving lines are arranged. The light-emitting elements of the pixels may be arranged in the display area DP-DA. The display area DP-DA may be connected to the window WM (see reference). Figure 2 The transmission areas of the window WM overlap by at least a portion, and the non-display area DP-NDA can be covered by the border area of ​​the window WM.

[0080] In the following text, reference will be made to Figure 4 This section describes in detail the circuit element layer DP-CL, the display element layer DP-OLED, and the upper insulating layer TFL.

[0081] refer to Figure 4 The circuit element layer DP-CL may include circuit elements and at least one insulating layer. The circuit elements may include signal lines and pixel driving circuitry. The circuit element layer DP-CL can be formed by coating or deposition processes to form an insulating layer, a semiconductor layer, and a conductive layer, and by photolithography processes to pattern the insulating layer, the semiconductor layer, and the conductive layer.

[0082] The buffer layer BFL may include at least one inorganic layer. A semiconductor pattern may be disposed on the buffer layer BFL. The buffer layer BFL can increase the adhesion between the substrate layer BL and the semiconductor pattern.

[0083] Semiconductor patterns may include polycrystalline silicon, however, they should not be limited to or restricted by it. Semiconductor patterns may also include amorphous silicon or metal oxides. Figure 4 A portion of a semiconductor pattern is shown, and in the planar view, the semiconductor pattern can be further arranged in other areas of the pixel. The semiconductor pattern can be arranged across each pixel according to specific rules.

[0084] Semiconductor patterns can have different electrical properties depending on whether they are doped. A semiconductor pattern may include a first region A1 with low doping concentration and low conductivity, and second regions S1 and D1 with relatively high doping concentration and high conductivity. One second region S1 may be disposed adjacent to one side of the first region A1, and another second region D1 may be disposed adjacent to the other side of the first region A1. The second regions S1 and D1 may be doped with N-type or P-type dopant. A P-type transistor may include a doped region doped with P-type dopant. The first region A1 may be an undoped region, or it may be doped at a lower concentration than the second regions S1 and D1.

[0085] The second regions S1 and D1 can be essentially used as electrodes or signal lines. One second region S1 can correspond to the source of a transistor, and the other second region D1 can correspond to the drain of a transistor. Figure 4 A portion of a connection signal line SCL formed by a semiconductor pattern is shown. For example, in a planar diagram, the connection signal line SCL can be connected to the drain of a transistor TR.

[0086] The first insulating layer 10 can be disposed on the buffer layer BFL. The first insulating layer 10 can be disposed in common with the display area DP-DA (reference). Figure 3 The pixels in the DP-CL overlap and can cover the semiconductor pattern. The first insulating layer 10 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The first insulating layer 10 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. Not only the first insulating layer 10, but also the insulating layer of the circuit element layer DP-CL, which is described later, can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure.

[0087] Gate G1 may be disposed on the first insulating layer 10. Gate G1 may be part of a metal pattern. Gate G1 may overlap with the first region A1. Gate G1 may be used as a mask in a process of doping the semiconductor pattern.

[0088] A second insulating layer 20 can be disposed on the first insulating layer 10 and can cover the gate G1. The second insulating layer 20 can overlap each pixel in common. An upper electrode UE can be disposed on the second insulating layer 20. The upper electrode UE can overlap the gate G1. The upper electrode UE can include a plurality of metal layers. In another example, the upper electrode UE can be omitted.

[0089] A third insulating layer 30 can be disposed on the second insulating layer 20 and can cover the upper electrode UE. A first connection electrode CNE1 can be disposed on the third insulating layer 30. The first connection electrode CNE1 can be connected to the connection signal line SCL via a contact hole CNT-1 defined through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0090] A fourth insulating layer 40 can be disposed on the third insulating layer 30 and can cover the first connection electrode CNE1. A fifth insulating layer 50 can be disposed on the fourth insulating layer 40. The fourth insulating layer 40 can be an organic layer. A second connection electrode CNE2 can be disposed on the fourth insulating layer 40. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 via a contact hole CNT-2 defined through the fourth insulating layer 40.

[0091] The fifth insulating layer 50 can be disposed on the fourth insulating layer 40 and can cover the second connection electrode CNE2. The fifth insulating layer 50 can be an organic layer.

[0092] The light emitting element OLED can include a first electrode AE, a first light emitting layer EML1, a charge generation layer CGL, a second light emitting layer EML2, and a second electrode CE, which are sequentially stacked. The light emitting element OLED can be a light emitting element having a series structure including the light emitting layers EML1 and EML2. A detailed description of the series structure will be described later.

[0093] The first electrode AE can be disposed on the circuit element layer DP-CL. The first electrode AE can be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The first electrode AE can be connected to the second connection electrode CNE2 via a contact hole CNT-3 defined through the fifth insulating layer 50. Accordingly, the first electrode AE can be electrically connected to the connection signal line SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and thus, the first electrode AE can be electrically connected to the corresponding circuit element. The first electrode AE can have a single layer structure or a multi-layer structure.

[0094] The first electrode AE can be an anode or a cathode. For example, the first electrode AE can be a pixel electrode. The second electrode CE can be a cathode or an anode. The second electrode CE can be a common electrode. As an example, in the case where the first electrode AE is an anode, the second electrode CE can be a cathode, and in the case where the first electrode AE is a cathode, the second electrode CE can be an anode.

[0095] The first and second light emitting layers EML1 and EML2 can emit light having the same wavelength as each other. As an example, the light emitted from each of the first and second light emitting layers EML1 and EML2 can be blue light, however, the present disclosure should not be limited thereto or be restricted thereto. According to an embodiment, the light emitted from the light emitting layers EML1 and EML2 can have different wavelength ranges from each other. As an example, at least one of the light emitting layers EML1 and EML2 can emit blue light, and the other of the light emitting layers EML1 and EML2 can emit green light. The light emitting element OLED including the light emitting layers EML1 and EML2 emitting light having different wavelength ranges from each other can emit white light.

[0096] The charge generation layer CGL can be disposed between the first and second light emitting layers EML1 and EML2. In the case where a voltage is applied to the charge generation layer CGL, the charge generation layer CGL can form a complex through a redox reaction, and thus, can generate charges (e.g., electrons and holes). For example, the charge generation layer CGL can provide the generated charges to each of the light emitting layers EML1 and EML2. The charge generation layer CGL can double the efficiency of the current generated in the light emitting layers EML1 and EML2, and can adjust the charge balance between the light emitting layers EML1 and EML2. The charge generation layer CGL can have a single unitary shape, and can be disposed commonly across the pixels.

[0097] The second electrode CE can be disposed on the second light emitting layer EML2. The second electrode CE can have a single unitary shape, and can be disposed commonly across the pixels.

[0098] The display element layer DP-OLED can include a pixel definition layer PDL disposed on the circuit element layer DP-CL. The light emitting opening OP can be defined through the pixel definition layer PDL, and at least a portion of the first electrode AE can be exposed through the light emitting opening OP of the pixel definition layer PDL. According to an embodiment, the pixel definition layer PDL can cover the edge portion of the first electrode AE.

[0099] The display area DP-DA (refer to FIG. 2A) can be defined by the display element layer DP-OLED and the circuit element layer DP-CL. The display area DP-DA can be defined by the display element layer DP-OLED and the circuit element layer DP-CL, and the display area DP-DA can be defined by the display element layer DP-OLED and the circuit element layer DP-CL. Figure 3) can include a light emitting area PXA and a non-light emitting area NPXA adjacent to the light emitting area PXA. The non-light emitting area NPXA can surround the light emitting area PXA. In the present embodiment, the light emitting area PXA can be defined to correspond to a portion of the first electrode AE exposed through the light emitting opening OP. In the present disclosure, the light emitting area PXA can be referred to as a pixel area, and the non-light emitting area NPXA can be referred to as a non-pixel area.

[0100] The pixel definition layer PDL can have a single-layer structure or a multi-layer structure. The pixel definition layer PDL can include a polymer resin. As an example, the pixel definition layer PDL can include a polyacrylate-based resin or a polyimide-based resin. For example, the pixel definition layer PDL can further include an inorganic material in addition to the polymer resin. The pixel definition layer PDL can include a light absorbing material, a black pigment, or a black dye. The pixel definition layer PDL including the black pigment or the black dye can be implemented as a black pixel definition layer. In the case of forming the black pixel definition layer PDL, carbon black can be used as the black pigment or the black dye, however, the present embodiment should not be limited thereto or thereby.

[0101] For example, the pixel definition layer PDL can include an inorganic material. As an example, the pixel definition layer PDL can include an inorganic material such as silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ).

[0102] Referring to Figure 4 , the upper insulating layer TFL can be disposed on the display element layer DP-OLED, and can include a thin film. According to an embodiment, the upper insulating layer TFL can include a capping layer CPL and a packaging layer TFE disposed on the capping layer CPL. The capping layer CPL can be disposed on the second electrode CE, and can be in contact with the second electrode CE. The capping layer CPL can include an organic material.

[0103] The packaging layer TFE can include a first inorganic packaging layer TIOL1, an organic packaging layer TOL disposed on the first inorganic packaging layer TIOL1, and a second inorganic packaging layer TIOL2 disposed on the organic packaging layer TOL. The first inorganic packaging layer TIOL1 and the second inorganic packaging layer TIOL2 can protect the display element layer DP-OLED from moisture and oxygen, and the organic packaging layer TOL can protect the display element layer DP-OLED from foreign substances such as dust particles.

[0104] Figure 5A is a magnified schematic plan view of a portion of a display panel DP (refer to Figure 2 ) according to an embodiment,Figure 5B is a schematic cross-sectional view of a display panel DP according to an embodiment, and Figure 5C is an enlarged schematic cross-sectional view of a portion of a light emitting element OLED according to an embodiment. Figure 6 is a schematic plan view of a display panel DP according to an embodiment. Figure 5B is an enlarged schematic cross-sectional view of a region BB' of

[0105] Figure 5A is an enlarged schematic plan view showing Figure 2 an arrangement of pixels in a region AA' and a valley pattern defined adjacent to the pixels.

[0106] Referring to Figure 2 and Figure 5A , a display area DP-DA of the display panel DP can include light emitting areas PXA-G, PXA-B, and PXA-R and non-light emitting areas NPXA surrounding the light emitting areas PXA-G, PXA-B, and PXA-R. The light emitting areas PXA-G, PXA-B, and PXA-R can include a first light emitting area PXA-G, a second light emitting area PXA-B, and a third light emitting area PXA-R. The first light emitting area PXA-G, the second light emitting area PXA-B, and the third light emitting area PXA-R can display light of different wavelengths. The first light emitting area PXA-G can display first light of a green wavelength, the second light emitting area PXA-B can display second light of a blue wavelength, and the third light emitting area PXA-R can display third light of a red wavelength.

[0107] As shown in Figure 5A , the first light emitting area PXA-G can be alternately arranged with the third light emitting area PXA-R in the second direction DR2 to form a first light emitting group, and the second light emitting area PXA-B can be arranged in the second direction DR2 to form a second light emitting group. In the present embodiment, the second light emitting group can include a sub light emitting group, and each of the sub light emitting groups can include two second light emitting areas PXA-B. The two second light emitting areas PXA-B included in one sub light emitting group can be referred to as a second-first light emitting area PXA-B1 and a second-second light emitting area PXA-B2, respectively.

[0108] Each of the first light emitting group including the first light emitting area PXA-G and the third light emitting area PXA-R and the second light emitting group including the second-first light emitting area PXA-B1 and the second-second light emitting area PXA-B2 can be provided as a plurality, and the first light emitting group can be alternately arranged with the second light emitting group in the first direction DR1.

[0109] The light emitting areas PXA-G, PXA-B, and PXA-R can be defined by a pixel defining layer PDL (refer to Figure 4) are distinguished from each other. The non-light emitting area NPXA can correspond to an area between the light emitting areas PXA-G, PXA-B, and PXA-R, and can correspond to a pixel definition layer PDL (refer to Figure 4 ).

[0110] In the present disclosure, each of the light emitting areas PXA-G, PXA-B, and PXA-R can correspond to a pixel. The light emitting areas PXA-G, PXA-B, and PXA-R can be distinguished from each other to correspond to a light emitting opening OP (refer to Figure 4 ) defined by passing through a pixel definition layer PDL (refer to Figure 4 ).

[0111] The light emitting areas PXA-G, PXA-B, and PXA-R can have different sizes from each other according to wavelengths of light emitted from the light emitting areas PXA-G, PXA-B, and PXA-R. As an example, as shown in Figure 5A , the second light emitting area PXA-B that emits second light can have the largest size, and the third light emitting area PXA-R that emits third light can have the smallest size, however, the present disclosure should not be limited thereto or be restricted thereto. According to an embodiment, the light emitting areas PXA-G, PXA-B, and PXA-R can have the same size as each other, or the light emitting areas PXA-G, PXA-B, and PXA-R can be defined to have an area ratio different from the area ratio shown in Figure 5A . According to an embodiment, the light emitting areas PXA-G, PXA-B, and PXA-R can emit light of other colors in addition to green wavelength light, blue wavelength light, and red wavelength light.

[0112] Each of the light emitting areas PXA-G, PXA-B, and PXA-R can have a rectangular shape with rounded corners in a plan view. Each of the first light emitting area PXA-G and the second light emitting area PXA-B can have a rectangular shape with long sides extending in the second direction DR2 and short sides extending in the first direction DR1 and corners where adjacent long sides and short sides meet can have a rounded shape. The third light emitting area PXA-R can have a rectangular shape with long sides extending in the first direction DR1 and short sides extending in the second direction DR2 and corners where adjacent long sides and short sides meet can have a rounded shape.

[0113] As Figure 5A and Figure 5BAs illustrated in FIG. 1A, the base layer BL can include a first light emitting area PXA-G, a second light emitting area PXA-B adjacent to the first light emitting area PXA-G, and a non-light emitting area NPXA adjacent to the first light emitting area PXA-G and the second light emitting area PXA-B. A first light emitting opening OP1 corresponding to the first light emitting area PXA-G and a second light emitting opening OP2 corresponding to the second light emitting area PXA-B can be defined through a pixel definition layer PDL disposed on the base layer BL.

[0114] For example, the valley patterns VP1, VP2, and VP3 can be defined in a plan view to overlap the non-light emitting area NPXA adjacent to each of the light emitting areas PXA-G, PXA-B, and PXA-R and to surround a portion of the light emitting areas PXA-G, PXA-B, and PXA-R, respectively.

[0115] The valley patterns VP1, VP2, and VP3 can be defined in the pixel definition layer PDL. When viewed in a cross-section, the valley patterns VP1, VP2, and VP3 can have a shape that is recessed from an upper surface of the pixel definition layer PDL in a thickness direction of the pixel definition layer PDL. The shape of the valley patterns VP1, VP2, and VP3 in a cross-section will be described in detail later.

[0116] The valley patterns VP1, VP2, and VP3 can include a first valley pattern VP1 surrounding a portion of the first light emitting area PXA-G, a second valley pattern VP2 surrounding a portion of the second light emitting area PXA-B, and a third valley pattern VP3 surrounding a portion of the third light emitting area PXA-R. Each of the first valley pattern VP1, the second valley pattern VP2, and the third valley pattern VP3 can surround a portion of a corresponding one of the first light emitting area PXA-G, the second light emitting area PXA-B, and the third light emitting area PXA-R, and can not surround other portions of the corresponding one of the first light emitting area PXA-G, the second light emitting area PXA-B, and the third light emitting area PXA-R.

[0117] The first valley pattern VP1 can include a first-first valley pattern VP1-1 and a first-second valley pattern VP1-2 arranged to surround a portion of the first light emitting area PXA-G. The first-first valley pattern VP1-1 and the first-second valley pattern VP1-2 can be spaced apart from each other. As illustrated in FIG. 1A, the first-first valley pattern VP1-1 and the first-second valley pattern VP1-2 can be spaced apart from each other in the second direction DR2. Figure 5A As illustrated in FIG. 1A, the first-first valley pattern VP1-1 and the first-second valley pattern VP1-2 can be spaced apart from each other in the second direction DR2.

[0118] In a plan view, the portions of the first-first valley pattern VP1-1 and the first-second valley pattern VP1-2 at which the first-first valley pattern VP1-1 and the first-second valley pattern VP1-2 are spaced apart from each other can face the second valley pattern VP2 adjacent to the portions in the first direction DR1. According to an embodiment, in a plan view, the second valley pattern VP2 can include a plurality of spaced-apart portions, wherein one of the spaced-apart portions of the second valley pattern VP2 can face the third valley pattern VP3 adjacent to the portion in the first direction DR1, and another of the spaced-apart portions of the second valley pattern VP2 can face another of the second valley patterns VP2 adjacent to the portion in the second direction DR2. Similarly, in a plan view, the third valley pattern VP3 can include spaced-apart portions, wherein the spaced-apart portions face the first valley pattern VP1 in the second direction DR2.

[0119] In the display panel according to the present embodiment, the valley patterns VP1, VP2, and VP3 surrounding a portion of the light emitting regions PXA-G, PXA-B, and PXA-R, respectively, can be defined to prevent a lateral leakage current from being generated between the pixels adjacent to each other. In the present disclosure, the lateral leakage current can refer to a current flowing in a direction other than a third direction DR3 (e.g., a direction in which the image IM is displayed) that is a stacking direction of the light emitting element OLED. The lateral leakage current can refer to a current flowing in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2.

[0120] Reference Figure 5A and Figure 5B Since the valley patterns VP1, VP2, and VP3 recessed in the thickness direction of the pixel definition layer PDL are defined in the display panel DP according to the present disclosure, it is possible to prevent a lateral leakage current from being generated between the light emitting regions PXA-G, PXA-B, and PXA-R. Accordingly, it is possible to prevent color mixing between the pixels adjacent to each other, and it is possible to prevent luminance degradation.

[0121] As shown in Figure 5A and Figure 5B The first valley pattern VP1 disposed between the first light emitting opening OP1 and the second light emitting opening OP2 can be disposed closer to the first light emitting opening OP1 than to the second light emitting opening OP2. For example, the first valley pattern VP1 can be disposed closer to the first light emitting region PXA-G than to the second light emitting region PXA-B. For example, the first valley pattern VP1 disposed between the first light emitting opening OP1 and the third light emitting opening OP3 can be disposed closer to the first light emitting opening OP1 than to the third light emitting opening OP3.

[0122] The second valley pattern VP2, located between the second light-emitting opening OP2 and the first light-emitting opening OP1, can be positioned closer to the second light-emitting opening OP2 than to the first light-emitting opening OP1. Similarly, the second valley pattern VP2, located between the second light-emitting opening OP2 and the third light-emitting opening OP3, can be positioned closer to the second light-emitting opening OP2 than to the third light-emitting opening OP3. For example, the second valley pattern VP2 can be positioned closer to the second light-emitting region PXA-B than to the first light-emitting region PXA-G. Likewise, the third valley pattern VP3, located between the third light-emitting opening OP3 and the first light-emitting opening OP1, can be positioned closer to the third light-emitting opening OP3 than to the first light-emitting opening OP1. And the third valley pattern VP3, located between the third light-emitting opening OP3 and the second light-emitting opening OP2, can be positioned closer to the third light-emitting opening OP3 than to the second light-emitting opening OP2.

[0123] Figure 5B According to the embodiments along Figure 5A A schematic cross-sectional view of a portion of the display panel DP taken by line I-I', and Figure 5C This is an enlarged schematic cross-sectional view of a portion of the OLED light-emitting element. Figure 5B and Figure 5C In the diagram, the same / similar reference numerals refer to the same as those in the attached diagram. Figures 1 to 5A The components in the text are the same / similar components, and therefore, detailed descriptions of the same / similar components will be omitted.

[0124] refer to Figure 5A , Figure 5B and Figure 5C The display panel DP may include a substrate layer BL and a circuit element layer DP-CL and a display element layer DP-OLED disposed on the substrate layer BL. For example, the upper insulating layer TFL (reference) Figure 4 It can be further set on the display element layer DP-OLED.

[0125] An OLED light-emitting element disposed on a circuit element layer DP-CL may include a first electrode AE, a first light-emitting stack ST1, a charge-generating layer CGL, a second light-emitting stack ST2, and a second electrode CE, sequentially stacked on a third-direction DR3. Figure 5BIn the middle, the first light emitting stack ST1 can include the first light emitting layer EML1 and a hole control layer HTR disposed between the first light emitting layer EML1 and the first electrode AE, and the second light emitting stack ST2 can include the second light emitting layer EML2 and an electron control layer ETR disposed between the second light emitting layer EML2 and the second electrode CE. For example, the electron control layer ETR can be further disposed between the first light emitting layer EML1 and the charge generation layer CGL, and the hole control layer HTR can be further disposed between the charge generation layer CGL and the second light emitting layer EML2.

[0126] The charge generation layer CGL can include a plurality of layers of an n-type charge generation layer n-CGL and a p-type charge generation layer p-CGL attached to each other. The n-type charge generation layer n-CGL can be a charge generation layer that provides electrons to the first light emitting layer EML1 adjacent to the n-type charge generation layer n-CGL. The n-type charge generation layer n-CGL can be a layer formed by doping a base material with an n-dopant. The p-type charge generation layer p-CGL can be a charge generation layer that provides holes to the second light emitting layer EML2 adjacent to the p-type charge generation layer p-CGL. The p-type charge generation layer p-CGL can be a layer formed by doping a base material with a p-dopant.

[0127] Referring to Figure 5A , Figure 5B and Figure 5C A first light emitting opening OP1 corresponding to the first light emitting area PXA-G and a second light emitting opening OP2 corresponding to the second light emitting area PXA-B can be defined through the pixel definition layer PDL. For example, referring to Figure 5A A third light emitting opening OP3 corresponding to the third light emitting area PXA-R can be defined.

[0128] The light emitting element OLED can include a first light emitting element OLED1 corresponding to the first light emitting opening OP1 and a second light emitting element OLED2 corresponding to the second light emitting opening OP2. The second light emitting element OLED2 can have the same stack structure as the first light emitting element OLED1 except for the light emitting layers EML1-1 and EML2-1 of the first light emitting element OLED1.

[0129] The first light emitting element OLED1 can include a first-first electrode AE-1 partially exposed through the first light emitting opening OP1, a first light emitting stack ST1 disposed on the first-first electrode AE, a charge generation layer CGL, a second light emitting stack ST2, and a second electrode CE stacked in order on a base layer BL along a third direction DR3.

[0130] The first light emitting stack ST1 of the first light emitting element OLED1 can include a first hole control layer HTR1, a first-first light emitting layer EML1-1, and a first electron control layer ETR1. The second light emitting stack ST2 of the first light emitting element OLED1 can include a second hole control layer HTR2, a second-first light emitting layer EML2-1, and a second electron control layer ETR2.

[0131] According to an embodiment, the first-first light emitting layer EML1-1 and the second-first light emitting layer EML2-1 can emit light having the same wavelength as each other. As an example, the light emitted from each of the first-first light emitting layer EML1-1 and the second-first light emitting layer EML2-1 can be green light.

[0132] The second light emitting element OLED2 can include a first-second electrode AE-2 partially exposed through a second light emitting opening OP2, a first light emitting stack ST1 disposed on the first-second electrode AE-2, a charge generation layer CGL, a second light emitting stack ST2, and a second electrode CE, which are sequentially stacked on a base layer BL along a third direction DR3.

[0133] The first-first electrode AE-1 partially exposed through the first light emitting opening OP1 can be referred to as a first anode, and the first-second electrode AE-2 partially exposed through the second light emitting opening OP2 can be referred to as a second anode.

[0134] The first light emitting stack ST1 of the second light emitting element OLED2 can include a first hole control layer HTR1, a first-second light emitting layer EML1-2, and a first electron control layer ETR1. The second light emitting stack ST2 of the second light emitting element OLED2 can include a second hole control layer HTR2, a second-second light emitting layer EML2-2, and a second electron control layer ETR2.

[0135] According to an embodiment, the first-first light emitting layer EML1-1 and the first-second light emitting layer EML1-2 can emit light having different wavelengths. As an example, the first-first light emitting layer EML1-1 can emit green light, and the first-second light emitting layer EML1-2 can emit blue light. For example, the second-first light emitting layer EML2-1 and the second-second light emitting layer EML2-2 can also emit light having different wavelengths. As an example, the second-first light emitting layer EML2-1 can emit green light, and the second-second light emitting layer EML2-2 can emit blue light.

[0136] Reference Figure 5CThe first light emitting stack ST1 can include a first light emitting layer EML1, a first hole control layer HTR1, and a first electron control layer ETR1, and the first light emitting layer EML1 can be disposed between the first hole control layer HTR1 and the first electron control layer ETR1.

[0137] The first hole control layer HTR1 can include at least one of a first hole injection layer and a first hole transport layer. The first hole control layer HTR1 can further include at least one of a first hole buffer layer and a first electron blocking layer.

[0138] The first electron control layer ETR1 can include at least one of a first electron injection layer and a first electron transport layer. The first electron control layer ETR1 can further include a first hole blocking layer.

[0139] The second light emitting stack ST2 can include a second light emitting layer EML2, a second hole control layer HTR2, and a second electron control layer ETR2. The second light emitting layer EML2 can be disposed between the second hole control layer HTR2 and the second electron control layer ETR2.

[0140] The second hole control layer HTR2 can include at least one of a second hole injection layer and a second hole transport layer. The second electron control layer ETR2 can include at least one of a second electron injection layer and a second electron transport layer. The description of the first hole control layer HTR1 and the first electron control layer ETR1 can be equally applied to the second hole control layer HTR2 and the second electron control layer ETR2.

[0141] According to the present embodiment, each of the first electrode AE, the first light emitting layer EML1, and the second light emitting layer EML2 can be patterned using a mask and can be formed individually for each pixel. For example, the first hole control layer HTR1 and the second hole control layer HTR2, the first electron control layer ETR1 and the second electron control layer ETR2, the charge generation layer CGL, and the second electrode CE can be formed commonly throughout the pixels using an opening mask. For example, each of the first hole control layer HTR1 and the second hole control layer HTR2, the first electron control layer ETR1 and the second electron control layer ETR2, the charge generation layer CGL, and the second electrode CE can have a single unitary shape. However, the present disclosure should not be limited thereto or be construed as being limited thereto, and at least one of the first hole control layer HTR1 and the second hole control layer HTR2 and the first electron control layer ETR1 and the second electron control layer ETR2 can be formed individually for each pixel using a mask.

[0142] Figure 5CA structure in which the light emitting element OLED includes two light emitting stacks ST1 and ST2 and one charge generation layer CGL disposed between the light emitting stacks ST1 and ST2 is shown as a representative example, however, the present disclosure should not be limited thereto or be restricted thereto. According to an embodiment, the light emitting element OLED can include three, four, or more light emitting stacks.

[0143] However, the present disclosure should not be limited thereto or be restricted thereto, and the above description can be applied to the light emitting element OLED corresponding to each of the light emitting areas PXA-G, PXA-B, and PXA-R.

[0144] Referring again to Figure 5B and Figure 6 , a shape of the first valley pattern VP1 is shown when viewed in cross-section. In the following description, the first valley pattern VP1 can be referred to as a valley pattern, and an inclination angle and a depth of the first valley pattern VP1 will be described as representative examples, however, the description of the first valley pattern VP1 can also be applied to the second valley pattern VP2 and the third valley pattern VP3.

[0145] As shown in Figure 5B , the first valley pattern VP1 can include a first-first side surface SS1-1 closer to the first light emitting opening OP1 than to the second light emitting opening OP2, a first-second side surface SS1-2 adjacent to the second light emitting opening OP2 closer to the second light emitting opening OP2 than to the first-first side surface SS1-1, and a lower surface DS1 disposed between the first-first side surface SS1-1 and the first-second side surface SS1-2. For example, the first valley pattern VP1 can include a first-first side surface SS1-1 closer to the first light emitting area PXA-G than to the second light emitting area PXA-B, and a first-second side surface SS1-2 adjacent to the second light emitting area PXA-B closer to the second light emitting area PXA-B than to the first-first side surface SS1-1.

[0146] A distance d2 from a boundary between the first electrode AE and the first light emitting opening OP1 to the first-second side surface SS1-2 can be greater than a distance d1 from the boundary between the first electrode AE and the first light emitting opening OP1 to the first-first side surface SS1-1. For example, the first-second side surface SS1-2 having a relatively large inclination angle can be positioned a distance away from the first light emitting area PXA-G.

[0147] According to an embodiment, the distance d2 from the boundary between the first electrode AE and the first light emitting opening OP1 to the first-second side surface SS1-2 can be substantially equal to or greater than about 8 µm. As Figure 5BAs shown in FIG. 1, the thickness of the light emitting stack ST1 and ST2 and the charge generation layer CGL disposed on the first-second side surfaces SS1-2 can be thinned, and thus, the resistance of the light emitting stack ST1 and ST2 and the charge generation layer CGL can be increased. For example, the portion having a higher resistance can be positioned at a distance away from the first light emitting opening OP1 to reduce electrical noise and improve power efficiency.

[0148] As Figure 6 As shown in FIG. 1, the side surfaces SS1-1 and SS1-2 of the first valley pattern VP1 having a concave shape can be inclined at a selected angle with respect to the lower surface DS1. The inclination angle θ1 of the first-first side surface SS1-1 with respect to a virtual extension line of the lower surface can be less than the inclination angle θ2 of the first-second side surface SS1-2. As an example, the inclination angle θ1 of the first-first side surface SS1-1 can be greater than or equal to about zero (0) degrees and less than about 74 degrees, and the inclination angle θ2 of the first-second side surface SS1-2 can be greater than or equal to about 74 degrees and less than or equal to about 90 degrees.

[0149] In the case where the inclination angle θ1 of the first-first side surface SS1-1 is less than about 74 degrees, the thickness of the charge generation layer CGL disposed on the first-first side surface SS1-1 can be more uniform, and thus, accumulation of excess charges can be eliminated. For example, the charge distribution in the region adjacent to the first light emitting region PXA-G can be kept constant, and the path through which the charges move can be stably ensured, thereby preventing excess charge accumulation on the inclined surface. Accordingly, an overshoot phenomenon caused by excess charges can be suppressed, and a luminance corresponding to a gray value can be provided, thereby improving image quality characteristics.

[0150] In the case where the inclination angle θ2 of the first-second side surface SS1-2 is greater than or equal to about 74 degrees, the thickness of the charge generation layer CGL disposed on the first-second side surface SS1-2 can be thinned, and thus, the lateral leakage current between the first light emitting region PXA-G and the second light emitting region PXA-B can be reduced. For example, as the lateral leakage current is reduced, the luminance control accuracy for each pixel can be improved, and thus, the occurrence of a gray scale compression defect in which the luminance is reduced compared to white light in the case where only one pixel emits light can be reduced.

[0151] According to an embodiment, the first valley pattern VP1 can have a depth h that is greater than or equal to about 100 nm and less than or equal to about 650 nm. The depth h of the first valley pattern VP1 can refer to a depth of recess from an upper surface of the pixel-defining layer PDL. In a case where the depth h of the first valley pattern VP1 is less than about 100 nm, a reduction in thickness of the charge generation layer CGL disposed on the pixel-defining layer PDL can be reduced, thereby reducing an effect of preventing a lateral leakage current. Conversely, in a case where the depth h of the first valley pattern VP1 is greater than about 650 nm, the charge generation layer CGL disposed on the pixel-defining layer PDL can be physically damaged, and electrical reliability can be reduced.

[0152] As Figure 6 As shown in FIG. 1B, the organic layer OL can refer to a common layer including the first and second hole control layers HTR1 and HTR2, the first and second electron control layers ETR1 and ETR2, and the charge generation layer CGL, which are commonly disposed on the first electrode AE. The organic layer OL and the second electrode CE according to the present disclosure can be disposed on an upper surface of the pixel-defining layer PDL and inside the first valley pattern VP1. As described above, the organic layer OL and the second electrode CE can each be formed as a common layer having an integrated shape on the first electrode AE.

[0153] A thickness TH1 of the organic layer OL on the first-first side surface SS1-1 of the first valley pattern VP1 can be different from a thickness TH2 of the organic layer OL on the first-second side surface SS1-2 of the first valley pattern VP1. As described above, the inclination angle θ1 of the first-first side surface SS1-1 can be less than the inclination angle θ2 of the first-second side surface SS1-2. Accordingly, the thickness TH1 of the organic layer OL on the first-first side surface SS1-1 can be greater than the thickness TH2 of the organic layer OL on the first-second side surface SS1-2. For example, a thickness of the charge generation layer CGL overlapping the first-first side surface SS1-1 of the first valley pattern VP1 can be greater than a thickness of the charge generation layer CGL overlapping the first-second side surface SS1-2 of the first valley pattern VP1.

[0154] According to an embodiment, the thickness TH2 of the organic layer OL on the first-second side surface SS1-2 of the first valley pattern VP1 can be less than or equal to about 80 nm. The thickness TH2 of the organic layer OL on the first-second side surface SS1-2 of the first valley pattern VP1 can be thinner than the thickness TH1 of the organic layer OL on the first-first side surface SS1-1, and thus, the resistance of the organic layer OL can increase. For example, a lateral leakage current can flow through the first hole control layer HTR1 and the second hole control layer HTR2 and / or the charge generation layer CGL. However, since the resistance of the first hole control layer HTR1 and the second hole control layer HTR2 and / or the charge generation layer CGL increases, leakage of the current can be prevented. For example, the n-type charge generation layer n-CGL of the charge generation layer CGL can be broken on the first-second side surface SS1-2, and thus, the lateral leakage current between adjacent pixels can be further suppressed.

[0155] Referring again to Figure 5B , the second valley pattern VP2 can include a second-first side surface SS2-1 closer to the second light emission opening OP2 than to the first light emission opening OP1, a second-second side surface SS2-2 adjacent to the first light emission opening OP1 closer to the first light emission opening OP1 than to the second-first side surface SS2-1, and a lower surface DS2 disposed between the second-first side surface SS2-1 and the second-second side surface SS2-2. Similar to the first valley pattern VP1, the inclination angle of the second-first side surface SS2-1 can be less than the inclination angle of the second-second side surface SS2-2, and the descriptions of the inclination angle and the depth of the first valley pattern VP1 and the common layer thickness can be equally applied to the second valley pattern VP2.

[0156] Figure 7 , Figure 8 , Figure 9A and Figure 9B are enlarged schematic cross-sectional views of a portion of a display panel DP according to an embodiment. In Figure 7 , Figure 8 , Figure 9A and Figure 9B , the same / similar reference numerals refer to the same / similar elements as those in Figures 1 to 6 , and thus, detailed descriptions of the same / similar elements will be omitted.

[0157] Referring to Figure 7 , the organic layer OL can include a first electron control layer ETR1 (refer to Figure 6 ), a charge generation layer CGL (refer to Figure 6 ), and a second hole control layer HTR2 (refer to Figure 6 ). For example, the organic layer OL can include a first hole control layer HTR1 (refer toFigure 6 ) and a second electron control layer ETR2 (refer to Figure 6 ). For example, the organic layer OL can refer to a common layer having a single unit shape.

[0158] As shown in FIG. 1A, a lower surface DS1 of the first valley pattern VP1 can include a first region DS-1 and a second region DS-2. The second region DS-2 can be disposed between the first region DS-1 and the first-second side surface SS1-2, and can be recessed deeper than the first region DS-1. A portion deeply recessed between the second region DS-2 and the first-second side surface SS1-2 can be defined as a notch NTC. With the formation of the notch NTC, a thickness of the organic layer OL disposed on the second region DS-2 and the first-second side surface SS1-2 can be thinned, or the organic layer OL can be partially disconnected according to an inclination angle. Accordingly, the resistance of the organic layer OL on the first-second side surface SS1-2 can increase, and the lateral leakage current can decrease. Figure 7 Referring to FIG. 1A, the first valley pattern VP1 can include a first-first valley pattern VP1-1, a first-second valley pattern VP1-2, and a first-third valley pattern VP1-3. For example, the first valley pattern VP1 can not only be composed of a single valley pattern, but also can include a plurality of valley patterns sequentially disposed from the first light emitting opening OP1 toward the first direction DR1. According to an embodiment, a distance d2 from a boundary between the first electrode AE and the first light emitting opening OP1 to the first-first valley pattern VP1-1 can be greater than or equal to about 8 µm.

[0159] Figure 8 Three valley patterns are shown, however, the number of valley patterns should not be limited to three as shown in FIG. 1A. As an example, n valley patterns including a first valley pattern closest to the first light emitting opening OP1 to an n-th valley pattern and sequentially disposed toward the second light emitting opening OP2 (refer to FIG. 1B) can be disposed. Here, n can be an integer greater than 1.

[0160] Figure 8 Referring to FIG. 1B, the valley pattern can include the first valley pattern VP1, and can further include an additional valley pattern VP1' sequentially disposed along the first direction DR1. The additional valley pattern VP1' can include a first additional valley pattern VP1'-1 and a second additional valley pattern VP1'-2. Figure 8 Two valley patterns are shown as the additional valley pattern VP1', however, the number of additional valley patterns should not be limited to that shown in FIG. 1B. Figure 5B

[0161] Referring to FIG. 1B, the valley pattern can include the first valley pattern VP1, and can further include an additional valley pattern VP1' sequentially disposed along the first direction DR1. The additional valley pattern VP1' can include a first additional valley pattern VP1'-1 and a second additional valley pattern VP1'-2. Figure 9A Two valley patterns are shown as the additional valley pattern VP1', however, the number of additional valley patterns should not be limited to that shown in FIG. 1B. Figure 9A Figure 9A

[0162] ​​​​The inner surface of the additional valley pattern VP1' may have the same first and second side surfaces as the first valley pattern VP1 (see reference). Figure 6 The tilt angle θ2 of SS1-2 is the same as that of the other two valley patterns. Accordingly, the thickness of the organic layer OL disposed on the inner surface of the additional valley pattern VP1' can be greater than that disposed on the first-first side surface SS1-1 of the first valley pattern VP1 (refer to the first valley pattern VP1). Figure 6 The organic layer OL on the surface is thin.

[0163] According to an embodiment, the distance d2 from the boundary between the first electrode AE ​​and the first light-emitting opening OP1 to the additional valley pattern VP1' can be greater than or equal to about 8 μm. For example, the additional valley pattern VP1', including an inner surface with a large tilt angle θ2, can be positioned to ensure a sufficiently effective distance from the first light-emitting opening OP1. Accordingly, although the thickness of the organic layer OL disposed on the inner surface of the additional valley pattern VP1' is reduced, the path through which charge movement occurs can be sufficiently ensured, and thus, the accumulation of excessive charge on the tilted surface can be prevented. For example, due to the tilt of the additional valley pattern VP1', lateral leakage current phenomena between adjacent light-emitting regions can be prevented.

[0164] refer to Figure 9B The valley pattern may include a first valley pattern VP1, and may further include additional valley patterns VP1'' continuously arranged along the first direction DR1. The additional valley patterns VP1'' may include a first additional valley pattern VP1''-1 and a second additional valley pattern VP1''-2. Figure 9B Two valley patterns are shown as additional valley patterns VP1''; however, the number of additional valley patterns should not be limited to [specific number]. Figure 9B As shown in the image.

[0165] Except for the additional valley pattern VP1'', the lower surface is not included (see reference). Figure 6 Apart from DS1, the additional valley pattern VP1'' can have substantially the same structure as the first valley pattern VP1. For example, the additional valley pattern VP1'' can have a first-first side surface of the first valley pattern VP1 (refer to...). Figure 6 SS1-1) is directly connected to the first and second side surfaces (refer to Figure 6 The shape of SS1-2). One side surface of the additional valley pattern VP1'' can have the same shape as the first side surface (refer to the first side surface). Figure 6 The tilt angle θ1 of SS1-1 is the same as that of the first-second side surface (refer to the second-second side surface). Figure 6The inclination angle θ2 of the additional valley pattern VP1'' can be the same as the inclination angle θ2 of the SS1-2 of the first light emitting region PXA-G. Accordingly, the thickness of the organic layer OL disposed on the other side surface of the additional valley pattern VP1'' can be less than the thickness of the organic layer OL disposed in the first light emitting opening OP1.

[0166] With Figure 9A Similarly, the distance d2 from the boundary between the first electrode AE and the first light emitting opening OP1 to the additional valley pattern VP1'' can be greater than or equal to about 8 μm. Accordingly, the additional valley pattern VP1'' including the other side surface having a large inclination angle θ2 can be positioned to secure a sufficiently effective distance from the first light emitting opening OP1. Accordingly, it can be possible to prevent a lateral leakage current phenomenon from occurring between adjacent light emitting regions. As a result, charge imbalance in the region adjacent to the first light emitting region PXA-G can be addressed, and it can be possible to prevent a lateral leakage current phenomenon from occurring between adjacent light emitting regions.

[0167] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without substantially departing from the principles and spirit of the present disclosure and the scope. Therefore, the disclosed embodiments are used only in a general and descriptive sense and are not for the purpose of limitation.

Claims

1. A display panel, comprising: basal layer; A pixel defining layer is disposed on the substrate layer and includes a first light-emitting opening and a second light-emitting opening; as well as The light-emitting element layer includes a first light-emitting element overlapping the first light-emitting opening and a second light-emitting element overlapping the second light-emitting opening. in: The pixel defining layer includes a valley pattern disposed between the first light-emitting opening and the second light-emitting opening, and is recessed from the upper surface of the pixel defining layer in the thickness direction. The valley pattern includes a first valley pattern, which is disposed between the first light-emitting opening and the second light-emitting opening, and is configured to be closer to the first light-emitting opening than to the second light-emitting opening. The first valley pattern includes: First-first side surface; The first and second side surfaces are configured to be closer to the second light-emitting opening than the first and second side surfaces; and The lower surface is disposed between the first-first side surface and the first-second side surface, and The first-first side surface has a smaller tilt angle than the tilt angle of the first-second side surface.

2. The display panel according to claim 1, wherein, The tilt angle of the first-first side surface is less than 74 degrees, and The tilt angle of the first and second side surfaces is greater than or equal to 74 degrees and less than or equal to 90 degrees.

3. The display panel according to claim 1, wherein, The first light-emitting element includes a first electrode that is partially exposed through the first light-emitting opening, and The distance from the boundary between the first electrode and the first light-emitting opening to the first and second side surfaces is greater than or equal to 8 micrometers.

4. The display panel according to claim 1, wherein, The first valley pattern has a depth of less than or equal to 650 nm.

5. The display panel according to claim 1, wherein, The valley pattern further includes a second valley pattern, which is disposed between the first light-emitting opening and the second light-emitting opening, and is configured to be closer to the second light-emitting opening than to the first light-emitting opening. The second valley pattern includes: Second-first side surface; The second-second side surface is configured to be closer to the first light-emitting opening than the second-first side surface; and The lower surface is disposed between the second-first side surface and the second-second side surface, and The second-first side surface has a smaller tilt angle than the tilt angle of the second-second side surface.

6. The display panel according to claim 5, wherein, The first valley pattern includes: The first-first valley pattern and the first-second valley pattern are arranged to surround a portion of the first light-emitting opening, and The first valley pattern faces the second valley pattern in the area where it is spaced apart from the first valley pattern.

7. The display panel according to claim 1, wherein, The first light-emitting element includes: The first electrode is partially exposed through the first light-emitting opening; A first light-emitting layer is disposed on the first electrode; A charge generation layer is disposed on the first light-emitting layer; A second-first light-emitting layer overlaps with the first-first light-emitting layer and is disposed on the charge-generating layer; and The second electrode is disposed on the second-first light-emitting layer and the charge-generating layer.

8. The display panel according to claim 7, wherein, The first-first light-emitting layer and the second-first light-emitting layer emit light with the same wavelength.

9. The display panel according to claim 7, wherein, The second light-emitting element includes: The first electrode is partially exposed through the second light-emitting opening; The first and second light-emitting layers are disposed on the first electrode of the second light-emitting element; The charge generation layer is disposed on the first and second light-emitting layers; A second-second light-emitting layer overlaps with the first-second light-emitting layer and is disposed on the charge-generating layer; and The second electrode is disposed on the second-second light-emitting layer and the charge-generating layer. The charge-generating layer of the first light-emitting element and the charge-generating layer of the second light-emitting element have a single integral shape, and The second electrode of the first light-emitting element and the second electrode of the second light-emitting element have a single integral shape.

10. The display panel according to claim 9, wherein, The first-first light-emitting layer and the second-first light-emitting layer emit light with the same wavelength, and The first-first emitting layer and the first-second emitting layer emit light with different wavelengths from each other.

11. The display panel according to claim 9, wherein, The charge generation layer overlaps with the valley pattern. The charge generation layer includes an n-type charge generation layer and a p-type charge generation layer disposed on the n-type charge generation layer, and The n-type charge generation layer is broken on the first and second side surfaces of the first valley pattern.

12. The display panel according to claim 9, wherein, The thickness of the portion of the charge generation layer that overlaps with the first-first side surface of the first valley pattern is greater than the thickness of the portion of the charge generation layer that overlaps with the first-second side surface of the first valley pattern.

13. The display panel according to claim 1, wherein, The lower surface of the first valley pattern includes: First region; and The second region is disposed between the first region and the first-second side surface, and is recessed deeper than the first region.

14. The display panel according to claim 1, wherein, The first valley pattern includes the first to the nth valley patterns, where n is an integer greater than 1, and The first to the nth valley patterns are arranged continuously from the first light-emitting opening toward the second light-emitting opening.

15. The display panel according to claim 14, wherein, The first light-emitting element includes a first electrode that is partially exposed through the first light-emitting opening, and The distance from the boundary between the first electrode and the first light-emitting opening to the first valley pattern is greater than or equal to 8 micrometers.

16. A display panel, comprising: The substrate layer includes a first light-emitting region, a second light-emitting region adjacent to the first light-emitting region, and a non-light-emitting region adjacent to the first light-emitting region and the second light-emitting region; A pixel defining layer is disposed on the substrate layer and includes a first light-emitting opening and a second light-emitting opening that overlap with the first light-emitting region and the second light-emitting region, respectively. as well as A light-emitting element layer, at least a portion of which is disposed in the first light-emitting opening and the second light-emitting opening, wherein The pixel defining layer includes a valley pattern that overlaps with the non-light-emitting area and is recessed from the upper surface of the pixel defining layer in the thickness direction. The valley pattern includes: The first valley pattern is set to be closer to the first light-emitting opening than to the second light-emitting opening; and The second valley pattern is positioned closer to the second light-emitting opening than to the first light-emitting opening, and The first valley pattern includes: First-first side surface, surrounding a portion of the first light-emitting region; The first and second side surfaces are configured to be closer to the second light-emitting opening than the first and second side surfaces; and The lower surface is disposed between the first-first side surface and the first-second side surface, and The first-first side surface has a smaller tilt angle than the tilt angle of the first-second side surface.

17. The display panel according to claim 16, wherein, The light-emitting element layer includes: The first anode is partially exposed through the first light-emitting opening; The second anode is partially exposed through the second light-emitting opening; A first light-emitting layer is disposed on the first anode; The first and second light-emitting layers are disposed on the second anode; An organic layer is disposed on both the first anode and the second anode; The second-first light-emitting layer is disposed on the first-first light-emitting layer; A second light-emitting layer is disposed on the first second light-emitting layer; and The cathode is commonly disposed on the second-first light-emitting layer and the second-second light-emitting layer.

18. The display panel according to claim 17, wherein, Each of the first-first light-emitting layer and the second-first light-emitting layer emits first light, and Each of the first-second emitting layer and the second-second emitting layer emits a second light having a wavelength different from that of the first light.

19. The display panel according to claim 17, wherein, The thickness of the organic layer on the first-first side surface is greater than the thickness of the organic layer on the first-second side surface.

20. An electronic device, comprising: Display module; The window is set on the display module; as well as A housing is disposed below the display module, the display module comprising: basal layer; A pixel defining layer is disposed on the substrate layer and includes a first light-emitting opening and a second light-emitting opening; and The light-emitting element layer includes a first light-emitting element overlapping the first light-emitting opening and a second light-emitting element overlapping the second light-emitting opening. The pixel defining layer includes a valley pattern, which is disposed between the first light-emitting opening and the second light-emitting opening, and is recessed from the upper surface of the pixel defining layer in the thickness direction. The valley pattern includes a first valley pattern, which is disposed between the first light-emitting opening and the second light-emitting opening, and is configured to be closer to the first light-emitting opening than to the second light-emitting opening. The first valley pattern includes: First-first side surface; The first and second side surfaces are configured to be closer to the second light-emitting opening than the first and second side surfaces; and The lower surface is disposed between the first-first side surface and the first-second side surface. Wherein, the first-first side surface has a tilt angle smaller than the tilt angle of the first-second side surface.

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