High-yield low-capacitance TVS diode packaging process

Abstract

The invention provides a high-yield low-capacitance TVS (Transient Voltage Suppressor) diode packaging process, which comprises the following steps: S1, back metallization: a sputtering table is adopted, the thickness of Ti / Ni / Ag is 50 / 200 / 800nm, and the back temperature is lt; the contact resistance is less than or equal to 0.05 m omega.mm < 2 > and the resistance is gt; 0.08, sputtering again; s2, wafer thinning and stress release are carried out; s3, front passivation / low-k dielectric layer preparation; s4, preparing an aluminum-copper bump; s5, performing laser scribing; s6, inversely mounting a patch; s7, performing vacuum reflow soldering; s8, plasma cleaning and plasma underfilling are carried out; and S9, laser marking is carried out. According to the process, five contradictions of'extreme low capacitance, extreme yield, low temperature drift, zero cavity and green manufacturing 'are simultaneously grounded in the same package, so that the TVS device really meets the dual requirements of a 40Gbps high-speed interface and a vehicle gauge for the first time.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of semiconductor chip plastic packaging, and particularly relates to a high-yield low-capacitance TVS diode packaging process. BACKGROUND

[0002] The current low-capacitance TVS process has structural contradictions in the four axes of miniaturization, low capacitance, high current flow and high reliability, leading to area waste, parameter drift, thermal failure and low packaging yield, and has become a bottleneck for the large-scale landing of USB4 / Thunderbolt4 and other 40Gbps interfaces.

[0003] In view of the above prior art, it is expected to provide a high-yield low-capacitance TVS diode packaging process. SUMMARY

[0004] The application aims to provide a high-yield low-capacitance TVS diode packaging process, so as to solve the above technical problems.

[0005] A high-yield low-capacitance TVS diode packaging process comprises the following steps,

[0006] S1, back metallization: sputter, Ti / Ni / Ag thickness 50 / 200 / 800 nm, back temperature < 150 DEG C, contact resistance <= 0.05 m omega * mm 2 , and the resistance is > 0.08 to be resputtered;

[0007] S2, wafer thinning + stress release;

[0008] S3, front passivation / low-k interlayer;

[0009] S4, aluminum-copper bump;

[0010] S5, laser scribing;

[0011] S6, flip chip;

[0012] S7, vacuum reflow soldering;

[0013] S8, plasma cleaning + plasma underfilling;

[0014] S9, laser marking.

[0015] Specifically, in step S2, a grinder + clamp, total thickness 120 mu m, grinding wheel rotating speed 3000 rpm, breakage rate < 0.15%, breakage > 0.3%, and speed reduction 500 rpm.

[0016] Specifically, in step S2, wet Si etching + polishing, remove 5 mu m damage layer, surface roughness Ra <= 5 nm, warpage < 40 mu m, and 60 mu m re-polishing.

[0017] Specifically, in step S3, the front side is passivated, PECVD low kSiOF is performed with a thickness of 800 nm, k = 3.2, deposition temperature is 200 °C, and replating is performed when the breakdown voltage is >100V and <90V.

[0018] Specifically, in step S4, the sputtered AlCu (2%) + electroplated Cu bumps have a height of 25±2μm, a hardness of 0.9GPa, and a shear force ≥6g / mil. 2 <5g / mil 2 Replating.

[0019] Specifically, in step S5, the 355nm UV laser scribing speed is 200mm / s, the groove width is 30μm, the heat-affected zone is <5μm, the edge chipping is ≤8μm, and the power is reduced by 10% at 10μm.

[0020] Specifically, in step S6, the flip chip mounter (FC) has a mounting accuracy of ±5μm, a pressure of 0.15N / piece, a flux thickness of 10μm, an offset of ≤10μm, and a 15μm re-alignment.

[0021] Specifically, in step S7, a vacuum reflux furnace is used with a peak temperature of 260°C, a vacuum degree of <5 mbar, a time of 60 s, a void ratio of ≤3%, and a reflow rate of 5%.

[0022] Specifically, in step S8, plasma cleaning is performed using ICP oxygen plasma at a power of 300W for 60 seconds with an oxygen flow rate of 300 sccm and a contact angle of ≤10°. The plasma is then rewashed at 15°. PIF is applied to the plasma substrate, followed by low-stress epoxy. The substrate is preheated to 80°C, filled for 15 seconds, and cured at 125°C for 20 minutes. If any voids are found (X-ray), the entire substrate is scrapped.

[0023] Specifically, in step S9, the fiber laser is 1064nm, the character height is 0.3mm, the depth is ≤5μm, the position accuracy is ±0.1mm, the character recognition rate is 100%, and blurry characters are reprinted.

[0024] The high-yield, low-capacitance TVS diode packaging process of the present invention has the following advantages compared with the prior art:

[0025] This process combines five seemingly contradictory aspects—extremely low capacitance, extremely high yield, low temperature drift, zero voids, and green manufacturing—within a single package, enabling TVS devices to truly meet both 40Gbps high-speed interface and automotive-grade requirements for the first time. Detailed Implementation

[0026] The present invention will be further described below with reference to specific embodiments.

[0027] A high-yield, low-capacitance TVS diode packaging process includes the following steps.

[0028] S1, Backside metallization: Sputtering stage, Ti / Ni / Ag thickness 50 / 200 / 800nm, backside temperature <150℃, contact resistance ≤0.05mΩ·mm 2 Resputtering if resistance > 0.08;

[0029] S2, wafer thinning + stress relief;

[0030] S3, front passivation / low-k interlayer;

[0031] S4, Aluminum-copper bump;

[0032] S5, laser scribing;

[0033] S6, Flip Chip;

[0034] S7, Vacuum reflow soldering;

[0035] S8, Plasma cleaning + plasma underfill;

[0036] S9, laser marking.

[0037] Specifically, in step S2, the grinding machine and fixture have a total thickness of 120 μm, a grinding wheel speed of 3000 rpm, a fragmentation rate of <0.15%, fragmentation rate of >0.3%, and a speed reduction of 500 rpm.

[0038] Specifically, in step S2, wet Si etching and polishing are performed to remove the 5μm damaged layer, resulting in a surface roughness Ra≤5nm, warpage<40μm, and a 60μm repolishing.

[0039] Specifically, in step S3, the front side is passivated, PECVD low kSiOF is performed with a thickness of 800 nm, k = 3.2, deposition temperature is 200 °C, and replating is performed when the breakdown voltage is >100V and <90V.

[0040] Specifically, in step S4, the sputtered AlCu (2%) + electroplated Cu bumps have a height of 25±2μm, a hardness of 0.9GPa, and a shear force ≥6g / mil. 2 <5g / mil 2 Replating.

[0041] Specifically, in step S5, the 355nm UV laser scribing speed is 200mm / s, the groove width is 30μm, the heat-affected zone is <5μm, the edge chipping is ≤8μm, and the power is reduced by 10% at 10μm.

[0042] Specifically, in step S6, the flip chip mounter (FC) has a mounting accuracy of ±5μm, a pressure of 0.15N / piece, a flux thickness of 10μm, an offset of ≤10μm, and a 15μm re-alignment.

[0043] Specifically, in step S7, a vacuum reflux furnace is used with a peak temperature of 260°C, a vacuum degree of <5 mbar, a time of 60 s, a void ratio of ≤3%, and a reflow rate of 5%.

[0044] Specifically, in step S8, plasma cleaning is performed using ICP oxygen plasma at a power of 300W for 60 seconds with an oxygen flow rate of 300 sccm and a contact angle of ≤10°. The plasma is then rewashed at 15°. PIF is applied to the plasma substrate, followed by low-stress epoxy. The substrate is preheated to 80°C, filled for 15 seconds, and cured at 125°C for 20 minutes. If any voids are found (X-ray), the entire substrate is scrapped.

[0045] Specifically, in step S9, the fiber laser is 1064nm, the character height is 0.3mm, the depth is ≤5μm, the position accuracy is ±0.1mm, the character recognition rate is 100%, and blurry characters are reprinted.

[0046] Testing revealed capacitance as low as 0.25pF (@1MHz), USB4 / Thunderbolt 440Gbps, and a 12% improvement in eye diagram margin, achieving 30GHz S21 insertion loss compliance without sacrificing ESD protection. Packaging yield reached 98.7%, with an additional 1.1kk genuine products produced per month for every 30kk units produced, resulting in a direct gross profit increase of approximately $550,000 per month; simultaneously reducing overstock inventory and inspection labor. Breakage rate was <0.15%, saving approximately $72,000 per month (120 wafers x $600 per wafer) at $600 per 12-inch wafer; and reducing machine cleaning downtime by 8 hours per month. Solder ball void rate was ≤3%, thermal resistance RθJA decreased by 30% (180→120℃ / W), failure rate after 10 cycles of 30A surge was <10ppm, and customer return rate decreased by 85%. Temperature-capacitance drift was ≤±3%. The automotive USB-C interface (100 times) still meets the ±5% specification when operating at 125℃, the system bit error rate is reduced by one order of magnitude, and it supports automotive-grade AEC-Q101 certification. The back is metallized without diffusion, the capacitance is increased to 0pF, eliminating the hidden risk of a 50mV drop at eye height for high-speed HDMI 2.1, and reducing the bulk return rate from 8% to 0.1%.

[0047] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A high-yield, low-capacitance TVS diode packaging process, characterized in that, Includes the following steps, S1, Backside metallization: Sputtering stage, Ti / Ni / Ag thickness 50 / 200 / 800nm, backside temperature <150℃, contact resistance ≤0.05mΩ·mm 2 Resputtering if resistance > 0.08; S2, wafer thinning + stress relief; S3, front passivation / low-k interlayer; S4, Aluminum-copper bump; S5, laser scribing; S6, Flip Chip; S7, Vacuum reflow soldering; S8, Plasma cleaning + plasma underfill; S9, laser marking.

2. The high-yield, low-capacitance TVS diode packaging process as described in claim 1, characterized in that, In step S2, the grinding machine and fixture have a total thickness of 120 μm, a grinding wheel speed of 3000 rpm, a fragmentation rate of <0.15%, a fragmentation rate of >0.3%, and a speed reduction of 500 rpm.

3. The high-yield, low-capacitance TVS diode packaging process as described in claim 1, characterized in that, In step S2, wet Si etching and polishing are performed to remove the 5μm damaged layer, resulting in a surface roughness Ra≤5nm, warpage<40μm, and a 60μm repolishing.

4. The high-yield, low-capacitance TVS diode packaging process as described in claim 1, characterized in that, In step S3, the front side is passivated, PECVD low kSiOF is performed with a thickness of 800 nm, k = 3.2, deposition temperature is 200 °C, and replating is performed if the breakdown voltage is >100V and <90V.

5. The high-yield, low-capacitance TVS diode packaging process as described in claim 1, characterized in that, In step S4, the sputtered AlCu (2%) + electroplated Cu bumps have a height of 25±2μm, a hardness of 0.9GPa, and a shear force ≥6g / mil. 2 <5g / mil 2 Replating.

6. The high-yield, low-capacitance TVS diode packaging process as described in claim 1, characterized in that, In step S5, the 355nm UV laser scribing speed is 200mm / s, the groove width is 30μm, the heat-affected zone is <5μm, the edge chipping is ≤8μm, and the power is reduced by 10% at 10μm.

7. The high-yield, low-capacitance TVS diode packaging process as described in claim 1, characterized in that, In step S6, the flip chip mounter (FC) is used with a mounting accuracy of ±5μm, a pressure of 0.15N / piece, a flux thickness of 10μm, an offset of ≤10μm, and a 15μm re-alignment.

8. The high-yield, low-capacitance TVS diode packaging process as described in claim 1, characterized in that, In step S7, a vacuum reflux furnace is used with a peak temperature of 260°C, a vacuum degree of <5 mbar, a time of 60 s, a void ratio of ≤3%, and a reflow rate of 5%.

9. The high-yield, low-capacitance TVS diode packaging process as described in claim 1, characterized in that, In step S8, plasma cleaning is performed using ICP oxygen plasma at a power of 300W for 60 seconds with an oxygen flow rate of 300 sccm and a contact angle of ≤10°. The plasma is then rewashed at 15°. PIF is applied to the plasma substrate, followed by low-stress epoxy. The substrate is preheated to 80°C, with a filling time of 15 seconds. It is then cured at 125°C for 20 minutes. The substrate is filled with zero voids (X-ray). If voids are found, the entire substrate is scrapped.

10. The high-yield, low-capacitance TVS diode packaging process as described in claim 1, characterized in that, In step S9, the fiber laser is 1064nm, the character height is 0.3mm, the depth is ≤5μm, the position accuracy is ±0.1mm, the character recognition rate is 100%, and blurry characters are reprinted.