Chip and 3D stacked chip structure

Abstract

The embodiment of the invention discloses a chip and a 3D stacked chip structure, and relates to the technical field of semiconductor integrated circuits. The voltage drop problem can be effectively suppressed, so that the chip power supply integrity is improved. Comprising a semiconductor substrate; the functional circuit and the deep groove capacitor structure are formed on the semiconductor substrate, and the deep groove capacitor structure is formed in the semiconductor substrate and electrically connected with the functional circuit; wherein the deep groove capacitor structures are symmetrically distributed in an adjacent area of the functional circuit on the semiconductor substrate in an array mode and connected with a power supply network of a chip through a metal wiring layer, and the deep groove capacitor structures are used for restraining voltage drop of the functional circuit. The method and the device are suitable for a 3D stacked chip voltage drop optimization scene.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular to a chip and a 3D stacked chip structure. BACKGROUND

[0002] With the semiconductor process entering the nanometer scale, the transistor density and working frequency of integrated circuits continue to rise, while the power supply voltage continues to decrease, resulting in a sharp increase in the dynamic current and current change rate of the chip. This trend makes the power integrity problem, especially the voltage drop (IR-Drop, Internal Resistance Drop), a bottleneck restricting the performance, stability and even yield of the chip. To cope with this challenge, decoupling capacitors are generally used to provide local charge compensation for transient current and suppress power voltage fluctuations.

[0003] In recent years, deep trench capacitors have attracted widespread attention as an innovative on-chip silicon-based decoupling solution.

[0004] In the prior art, deep trench capacitors (DTC, Deep Trench Capacitor) are generally integrated in an interposer, but as the number of stacked layers and the size of the chip continue to increase, the suppression effect of the voltage drop (IR-Drop) continues to decrease. SUMMARY

[0005] Therefore, the embodiments of the present application provide a chip and a 3D stacked chip structure, which can effectively suppress the voltage drop problem and thus improve the power integrity of the chip.

[0006] In a first aspect, the present application provides a chip, comprising: a semiconductor substrate; a functional circuit and a deep trench capacitor structure formed on the semiconductor substrate, the deep trench capacitor structure being formed in the semiconductor substrate and electrically connected with the functional circuit; wherein the deep trench capacitor structure is array-symmetrically distributed in the adjacent region of the functional circuit on the semiconductor substrate, and is connected with the power supply network of the chip through a metal wiring layer, and the deep trench capacitor structure is used to suppress the voltage drop of the functional circuit.

[0007] According to one embodiment of the present application, the functional circuit comprises at least a first functional circuit and a second functional circuit, wherein the first functional circuit works on a first power supply network, the second functional circuit works on a second power supply network, and the first power supply network and the second power supply network are independently arranged; the deep trench capacitor structure comprises at least a first group of deep trench capacitor structures and a second group of deep trench capacitor structures, the first group of deep trench capacitor structures are formed in the adjacent region of the first functional circuit, connected with the first power supply network, and used for suppressing the voltage drop of the first functional circuit; the second group of deep trench capacitor structures are formed in the adjacent region of the second functional circuit, connected with the second power supply network, and used for suppressing the voltage drop of the second functional circuit.

[0008] According to one embodiment of the present application, the deep trench capacitor structure is distributed in an array of crosses on the semiconductor substrate, and a preset distance is arranged between adjacent deep trench capacitor structures.

[0009] According to one embodiment of the present application, the deep trench capacitor structure is symmetrically and centrally distributed in an array on the four corners of the semiconductor substrate, and adjacent deep trench capacitor structures are connected with each other.

[0010] According to one embodiment of the present application, the functional circuit and the deep trench capacitor structure are simultaneously prepared on the chip.

[0011] Second aspect. The present application also provides a 3D stacked chip structure, comprising: a logic chip located at the bottom layer, a buffer chip vertically stacked on the logic chip, and a plurality of memory chips vertically stacked on the buffer chip in sequence, wherein the active surface of the plurality of memory chips is arranged downward; the logic chip, the buffer chip and the plurality of memory chips are connected through a vertical interconnection structure, and the deep trench capacitor structure arranged on the buffer chip and the plurality of memory chips is used for supplying power to the upper layer chip to suppress the voltage drop caused by chip stacking; the buffer chip and the plurality of memory chips are the chip of any one of the first aspect.

[0012] According to one embodiment of the present application, the vertical interconnection structure comprises: a through silicon via and a bump array, wherein the through silicon via is arranged inside the logic chip, the buffer chip and the plurality of memory chips stacked in the middle, the bump array is arranged between two vertically stacked chips, and is arranged correspondingly with the through silicon via.

[0013] According to one embodiment of this application, the arrangement of the logic chip located at the bottom layer and the buffer chip vertically stacked on the logic chip includes at least the following: the logic chip and the buffer chip are arranged with their active surfaces facing down, the logic chip and the buffer chip are arranged with their active surfaces facing up, and any one of the logic chip and the buffer chip is arranged with its active surface facing up and the other active surface facing down.

[0014] According to one embodiment of this application, the deep trench capacitor structure is disposed on the active surface and / or back surface of the buffer chip and the memory chip. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a chip architecture provided in an embodiment of this application; Figure 2 This is a schematic diagram of the deep trench capacitor structure arrangement according to an embodiment of this application; Figure 3 This is a schematic diagram of the deep trench capacitor structure arrangement in another embodiment of this application; Figure 4 This is a schematic diagram of the deep trench capacitor structure in this application; Figure 5 This is a schematic diagram of a 3D stacked chip structure provided in one embodiment of this application; Figure 6 This is a schematic diagram of a 3D stacked chip structure provided in another embodiment of this application; Figure 7 This is a schematic diagram of a 3D stacked chip structure provided in another embodiment of this application.

[0017] Figure 8 This is a schematic diagram of a 3D stacked chip structure provided in yet another embodiment of this application. Detailed Implementation

[0018] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0019] It should be understood that the described embodiments are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments in this application without creative effort are within the scope of protection of this application. With the increasing demand for high-performance and highly integrated electronic chips from high-performance computing, artificial intelligence, and unmanned systems, 2.5D / 3D integration technology has become an important means of integrating various types, materials, and functions of chips. However, as the number of stacked layers increases, chip size expands, and the size of micro-bumps and hybrid bonding shrinks, the resistance of power / ground network metal interconnects increases significantly, leading to the Internal Resistance Drop (IR-Drop) problem. IR-Drop not only reduces transistor switching speed and causes timing violations, but may also lead to reliability problems such as power supply noise and electromigration, becoming one of the core bottlenecks limiting the performance and yield of 2.5D / 3D chips.

[0020] Existing technologies have achieved a capacitance density of 300 nF / mm² by integrating deep trench capacitors (DTCs) in the interposer, significantly reducing PDN impedance (power distribution network impedance) and voltage sag in the logic chip-HBM2E system. However, with further increases in the number of stacked layers and chip size, the existing deep trench capacitor (DTC) structure remains insufficient in terms of capacitance density, parasitic parameters, and integration flexibility.

[0021] Based on this, this embodiment provides a chip and a 3D stacked chip structure.

[0022] See Figure 1 This embodiment provides a chip 100, including: Semiconductor substrate 101; A functional circuit 102 and a deep trench capacitor structure 103 are formed on the semiconductor substrate. The deep trench capacitor structure 103 is formed in the semiconductor substrate 101 and is electrically connected to the functional circuit 102. The deep trench capacitor structure 103 is symmetrically distributed in an array in the vicinity of the functional circuit 102 on the semiconductor substrate 101, and is connected to the power supply network of the chip through a metal wiring layer. The deep trench capacitor structure 103 is used to suppress the voltage drop of the functional circuit.

[0023] The semiconductor substrate 101 provided in this embodiment is a Si substrate or other compound semiconductor substrate, such as a gallium arsenide (GaAs) substrate, a gallium nitride (GaN) substrate, or a silicon carbide (SiC) substrate.

[0024] In some embodiments, the adjacent region of the functional circuit includes: the blank region between the edge region of the semiconductor substrate and the functional circuit.

[0025] In this embodiment, see Figures 2-3 Deep trench capacitor (DTC) structures are placed in the vicinity of the functional circuits of the chip, such as the edge region of the semiconductor substrate, i.e., the chip edge region, empty region, empty region near the functional circuits adjacent to the dicing slot, or blank region between functional circuits, such as the blank region between standard functional units. By arranging the DTC structure in the predetermined blank region of the functional circuits, it does not occupy the core area of ​​the chip. Furthermore, in multi-stacked chip structures, DTCs can quickly replenish the instantaneous charge demand of the power network and effectively suppress the voltage drop of the power network.

[0026] In some embodiments, the deep trench capacitor structures 103 are distributed in a grid-like array on the semiconductor substrate, and a preset distance is provided between adjacent deep trench capacitor structures.

[0027] In this embodiment, see Figure 3 The deep trench capacitor structure 103 is symmetrically distributed along the chip in a grid-like array. The high capacitance density and low parasitic resistance of the deep trench capacitors provide a uniform and global decoupling network for the entire chip. It is equivalent to connecting countless distributed small capacitors between the chip's power supply network, which can reduce the AC impedance of the power supply network and provide a shorter charge supply path for functional circuits at any location in the chip. It can effectively suppress the voltage drop caused by excessively long power supply paths. At the same time, the uniformly distributed grid helps to quickly dissipate the heat from local hot spots to the entire chip area, avoiding heat accumulation.

[0028] In some embodiments, the deep trench capacitor structures are symmetrically distributed in an array at the four corner edges of the semiconductor substrate, and adjacent deep trench capacitor structures are interconnected.

[0029] In this embodiment, see Figure 2The deep trench capacitor structure 103 is symmetrically distributed in an array at the four corners of the chip. For functional circuits located at the corners and around the chip, this optimizes power integrity, especially for input / output interface circuits and peripheral control circuits at the chip edge. Input / output interface circuits are concentrated around the chip and require frequent current switching. The deep trench capacitor structure at the four corners can provide instantaneous current for driving, suppressing synchronous switching noise of input / output signals. At the same time, the symmetrical arrangement of the deep trench capacitor structure at the four corners ensures uniform current distribution in the power supply network, with each corner bearing a certain load current. This avoids local voltage drop peaks, reduces electromigration risks, and extends chip lifespan. Furthermore, the deep trench capacitor structure is located away from the core heat-generating area, preventing capacitor performance degradation due to excessively high local temperatures. The capacitor array is dispersed at the four corners, rather than concentrated on one side, avoiding thermal stress concentration in a single area, reducing the risk of chip warping due to uneven thermal expansion, and improving long-term operational reliability.

[0030] In some embodiments, deep trench capacitor arrays are symmetrically and centrally distributed at the four corners of the chip, each deep trench capacitor has a capacitance of 50 pF, the total area of ​​the deep trench capacitor structure occupies 3% of the chip area, and the capacitance density is 200 nF / mm². 2 Among them, the trench depth of the deep trench capacitor is greater than or equal to 10 μm.

[0031] In some embodiments, see Figure 2 and Figure 3 The deep trench capacitor array structure distributed on the chip employs an alternating arrangement of large and small capacitors. Specifically, during the etching of the deep trenches, wide and narrow trenches are etched alternately, followed by filling with a high-dielectric-constant dielectric layer and a metal filler layer, forming a cooperative array of large and small capacitors. This alternating arrangement of wide and narrow deep trenches creates stress relief channels, and the stress fields of trenches of different sizes cancel each other out, resulting in a more uniform overall stress distribution. Furthermore, it leverages the advantages of both types of capacitors at different frequencies, forming a complete filtering link.

[0032] Meanwhile, when fabricating deep trench capacitors using the deep trench process, after etching out the deep trenches, a 5 nm high-dielectric-constant HfO2 dielectric layer is deposited, followed by filling with TiN or W metal to form a MIM structure capacitor. Capacitance density is directly proportional to the dielectric constant K and inversely proportional to the dielectric thickness d. The K value of HfO2 is much higher than that of traditional SiO2, and combined with a 5 nm thickness, it can significantly improve capacitance density, enabling larger decoupling capacitors within a limited chip area. Furthermore, HfO2 exhibits good thermal and electrical stability, and TiN, as an electrode, can be well matched with HfO2 to form a stable interface, ensuring stable performance and controllable degradation of the capacitor throughout the chip's long service life, especially under high temperature and high electric field conditions, thus improving chip lifespan and reliability.

[0033] In some embodiments, the functional circuit includes at least a first functional circuit and a second functional circuit, wherein the first functional circuit operates on a first power supply network, the second functional circuit operates on a second power supply network, and the first power supply network and the second power supply network are respectively independently configured; The deep trench capacitor structure includes at least: a first group of deep trench capacitor structures and a second group of deep trench capacitor structures. The first group of deep trench capacitor structures is formed in the vicinity of the first functional circuit and connected to the first power supply network to suppress the voltage drop of the first functional circuit. The second group of deep trench capacitor structures is formed in the vicinity of the second functional circuit and connected to the second power supply network to suppress the voltage drop of the second functional circuit.

[0034] In this embodiment, the deep-slot capacitor structure supports the planning and arrangement of multiple voltage domains or power supply networks. For different power domains or power supply networks within the chip, such as the core logic voltage domain (Vcore) or the input / output interface voltage domain (Vio), independent deep-slot capacitor arrays are planned and arranged to avoid cross-domain interference. Each voltage domain has its own deep-slot capacitor structure array, effectively blocking noise propagation between different voltage domains through the power path and improving stability. Each group of deep-slot capacitors independently serves its corresponding power supply network, achieving localized power supply and enabling rapid response to instantaneous current, thereby reducing power supply voltage fluctuations. Furthermore, the independent deep-slot capacitor structure can also serve as an independent power management unit. Combined with the chip's power management unit (PMU), it can achieve on-demand start / stop: when each voltage domain enters sleep mode, its corresponding deep-slot capacitor group can be turned off to reduce static power consumption; dynamic adjustment: during dynamic voltage frequency adjustment, the connection method of the corresponding deep-slot capacitor group can be dynamically adjusted to achieve voltage switching; and independent monitoring and feedback control of the power integrity of different domains can also be achieved.

[0035] In some embodiments, the functional circuitry and the deep trench capacitor structure are fabricated simultaneously on the chip.

[0036] In this embodiment, the deep trench capacitor structure is integrated into a complete chip. During the chip design phase, the deep trench capacitor placement area and the functional circuit area are planned simultaneously. During the chip manufacturing process, the deep trench capacitor structure is manufactured together with the functional circuit in the chip. That is, the deep trench capacitor is equivalent to a part of the circuit. Compared with external capacitors, it can reduce parasitic parameters and improve instantaneous response speed. At the same time, as part of the circuit, the DTC deep trench capacitor can be optimized synchronously with the power grid and functional circuit during the layout design phase. For example, according to the current density distribution in the core area, the deep trench density and position of the deep trench capacitor can be precisely adjusted, such as the four corners, the edges, or the grid shape, so that the impedance of the power network is uniform throughout the entire domain, avoiding voltage drop caused by local current congestion.

[0037] In some embodiments, see Figure 4 The deep trench capacitor structure 103 includes: a deep trench 103A disposed on a semiconductor substrate, a multilayer high dielectric constant dielectric layer 103B, and a multilayer metal filling layer 103C, wherein the multilayer high dielectric constant dielectric layer 103B and the multilayer metal filling layer 103C are alternately filled, and the high dielectric constant dielectric layer 103B and the metal filling layer 103C extend to the substrate 101 surrounding the deep trench 103A, and the bottom region and sidewalls of the deep trench 103A are filled with high dielectric constant dielectric layers.

[0038] See Figure 5 The deep trench capacitor structure 103 used in this embodiment includes a deep trench 103A with a depth greater than or equal to 10 μm etched on a semiconductor substrate 101, a multilayer high dielectric constant dielectric layer 103B (e.g., hafnium oxide (HfO2) and aluminum oxide (Al2O3)) alternately and uniformly filled in the deep trench 103A, and a multilayer metal filling layer 103C (e.g., tungsten (W), copper (Cu), titanium (Ti), and titanium nitride (TiN)). The high dielectric constant dielectric layer 103B and the metal filling layer 103C extend to the substrate 101 surrounding the deep trench 103A. The bottom region and sidewalls of the deep trench 103A are filled with a first high dielectric constant dielectric layer 103B, and a first metal filling layer 103C is filled on the first high dielectric constant dielectric layer 103B. The metal filling layer extending to the substrate 101 surrounding the deep trench 103A serves as a lead electrode and is connected to the power / ground network of the chip.

[0039] In other embodiments, the deep trench capacitor structure has a capacitance density of 50 nF / mm². 2 -5000 nF / mm 2 Its equivalent series resistance (also known as low parasitic resistance) is less than 10 mΩ, and its resonant frequency is greater than 1 GHz. Due to its high capacitance density and low parasitic resistance, it can quickly replenish the instantaneous charge demand of the power network and effectively suppress IR-Drop. Experiments have shown that it can reduce the IR-Drop peak by 20%-40% and improve the timing convergence rate.

[0040] In this embodiment, the deep trench capacitor structure is connected in parallel with the chip's power / ground network through the top metal wiring layer of the chip, thereby achieving high-frequency decoupling and transient charge replenishment.

[0041] See Figure 5 This embodiment also provides a 3D stacked chip structure 200, including: The logic chip 201 is located at the bottom layer, the buffer chip 202 is vertically stacked on the logic chip, and a plurality of memory chips 203 to 206 are vertically stacked on the buffer chip in sequence, with the active surfaces of the plurality of memory chips facing downwards. The logic chip 201, the buffer chip 202, and the plurality of memory chips 203-206 are connected by a vertical interconnect structure 207. The deep trench capacitor structure 103 provided on the buffer chip 202 and the plurality of memory chips 203-206 is used to supply power to the upper layer chip to suppress the voltage drop caused by chip stacking. The buffer chip 202 and the plurality of memory chips 203-206 are the chips described above.

[0042] In a 3D stacked structure, the bottom layer chip is typically a logic die, also known as a logic chip or logic computing chip. Stacked on top of this bottom layer are several memory chips. Since power supply to the chips is usually from bottom to top, and there are often differences in communication protocols and electrical drives between the logic chips and memory chips, this embodiment of the application places a buffer chip between the bottom logic chip and the memory chips. This buffer chip is used to control or drive the memory chips above it to operate.

[0043] See Figure 5 The 3D stacked chip structure 200 provided in this embodiment includes a logic chip 201 at the bottom layer, a buffer chip 202 vertically stacked on top of the logic chip, and a plurality of memory chips 203-206 vertically stacked sequentially on top of the buffer chip. In this chip stacking structure, the chips are powered from bottom to top. As the number of stacking layers increases, insufficient chip power supply can easily lead to voltage drop problems. By integrating a deep trench capacitor structure 103 in the chip, the charge storage capacity of the power network can be supplemented, the power supply voltage drop (IR-Drop) caused by current fluctuations can be suppressed, and the power supply voltage of the multi-layer stacked structure can be stabilized.

[0044] In some embodiments, the vertical interconnect structure 207 includes a through-silicon via (TSV) 207A and a bump array 207B. The TSV 207A is disposed inside the logic chip 201, the buffer chip 202, and a plurality of memory chips 203-205 stacked in between. The bump array 207B is disposed between two vertically stacked chips and is disposed corresponding to the TSV 207A.

[0045] See Figure 5 The 3D stacked chip structure 200 provided in this embodiment enables power supply and signal transmission between each chip layer through through-silicon vias 207A disposed inside the chip and bump arrays 207B between the chips.

[0046] In some embodiments, the arrangement of the logic chip located at the bottom layer and the buffer chip vertically stacked on the logic chip includes at least the following: the logic chip and the buffer chip are arranged with their active surfaces facing down, the logic chip and the buffer chip are arranged with their active surfaces facing up, and one of the logic chip and the buffer chip is arranged with its active surface facing up and the other active surface facing down.

[0047] In some embodiments, the deep trench capacitor structure is disposed on the active surface and / or back surface of the buffer chip and the memory chip.

[0048] In this embodiment, the 3D stacked chip structure 200 has memory chips 203-206 arranged with their active surfaces facing down, while the arrangement of logic chips 201 and buffer chips 202 is not fixed, for example... Figure 5 The logic chip 201 and the buffer chip 202 shown are arranged with their active surfaces facing downwards, or with their active surfaces facing upwards, or... Figure 6 The logic chips shown are arranged with their active surfaces facing upwards, and the buffer chips are arranged with their active surfaces facing downwards. Figure 7 The logic chip shown is arranged with its active side facing down, and the buffer chip is arranged with its active side facing up.

[0049] In this embodiment, since power supply is typically from bottom to top in a 3D stacked chip structure, too many stacked layers can easily lead to inconsistent power supply, resulting in a voltage drop. Therefore, deep trench capacitors are integrated into the 3D stacked chip structure. These deep trench capacitors are integrated on the middle layer chip and on the back side of the chip, allowing them to be closer to the memory chip above, thus facilitating power supply to the upper chip. It should be noted that the buffer chip does not have large-area functional circuitry, so the deep trench capacitor structure can be placed on the active side or the back side of the buffer chip, or both.

[0050] In some embodiments, the logic chip is arranged with its active surface facing down, the buffer chip is arranged with its active surface facing down, the plurality of memory chips are arranged with their active surfaces facing down, and the deep trench capacitor structure is disposed on the active surface of the buffer chip.

[0051] See Figure 8In this embodiment, the bottom logic chip 201, the intermediate buffer chip 202, and the upper memory chips 203-206 are all arranged with their active surfaces facing down, which can optimize the data path and transmission bandwidth. The bottom logic chip 201, with its active surface facing down, can be directly connected to the packaging substrate or interposer through the vertical interconnect structure 207, thereby obtaining a stable power supply. The buffer chip 202, placed in the intermediate layer, has its active surface facing down, and the deep trench capacitor structure 103 is set in the empty area of ​​the active surface. It is connected to the power supply network through the vertical interconnect structure 207, providing a shorter power supply loop inductance, which can absorb the sudden current demand generated by the logic chip. At the same time, the buffer chip 202 vertically conducts signals and power to the back side through the vertical interconnect structure 207, connecting to the active surface of the upper memory chip, and providing a stable power supply voltage for the upper memory chip.

[0052] Furthermore, since deep trench capacitors are passive devices with low heat generation, placing them in the buffer chip will not increase the burden on the main heat source, such as the logic chip; at the same time, the buffer chip is located between the logic chip and the memory chip, which helps to distribute heat evenly.

[0053] In this embodiment, the deployment and connection of deep trench capacitors in the chip, as demonstrated in experiments, reduced the critical path voltage drop (IR-Drop) from 85 mV to 32 mV in a 3D stacked chip structure, improving timing margin by 18%. In a 2.5D integrated chip structure, under burst load conditions, the peak power supply voltage fluctuation decreased from 120 mV to 45 mV.

[0054] In some embodiments, the deep trench capacitor structure is laid out during the physical design phase of the chip. This can be achieved by obtaining the chip's layout design and power distribution network model; performing power network simulation on the layout design based on the power distribution network model to identify regions in the chip where the voltage drop exceeds a preset threshold; and pre-planning the layout positions of the deep trench capacitors within the semiconductor substrate of the identified regions where the voltage drop exceeds the preset threshold.

[0055] Specifically, the process involves acquiring preliminary chip physical layout data during the chip layout design phase. This data includes the placement locations of standard cells, functional circuits, macrocells, and a preliminary global power / ground distribution network. Simultaneously, it involves acquiring process information, such as process files for sheet resistance, via resistance, or capacitance per unit area of ​​each metal layer, as well as power model files containing the operating modes and current consumption characteristics of each chip module.

[0056] The simulation identifies areas in the chip that require enhanced decoupling capacitors. First, a static IR-Drop analysis is performed to assess the DC voltage drop across the power distribution network based on average current consumption, initially identifying high-impedance areas caused by excessively long power distribution network paths. Second, a transient IR-Drop analysis is performed to simulate the impact of instantaneous large currents on the power network during actual operation, particularly when switching between high-dynamic-current load modules such as processor cores, clock drivers, or high-speed interfaces. This generates an IR-Drop distribution map on the chip surface, typically presented as voltage contour lines or a heatmap. Finally, based on a preset IR-Drop threshold (e.g., requiring the power supply voltage drop to not exceed 5% of the standard value), the simulation results are automatically analyzed to identify all continuous areas where the voltage drop exceeds the threshold, marking these areas as potential IR-Drop exceedance areas or weak power supply areas.

[0057] After identifying regions where the voltage drop exceeds a preset threshold, deep trench capacitor layout planning is performed to ensure efficient integration of deep trench capacitors into the chip without interfering with the performance of existing functional circuits. Specifically, for each identified power supply weakness region, regions that meet layout constraints are searched around or inside it. These constraints include logic cell layout density. Priority is given to regions within or adjacent to the power supply weakness region that have sparse or empty logic standard cell layouts, such as gaps between functional circuits or macrocells, underutilized space in cell rows, or chip edges and corners. Then, within the selected regions, the specific layout of the deep trench capacitor array is automatically planned based on the severity of the voltage drop (IR-Drop), spatial shape, and available substrate area. The planning includes determining the number and arrangement of deep trench capacitors (e.g., matrix or strip), as well as the physical dimensions of individual deep trench capacitors (e.g., depth and diameter), which together determine the total decoupling capacitance value provided. Finally, the top electrode of the planned deep trench capacitor array is connected to the on-chip power supply network through the chip's internal multilayer interconnect structure.

[0058] In summary, the chip and 3D stacked chip structure provided in this embodiment, by symmetrically distributing and integrating deep trench capacitor structures in the chip, supplements the charge storage capacity of the power network, effectively suppresses voltage drop problems, stabilizes the power supply voltage of the multi-layer stacked structure, and thus improves the power integrity of the chip.

[0059] Furthermore, deep-groove capacitors are integrated into the non-functional area of ​​the chip, without occupying the core functional area of ​​the chip, eliminating the need to reconstruct the chip layout, and balancing optimization effects with process compatibility; at the same time, they simultaneously reduce power supply crosstalk noise and electromigration risks, extend chip lifespan, and improve the stability of multi-chip stacked systems.

[0060] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0061] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0062] For ease of description, if systems, servers, etc. are involved, they may be described separately as various units / modules based on their functions. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0063] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, include: Semiconductor substrate; A functional circuit and a deep trench capacitor structure formed on the semiconductor substrate, wherein the deep trench capacitor structure is formed within the semiconductor substrate and electrically connected to the functional circuit; The deep trench capacitor structure is symmetrically distributed in an array in the vicinity of the functional circuit on the semiconductor substrate and is connected to the power supply network of the chip through a metal wiring layer. The deep trench capacitor structure is used to suppress the voltage drop of the functional circuit.

2. The chip according to claim 1, characterized in that, The functional circuit includes at least a first functional circuit and a second functional circuit, wherein the first functional circuit operates on a first power supply network, the second functional circuit operates on a second power supply network, and the first power supply network and the second power supply network are respectively set independently; The deep trench capacitor structure includes at least: a first group of deep trench capacitor structures and a second group of deep trench capacitor structures. The first group of deep trench capacitor structures is formed in the vicinity of the first functional circuit and connected to the first power supply network to suppress the voltage drop of the first functional circuit. The second group of deep trench capacitor structures is formed in the vicinity of the second functional circuit and connected to the second power supply network to suppress the voltage drop of the second functional circuit.

3. The chip according to claim 1, characterized in that, The adjacent area of ​​the functional circuit includes the edge region of the semiconductor substrate and the blank area between the functional circuit.

4. The chip according to claim 1, characterized in that, The deep trench capacitor structures are arranged in a grid-like array on the semiconductor substrate, and a preset distance is provided between adjacent deep trench capacitor structures.

5. The chip according to claim 1, characterized in that, The deep trench capacitor structures are symmetrically distributed in an array at the four corner edges of the semiconductor substrate, and adjacent deep trench capacitor structures are interconnected.

6. The chip according to claim 1, characterized in that, The functional circuit and the deep trench capacitor structure are fabricated on the chip simultaneously.

7. A 3D stacked chip structure, characterized in that, include: The bottom layer consists of a logic chip, a buffer chip stacked vertically on top of the logic chip, and multiple memory chips stacked vertically on top of the buffer chip in sequence, with the active surfaces of the multiple memory chips facing downwards. The logic chip, the buffer chip, and the plurality of memory chips are connected by a vertical interconnect structure. The deep trench capacitor structure disposed on the buffer chip and the plurality of memory chips is used to supply power to the upper layer chip to suppress the voltage drop caused by chip stacking. The buffer chip and the plurality of memory chips are chips as described in any one of claims 1-6.

8. The 3D stacked chip structure according to claim 7, characterized in that, The vertical interconnect structure includes: through-silicon vias (TSVs) and a bump array. The TSVs are disposed inside the logic chip, the buffer chip, and a plurality of memory chips stacked in between. The bump array is disposed between two vertically stacked chips and is disposed corresponding to the TSVs.

9. The 3D stacked chip structure according to claim 7, characterized in that, The arrangement of the logic chip at the bottom layer and the buffer chip vertically stacked on top of the logic chip includes at least the following: the logic chip and the buffer chip are arranged with their active surfaces facing down, the logic chip and the buffer chip are arranged with their active surfaces facing up, and one of the logic chip and the buffer chip is arranged with its active surface facing up and the other active surface facing down.

10. The 3D stacked chip structure according to claim 7, characterized in that, The deep trench capacitor structure is disposed on the active surface and / or back surface of the buffer chip and the memory chip.

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