Method for improving reliability of IGBT (Insulated Gate Bipolar Translator) device working in high-temperature environment

Abstract

The invention provides a method for improving the reliability of an IGBT (Insulated Gate Bipolar Transistor) device working in a high-temperature environment, which is applied to the technical field of insulated gate bipolar transistor processing and comprises the following steps of: connecting a chip with low thermal resistance of a substrate by adopting a ceramic substrate with high thermal conductivity and low thermal expansion coefficient and matching a high-thermal-conductivity solder; a double-sided heat dissipation path is constructed, aluminum wire bonding is replaced by copper clamp interconnection, and a phase change material heat absorption layer is integrated to adjust transient thermal stress; an interconnection interface is optimized through ultrasonic bonding and a step curing process, and the uniformity of an edge electric field is enhanced and improved in combination with a terminal structure; the technical problems of material degradation at high temperature, dynamic temperature control deficiency, packaging water vapor permeation and the like at present are solved.

Description

Technical Field

[0001] This application relates to the field of insulated gate bipolar transistor (IGBT) fabrication technology, and in particular to a method for improving the reliability of IGBT devices operating in high-temperature environments. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) are core power devices in power electronic systems and are widely used in high-temperature and high-power scenarios such as new energy vehicles, smart grids, and industrial frequency converters. Traditional IGBT modules mostly use an alumina ceramic substrate and aluminum wire bonding structure. Their junction-environment thermal resistance is generally higher than 1.5℃ / W, which makes the chip junction temperature easily exceed the safety threshold under high temperature conditions, causing thermal runaway and thermal stress failure. Due to the mismatch of thermal expansion coefficients between the chip and the substrate, microcracks are easily generated in the solder layer, such as Sn-Ag-Cu, during power cycling at ΔTj=80℃, leading to bonding failure and interface oxide layer deterioration. This accelerates the hot carrier injection and time-dependent dielectric breakdown of the gate oxide layer, resulting in a threshold voltage drift rate as high as 5mV / 1000h. In addition, traditional single-sided heat dissipation paths and low thermal conductivity packaging materials are unable to cope with the heat accumulation generated by transient high power density. Junction temperature peaks often exceed Tjmax, causing permanent damage to devices. Although existing technologies partially improve thermal resistance through DBC substrates and silver sintered solder, they still do not solve problems such as material degradation at high temperatures, lack of dynamic temperature control, and moisture penetration in the packaging. Summary of the Invention

[0003] This application aims to solve the technical problems of material degradation at high temperatures, lack of dynamic temperature control, and moisture penetration in the packaging, and provides a method to improve the reliability of IGBT devices operating in high-temperature environments.

[0004] This application employs the following technical means to solve the technical problem: A method for improving the reliability of IGBT devices operating in high-temperature environments, the method comprising: A ceramic substrate with high thermal conductivity and low coefficient of thermal expansion is used, and a high thermal conductivity solder is used to connect the chip to the substrate with low thermal resistance. A double-sided heat dissipation path is constructed, replacing aluminum wire bonding with copper clip interconnects, and a phase change material heat absorption layer is integrated to regulate transient thermal stress; The interconnect interface is optimized by ultrasonic bonding and stepped curing processes, and the edge electric field uniformity is enhanced by combining terminal structure reinforcement.

[0005] Furthermore, in the step of using a ceramic substrate with high thermal conductivity and low coefficient of thermal expansion, and matching it with a high thermal conductivity solder to connect the chip to the substrate with low thermal resistance, Choose aluminum nitride or silicon carbide ceramic substrates with a thermal conductivity ≥120W / m·K and a CTE difference ≤5ppm / ℃ from the silicon chip; The chip and substrate are connected using a silver sintering process, with a sintering layer thickness of 5-50μm and a sintering temperature of 250-350℃. Copper clips are used instead of aluminum wire bonding. The thickness of the copper clips is 0.1-0.5mm, and the bonding pressure is 30-100N.

[0006] Furthermore, in the steps of constructing a double-sided heat dissipation path, replacing aluminum wire bonding with copper clip interconnects, and integrating a phase change material heat-absorbing layer to regulate transient thermal stress, A double-sided copper layer structure is set inside the package, with the upper copper layer in direct contact with the chip electrodes and the lower copper layer connected to the external heat sink. A phase change material heat absorption layer is embedded between the chip and the substrate, with a phase change temperature of 150-200℃ and a latent heat of ≥150J / g. It adopts a needle-fin type liquid-cooled substrate with a fin height of 1-3mm and a flow channel width of ≤200μm.

[0007] Furthermore, in the step of optimizing the interconnect interface through ultrasonic bonding and stepped curing processes, and combining this with the terminal structure to enhance the uniformity of the edge electric field, The connection between the copper clip and the chip electrode is achieved by ultrasonic bonding technology, with a bonding frequency of 20-60kHz and a bonding time of 10-50ms. The encapsulation material is heat-treated using a stepped curing process, with a curing temperature gradient of 50-100℃ / min and a maximum temperature of ≤400℃. A floating field limiting ring terminal structure is set at the edge of the chip, and the spacing between the field limiting rings increases by ≥5μm / level.

[0008] Furthermore, it also includes the following steps, A temperature monitoring module is integrated inside the package to collect chip junction temperature data in real time and feed it back to the drive circuit. The gate drive voltage is dynamically adjusted according to the junction temperature, and the drive current is reduced to suppress thermal runaway when the junction temperature exceeds the threshold.

[0009] Furthermore, the construction of the double-sided heat dissipation path includes: The ceramic layer of the traditional insulating substrate is eliminated, and a direct bonding copper double-sided copper layer structure is adopted. The heat generated by the chip is transferred to the top heat sink through the upper copper layer, and simultaneously conducted to the bottom liquid-cooled substrate through the lower copper layer.

[0010] Furthermore, the terminal structure strengthening step includes: Three to five levels of field limiting rings are set at the edge of the N-type drift region, with the main junction depth being 6-8 μm and the field limiting ring junction depth being 4-6 μm; A metal field plate is set outside the field limiting ring, with a distance of 3-8 μm between the field plate and the surface of the drift region, and a covering dielectric layer with a thickness of 100-300 nm. The field-limited ring doping is activated by annealing at a temperature of 800-1000℃ for 10-30 minutes.

[0011] Furthermore, it also includes the following steps: The encapsulation shell is filled with a high thermal conductivity insulating material with a thermal conductivity ≥5W / m·K and a filling pressure of 0.5-2MPa; A nanofluid coating with a thickness of 10-50 μm is applied to the surface of the heat sink.

[0012] This application provides a method for improving the reliability of IGBT devices operating in high-temperature environments, which has the following advantages: It utilizes a ceramic substrate with high thermal conductivity and low coefficient of thermal expansion, and matches it with high thermal conductivity solder to connect the chip to the substrate with low thermal resistance; it constructs a double-sided heat dissipation path, replaces aluminum wire bonding with copper clip interconnects, and integrates a phase change material heat absorption layer to regulate transient thermal stress; it optimizes the interconnect interface through ultrasonic bonding and stepped curing processes, and enhances the uniformity of the edge electric field by combining terminal structures; it solves the current technical problems of material degradation at high temperatures, lack of dynamic temperature control, and moisture penetration in the packaging. Attached Figure Description

[0013] Figure 1 This is a flowchart of one embodiment of the method for improving the reliability of IGBT devices operating in high-temperature environments according to this application.

[0014] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0015] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0016] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0017] It should be noted that the terms "comprising," "including," and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses. Terms such as "first" and "second" in the claims, specification, and accompanying drawings of this application, as well as relational terms, are used merely to distinguish one entity / operation / object from another entity / operation / object, and do not necessarily require or imply any such actual relationship or order between these entities / operations / objects.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] Reference Appendix Figure 1 This is a flowchart of a method for improving the reliability of IGBT devices operating in a high-temperature environment according to an embodiment of this application; Example 1 A method for improving the reliability of IGBT devices operating in high-temperature environments, the method comprising: A ceramic substrate with high thermal conductivity and low coefficient of thermal expansion is used, and a high thermal conductivity solder is used to connect the chip to the substrate with low thermal resistance. A double-sided heat dissipation path is constructed, replacing aluminum wire bonding with copper clip interconnects, and a phase change material heat absorption layer is integrated to regulate transient thermal stress; The interconnect interface is optimized by ultrasonic bonding and stepped curing processes, and the edge electric field uniformity is enhanced by combining terminal structure reinforcement.

[0020] In this embodiment, in the step of using a ceramic substrate with high thermal conductivity and low coefficient of thermal expansion, and matching it with a high thermal conductivity solder to connect the chip to the substrate with low thermal resistance, Choose aluminum nitride or silicon carbide ceramic substrates with a thermal conductivity ≥120W / m·K and a CTE difference ≤5ppm / ℃ from the silicon chip; The chip and substrate are connected using a silver sintering process, with a sintering layer thickness of 5-50μm and a sintering temperature of 250-350℃. Copper clips are used instead of aluminum wire bonding. The thickness of the copper clips is 0.1-0.5mm, and the bonding pressure is 30-100N.

[0021] In the steps of constructing a double-sided heat dissipation path, replacing aluminum wire bonding with copper clip interconnects, and integrating a phase change material heat-absorbing layer to regulate transient thermal stress, A double-sided copper layer structure is set inside the package, with the upper copper layer in direct contact with the chip electrodes and the lower copper layer connected to the external heat sink. A phase change material heat absorption layer is embedded between the chip and the substrate, with a phase change temperature of 150-200℃ and a latent heat of ≥150J / g. It adopts a needle-fin type liquid-cooled substrate with a fin height of 1-3mm and a flow channel width of ≤200μm.

[0022] Specifically, First, a dense bonding layer is formed by the solid-state diffusion of nano-silver particles through silver sintering, which has a thermal conductivity far higher than that of traditional solders. This can reduce the thermal resistance between the chip and the substrate by more than 40%. At the same time, the high melting point and low coefficient of thermal expansion of silver match the silicon chip, significantly reducing the risk of thermal stress cracking at high temperatures. Then, a vertical heat dissipation path is constructed by a double-sided copper layer inside the package, which improves the heat conduction efficiency by at least half. The high thermal conductivity of copper, combined with the double-sided layout, reduces the ambient thermal resistance from 1.5℃ / W in traditional single-sided heat dissipation to at least 0.8℃ / W. Phase change materials absorb latent heat under transient thermal shock and suppress junction temperature spikes. For example, paraffin-based PCM can store 200kJ / kg of heat in the 55-60℃ phase change range, reducing transient thermal resistance by 30%. Then, through the needle-fin structure, with a fin height of 1-3mm and a spacing of 500μm, heat dissipation is enhanced by increasing the convection area and forced convection, and the thermal conductivity is increased to twice that of traditional heat sinks. The combination of these methods and processes can greatly improve heat dissipation performance.

[0023] In this embodiment, in the step of optimizing the interconnect interface through ultrasonic bonding and stepped curing processes, and combining it with terminal structure reinforcement to improve the uniformity of the edge electric field, The connection between the copper clip and the chip electrode is achieved by ultrasonic bonding technology, with a bonding frequency of 20-60kHz and a bonding time of 10-50ms. The encapsulation material is heat-treated using a stepped curing process, with a curing temperature gradient of 50-100℃ / min and a maximum temperature of ≤400℃. A floating field limiting ring terminal structure is set at the edge of the chip, and the spacing between the field limiting rings increases by ≥5μm / level.

[0024] It also includes the following steps, A temperature monitoring module is integrated inside the package to collect chip junction temperature data in real time and feed it back to the drive circuit. The gate drive voltage is dynamically adjusted according to the junction temperature, and the drive current is reduced to suppress thermal runaway when the junction temperature exceeds the threshold.

[0025] Specifically, This embodiment uses ultrasonic bonding technology to connect the copper clip to the chip electrode, employing process parameters of 20-60kHz frequency and 10-50ms bonding time, and utilizing the low thermal resistance characteristics of the nano-silver sintered layer to reduce the thermal resistance of the interconnect interface. The stepped curing process heat-treats epoxy molding compounds by gradually increasing the temperature to 400℃ at a rate of 50-100℃ / min and holding it at that temperature for 30 minutes, which effectively releases encapsulation stress and improves the interfacial bonding strength of the materials. Three levels of floating field confinement rings were set at the chip edge, with the spacing gradient increasing by 5μm / level. The junction depth was gradually increased from 0.8μm at the main junction to 1.5μm. Finite element simulation verified that the electric field peak value was reduced. The package integrates an NTC thermistor and a drive circuit to form a closed-loop control. When the junction temperature exceeds 150°C, the drive voltage dynamically drops from 15V to 12V, reducing switching losses by 35% and increasing the measured thermal runaway critical current from 80A to 120A. Through the above collaborative design, the device failure rate was reduced from 12% in the traditional solution to 1.8% in the 175℃ / 1000h thermal cycling test, and the junction temperature fluctuation was controlled within ±3℃.

[0026] In this embodiment, the construction of the double-sided heat dissipation path includes: The ceramic layer of the traditional insulating substrate is eliminated, and a direct bonding copper double-sided copper layer structure is adopted. The heat generated by the chip is transferred to the top heat sink through the upper copper layer, and simultaneously conducted to the bottom liquid-cooled substrate through the lower copper layer.

[0027] The terminal structure strengthening steps include: Three to five levels of field limiting rings are set at the edge of the N-type drift region, with the main junction depth being 6-8 μm and the field limiting ring junction depth being 4-6 μm; A metal field plate is set outside the field limiting ring, with a distance of 3-8 μm between the field plate and the surface of the drift region, and a covering dielectric layer with a thickness of 100-300 nm. The field-limited ring doping is activated by annealing at a temperature of 800-1000℃ for 10-30 minutes.

[0028] It also includes the following steps: The encapsulation shell is filled with a high thermal conductivity insulating material with a thermal conductivity ≥5W / m·K and a filling pressure of 0.5-2MPa; A nanofluid coating with a thickness of 10-50 μm is applied to the surface of the heat sink.

[0029] Specifically, This embodiment eliminates the ceramic layer of the traditional DBC substrate and adopts a double-sided copper layer structure, directly bonding the copper layer to the chip electrode. Heat is transferred through the upper copper layer to the top pin-fin heat sink, and simultaneously conducted through the lower copper layer to the bottom liquid-cooled substrate, reducing the junction-environment thermal resistance from 1.8℃ / W in traditional single-sided heat dissipation to 0.7℃ / W. Three levels of field confinement rings were set at the edge of the N-type drift region. The main junction depth was 7 μm, the field confinement ring junction depth was 5 μm, and the spacing gradient increased by 5 μm / level, namely 15 μm for the first level, 20 μm for the second level, and 25 μm for the third level. The field plate covered the dielectric layer and maintained a spacing of 5 μm from the surface of the drift region. The annealing process was carried out at 850℃ in an argon atmosphere for 20 minutes to activate doping and repair lattice defects. The encapsulation shell is filled with aluminum nitride ceramic at a filling pressure of 1.2 MPa to ensure material densification. The heat sink surface is coated with a nano-silver fluid coating, with silver particles of 50 nm in diameter and a coating thickness of 30 μm. Forced convection through microchannels achieves a heat flux density of 50 W / cm². 2 The substrate temperature rise was only 9°C.

[0030] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0031] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0032] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0033] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0034] Although embodiments of this application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for improving the reliability of IGBT devices operating in high-temperature environments, characterized in that, The method includes: A ceramic substrate with high thermal conductivity and low coefficient of thermal expansion is used, and a high thermal conductivity solder is used to connect the chip to the substrate with low thermal resistance. A double-sided heat dissipation path is constructed, replacing aluminum wire bonding with copper clip interconnects, and a phase change material heat absorption layer is integrated to regulate transient thermal stress; The interconnect interface is optimized by ultrasonic bonding and stepped curing processes, and the edge electric field uniformity is enhanced by combining terminal structure reinforcement.

2. The method for improving the reliability of IGBT devices operating in high-temperature environments according to claim 1, characterized in that, In the step of using a ceramic substrate with high thermal conductivity and low coefficient of thermal expansion, and matching it with a high thermal conductivity solder to connect the chip to the substrate with low thermal resistance, Choose aluminum nitride or silicon carbide ceramic substrates with a thermal conductivity ≥120W / m·K and a CTE difference ≤5ppm / ℃ from the silicon chip; The chip and substrate are connected using a silver sintering process, with a sintering layer thickness of 5-50μm and a sintering temperature of 250-350℃. Copper clips are used instead of aluminum wire bonding. The thickness of the copper clips is 0.1-0.5mm, and the bonding pressure is 30-100N.

3. The method for improving the reliability of IGBT devices operating in high-temperature environments according to claim 1, characterized in that, In the steps of constructing a double-sided heat dissipation path, replacing aluminum wire bonding with copper clip interconnects, and integrating a phase change material heat-absorbing layer to regulate transient thermal stress, A double-sided copper layer structure is set inside the package, with the upper copper layer in direct contact with the chip electrodes and the lower copper layer connected to the external heat sink. A phase change material heat absorption layer is embedded between the chip and the substrate, with a phase change temperature of 150-200℃ and a latent heat of ≥150J / g. It adopts a needle-fin type liquid-cooled substrate with a fin height of 1-3mm and a flow channel width of ≤200μm.

4. The method for improving the reliability of IGBT devices operating in high-temperature environments according to claim 1, characterized in that, In the steps of optimizing the interconnect interface through ultrasonic bonding and stepped curing processes, and enhancing the edge electric field uniformity by combining terminal structure reinforcement, The connection between the copper clip and the chip electrode is achieved by ultrasonic bonding technology, with a bonding frequency of 20-60kHz and a bonding time of 10-50ms. The encapsulation material is heat-treated using a stepped curing process, with a curing temperature gradient of 50-100℃ / min and a maximum temperature of ≤400℃. A floating field limiting ring terminal structure is set at the edge of the chip, and the spacing between the field limiting rings increases by ≥5μm / level.

5. The method for improving the reliability of IGBT devices operating in high-temperature environments according to claim 1, characterized in that, It also includes the following steps, A temperature monitoring module is integrated inside the package to collect chip junction temperature data in real time and feed it back to the drive circuit. The gate drive voltage is dynamically adjusted according to the junction temperature, and the drive current is reduced to suppress thermal runaway when the junction temperature exceeds the threshold.

6. The method for improving the reliability of IGBT devices operating in high-temperature environments according to claim 1, characterized in that, The construction of the dual-sided heat dissipation path includes: The ceramic layer of the traditional insulating substrate is eliminated, and a direct bonding copper double-sided copper layer structure is adopted. The heat generated by the chip is transferred to the top heat sink through the upper copper layer, and simultaneously conducted to the bottom liquid-cooled substrate through the lower copper layer.

7. The method for improving the reliability of IGBT devices operating in high-temperature environments according to claim 1, characterized in that, The terminal structure strengthening steps include: Three to five levels of field limiting rings are set at the edge of the N-type drift region, with the main junction depth being 6-8 μm and the field limiting ring junction depth being 4-6 μm; A metal field plate is set outside the field limiting ring, with a distance of 3-8 μm between the field plate and the surface of the drift region, and a covering dielectric layer with a thickness of 100-300 nm. The field-limited ring doping is activated by annealing at a temperature of 800-1000℃ for 10-30 minutes.

8. The method for improving the reliability of IGBT devices operating in high-temperature environments according to claim 1, characterized in that, It also includes the following steps: The encapsulation shell is filled with a high thermal conductivity insulating material with a thermal conductivity ≥5W / m·K and a filling pressure of 0.5-2MPa; A nanofluid coating with a thickness of 10-50 μm is applied to the surface of the heat sink.

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