Pixel circuit, pixel driving method and display device

Abstract

The invention provides a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a first driving circuit, a second driving circuit, a first light-emitting element, a second light-emitting element, a first compensation control circuit, a second compensation control circuit and a first on-off control circuit. The first on-off control circuit controls the connection or disconnection between the first first node and the second first node under the control of the first on-off control signal. According to the pixel circuit, the number of transistors adopted by the pixel circuit can be reduced, and low-frequency display can be achieved.

Description

Pixel circuits, pixel driving methods, and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device. Background Technology

[0002] In display products supporting both high and low refresh rates, at low refresh rates, a single frame can be divided into refresh subframes and hold subframes. Data voltage is written during the refresh subframe but not during the hold subframe, leading to a significant brightness drop within a single frame at low refresh rates, resulting in flickering. With the increasing demands on product specifications, there is an urgent need for a pixel circuit that can simultaneously reduce the number of transistors and achieve low-frequency display.

[0003] Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a pixel circuit, including a first driving circuit, a second driving circuit, a first light-emitting element, a second light-emitting element, a first compensation control circuit, a second compensation control circuit, and a first on / off control circuit;

[0005] The first driving circuit is electrically connected to the first first node, the first second node and the first third node respectively. The first driving circuit is used to generate a first driving current to drive the first light-emitting element under the control of the potential of the first first node.

[0006] The second driving circuit is electrically connected to the second first node, the second second node and the second third node respectively. The first driving circuit is used to generate a first driving current to drive the first light-emitting element under the control of the potential of the second first node.

[0007] The first compensation control circuit is electrically connected to the compensation control terminal and the first first node and the first control node respectively, and is used to control the connection or disconnection between the first first node and the first control node under the control of the compensation control signal provided by the compensation control terminal.

[0008] The second compensation control circuit is electrically connected to the compensation control terminal, the second first node, and the second control node, respectively, and is used to control the connection or disconnection between the second first node and the second control node under the control of the compensation control signal provided by the compensation control terminal;

[0009] The first on / off control circuit is electrically connected to the first on / off control terminal, the first first node, and the second first node, respectively, and is used to control the connection or disconnection between the first first node and the second first node under the control of the first on / off control signal provided by the first on / off control terminal.

[0010] Optionally, the first control node is the first second node, and the second control node is the second second node.

[0011] Optionally, the first control node is the first third node, and the second control node is the second third node.

[0012] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a first reset circuit and a second reset circuit;

[0013] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the first second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first second node under the control of the first reset control signal provided by the first reset control terminal.

[0014] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the second control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second control node under the control of the second reset control signal provided by the second reset control terminal.

[0015] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a first reset circuit and a second reset circuit;

[0016] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the second second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second second node under the control of the first reset control signal provided by the first reset control terminal;

[0017] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the first control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first control node under the control of the second reset control signal provided by the second reset control terminal.

[0018] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a first reset circuit and a second reset circuit;

[0019] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the first second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first second node under the control of the first reset control signal provided by the first reset control terminal.

[0020] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the first control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first control node under the control of the second reset control signal provided by the second reset control terminal.

[0021] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a first reset circuit and a second reset circuit;

[0022] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the second second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second second node under the control of the first reset control signal provided by the first reset control terminal;

[0023] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the second control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second control node under the control of the second reset control signal provided by the second reset control terminal.

[0024] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a first reset circuit and a second reset circuit;

[0025] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the second second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second second node under the control of the first reset control signal provided by the first reset control terminal;

[0026] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal and the first second node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first second node under the control of the second reset control signal provided by the second reset control terminal.

[0027] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a second on / off control circuit;

[0028] The second on / off control circuit is electrically connected to the second on / off control terminal, the first second node, and the second second node, respectively, and is used to control the connection or disconnection between the first second node and the second second node under the control of the second on / off control signal provided by the second on / off control terminal.

[0029] Optionally, the transistors included in the first compensation control circuit, the second compensation control circuit, and the first on / off control circuit are oxide transistors; the transistors included in the second on / off control circuit are oxide transistors.

[0030] Optionally, the pixel circuit further includes a first reset circuit, a second reset circuit, and a third reset circuit;

[0031] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal and the first second node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first second node under the control of the first reset control signal provided by the first reset control terminal;

[0032] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the second second node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second second node under the control of the second reset control signal provided by the second reset control terminal;

[0033] The third reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the second second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second second node under the control of the first reset control signal provided by the first reset control terminal.

[0034] Optionally, the pixel circuit further includes a first data writing circuit and a second data writing circuit;

[0035] The first data writing circuit is electrically connected to the scanning end, the first data line and the first third node respectively, and is used to write the first data voltage provided by the first data line into the first third node under the control of the scanning signal provided by the scanning end;

[0036] The second data writing circuit is electrically connected to the scanning end, the second data line and the second third node, respectively, and is used to write the second data voltage provided by the second data line into the second third node under the control of the scanning signal provided by the scanning end.

[0037] Optionally, the pixel circuit further includes a first data writing circuit and a second data writing circuit;

[0038] The first data writing circuit is electrically connected to the scanning end, the first data line and the first second node respectively, and is used to write the first data voltage provided by the first data line into the first second node under the control of the scanning signal provided by the scanning end;

[0039] The second data writing circuit is electrically connected to the scanning end, the second data line and the second second node, respectively, and is used to write the second data voltage provided by the second data line into the second second node under the control of the scanning signal provided by the scanning end.

[0040] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit, a first second light-emitting control circuit, a second first light-emitting control circuit, and a second second light-emitting control circuit;

[0041] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the first second node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the first second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0042] The first second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first third node, and the first electrode of the first light-emitting element, respectively, and is used to control the connection or disconnection between the first third node and the first electrode of the first light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal;

[0043] The second first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the second second node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0044] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second third node, and the first electrode of the second light-emitting element, respectively, and is used to control the connection or disconnection between the second third node and the first electrode of the second light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal.

[0045] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit, a second initialization circuit, a first energy storage circuit, and a second energy storage circuit;

[0046] The first initialization circuit is electrically connected to the initial control terminal, the second initial voltage terminal, and the first electrode of the first light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the first light-emitting element under the control of the initial control signal provided by the initial control terminal;

[0047] The second initialization circuit is electrically connected to the initial control terminal, the third initial voltage terminal, and the first electrode of the second light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the second light-emitting element under the control of the initial control signal provided by the initial control terminal;

[0048] The first energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node;

[0049] The second energy storage circuit is electrically connected to the second first node and is used to maintain the potential of the second first node.

[0050] Optionally, the first driving circuit includes a first driving transistor, the second driving circuit includes a second driving transistor, the first compensation control circuit includes a first transistor, the second compensation control circuit includes a second transistor, and the first on / off control circuit includes a third transistor.

[0051] The gate of the first driving transistor is electrically connected to the first first node, the first electrode of the first driving transistor is electrically connected to the first second node, and the second electrode of the first driving transistor is electrically connected to the first third node.

[0052] The gate of the second driving transistor is electrically connected to the second first node, the first terminal of the second driving transistor is electrically connected to the second second node, and the second terminal of the second driving transistor is electrically connected to the second third node.

[0053] The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the first first node, and the second electrode of the first transistor is electrically connected to the first control node.

[0054] The gate of the second transistor is electrically connected to the compensation control terminal, the first terminal of the second transistor is electrically connected to the second first node, and the second terminal of the second transistor is electrically connected to the second control node.

[0055] The gate of the third transistor is electrically connected to the first on / off control terminal, the first electrode of the third transistor is electrically connected to the first first node, and the second electrode of the third transistor is electrically connected to the second first node.

[0056] Optionally, the second on / off control circuit includes a sixth transistor;

[0057] The gate of the sixth transistor is electrically connected to the second on / off control terminal, the first terminal of the sixth transistor is electrically connected to the first second node, and the second terminal of the sixth transistor is electrically connected to the second second node.

[0058] Optionally, the first initialization circuit includes a fourteenth transistor, the second initialization circuit includes a fifteenth transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor.

[0059] The gate of the fourteenth transistor is electrically connected to the initial control terminal, the first terminal of the fourteenth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the first light-emitting element.

[0060] The gate of the fifteenth transistor is electrically connected to the initial control terminal, the first terminal of the fifteenth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the fifteenth transistor is electrically connected to the first terminal of the second light-emitting element.

[0061] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the first DC voltage terminal.

[0062] The first terminal of the second capacitor is electrically connected to the second first node, and the second terminal of the second capacitor is electrically connected to the second DC voltage terminal.

[0063] Optionally, the first reset circuit includes a fourth transistor, the second reset circuit includes a fifth transistor, and the third reset circuit includes a seventh transistor;

[0064] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the reference voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first second node.

[0065] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second second node.

[0066] The gate of the seventh transistor is electrically connected to the first reset control terminal, the first terminal of the seventh transistor is electrically connected to the reference voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second second node.

[0067] The pixel circuit further includes a first data writing circuit, a second data writing circuit, a first first light emission control circuit, a first second light emission control circuit, a second first light emission control circuit, and a second second light emission control circuit;

[0068] The first data writing circuit includes an eighth transistor, and the second data writing circuit includes a ninth transistor;

[0069] The gate of the eighth transistor is electrically connected to the scan terminal, the first terminal of the eighth transistor is electrically connected to the first data line, and the second terminal of the eighth transistor is electrically connected to the first third node.

[0070] The gate of the ninth transistor is electrically connected to the scan terminal, the first terminal of the ninth transistor is electrically connected to the second data line, and the second terminal of the ninth transistor is electrically connected to the second third node.

[0071] The first light-emitting control circuit includes a tenth transistor, the first second light-emitting control circuit includes an eleventh transistor, the second first light-emitting control circuit includes a twelfth transistor, and the second second light-emitting control circuit includes a thirteenth transistor;

[0072] The gate of the tenth transistor is electrically connected to the first light-emitting control terminal, the first terminal of the tenth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the tenth transistor is electrically connected to the first second node.

[0073] The gate of the eleventh transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eleventh transistor is electrically connected to the first third node, and the second terminal of the eleventh transistor is electrically connected to the first terminal of the first light-emitting element.

[0074] The gate of the twelfth transistor is electrically connected to the first light-emitting control terminal, the first terminal of the twelfth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the twelfth transistor is electrically connected to the second second node.

[0075] The gate of the thirteenth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the thirteenth transistor is electrically connected to the second third node, and the second terminal of the thirteenth transistor is electrically connected to the first terminal of the second light-emitting element.

[0076] In a second aspect, embodiments of this disclosure provide a pixel driving method applied to the aforementioned pixel circuit, wherein the display cycle includes a reset phase and a compensation phase set sequentially; the pixel driving method includes:

[0077] During the reset phase, the first on / off control circuit, under the control of the first on / off control signal, controls the connection between the first first node and the second first node; the first compensation control circuit, under the control of the compensation control signal, controls the connection between the first first node and the first control node; and the second compensation control circuit, under the control of the compensation control signal, controls the connection between the second first node and the second control node.

[0078] During the compensation phase, the first compensation control circuit, under the control of the compensation control signal, controls the connection between the first first node and the first control node; the second compensation control circuit, under the control of the compensation control signal, controls the connection between the second first node and the second control node.

[0079] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above. Attached Figure Description

[0080] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0082] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0084] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0085] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0086] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0087] Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0088] Figure 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0089] Figure 10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0090] Figure 11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0091] Figure 12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0092] Figure 13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0093] Figure 14 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0094] Figure 15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0095] Figure 16 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0096] Figure 17 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0097] Figure 18 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0098] Figure 19 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0099] Figure 20 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0100] Figure 21 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0101] Figure 22 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0102] Figure 23 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0103] Figure 24 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 23;

[0104] Figure 25 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0105] Figure 26 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 25;

[0106] Figure 27 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0107] Figure 28 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 27;

[0108] Figure 29 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0109] Figure 30 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 29;

[0110] Figure 31A is a first simulation timing diagram of at least one embodiment of the pixel circuit shown in Figure 23;

[0111] Figure 31B is a second simulation timing diagram of at least one embodiment of the pixel circuit shown in Figure 23;

[0112] Figure 31C is a third simulation timing diagram of at least one embodiment of the pixel circuit shown in Figure 23;

[0113] Figure 32 is a structural diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0114] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0115] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0116] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0117] The pixel circuit described in this embodiment includes a first driving circuit, a second driving circuit, a first light-emitting element, a second light-emitting element, a first compensation control circuit, a second compensation control circuit, and a first on / off control circuit;

[0118] The first driving circuit is electrically connected to the first first node, the first second node and the first third node respectively. The first driving circuit is used to generate a first driving current to drive the first light-emitting element under the control of the potential of the first first node.

[0119] The second driving circuit is electrically connected to the second first node, the second second node and the second third node respectively. The first driving circuit is used to generate a first driving current to drive the first light-emitting element under the control of the potential of the second first node.

[0120] The first compensation control circuit is electrically connected to the compensation control terminal, the first first node and the first control node respectively, and is used to control the connection or disconnection between the first first node and the first control node under the control of the compensation control signal provided by the compensation control terminal;

[0121] The second compensation control circuit is electrically connected to the compensation control terminal, the second first node, and the second control node, respectively, and is used to control the connection or disconnection between the second first node and the second control node under the control of the compensation control signal provided by the compensation control terminal;

[0122] The first on / off control circuit is electrically connected to the first on / off control terminal, the first first node, and the second first node, respectively, and is used to control the connection or disconnection between the first first node and the second first node under the control of the first on / off control signal provided by the first on / off control terminal.

[0123] In at least one embodiment of this disclosure, the first control node is a first second node and the second control node is a second second node; or, the first control node is a first third node and the second control node is a second third node.

[0124] The pixel circuit described in this embodiment includes a first pixel driving circuit and a second pixel driving circuit. The first pixel driving circuit includes a first driving circuit and a first compensation control circuit, and the second pixel driving circuit includes a second driving circuit and a second compensation control circuit. The pixel circuit described in this embodiment employs a first on / off control circuit. Under the control of a first on / off control signal, the first on / off control circuit controls the connection or disconnection between the first first node and the second first node, so that the same transistor can provide an initial voltage to the two pixel driving circuits and a reference voltage to the two pixel driving circuits, thereby reducing the number of transistors used in the pixel circuit.

[0125] In at least one embodiment of this disclosure, the transistors included in the first compensation control circuit, the second compensation control circuit, and the first on / off control circuit are oxide transistors, so as to effectively reduce the leakage current of the first node and the second node, improve the gate voltage holding capability of the first driving transistor included in the first driving circuit, and improve the gate voltage holding capability of the second driving transistor included in the second driving circuit, so as to realize low-frequency display.

[0126] As shown in Figure 1, the pixel circuit described in this embodiment includes a first driving circuit 10, a second driving circuit 20, a first light-emitting element E1, a second light-emitting element E2, a first compensation control circuit 21, a second compensation control circuit 22, and a first on / off control circuit 23.

[0127] The first driving circuit 10 is electrically connected to the first first node N11, the first second node N12 and the first third node N13 respectively. The first driving circuit 10 is used to generate a first driving current to drive the first light-emitting element E1 under the control of the potential of the first first node N11.

[0128] The second driving circuit 20 is electrically connected to the second first node N21, the second second node N22 and the second third node N23 respectively. The second driving circuit 20 is used to generate a first driving current to drive the first light-emitting element E1 under the control of the potential of the second first node N21.

[0129] The first compensation control circuit 21 is electrically connected to the compensation control terminal GN, the first first node N11 and the first second node N12 respectively, and is used to control the connection or disconnection between the first first node N11 and the first second node N12 under the control of the compensation control signal provided by the compensation control terminal GN.

[0130] The second compensation control circuit 22 is electrically connected to the compensation control terminal GN, the second first node N21 and the second second node N22 respectively, and is used to control the connection or disconnection between the second first node N21 and the second second node N22 under the control of the compensation control signal provided by the compensation control terminal GN;

[0131] The first on / off control circuit 23 is electrically connected to the first on / off control terminal ST1, the first first node N11 and the second first node N21 respectively, and is used to control the connection or disconnection between the first first node N21 and the second first node N21 under the control of the first on / off control signal provided by the first on / off control terminal ST1.

[0132] In at least one embodiment of the pixel circuit shown in Figure 1, the first control node is a first third node, and the second control node is a second third node.

[0133] In at least one embodiment of this disclosure, the compensation control terminal can be the Nth level first scan terminal, and the first on / off control terminal can be the Nmth level first scan terminal, where N and m can be positive integers, for example, m can be equal to 7.

[0134] As shown in Figure 2, the pixel circuit described in this embodiment includes a first driving circuit 10, a second driving circuit 20, a first light-emitting element E1, a second light-emitting element 32, a first compensation control circuit 21, a second compensation control circuit 22, and a first on / off control circuit 23.

[0135] The first driving circuit 10 is electrically connected to the first first node N11, the first second node N12 and the first third node N13 respectively. The first driving circuit 10 is used to generate a first driving current to drive the first light-emitting element E1 under the control of the potential of the first first node N11.

[0136] The second driving circuit 20 is electrically connected to the second first node N21, the second second node N22 and the second third node N23 respectively. The second driving circuit 20 is used to generate a first driving current to drive the first light-emitting element E1 under the control of the potential of the second first node N21.

[0137] The first compensation control circuit 21 is electrically connected to the compensation control terminal GN, the first first node N11 and the first third node N13 respectively, and is used to control the connection or disconnection between the first first node N11 and the first third node N13 under the control of the compensation control signal provided by the compensation control terminal GN.

[0138] The second compensation control circuit 22 is electrically connected to the compensation control terminal GN, the second first node N21 and the second third node N23 respectively, and is used to control the connection or disconnection between the second first node N21 and the second third node N23 under the control of the compensation control signal provided by the compensation control terminal GN;

[0139] The first on / off control circuit 23 is electrically connected to the first on / off control terminal ST1, the first first node N11 and the second first node N21 respectively, and is used to control the connection or disconnection between the first first node N21 and the second first node N21 under the control of the first on / off control signal provided by the first on / off control terminal ST1.

[0140] In at least one embodiment of the pixel circuit shown in Figure 2, the first control node is a first third node, and the second control node is a second third node.

[0141] In at least one embodiment of this disclosure, the compensation control terminal can be the Nth level first scan terminal, and the first on / off control terminal can be the Nmth level first scan terminal, where N and m can be positive integers, for example, m can be equal to 7.

[0142] The pixel circuit described in at least one embodiment of this disclosure further includes a second on / off control circuit;

[0143] The second on / off control circuit is electrically connected to the second on / off control terminal, the first second node, and the second second node, respectively, and is used to control the connection or disconnection between the first second node and the second second node under the control of the second on / off control signal provided by the second on / off control terminal.

[0144] In a specific implementation, the pixel circuit may further include a second on / off control circuit, which, under the control of a second on / off control signal, controls the connection or disconnection between the first second node and the second second node.

[0145] The pixel circuit described in at least one embodiment of this disclosure further includes a first reset circuit and a second reset circuit;

[0146] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the first second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first second node under the control of the first reset control signal provided by the first reset control terminal.

[0147] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the second control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second control node under the control of the second reset control signal provided by the second reset control terminal.

[0148] In a specific implementation, the pixel circuit may further include a first reset circuit, which, under the control of a first reset control signal, writes a reference voltage into a first second node, and the second reset circuit, under the control of a second reset control signal, writes the first initial voltage into a second control node.

[0149] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a first reset circuit 31, a second reset circuit 32, and a second on / off control circuit 30.

[0150] The first reset circuit 31 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF, and the first second node N12, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the first second node N12 under the control of the first reset control signal provided by the first reset control terminal R1.

[0151] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the second second node N22 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second second node N22 under the control of the second reset control signal provided by the second reset control terminal R2.

[0152] The second on / off control circuit 30 is electrically connected to the second on / off control terminal ST2, the first second node N12 and the second second node N22 respectively, and is used to control the connection or disconnection between the first second node N12 and the second second node N22 under the control of the second on / off control signal provided by the second on / off control terminal ST2.

[0153] At least one embodiment of the pixel circuit shown in Figure 3 of this disclosure, when in operation,

[0154] The first second node can be reset by the first reset circuit, and the second second node can be reset by the first reset circuit and the second on / off control circuit.

[0155] The second first node can be reset by the second reset circuit and the second compensation control circuit, and the first first node can be reset by the second reset circuit, the second compensation control circuit and the first on / off control circuit.

[0156] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes a first reset circuit 31, a second reset circuit 32, and a second on / off control circuit 30.

[0157] The first reset circuit 31 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF, and the first second node N12, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the first second node N12 under the control of the first reset control signal provided by the first reset control terminal R1.

[0158] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the second third node N23 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second third node N23 under the control of the second reset control signal provided by the second reset control terminal R2.

[0159] The second on / off control circuit 30 is electrically connected to the second on / off control terminal ST2, the first second node N12 and the second second node N22 respectively, and is used to control the connection or disconnection between the first second node N12 and the second second node N22 under the control of the second on / off control signal provided by the second on / off control terminal ST2.

[0160] At least one embodiment of the pixel circuit shown in Figure 4 of this disclosure, when in operation,

[0161] The first second node can be reset by the first reset circuit, and the second second node can be reset by the first reset circuit and the second on / off control circuit.

[0162] The second first node can be reset by the second reset circuit and the second compensation control circuit, and the first first node can be reset by the second reset circuit, the second compensation control circuit and the first on / off control circuit.

[0163] The pixel circuit described in at least one embodiment of this disclosure further includes a first reset circuit and a second reset circuit;

[0164] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the second second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second second node under the control of the first reset control signal provided by the first reset control terminal;

[0165] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the first control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first control node under the control of the second reset control signal provided by the second reset control terminal.

[0166] In a specific implementation, the pixel circuit may further include a first reset circuit and a second reset circuit. Under the control of a first reset control signal, the first reset circuit writes a reference voltage into a second second node, and under the control of a second reset control signal, the second reset circuit writes a first initial voltage into a first control node.

[0167] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a first reset circuit 31, a second reset circuit 32, and a second on / off control circuit 30.

[0168] The first reset circuit 31 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF, and the second node N22, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second node N22 under the control of the first reset control signal provided by the first reset control terminal R1.

[0169] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the first second node N12 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first second node N12 under the control of the second reset control signal provided by the second reset control terminal R2.

[0170] The second on / off control circuit 30 is electrically connected to the second on / off control terminal ST2, the first second node N12 and the second second node N22 respectively, and is used to control the connection or disconnection between the first second node N12 and the second second node N22 under the control of the second on / off control signal provided by the second on / off control terminal ST2.

[0171] At least one embodiment of the pixel circuit shown in FIG5 of this disclosure, when in operation,

[0172] The second second node can be reset by the first reset circuit, and the first second node can be reset by the first reset circuit and the second on / off control circuit.

[0173] The first node can be reset by the second reset circuit and the first compensation control circuit, and the second node can be reset by the second reset circuit, the first compensation control circuit and the first on / off control circuit.

[0174] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes a first reset circuit 31, a second reset circuit 32, and a second on / off control circuit 30.

[0175] The first reset circuit 31 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF, and the second node N22, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second node N22 under the control of the first reset control signal provided by the first reset control terminal R1.

[0176] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the first third node N13 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first third node N13 under the control of the second reset control signal provided by the second reset control terminal R2.

[0177] The second on / off control circuit 30 is electrically connected to the second on / off control terminal ST2, the first second node N12 and the second second node N22 respectively, and is used to control the connection or disconnection between the first second node N12 and the second second node N22 under the control of the second on / off control signal provided by the second on / off control terminal ST2.

[0178] At least one embodiment of the pixel circuit shown in FIG6 of this disclosure, when in operation,

[0179] The second second node can be reset by the first reset circuit, and the first second node can be reset by the first reset circuit and the second on / off control circuit.

[0180] The first node can be reset by the second reset circuit and the first compensation control circuit, and the second node can be reset by the second reset circuit, the first compensation control circuit and the first on / off control circuit.

[0181] The pixel circuit described in at least one embodiment of this disclosure further includes a first reset circuit and a second reset circuit;

[0182] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the first second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first second node under the control of the first reset control signal provided by the first reset control terminal.

[0183] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the first control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first control node under the control of the second reset control signal provided by the second reset control terminal.

[0184] In a specific implementation, the pixel circuit may further include a first reset circuit, which, under the control of a first reset control signal, writes a reference voltage into a first second node, and the second reset circuit, under the control of a second reset control signal, writes a first initial voltage into the first control node.

[0185] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a first reset circuit 31, a second reset circuit 32, and a second on / off control circuit 30.

[0186] The first reset circuit 31 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF, and the first second node N12, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the first second node N12 under the control of the first reset control signal provided by the first reset control terminal R1.

[0187] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the first second node N12 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first second node N12 under the control of the second reset control signal provided by the second reset control terminal R2.

[0188] The second on / off control circuit 30 is electrically connected to the second on / off control terminal ST2, the first second node N12 and the second second node N22 respectively, and is used to control the connection or disconnection between the first second node N12 and the second second node N22 under the control of the second on / off control signal provided by the second on / off control terminal ST2.

[0189] At least one embodiment of the pixel circuit shown in FIG7 of this disclosure, when in operation,

[0190] The first second node can be reset by the first reset circuit, and the second second node can be reset by the first reset circuit and the second on / off control circuit.

[0191] The first node is reset by the second reset circuit and the first compensation control circuit, and the second node is reset by the second reset circuit, the first compensation control circuit and the first on / off control circuit.

[0192] As shown in Figure 8, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes a first reset circuit 31, a second reset circuit 32, and a second on / off control circuit 30.

[0193] The first reset circuit 31 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF, and the first second node N12, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the first second node N12 under the control of the first reset control signal provided by the first reset control terminal R1.

[0194] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the first third node N13 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first third node N13 under the control of the second reset control signal provided by the second reset control terminal R2.

[0195] The second on / off control circuit 30 is electrically connected to the second on / off control terminal ST2, the first second node N12 and the second second node N22 respectively, and is used to control the connection or disconnection between the first second node N12 and the second second node N22 under the control of the second on / off control signal provided by the second on / off control terminal ST2.

[0196] At least one embodiment of the pixel circuit shown in FIG8 of this disclosure, when in operation,

[0197] The first second node can be reset by the first reset circuit, and the second second node can be reset by the first reset circuit and the second on / off control circuit.

[0198] The first node is reset by the second reset circuit and the first compensation control circuit, and the second node is reset by the second reset circuit, the first compensation control circuit and the first on / off control circuit.

[0199] The pixel circuit described in at least one embodiment of this disclosure further includes a first reset circuit and a second reset circuit;

[0200] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the second second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second second node under the control of the first reset control signal provided by the first reset control terminal;

[0201] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the second control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second control node under the control of the second reset control signal provided by the second reset control terminal.

[0202] In a specific implementation, the pixel circuit may further include a first reset circuit and a second reset circuit. Under the control of a first reset control signal, the first reset circuit writes a reference voltage into a second second node, and under the control of a second reset control signal, the second reset circuit writes a first initial voltage into a second control node.

[0203] As shown in Figure 9, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a first reset circuit 31, a second reset circuit 32, and a second on / off control circuit 30.

[0204] The first reset circuit 31 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF, and the second node N22, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second node N22 under the control of the first reset control signal provided by the first reset control terminal R1.

[0205] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the second second node N22 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second second node N22 under the control of the second reset control signal provided by the second reset control terminal R2.

[0206] The second on / off control circuit 30 is electrically connected to the second on / off control terminal ST2, the first second node N12 and the second second node N22 respectively, and is used to control the connection or disconnection between the first second node N12 and the second second node N22 under the control of the second on / off control signal provided by the second on / off control terminal ST2.

[0207] At least one embodiment of the pixel circuit shown in FIG9 of this disclosure, when in operation,

[0208] The second second node can be reset by the first reset circuit, and the first second node can be reset by the first reset circuit and the second on / off control circuit.

[0209] The first node is reset by the second reset circuit and the first compensation control circuit, and the second node is reset by the second reset circuit, the first compensation control circuit and the first on / off control circuit.

[0210] As shown in Figure 10, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes a first reset circuit 31, a second reset circuit 32, and a second on / off control circuit 30.

[0211] The first reset circuit 31 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF, and the second node N22, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second node N22 under the control of the first reset control signal provided by the first reset control terminal R1.

[0212] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the second third node N23 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second third node N23 under the control of the second reset control signal provided by the second reset control terminal R2.

[0213] The second on / off control circuit 30 is electrically connected to the second on / off control terminal ST2, the first second node N12 and the second second node N22 respectively, and is used to control the connection or disconnection between the first second node N12 and the second second node N22 under the control of the second on / off control signal provided by the second on / off control terminal ST2.

[0214] At least one embodiment of the pixel circuit shown in FIG10 of this disclosure, when in operation,

[0215] The second second node can be reset by a reset circuit, and the first second node can be reset by a first reset circuit and a second on / off control circuit.

[0216] The second first node is reset by the second reset circuit and the second compensation control circuit, and the first first node is reset by the second reset circuit, the second compensation control circuit and the first on / off control circuit.

[0217] As shown in Figure 11, based on at least one embodiment of the pixel circuit shown in Figure 2,

[0218] The pixel circuit described in at least one embodiment of this disclosure further includes a first reset circuit 31, a second reset circuit 32, and a second on / off control circuit 30;

[0219] The first reset circuit 31 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF, and the second node N22, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second node N22 under the control of the first reset control signal provided by the first reset control terminal R1.

[0220] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the first second node N12 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first second node N12 under the control of the second reset control signal provided by the second reset control terminal R2.

[0221] The second on / off control circuit 30 is electrically connected to the second on / off control terminal ST2, the first second node N12 and the second second node N22 respectively, and is used to control the connection or disconnection between the first second node N12 and the second second node N22 under the control of the second on / off control signal provided by the second on / off control terminal ST2.

[0222] At least one embodiment of the pixel circuit shown in FIG11 of this disclosure, when in operation,

[0223] The second second node can be reset by a reset circuit, and the first second node can be reset by a first reset circuit and a second on / off control circuit.

[0224] The first node is reset by the second reset circuit, the first drive circuit and the first compensation control circuit, and then the second node is reset by the first on / off control circuit.

[0225] In at least one embodiment of this disclosure, the first control node is a first second node, and the second control node is a second second node; the pixel circuit further includes a first reset circuit, a second reset circuit, and a third reset circuit;

[0226] The first reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal and the first second node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first second node under the control of the first reset control signal provided by the first reset control terminal;

[0227] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the second second node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second second node under the control of the second reset control signal provided by the second reset control terminal;

[0228] The third reset circuit is electrically connected to the first reset control terminal, the reference voltage terminal, and the second second node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second second node under the control of the first reset control signal provided by the first reset control terminal.

[0229] In a specific implementation, when the first control node is the first second node and the second control node is the second second node, the pixel circuit may further include a first reset circuit, a second reset circuit, and a third reset circuit; the first reset circuit, under the control of a first reset control signal, writes a reference voltage into the first second node; the second reset circuit, under the control of a second reset control signal, writes a first initial voltage into the second second node; and the third reset circuit, under the control of the first reset control signal, writes a reference voltage into the second second node.

[0230] As shown in Figure 12, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit further includes a first reset circuit 31, a second reset circuit 32, and a third reset circuit 33.

[0231] The first reset circuit 31 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF and the first second node N12 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the first second node N12 under the control of the first reset control signal provided by the first reset control terminal R1.

[0232] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the second second node N22 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second second node N22 under the control of the second reset control signal provided by the second reset control terminal R2.

[0233] The third reset circuit 33 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF, and the second node N22, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second node N22 under the control of the first reset control signal provided by the first reset control terminal R1.

[0234] At least one embodiment of the pixel circuit shown in FIG12 of this disclosure, when in operation,

[0235] The first second node can be reset using the first reset circuit, and the second second node can be reset using the third reset circuit.

[0236] The second first node is reset by the second reset circuit and the second compensation control circuit, and the first first node is reset by the second reset circuit, the second compensation control circuit and the first on / off control circuit.

[0237] In at least one embodiment of this disclosure, the first control node is a first second node, and the second control node is a second second node; the pixel circuit further includes a first data writing circuit and a second data writing circuit;

[0238] The first data writing circuit is electrically connected to the scanning end, the first data line and the first third node respectively, and is used to write the first data voltage provided by the first data line into the first third node under the control of the scanning signal provided by the scanning end;

[0239] The second data writing circuit is electrically connected to the scanning end, the second data line and the second third node, respectively, and is used to write the second data voltage provided by the second data line into the second third node under the control of the scanning signal provided by the scanning end.

[0240] In a specific implementation, when the first control node is the first second node and the second control node is the second second node, the pixel circuit may include a first data writing circuit and a second data writing circuit. Under the control of the scan signal, the first data writing circuit writes a first data voltage to the first third node; the second data writing circuit writes a second data voltage to the second third node under the control of the scan signal.

[0241] In at least one embodiment of this disclosure, the first control node is a first third node, and the second control node is a second third node; the pixel circuit further includes a first data writing circuit and a second data writing circuit;

[0242] The first data writing circuit is electrically connected to the scanning end, the first data line and the first second node respectively, and is used to write the first data voltage provided by the first data line into the first second node under the control of the scanning signal provided by the scanning end;

[0243] The second data writing circuit is electrically connected to the scanning end, the second data line and the second second node, respectively, and is used to write the second data voltage provided by the second data line into the second second node under the control of the scanning signal provided by the scanning end.

[0244] In a specific implementation, when the first control node is the first third node and the second control node is the second third node, the pixel circuit may include a first data writing circuit and a second data writing circuit. Under the control of the scan signal, the first data writing circuit writes a first data voltage to the first second node; under the control of the scan signal, the second data writing circuit writes a second data voltage to the second second node.

[0245] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit, a first second light-emitting control circuit, a second first light-emitting control circuit, and a second second light-emitting control circuit;

[0246] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the first second node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the first second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0247] The first second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first third node, and the first electrode of the first light-emitting element, respectively, and is used to control the connection or disconnection between the first third node and the first electrode of the first light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal.

[0248] The second first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the second second node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0249] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second third node, and the first electrode of the second light-emitting element, respectively, and is used to control the connection or disconnection between the second third node and the first electrode of the second light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal.

[0250] In a specific implementation, the pixel circuit may further include a first first light-emitting control circuit, a first second light-emitting control circuit, a second first light-emitting control circuit, and a second second light-emitting control circuit to control light emission.

[0251] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit, a second initialization circuit, a first energy storage circuit, and a second energy storage circuit;

[0252] The first initialization circuit is electrically connected to the initial control terminal, the second initial voltage terminal, and the first electrode of the first light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the first light-emitting element under the control of the initial control signal provided by the initial control terminal;

[0253] The second initialization circuit is electrically connected to the initial control terminal, the third initial voltage terminal, and the first electrode of the second light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the second light-emitting element under the control of the initial control signal provided by the initial control terminal;

[0254] The first energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node;

[0255] The second energy storage circuit is electrically connected to the second first node and is used to maintain the potential of the second first node.

[0256] In a specific implementation, the pixel circuit may further include a first initialization circuit, a second initialization circuit, a first energy storage circuit, and a second energy storage circuit. Under the control of an initial control signal, the first initialization circuit writes a second initial voltage into the first electrode of the first light-emitting element to clear the residual charge on the first electrode of the first light-emitting element. Under the control of an initial control signal, the second initialization circuit writes a third initial voltage into the first electrode of the second light-emitting element to clear the residual charge on the first electrode of the second light-emitting element.

[0257] Optionally, the second initial voltage terminal and the third initial voltage terminal can be the same initial voltage terminal.

[0258] As shown in Figure 13, based on at least one embodiment of the pixel circuit shown in Figure 3,

[0259] The pixel circuit described in at least one embodiment of this disclosure further includes a first data writing circuit 41 and a second data writing circuit 42;

[0260] The first data writing circuit 41 is electrically connected to the scanning end GT, the first data line DL1 and the first third node N13 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first third node N13 under the control of the scanning signal provided by the scanning end GT.

[0261] The second data writing circuit 42 is electrically connected to the scanning end GT, the second data line DL2 and the second third node N23 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second third node N23 under the control of the scanning signal provided by the scanning end GT.

[0262] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit 511, a first second light-emitting control circuit 512, a second first light-emitting control circuit 521, and a second second light-emitting control circuit 522;

[0263] The first light-emitting control circuit 511 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the first second node N12, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first second node V12 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0264] The first second light-emitting control circuit 512 is electrically connected to the second light-emitting control terminal EM2, the first third node N13 and the first pole of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first third node N13 and the first pole of the first light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0265] The second first light-emitting control circuit 521 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the second second node N22, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second second node N22 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0266] The second second light-emitting control circuit 522 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E2 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0267] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit 61, a second initialization circuit 62, a first energy storage circuit 71, and a second energy storage circuit 72;

[0268] The first initialization circuit 61 is electrically connected to the initial control terminal R0, the second initial voltage terminal I2 and the first pole of the first light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the first light-emitting element E1 under the control of the initial control signal provided by the initial control terminal R0.

[0269] The second initialization circuit 62 is electrically connected to the initial control terminal R0, the third initial voltage terminal I3 and the first pole of the second light-emitting element E2, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the second light-emitting element E2 under the control of the initial control signal provided by the initial control terminal R0.

[0270] The first energy storage circuit 71 is electrically connected to the first node N11 and is used to maintain the potential of the first node N11;

[0271] The second energy storage circuit 72 is electrically connected to the second first node N21 and is used to maintain the potential of the second first node N21.

[0272] As shown in Figure 14, based on at least one embodiment of the pixel circuit shown in Figure 4,

[0273] The pixel circuit described in at least one embodiment of this disclosure further includes a first data writing circuit 41 and a second data writing circuit 42;

[0274] The first data writing circuit 41 is electrically connected to the scanning end GT, the first data line DL1 and the first second node N12 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first second node N12 under the control of the scanning signal provided by the scanning end GT.

[0275] The second data writing circuit 42 is electrically connected to the scanning end GT, the second data line DL2 and the second second node N22 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second second node N22 under the control of the scanning signal provided by the scanning end GT.

[0276] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit 511, a first second light-emitting control circuit 512, a second first light-emitting control circuit 521, and a second second light-emitting control circuit 522;

[0277] The first light-emitting control circuit 511 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the first second node N12, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first second node V12 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0278] The first second light-emitting control circuit 512 is electrically connected to the second light-emitting control terminal EM2, the first third node N13 and the first pole of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first third node N13 and the first pole of the first light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0279] The second first light-emitting control circuit 521 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the second second node N22, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second second node N22 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0280] The second second light-emitting control circuit 522 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E2 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0281] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit 61, a second initialization circuit 62, a first energy storage circuit 71, and a second energy storage circuit 72;

[0282] The first initialization circuit 61 is electrically connected to the initial control terminal R0, the second initial voltage terminal I2 and the first pole of the first light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the first light-emitting element E1 under the control of the initial control signal provided by the initial control terminal R0.

[0283] The second initialization circuit 62 is electrically connected to the initial control terminal R0, the third initial voltage terminal I3 and the first pole of the second light-emitting element E2, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the second light-emitting element E2 under the control of the initial control signal provided by the initial control terminal R0.

[0284] The first energy storage circuit 71 is electrically connected to the first node N11 and is used to maintain the potential of the first node N11;

[0285] The second energy storage circuit 72 is electrically connected to the second first node N21 and is used to maintain the potential of the second first node N21.

[0286] As shown in Figure 15, based on at least one embodiment of the pixel circuit shown in Figure 5,

[0287] The pixel circuit described in at least one embodiment of this disclosure further includes a first data writing circuit 41 and a second data writing circuit 42;

[0288] The first data writing circuit 41 is electrically connected to the scanning end GT, the first data line DL1 and the first third node N13 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first third node N13 under the control of the scanning signal provided by the scanning end GT.

[0289] The second data writing circuit 42 is electrically connected to the scanning end GT, the second data line DL2 and the second third node N23 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second third node N23 under the control of the scanning signal provided by the scanning end GT.

[0290] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit 511, a first second light-emitting control circuit 512, a second first light-emitting control circuit 521, and a second second light-emitting control circuit 522;

[0291] The first light-emitting control circuit 511 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the first second node N12, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first second node V12 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0292] The first second light-emitting control circuit 512 is electrically connected to the second light-emitting control terminal EM2, the first third node N13 and the first pole of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first third node N13 and the first pole of the first light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0293] The second first light-emitting control circuit 521 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the second second node N22, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second second node N22 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0294] The second second light-emitting control circuit 522 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E2 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0295] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit 61, a second initialization circuit 62, a first energy storage circuit 71, and a second energy storage circuit 72;

[0296] The first initialization circuit 61 is electrically connected to the initial control terminal R0, the second initial voltage terminal I2 and the first pole of the first light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the first light-emitting element E1 under the control of the initial control signal provided by the initial control terminal R0.

[0297] The second initialization circuit 62 is electrically connected to the initial control terminal R0, the third initial voltage terminal I3 and the first pole of the second light-emitting element E2, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the second light-emitting element E2 under the control of the initial control signal provided by the initial control terminal R0.

[0298] The first energy storage circuit 71 is electrically connected to the first node N11 and is used to maintain the potential of the first node N11;

[0299] The second energy storage circuit 72 is electrically connected to the second first node N21 and is used to maintain the potential of the second first node N21.

[0300] As shown in Figure 16, based on at least one embodiment of the pixel circuit shown in Figure 6,

[0301] The pixel circuit described in at least one embodiment of this disclosure further includes a first data writing circuit 41 and a second data writing circuit 42;

[0302] The first data writing circuit 41 is electrically connected to the scanning end GT, the first data line DL1 and the first second node N12 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first second node N12 under the control of the scanning signal provided by the scanning end GT.

[0303] The second data writing circuit 42 is electrically connected to the scanning end GT, the second data line DL2 and the second second node N22 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second second node N22 under the control of the scanning signal provided by the scanning end GT.

[0304] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit 511, a first second light-emitting control circuit 512, a second first light-emitting control circuit 521, and a second second light-emitting control circuit 522;

[0305] The first light-emitting control circuit 511 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the first second node N12, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first second node V12 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0306] The first second light-emitting control circuit 512 is electrically connected to the second light-emitting control terminal EM2, the first third node N13 and the first pole of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first third node N13 and the first pole of the first light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0307] The second first light-emitting control circuit 521 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the second second node N22, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second second node N22 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0308] The second second light-emitting control circuit 522 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E2 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0309] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit 61, a second initialization circuit 62, a first energy storage circuit 71, and a second energy storage circuit 72;

[0310] The first initialization circuit 61 is electrically connected to the initial control terminal R0, the second initial voltage terminal I2 and the first pole of the first light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the first light-emitting element E1 under the control of the initial control signal provided by the initial control terminal R0.

[0311] The second initialization circuit 62 is electrically connected to the initial control terminal R0, the third initial voltage terminal I3 and the first pole of the second light-emitting element E2, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the second light-emitting element E2 under the control of the initial control signal provided by the initial control terminal R0.

[0312] The first energy storage circuit 71 is electrically connected to the first node N11 and is used to maintain the potential of the first node N11;

[0313] The second energy storage circuit 72 is electrically connected to the second first node N21 and is used to maintain the potential of the second first node N21.

[0314] As shown in Figure 17, based on at least one embodiment of the pixel circuit shown in Figure 7,

[0315] The pixel circuit described in at least one embodiment of this disclosure further includes a first data writing circuit 41 and a second data writing circuit 42;

[0316] The first data writing circuit 41 is electrically connected to the scanning end GT, the first data line DL1 and the first third node N13 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first third node N13 under the control of the scanning signal provided by the scanning end GT.

[0317] The second data writing circuit 42 is electrically connected to the scanning end GT, the second data line DL2 and the second third node N23 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second third node N23 under the control of the scanning signal provided by the scanning end GT.

[0318] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit 511, a first second light-emitting control circuit 512, a second first light-emitting control circuit 521, and a second second light-emitting control circuit 522;

[0319] The first light-emitting control circuit 511 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the first second node N12, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first second node V12 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0320] The first second light-emitting control circuit 512 is electrically connected to the second light-emitting control terminal EM2, the first third node N13 and the first pole of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first third node N13 and the first pole of the first light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0321] The second first light-emitting control circuit 521 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the second second node N22, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second second node N22 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0322] The second second light-emitting control circuit 522 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E2 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0323] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit 61, a second initialization circuit 62, a first energy storage circuit 71, and a second energy storage circuit 72;

[0324] The first initialization circuit 61 is electrically connected to the initial control terminal R0, the second initial voltage terminal I2 and the first pole of the first light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the first light-emitting element E1 under the control of the initial control signal provided by the initial control terminal R0.

[0325] The second initialization circuit 62 is electrically connected to the initial control terminal R0, the third initial voltage terminal I3 and the first pole of the second light-emitting element E2, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the second light-emitting element E2 under the control of the initial control signal provided by the initial control terminal R0.

[0326] The first energy storage circuit 71 is electrically connected to the first node N11 and is used to maintain the potential of the first node N11;

[0327] The second energy storage circuit 72 is electrically connected to the second first node N21 and is used to maintain the potential of the second first node N21.

[0328] As shown in Figure 18, based on at least one embodiment of the pixel circuit shown in Figure 8,

[0329] The pixel circuit described in at least one embodiment of this disclosure further includes a first data writing circuit 41 and a second data writing circuit 42;

[0330] The first data writing circuit 41 is electrically connected to the scanning end GT, the first data line DL1 and the first second node N12 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first second node N12 under the control of the scanning signal provided by the scanning end GT.

[0331] The second data writing circuit 42 is electrically connected to the scanning end GT, the second data line DL2 and the second second node N22 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second second node N22 under the control of the scanning signal provided by the scanning end GT.

[0332] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit 511, a first second light-emitting control circuit 512, a second first light-emitting control circuit 521, and a second second light-emitting control circuit 522;

[0333] The first light-emitting control circuit 511 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the first second node N12, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first second node V12 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0334] The first second light-emitting control circuit 512 is electrically connected to the second light-emitting control terminal EM2, the first third node N13 and the first pole of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first third node N13 and the first pole of the first light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0335] The second first light-emitting control circuit 521 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the second second node N22, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second second node N22 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0336] The second second light-emitting control circuit 522 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E2 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0337] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit 61, a second initialization circuit 62, a first energy storage circuit 71, and a second energy storage circuit 72;

[0338] The first initialization circuit 61 is electrically connected to the initial control terminal R0, the second initial voltage terminal I2 and the first pole of the first light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the first light-emitting element E1 under the control of the initial control signal provided by the initial control terminal R0.

[0339] The second initialization circuit 62 is electrically connected to the initial control terminal R0, the third initial voltage terminal I3 and the first pole of the second light-emitting element E2, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the second light-emitting element E2 under the control of the initial control signal provided by the initial control terminal R0.

[0340] The first energy storage circuit 71 is electrically connected to the first node N11 and is used to maintain the potential of the first node N11;

[0341] The second energy storage circuit 72 is electrically connected to the second first node N21 and is used to maintain the potential of the second first node N21.

[0342] As shown in Figure 19, based on at least one embodiment of the pixel circuit shown in Figure 9,

[0343] The pixel circuit described in at least one embodiment of this disclosure further includes a first data writing circuit 41 and a second data writing circuit 42;

[0344] The first data writing circuit 41 is electrically connected to the scanning end GT, the first data line DL1 and the first third node N13 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first third node N13 under the control of the scanning signal provided by the scanning end GT.

[0345] The second data writing circuit 42 is electrically connected to the scanning end GT, the second data line DL2 and the second third node N23 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second third node N23 under the control of the scanning signal provided by the scanning end GT.

[0346] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit 511, a first second light-emitting control circuit 512, a second first light-emitting control circuit 521, and a second second light-emitting control circuit 522;

[0347] The first light-emitting control circuit 511 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the first second node N12, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first second node V12 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0348] The first second light-emitting control circuit 512 is electrically connected to the second light-emitting control terminal EM2, the first third node N13 and the first pole of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first third node N13 and the first pole of the first light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0349] The second first light-emitting control circuit 521 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the second second node N22, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second second node N22 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0350] The second second light-emitting control circuit 522 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E2 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0351] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit 61, a second initialization circuit 62, a first energy storage circuit 71, and a second energy storage circuit 72;

[0352] The first initialization circuit 61 is electrically connected to the initial control terminal R0, the second initial voltage terminal I2 and the first pole of the first light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the first light-emitting element E1 under the control of the initial control signal provided by the initial control terminal R0.

[0353] The second initialization circuit 62 is electrically connected to the initial control terminal R0, the third initial voltage terminal I3 and the first pole of the second light-emitting element E2, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the second light-emitting element E2 under the control of the initial control signal provided by the initial control terminal R0.

[0354] The first energy storage circuit 71 is electrically connected to the first node N11 and is used to maintain the potential of the first node N11;

[0355] The second energy storage circuit 72 is electrically connected to the second first node N21 and is used to maintain the potential of the second first node N21.

[0356] As shown in Figure 20, based on at least one embodiment of the pixel circuit shown in Figure 10,

[0357] The pixel circuit described in at least one embodiment of this disclosure further includes a first data writing circuit 41 and a second data writing circuit 42;

[0358] The first data writing circuit 41 is electrically connected to the scanning end GT, the first data line DL1 and the first second node N12 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first second node N12 under the control of the scanning signal provided by the scanning end GT.

[0359] The second data writing circuit 42 is electrically connected to the scanning end GT, the second data line DL2 and the second second node N22 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second second node N22 under the control of the scanning signal provided by the scanning end GT.

[0360] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit 511, a first second light-emitting control circuit 512, a second first light-emitting control circuit 521, and a second second light-emitting control circuit 522;

[0361] The first light-emitting control circuit 511 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the first second node N12, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first second node V12 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0362] The first second light-emitting control circuit 512 is electrically connected to the second light-emitting control terminal EM2, the first third node N13 and the first pole of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first third node N13 and the first pole of the first light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0363] The second first light-emitting control circuit 521 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the second second node N22, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second second node N22 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0364] The second second light-emitting control circuit 522 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E2 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0365] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit 61, a second initialization circuit 62, a first energy storage circuit 71, and a second energy storage circuit 72;

[0366] The first initialization circuit 61 is electrically connected to the initial control terminal R0, the second initial voltage terminal I2 and the first pole of the first light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the first light-emitting element E1 under the control of the initial control signal provided by the initial control terminal R0.

[0367] The second initialization circuit 62 is electrically connected to the initial control terminal R0, the third initial voltage terminal I3 and the first pole of the second light-emitting element E2, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the second light-emitting element E2 under the control of the initial control signal provided by the initial control terminal R0.

[0368] The first energy storage circuit 71 is electrically connected to the first node N11 and is used to maintain the potential of the first node N11;

[0369] The second energy storage circuit 72 is electrically connected to the second first node N21 and is used to maintain the potential of the second first node N21.

[0370] As shown in Figure 21, based on at least one embodiment of the pixel circuit shown in Figure 11,

[0371] The pixel circuit described in at least one embodiment of this disclosure further includes a first data writing circuit 41 and a second data writing circuit 42;

[0372] The first data writing circuit 41 is electrically connected to the scanning end GT, the first data line DL1 and the first third node N13 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first third node N13 under the control of the scanning signal provided by the scanning end GT.

[0373] The second data writing circuit 42 is electrically connected to the scanning end GT, the second data line DL2 and the second third node N23 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second third node N23 under the control of the scanning signal provided by the scanning end GT.

[0374] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit 511, a first second light-emitting control circuit 512, a second first light-emitting control circuit 521, and a second second light-emitting control circuit 522;

[0375] The first light-emitting control circuit 511 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the first second node N12, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first second node V12 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0376] The first second light-emitting control circuit 512 is electrically connected to the second light-emitting control terminal EM2, the first third node N13 and the first pole of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first third node N13 and the first pole of the first light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0377] The second first light-emitting control circuit 521 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the second second node N22, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second second node N22 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0378] The second second light-emitting control circuit 522 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E2 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0379] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit 61, a second initialization circuit 62, a first energy storage circuit 71, and a second energy storage circuit 72;

[0380] The first initialization circuit 61 is electrically connected to the initial control terminal R0, the second initial voltage terminal I2 and the first pole of the first light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the first light-emitting element E1 under the control of the initial control signal provided by the initial control terminal R0.

[0381] The second initialization circuit 62 is electrically connected to the initial control terminal R0, the third initial voltage terminal I3 and the first pole of the second light-emitting element E2, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the second light-emitting element E2 under the control of the initial control signal provided by the initial control terminal R0.

[0382] The first energy storage circuit 71 is electrically connected to the first node N11 and is used to maintain the potential of the first node N11;

[0383] The second energy storage circuit 72 is electrically connected to the second first node N21 and is used to maintain the potential of the second first node N21.

[0384] As shown in Figure 22, based on at least one embodiment of the pixel circuit shown in Figure 12,

[0385] The pixel circuit described in at least one embodiment of this disclosure further includes a first data writing circuit 41 and a second data writing circuit 42;

[0386] The first data writing circuit 41 is electrically connected to the scanning end GT, the first data line DL1 and the first third node N13 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first third node N13 under the control of the scanning signal provided by the scanning end GT.

[0387] The second data writing circuit 42 is electrically connected to the scanning end GT, the second data line DL2 and the second third node N23 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second third node N23 under the control of the scanning signal provided by the scanning end GT.

[0388] The pixel circuit described in at least one embodiment of this disclosure further includes a first first light-emitting control circuit 511, a first second light-emitting control circuit 512, a second first light-emitting control circuit 521, and a second second light-emitting control circuit 522;

[0389] The first light-emitting control circuit 511 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the first second node N12, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first second node V12 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0390] The first second light-emitting control circuit 512 is electrically connected to the second light-emitting control terminal EM2, the first third node N13 and the first pole of the first light-emitting element E1, respectively, and is used to control the connection or disconnection between the first third node N13 and the first pole of the first light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0391] The second first light-emitting control circuit 521 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal VDD, and the second second node N22, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second second node N22 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0392] The second second light-emitting control circuit 522 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E2 respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E2 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0393] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit 61, a second initialization circuit 62, a first energy storage circuit 71, and a second energy storage circuit 72;

[0394] The first initialization circuit 61 is electrically connected to the initial control terminal R0, the second initial voltage terminal I2 and the first pole of the first light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the first light-emitting element E1 under the control of the initial control signal provided by the initial control terminal R0.

[0395] The second initialization circuit 62 is electrically connected to the initial control terminal R0, the third initial voltage terminal I3 and the first pole of the second light-emitting element E2, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the second light-emitting element E2 under the control of the initial control signal provided by the initial control terminal R0.

[0396] The first energy storage circuit 71 is electrically connected to the first node N11 and is used to maintain the potential of the first node N11;

[0397] The second energy storage circuit 72 is electrically connected to the second first node N21 and is used to maintain the potential of the second first node N21.

[0398] Optionally, the first driving circuit includes a first driving transistor, the second driving circuit includes a second driving transistor, the first compensation control circuit includes a first transistor, the second compensation control circuit includes a second transistor, and the first on / off control circuit includes a third transistor.

[0399] The gate of the first driving transistor is electrically connected to the first first node, the first electrode of the first driving transistor is electrically connected to the first second node, and the second electrode of the first driving transistor is electrically connected to the first third node.

[0400] The gate of the second driving transistor is electrically connected to the second first node, the first terminal of the second driving transistor is electrically connected to the second second node, and the second terminal of the second driving transistor is electrically connected to the second third node.

[0401] The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the first first node, and the second electrode of the first transistor is electrically connected to the first control node.

[0402] The gate of the second transistor is electrically connected to the compensation control terminal, the first terminal of the second transistor is electrically connected to the second first node, and the second terminal of the second transistor is electrically connected to the second control node.

[0403] The gate of the third transistor is electrically connected to the first on / off control terminal, the first electrode of the third transistor is electrically connected to the first control node, and the second electrode of the third transistor is electrically connected to the second control node.

[0404] Optionally, the first reset circuit includes a fourth transistor, and the second reset circuit includes a fifth transistor;

[0405] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the reference voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first second node.

[0406] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second control node.

[0407] Optionally, the first reset circuit includes a fourth transistor, and the second reset circuit includes a fifth transistor;

[0408] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the reference voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second second node.

[0409] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the first control node.

[0410] Optionally, the first reset circuit includes a fourth transistor, and the second reset circuit includes a fifth transistor;

[0411] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the reference voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first second node.

[0412] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the first control node.

[0413] Optionally, the first reset circuit includes a fourth transistor, and the second reset circuit includes a fifth transistor;

[0414] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the reference voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second second node.

[0415] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second control node.

[0416] Optionally, the first reset circuit includes a fourth transistor, and the second reset circuit includes a fifth transistor;

[0417] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the reference voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second second node.

[0418] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the first second node.

[0419] Optionally, the second on / off control circuit includes a sixth transistor;

[0420] The gate of the sixth transistor is electrically connected to the second on / off control terminal, the first terminal of the sixth transistor is electrically connected to the first second node, and the second terminal of the sixth transistor is electrically connected to the second second node.

[0421] Optionally, the first reset circuit includes a fourth transistor, the second reset circuit includes a fifth transistor, and the third reset circuit includes a seventh transistor;

[0422] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the reference voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first second node.

[0423] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second second node.

[0424] The gate of the seventh transistor is electrically connected to the first reset control terminal, the first terminal of the seventh transistor is electrically connected to the reference voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second second node.

[0425] Optionally, the first data writing circuit includes an eighth transistor, and the second data writing circuit includes a ninth transistor;

[0426] The gate of the eighth transistor is electrically connected to the scan terminal, the first terminal of the eighth transistor is electrically connected to the first data line, and the second terminal of the eighth transistor is electrically connected to the first third node.

[0427] The gate of the ninth transistor is electrically connected to the scan terminal, the first terminal of the ninth transistor is electrically connected to the second data line, and the second terminal of the ninth transistor is electrically connected to the second third node.

[0428] Optionally, the first data writing circuit includes an eighth transistor, and the second data writing circuit includes a ninth transistor;

[0429] The gate of the eighth transistor is electrically connected to the scan terminal, the first terminal of the eighth transistor is electrically connected to the first data line, and the second terminal of the eighth transistor is electrically connected to the first second node.

[0430] The gate of the ninth transistor is electrically connected to the scan terminal, the first terminal of the ninth transistor is electrically connected to the second data line, and the second terminal of the ninth transistor is electrically connected to the second second node.

[0431] Optionally, the first first light-emitting control circuit includes a tenth transistor, the first second light-emitting control circuit includes an eleventh transistor, the second first light-emitting control circuit includes a twelfth transistor, and the second second light-emitting control circuit includes a thirteenth transistor;

[0432] The gate of the tenth transistor is electrically connected to the first light-emitting control terminal, the first terminal of the tenth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the tenth transistor is electrically connected to the first second node.

[0433] The gate of the eleventh transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eleventh transistor is electrically connected to the first third node, and the second terminal of the eleventh transistor is electrically connected to the first terminal of the first light-emitting element.

[0434] The gate of the twelfth transistor is electrically connected to the first light-emitting control terminal, the first terminal of the twelfth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the twelfth transistor is electrically connected to the second second node.

[0435] The gate of the thirteenth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the thirteenth transistor is electrically connected to the second third node, and the second terminal of the thirteenth transistor is electrically connected to the first terminal of the second light-emitting element.

[0436] Optionally, the first initialization circuit includes a fourteenth transistor, the second initialization circuit includes a fifteenth transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor.

[0437] The gate of the fourteenth transistor is electrically connected to the initial control terminal, the first terminal of the fourteenth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the first light-emitting element.

[0438] The gate of the fifteenth transistor is electrically connected to the initial control terminal, the first terminal of the fifteenth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the fifteenth transistor is electrically connected to the first terminal of the second light-emitting element.

[0439] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the first DC voltage terminal.

[0440] The first terminal of the second capacitor is electrically connected to the second first node, and the second terminal of the second capacitor is electrically connected to the second DC voltage terminal.

[0441] Optionally, the first DC voltage terminal and the second DC voltage terminal can be power supply voltage terminals.

[0442] In at least one embodiment of this disclosure, the second reset control terminal and the initial control terminal can be the same control terminal to reduce the number of control terminals used.

[0443] As shown in Figure 23, based on at least one embodiment of the pixel circuit shown in Figure 13, the first light-emitting element is a first organic light-emitting diode O1, and the second light-emitting element is a second organic light-emitting diode O2;

[0444] The first driving circuit includes a first driving transistor DT1, the second driving circuit includes a second driving transistor DT2, the first compensation control circuit includes a first transistor T1, the second compensation control circuit includes a second transistor T2, and the first on / off control circuit includes a third transistor T3.

[0445] The gate of the first driving transistor DT1 is electrically connected to the first first node N11, the source of the first driving transistor DT1 is electrically connected to the first second node N12, and the drain of the first driving transistor DT1 is electrically connected to the first third node N13.

[0446] The gate of the second driving transistor DT2 is electrically connected to the second first node N21, the source of the second driving transistor DT2 is electrically connected to the second second node N22, and the drain of the second driving transistor DT2 is electrically connected to the second third node N23.

[0447] The gate of the first transistor T1 is electrically connected to the compensation control terminal GN, the source of the first transistor T1 is electrically connected to the first node N11, and the drain of the first transistor T1 is electrically connected to the first node N12.

[0448] The gate of the second transistor T2 is electrically connected to the compensation control terminal GN, the source of the second transistor T2 is electrically connected to the second first node N21, and the drain of the second transistor T2 is electrically connected to the second second node N22.

[0449] The gate of the third transistor T3 is electrically connected to the first on / off control terminal ST1, the source of the third transistor T3 is electrically connected to the first first node N11, and the drain of the third transistor T3 is electrically connected to the second first node N21.

[0450] The first reset circuit includes a fourth transistor T4, and the second reset circuit includes a fifth transistor T5;

[0451] The gate of the fourth transistor T4 is electrically connected to the first reset control terminal R1, the source of the fourth transistor T4 is electrically connected to the reference voltage terminal REF, and the drain of the fourth transistor T4 is electrically connected to the first second node N12.

[0452] The gate of the fifth transistor T5 is electrically connected to the initial control terminal R0, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the second node N22.

[0453] The second on / off control circuit includes a sixth transistor T6;

[0454] The gate of the sixth transistor T6 is electrically connected to the second on / off control terminal ST2, the source of the sixth transistor T6 is electrically connected to the first second node N12, and the drain of the sixth transistor T6 is electrically connected to the second second node N22.

[0455] The first data writing circuit includes an eighth transistor T8, and the second data writing circuit includes a ninth transistor T9;

[0456] The gate of the eighth transistor T8 is electrically connected to the scan terminal GT, the source of the eighth transistor T8 is electrically connected to the first data line DL1, and the drain of the eighth transistor T8 is electrically connected to the first third node N13.

[0457] The gate of the ninth transistor T9 is electrically connected to the scan terminal GT, the source of the ninth transistor T9 is electrically connected to the second data line DL2, and the drain of the ninth transistor T9 is electrically connected to the second third node N23.

[0458] The first first light-emitting control circuit includes a tenth transistor T10, the first second light-emitting control circuit includes an eleventh transistor T11, the second first light-emitting control circuit includes a twelfth transistor T12, and the second second light-emitting control circuit includes a thirteenth transistor T13.

[0459] The gate of the tenth transistor T10 is electrically connected to the first light-emitting control terminal EM1, the source of the tenth transistor T10 is electrically connected to the power supply voltage terminal VDD, and the drain of the tenth transistor T10 is electrically connected to the first second node N12.

[0460] The gate of the eleventh transistor T11 is electrically connected to the second light-emitting control terminal EM2, the source of the eleventh transistor T11 is electrically connected to the first third node N13, the drain of the eleventh transistor T11 is electrically connected to the anode of the first organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0461] The gate of the twelfth transistor T12 is electrically connected to the first light-emitting control terminal EM1, the source of the twelfth transistor T12 is electrically connected to the power supply voltage terminal VDD, and the drain of the twelfth transistor T12 is electrically connected to the second node N22.

[0462] The gate of the thirteenth transistor T13 is electrically connected to the second light-emitting control terminal EM2, the source of the thirteenth transistor T13 is electrically connected to the second third node N23, the drain of the thirteenth transistor T13 is electrically connected to the anode of the second organic light-emitting diode O2, and the cathode of O2 is electrically connected to the low voltage terminal VSS.

[0463] The first initialization circuit includes a fourteenth transistor T14, the second initialization circuit includes a fifteenth transistor T15, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.

[0464] The gate of the fourteenth transistor T14 is electrically connected to the initial control terminal R0, the source of the fourteenth transistor T14 is electrically connected to the second initial voltage terminal I2, and the drain of the fourteenth transistor T14 is electrically connected to the anode of O1.

[0465] The gate of the fifteenth transistor T15 is electrically connected to the initial control terminal R0, the source of the fifteenth transistor T15 is electrically connected to the second initial voltage terminal I2, and the drain of the fifteenth transistor T15 is electrically connected to the anode of O2.

[0466] The first terminal of the first capacitor C1 is electrically connected to the first node N11, and the second terminal of the first capacitor C1 is electrically connected to the power supply voltage terminal VDD.

[0467] The first end of the second capacitor C2 is electrically connected to the second first node N21, and the second end of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD.

[0468] In at least one embodiment of the pixel circuit shown in Figure 23, T1, T2, T3 and T6 are oxide transistors, and the other transistors are low-temperature polysilicon transistors.

[0469] T1, T2, T3, and T6 are n-type transistors, while the other transistors are p-type transistors.

[0470] In Figure 23, the node labeled N4 is the fourth node, and N4 is electrically connected to the anode of O1.

[0471] As shown in FIG24, when at least one embodiment of the pixel circuit shown in FIG23 of this disclosure is in operation, the display cycle may include a reset stage S1, a compensation stage S2, a bias stage S3 and a light emission stage S4 set sequentially.

[0472] During the reset phase S1, EM1 and EM2 provide high voltage signals, ST1 provides a high voltage signal, GN provides a high voltage signal, R0 provides a low voltage signal, GT provides a high voltage signal, ST2 provides a low voltage signal, R1 provides a high voltage signal, T3 is turned on, controlling the connection between N11 and N21, T1 and T2 are turned on, T5 is turned on, I1 provides a first initial voltage Vinit1 to N11 and N21 to reset the gates of DT1 and DT2; simultaneously, T14 and T15 are turned on, I2 provides a second initial voltage Vinit2 to the anodes of O1 and O2 to clear the residual charge on the anodes of O1 and O2;

[0473] During compensation phase S2, EM1 and EM2 provide high voltage signals, ST1 provides a low voltage signal, GN provides a high voltage signal, R0 provides a high voltage signal, GT provides a low voltage signal, ST2 provides a low voltage signal, R1 provides a high voltage signal, T8 and T9 are turned on, DL1 provides the first data voltage Vdata1 to N13, and DL2 provides the second data voltage Vdata2 to N23; T1 and T2 are turned on, connecting N11 and N12, and connecting N21 and N22.

[0474] At the start of the compensation phase S2, DT1 and DT2 are turned on, charging C1 through Vdata1 and changing the potential of N11 until DT1 is turned off; charging C2 through Vdata2 and changing the potential of N21 until DT2 is turned off.

[0475] During the biasing phase S3, EM1 and EM2 provide high voltage signals, ST1 provides a low voltage signal, GN provides a low voltage signal, R0 provides a high voltage signal, GT provides a high voltage signal, ST2 provides a high voltage signal, R1 provides a low voltage signal, T6 is turned on, T4 is turned on, and REF provides a reference voltage Vref to N12 and N22, so that DT1 and DT2 are in the biased state, improving the hysteresis of DT1 and improving the hysteresis of DT2.

[0476] During the light emission stage S4, EM1 and EM2 provide low voltage signals, ST1 provides low voltage signals, GN provides low voltage signals, R0 provides high voltage signals, GT provides high voltage signals, ST2 provides low voltage signals, R1 provides high voltage signals, T10, T11, T12, and T13 are all turned on, DT1 drives O1 to emit light, and DT2 drives O2 to emit light.

[0477] When at least one embodiment of the pixel circuit shown in FIG23 of this disclosure operates at low frequency, the refresh frame operation process corresponds to the timing sequence corresponding to FIG24.

[0478] During the hold frame, EM1, EM2, and R0 output normal signals, while other control terminals provide invalid voltage signals.

[0479] As shown in Figure 25, based on at least one embodiment of the pixel circuit shown in Figure 14, the first light-emitting element is a first organic light-emitting diode O1, and the second light-emitting element is a second organic light-emitting diode O2;

[0480] The first driving circuit includes a first driving transistor DT1, the second driving circuit includes a second driving transistor DT2, the first compensation control circuit includes a first transistor T1, the second compensation control circuit includes a second transistor T2, and the first on / off control circuit includes a third transistor T3.

[0481] The gate of the first driving transistor DT1 is electrically connected to the first first node N11, the source of the first driving transistor DT1 is electrically connected to the first second node N12, and the drain of the first driving transistor DT1 is electrically connected to the first third node N13.

[0482] The gate of the second driving transistor DT2 is electrically connected to the second first node N21, the source of the second driving transistor DT2 is electrically connected to the second second node N22, and the drain of the second driving transistor DT2 is electrically connected to the second third node N23.

[0483] The gate of the first transistor T1 is electrically connected to the compensation control terminal GN, the source of the first transistor T1 is electrically connected to the first first node N11, and the drain of the first transistor T1 is electrically connected to the first third node N13.

[0484] The gate of the second transistor T2 is electrically connected to the compensation control terminal GN, the source of the second transistor T2 is electrically connected to the second first node N21, and the drain of the second transistor T2 is electrically connected to the second third node N23.

[0485] The gate of the third transistor T3 is electrically connected to the first on / off control terminal ST1, the source of the third transistor T3 is electrically connected to the first first node N11, and the drain of the third transistor T3 is electrically connected to the second first node N21.

[0486] The first reset circuit includes a fourth transistor T4, and the second reset circuit includes a fifth transistor T5;

[0487] The gate of the fourth transistor T4 is electrically connected to the first reset control terminal R1, the source of the fourth transistor T4 is electrically connected to the reference voltage terminal REF, and the drain of the fourth transistor T4 is electrically connected to the first second node N12.

[0488] The gate of the fifth transistor T5 is electrically connected to the initial control terminal R0, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the second third node N23.

[0489] The second on / off control circuit includes a sixth transistor T6;

[0490] The gate of the sixth transistor T6 is electrically connected to the second on / off control terminal ST2, the source of the sixth transistor T6 is electrically connected to the first second node N12, and the drain of the sixth transistor T6 is electrically connected to the second second node N22.

[0491] The first data writing circuit includes an eighth transistor T8, and the second data writing circuit includes a ninth transistor T9;

[0492] The gate of the eighth transistor T8 is electrically connected to the scan terminal GT, the source of the eighth transistor T8 is electrically connected to the first data line DL1, and the drain of the eighth transistor T8 is electrically connected to the first second node N12.

[0493] The gate of the ninth transistor T9 is electrically connected to the scan terminal GT, the source of the ninth transistor T9 is electrically connected to the second data line DL2, and the drain of the ninth transistor T9 is electrically connected to the second node N22.

[0494] The first first light-emitting control circuit includes a tenth transistor T10, the first second light-emitting control circuit includes an eleventh transistor T11, the second first light-emitting control circuit includes a twelfth transistor T12, and the second second light-emitting control circuit includes a thirteenth transistor T13.

[0495] The gate of the tenth transistor T10 is electrically connected to the first light-emitting control terminal EM1, the source of the tenth transistor T10 is electrically connected to the power supply voltage terminal VDD, and the drain of the tenth transistor T10 is electrically connected to the first second node N12.

[0496] The gate of the eleventh transistor T11 is electrically connected to the second light-emitting control terminal EM2, the source of the eleventh transistor T11 is electrically connected to the first third node N13, the drain of the eleventh transistor T11 is electrically connected to the anode of the first organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0497] The gate of the twelfth transistor T12 is electrically connected to the first light-emitting control terminal EM1, the source of the twelfth transistor T12 is electrically connected to the power supply voltage terminal VDD, and the drain of the twelfth transistor T12 is electrically connected to the second node N22.

[0498] The gate of the thirteenth transistor T13 is electrically connected to the second light-emitting control terminal EM2, the source of the thirteenth transistor T13 is electrically connected to the second third node N23, the drain of the thirteenth transistor T13 is electrically connected to the anode of the second organic light-emitting diode O2, and the cathode of O2 is electrically connected to the low voltage terminal VSS.

[0499] The first initialization circuit includes a fourteenth transistor T14, the second initialization circuit includes a fifteenth transistor T15, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.

[0500] The gate of the fourteenth transistor T14 is electrically connected to the initial control terminal R0, the source of the fourteenth transistor T14 is electrically connected to the second initial voltage terminal I2, and the drain of the fourteenth transistor T14 is electrically connected to the anode of O1.

[0501] The gate of the fifteenth transistor T15 is electrically connected to the initial control terminal R0, the source of the fifteenth transistor T15 is electrically connected to the second initial voltage terminal I2, and the drain of the fifteenth transistor T15 is electrically connected to the anode of O2.

[0502] The first terminal of the first capacitor C1 is electrically connected to the first node N11, and the second terminal of the first capacitor C1 is electrically connected to the power supply voltage terminal VDD.

[0503] The first end of the second capacitor C2 is electrically connected to the second first node N21, and the second end of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD.

[0504] In at least one embodiment of the pixel circuit shown in Figure 25, T1, T2, T3 and T6 are oxide transistors, and the other transistors are low-temperature polysilicon transistors.

[0505] T1, T2, T3, and T6 are n-type transistors, while the other transistors are p-type transistors.

[0506] As shown in FIG26, when at least one embodiment of the pixel circuit shown in FIG25 of this disclosure is in operation, the display cycle may include a reset stage S1, a compensation stage S2, a bias stage S3 and a light emission stage S4 that are set sequentially.

[0507] During the reset phase S1, EM1 and EM2 provide high voltage signals, ST1 provides a high voltage signal, GN provides a high voltage signal, R0 provides a low voltage signal, GT provides a high voltage signal, ST2 provides a low voltage signal, R1 provides a high voltage signal, T3 is turned on, controlling the connection between N11 and N21, T1 and T2 are turned on, T5 is turned on, I1 provides a first initial voltage Vinit1 to N11 and N21 to reset the gates of DT1 and DT2; simultaneously, T14 and T15 are turned on, I2 provides a second initial voltage Vinit2 to the anodes of O1 and O2 to clear the residual charge on the anodes of O1 and O2;

[0508] During compensation phase S2, EM1 and EM2 provide high voltage signals, ST1 provides a low voltage signal, GN provides a high voltage signal, R0 provides a high voltage signal, GT provides a low voltage signal, ST2 provides a low voltage signal, R1 provides a high voltage signal, T8 and T9 are turned on, DL1 provides the first data voltage Vdata1 to N12, and DL2 provides the second data voltage Vdata2 to N22; T1 and T2 are turned on, connecting N11 and N13, and connecting N21 and N23.

[0509] At the start of the compensation phase S2, DT1 and DT2 are turned on, charging C1 through Vdata1 and changing the potential of N11 until DT1 is turned off; charging C2 through Vdata2 and changing the potential of N21 until DT2 is turned off.

[0510] During the biasing phase S3, EM1 and EM2 provide high voltage signals, ST1 provides a low voltage signal, GN provides a low voltage signal, R0 provides a high voltage signal, GT provides a high voltage signal, ST2 provides a high voltage signal, R1 provides a low voltage signal, T6 is turned on, T4 is turned on, and REF provides a reference voltage Vref to N12 and N22, so that DT1 and DT2 are in the biased state, improving the hysteresis of DT1 and improving the hysteresis of DT2.

[0511] During the light emission stage S4, EM1 and EM2 provide low voltage signals, ST1 provides low voltage signals, GN provides low voltage signals, R0 provides high voltage signals, GT provides high voltage signals, ST2 provides low voltage signals, R1 provides high voltage signals, T10, T11, T12, and T13 are all turned on, DT1 drives O1 to emit light, and DT2 drives O2 to emit light.

[0512] When at least one embodiment of the pixel circuit shown in FIG25 of this disclosure operates at a low frequency, the operation process of refreshing the frame corresponds to the timing sequence corresponding to FIG26.

[0513] During the hold frame, EM1, EM2, and R0 output normal signals, while other control terminals provide invalid voltage signals.

[0514] The differences between at least one embodiment of the pixel circuit shown in FIG. 27 of this disclosure and at least one embodiment of the pixel circuit shown in FIG. 23 of this disclosure are as follows:

[0515] The drain of T4 is electrically connected to N22;

[0516] The drain of T5 is electrically connected to N12;

[0517] As shown in FIG28, when at least one embodiment of the pixel circuit shown in FIG27 of this disclosure is in operation, the display cycle may include a reset stage S1, a compensation stage S2, a bias stage S3 and a light emission stage S4 that are set sequentially.

[0518] During the reset phase S1, EM1 and EM2 provide high voltage signals, ST1 provides a high voltage signal, GN provides a high voltage signal, R0 provides a low voltage signal, GT provides a high voltage signal, ST2 provides a low voltage signal, R1 provides a high voltage signal, T3 is turned on, controlling the connection between N11 and N21, T1 and T2 are turned on, T5 is turned on, DT1 is turned on, I1 provides a first initial voltage Vinit1 to N11 and N21 to reset the gates of DT1 and DT2; simultaneously, T14 and T15 are turned on, I2 provides a second initial voltage Vinit2 to the anodes of O1 and O2 to clear the residual charge on the anodes of O1 and O2;

[0519] During compensation phase S2, EM1 and EM2 provide high voltage signals, ST1 provides a low voltage signal, GN provides a high voltage signal, R0 provides a high voltage signal, GT provides a low voltage signal, ST2 provides a low voltage signal, R1 provides a high voltage signal, T8 and T9 are turned on, DL1 provides the first data voltage Vdata1 to N12, and DL2 provides the second data voltage Vdata2 to N22; T1 and T2 are turned on, connecting N11 and N13, and connecting N21 and N23.

[0520] At the start of the compensation phase S2, DT1 and DT2 are turned on, charging C1 through Vdata1 and changing the potential of N11 until DT1 is turned off; charging C2 through Vdata2 and changing the potential of N21 until DT2 is turned off.

[0521] During the biasing phase S3, EM1 and EM2 provide high voltage signals, ST1 provides a low voltage signal, GN provides a low voltage signal, R0 provides a high voltage signal, GT provides a high voltage signal, ST2 provides a high voltage signal, R1 provides a low voltage signal, T6 is turned on, T4 is turned on, and REF provides a reference voltage Vref to N12 and N22, so that DT1 and DT2 are in the biased state, improving the hysteresis of DT1 and improving the hysteresis of DT2.

[0522] During the light emission stage S4, EM1 and EM2 provide low voltage signals, ST1 provides low voltage signals, GN provides low voltage signals, R0 provides high voltage signals, GT provides high voltage signals, ST2 provides low voltage signals, R1 provides high voltage signals, T10, T11, T12, and T13 are all turned on, DT1 drives O1 to emit light, and DT2 drives O2 to emit light.

[0523] When at least one embodiment of the pixel circuit shown in FIG27 of this disclosure operates at low frequency, the refresh frame operation process corresponds to the timing sequence corresponding to FIG28.

[0524] During the hold frame, EM1, EM2, and R0 output normal signals, while other control terminals provide invalid voltage signals.

[0525] As shown in Figure 29, based on at least one embodiment of the pixel circuit shown in Figure 22, the first light-emitting element is a first organic light-emitting diode O1, and the second light-emitting element is a second organic light-emitting diode O2;

[0526] The first driving circuit includes a first driving transistor DT1, the second driving circuit includes a second driving transistor DT2, the first compensation control circuit includes a first transistor T1, the second compensation control circuit includes a second transistor T2, and the first on / off control circuit includes a third transistor T3.

[0527] The gate of the first driving transistor DT1 is electrically connected to the first first node N11, the source of the first driving transistor DT1 is electrically connected to the first second node N12, and the drain of the first driving transistor DT1 is electrically connected to the first third node N13.

[0528] The gate of the second driving transistor DT2 is electrically connected to the second first node N21, the source of the second driving transistor DT2 is electrically connected to the second second node N22, and the drain of the second driving transistor DT2 is electrically connected to the second third node N23.

[0529] The gate of the first transistor T1 is electrically connected to the compensation control terminal GN, the source of the first transistor T1 is electrically connected to the first node N11, and the drain of the first transistor T1 is electrically connected to the first node N12.

[0530] The gate of the second transistor T2 is electrically connected to the compensation control terminal GN, the source of the second transistor T2 is electrically connected to the second first node N21, and the drain of the second transistor T2 is electrically connected to the second second node N22.

[0531] The gate of the third transistor T3 is electrically connected to the first on / off control terminal ST1, the source of the third transistor T3 is electrically connected to the first first node N11, and the drain of the third transistor T3 is electrically connected to the second first node N21.

[0532] The first reset circuit includes a fourth transistor T4, the second reset circuit includes a fifth transistor T5, and the third reset circuit includes a seventh transistor T7;

[0533] The gate of the fourth transistor T4 is electrically connected to the first reset control terminal R1, the source of the fourth transistor T4 is electrically connected to the reference voltage terminal REF, and the drain of the fourth transistor T4 is electrically connected to the first second node N12.

[0534] The gate of the fifth transistor T5 is electrically connected to the initial control terminal R0, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the second node N22.

[0535] The gate of the seventh transistor T7 is electrically connected to the first reset control terminal R1, the source of the seventh transistor T7 is electrically connected to the reference voltage terminal REF, and the drain of the seventh transistor T7 is electrically connected to the second node N22; the second on / off control circuit includes the sixth transistor T6;

[0536] The gate of the sixth transistor T6 is electrically connected to the second on / off control terminal ST2, the source of the sixth transistor T6 is electrically connected to the first second node N12, and the drain of the sixth transistor T6 is electrically connected to the second second node N22.

[0537] The first data writing circuit includes an eighth transistor T8, and the second data writing circuit includes a ninth transistor T9;

[0538] The gate of the eighth transistor T8 is electrically connected to the scan terminal GT, the source of the eighth transistor T8 is electrically connected to the first data line DL1, and the drain of the eighth transistor T8 is electrically connected to the first third node N13.

[0539] The gate of the ninth transistor T9 is electrically connected to the scan terminal GT, the source of the ninth transistor T9 is electrically connected to the second data line DL2, and the drain of the ninth transistor T9 is electrically connected to the second third node N23.

[0540] The first first light-emitting control circuit includes a tenth transistor T10, the first second light-emitting control circuit includes an eleventh transistor T11, the second first light-emitting control circuit includes a twelfth transistor T12, and the second second light-emitting control circuit includes a thirteenth transistor T13.

[0541] The gate of the tenth transistor T10 is electrically connected to the first light-emitting control terminal EM1, the source of the tenth transistor T10 is electrically connected to the power supply voltage terminal VDD, and the drain of the tenth transistor T10 is electrically connected to the first second node N12.

[0542] The gate of the eleventh transistor T11 is electrically connected to the second light-emitting control terminal EM2, the source of the eleventh transistor T11 is electrically connected to the first third node N13, the drain of the eleventh transistor T11 is electrically connected to the anode of the first organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0543] The gate of the twelfth transistor T12 is electrically connected to the first light-emitting control terminal EM1, the source of the twelfth transistor T12 is electrically connected to the power supply voltage terminal VDD, and the drain of the twelfth transistor T12 is electrically connected to the second node N22.

[0544] The gate of the thirteenth transistor T13 is electrically connected to the second light-emitting control terminal EM2, the source of the thirteenth transistor T13 is electrically connected to the second third node N23, the drain of the thirteenth transistor T13 is electrically connected to the anode of the second organic light-emitting diode O2, and the cathode of O2 is electrically connected to the low voltage terminal VSS.

[0545] The first initialization circuit includes a fourteenth transistor T14, the second initialization circuit includes a fifteenth transistor T15, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.

[0546] The gate of the fourteenth transistor T14 is electrically connected to the initial control terminal R0, the source of the fourteenth transistor T14 is electrically connected to the second initial voltage terminal I2, and the drain of the fourteenth transistor T14 is electrically connected to the anode of O1.

[0547] The gate of the fifteenth transistor T15 is electrically connected to the initial control terminal R0, the source of the fifteenth transistor T15 is electrically connected to the second initial voltage terminal I2, and the drain of the fifteenth transistor T15 is electrically connected to the anode of O2.

[0548] The first terminal of the first capacitor C1 is electrically connected to the first node N11, and the second terminal of the first capacitor C1 is electrically connected to the power supply voltage terminal VDD.

[0549] The first end of the second capacitor C2 is electrically connected to the second first node N21, and the second end of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD.

[0550] In at least one embodiment of the pixel circuit shown in Figure 29, T1, T2 and T3 are oxide transistors, and the other transistors are low-temperature polysilicon transistors.

[0551] T1, T2, and T3 are n-type transistors, while the other transistors are p-type transistors.

[0552] As shown in FIG30, when at least one embodiment of the pixel circuit shown in FIG29 of this disclosure is in operation, the display cycle may include a reset stage S1, a compensation stage S2, a bias stage S3 and a light emission stage S4 set sequentially.

[0553] During the reset phase S1, EM1 and EM2 provide high voltage signals, ST1 provides a high voltage signal, GN provides a high voltage signal, R0 provides a low voltage signal, GT provides a high voltage signal, ST2 provides a low voltage signal, R1 provides a high voltage signal, T3 is turned on, controlling the connection between N11 and N21, T1 and T2 are turned on, T5 is turned on, I1 provides a first initial voltage Vinit1 to N11 and N21 to reset the gates of DT1 and DT2; simultaneously, T14 and T15 are turned on, I2 provides a second initial voltage Vinit2 to the anodes of O1 and O2 to clear the residual charge on the anodes of O1 and O2;

[0554] During compensation phase S2, EM1 and EM2 provide high voltage signals, ST1 provides a low voltage signal, GN provides a high voltage signal, R0 provides a high voltage signal, GT provides a low voltage signal, ST2 provides a low voltage signal, R1 provides a high voltage signal, T8 and T9 are turned on, DL1 provides the first data voltage Vdata1 to N13, and DL2 provides the second data voltage Vdata2 to N23; T1 and T2 are turned on, connecting N11 and N12, and connecting N21 and N22.

[0555] At the start of the compensation phase S2, DT1 and DT2 are turned on, charging C1 through Vdata1 and changing the potential of N11 until DT1 is turned off; charging C2 through Vdata2 and changing the potential of N21 until DT2 is turned off.

[0556] During the biasing phase S3, EM1 and EM2 provide high voltage signals, ST1 provides a low voltage signal, GN provides a low voltage signal, R0 provides a high voltage signal, GT provides a high voltage signal, ST2 provides a high voltage signal, R1 provides a low voltage signal, T7 is turned on, T4 is turned on, and REF provides a reference voltage Vref to N12 and N22, so that DT1 and DT2 are in the biased state, improving the hysteresis of DT1 and improving the hysteresis of DT2.

[0557] During the light emission stage S4, EM1 and EM2 provide low voltage signals, ST1 provides low voltage signals, GN provides low voltage signals, R0 provides high voltage signals, GT provides high voltage signals, ST2 provides low voltage signals, R1 provides high voltage signals, T10, T11, T12, and T13 are all turned on, DT1 drives O1 to emit light, and DT2 drives O2 to emit light.

[0558] Figure 31A is a first simulation timing diagram of at least one embodiment of the pixel circuit shown in Figure 23, Figure 31B is a second simulation timing diagram of at least one embodiment of the pixel circuit shown in Figure 23, and Figure 31C is a third simulation timing diagram of at least one embodiment of the pixel circuit shown in Figure 23.

[0559] In Figure 31A, the potential of N11 is shown when the data voltage is 3.5V; the potential of N12 is shown when the data voltage is 3.5V; the potential of N13 is shown when the data voltage is 3.5V; and the potential of N4 is shown when the data voltage is 3.5V.

[0560] In Figure 31B, the potential of N11 is shown when the data voltage is 4.5V; the potential of N12 is shown when the data voltage is 4.5V; the potential of N13 is shown when the data voltage is 4.5V; and the potential of N4 is shown when the data voltage is 4.5V.

[0561] In Figure 31C, the potential of N11 is shown when the data voltage is 7V; the potential of N12 is shown when the data voltage is 7V; the potential of N13 is shown when the data voltage is 7V; and the potential of N4 is shown when the data voltage is 7V.

[0562] In at least one embodiment of this disclosure, EMC1 is a first light emission control signal generation circuit, GNC1 is a first compensation control signal generation circuit, GPC1 is a first scan signal generation circuit, GPC2 is a second scan signal generation circuit, GPC3 is a third scan signal generation circuit, GPC4 is a fourth scan signal generation circuit, ST2C1 is a first on / off control signal generation circuit, and R0C1 is a first initial control signal generation circuit.

[0563] The circuit labeled EMC2 is the second light emission control signal generation circuit, the circuit labeled GNC2 is the second compensation control signal generation circuit, the circuit labeled GPC5 is the fifth scan signal generation circuit, the circuit labeled GPC6 is the sixth scan signal generation circuit, the circuit labeled GPC7 is the seventh scan signal generation circuit, the circuit labeled GPC8 is the eighth scan signal generation circuit, the circuit labeled ST2C2 is the second on / off control signal generation circuit, and the circuit labeled R0C2 is the second initial control signal generation circuit.

[0564] Specifically, EMC1 provides a first light-emitting control signal for the first row pixel circuit P1 and the second row pixel circuit P2 located in the display area A0; GNC1 provides a compensation control signal for the first row pixel circuit P1 and the second row pixel circuit P2; GPC1 and CPC2 provide a scanning signal for the first row pixel circuit P1; GPC3 and CPC4 provide a scanning signal for the second row pixel circuit P2; ST2C1 provides a second on / off control signal for the first row pixel circuit P1 and the second row pixel circuit P2; and R0C2 provides an initial control signal for the first row pixel circuit P1 and the second row pixel circuit P2.

[0565] EMC2 provides a first light-emitting control signal to the 2m-1 row pixel circuit P2m-1 and the 2m row pixel circuit P2m located in the display area A0; GNC1 provides a compensation control signal to the 2m-1 row pixel circuit P2m-1 and the 2m row pixel circuit P2m; GPC5 and CPC6 provide a scan signal to the 2m-1 row pixel circuit P2m-1; GPC7 and CPC8 provide a scan signal to the 2m row pixel circuit P2m; ST2C1 provides a second on / off control signal to the 2m-1 row pixel circuit P2m-1 and the 2m row pixel circuit P2m; and R0C2 provides an initial control signal to the 2m-1 row pixel circuit P2m-1 and the 2m row pixel circuit P2m. Here, m is an integer greater than 1.

[0566] The pixel driving method described in this embodiment is applied to the pixel circuit described above, and the display cycle includes a reset phase and a compensation phase set sequentially; the pixel driving method includes:

[0567] During the reset phase, the first on / off control circuit, under the control of the first on / off control signal, controls the connection between the first first node and the second first node; the first compensation control circuit, under the control of the compensation control signal, controls the connection between the first first node and the first control node; and the second compensation control circuit, under the control of the compensation control signal, controls the connection between the second first node and the second control node.

[0568] During the compensation phase, the first compensation control circuit, under the control of the compensation control signal, controls the connection between the first first node and the first control node; the second compensation control circuit, under the control of the compensation control signal, controls the connection between the second first node and the second control node.

[0569] In at least one embodiment of this disclosure, the pixel circuit further includes a first reset circuit, a second reset circuit, and a second on / off control circuit; the display cycle further includes a bias phase disposed after the compensation phase; the pixel driving method further includes:

[0570] During the reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the second control node, thereby writing the first initial voltage into the second first node;

[0571] During the biasing phase, the first reset circuit, under the control of the first reset control signal, writes the reference voltage into the first second node. The second on / off control circuit, under the control of the second on / off control signal, controls the connection between the first second node and the second second node to write the reference voltage into the second second node, thereby improving the hysteresis phenomenon of the driving transistors included in the driving circuit.

[0572] In at least one embodiment of this disclosure, the pixel circuit further includes a first reset circuit, a second reset circuit, and a second on / off control circuit; the display cycle further includes a bias phase disposed after the compensation phase; the pixel driving method further includes:

[0573] During the reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the first control node, so as to write the first initial voltage into the first first node and the second first node;

[0574] During the biasing phase, the first reset circuit, under the control of the first reset control signal, writes the reference voltage into the second second node. The second on / off control circuit, under the control of the second on / off control signal, controls the connection between the first second node and the second second node to write the reference voltage into the first second node, thereby improving the hysteresis phenomenon of the driving transistor included in the driving circuit.

[0575] In at least one embodiment of this disclosure, the pixel circuit further includes a first reset circuit, a second reset circuit, and a second on / off control circuit; the display cycle further includes a bias phase disposed after the compensation phase; the pixel driving method further includes:

[0576] During the reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the first control node, so as to write the first initial voltage into the first first node and the second first node;

[0577] During the biasing phase, the first reset circuit, under the control of the first reset control signal, writes the reference voltage into the first second node. The second on / off control circuit, under the control of the second on / off control signal, controls the connection between the first second node and the second second node to write the reference voltage into the second second node, thereby improving the hysteresis phenomenon of the driving transistors included in the driving circuit.

[0578] In at least one embodiment of this disclosure, the pixel circuit further includes a first reset circuit, a second reset circuit, and a second on / off control circuit; the display cycle further includes a bias phase disposed after the compensation phase; the pixel driving method further includes:

[0579] During the reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the second control node, so as to write the first initial voltage into the first node and the second node.

[0580] During the biasing phase, the first reset circuit, under the control of the first reset control signal, writes the reference voltage into the second second node. The second on / off control circuit, under the control of the second on / off control signal, controls the connection between the first second node and the second second node to write the reference voltage into the first second node, thereby improving the hysteresis phenomenon of the driving transistor included in the driving circuit.

[0581] In at least one embodiment of this disclosure, the first control node is a first second node, and the second control node is a second second node; the pixel circuit further includes a first reset circuit, a second reset circuit, and a third reset circuit; the display cycle further includes a bias phase set after the compensation phase; the pixel driving method further includes:

[0582] During the reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the second second node to write the first initial voltage into the first first node.

[0583] During the biasing phase, the first reset circuit, under the control of the first reset control signal, writes the reference voltage into the first second node, and the third reset circuit, under the control of the first reset control signal, writes the reference voltage into the second second node, so as to improve the hysteresis phenomenon of the driving transistors included in the driving circuit.

[0584] The display device described in this disclosure includes the pixel circuit described above.

[0585] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a first driving circuit, a second driving circuit, a first light emitting element, a second light emitting element, a first compensation control circuit, a second compensation control circuit and a first on-off control circuit; the first driving circuit is electrically connected with a first first node, a first second node and a first third node respectively, and is used for generating a first driving current for driving the first light emitting element under the control of the potential of the first first node; the second driving circuit is electrically connected with a second first node, a second second node and a second third node respectively, and is used for generating a first driving current for driving the first light emitting element under the control of the potential of the second first node; the first compensation control circuit is electrically connected with a compensation control end, the first first node and a first control node respectively, and is used for controlling the communication or disconnection between the first first node and the first control node under the control of a compensation control signal provided by the compensation control end; the second compensation control circuit is electrically connected with a compensation control end, the second first node and a second control node respectively, and is used for controlling the communication or disconnection between the second first node and the second control node under the control of a compensation control signal provided by the compensation control end; the first on-off control circuit is electrically connected with a first on-off control end, the first first node and the second first node respectively, and is used for controlling the communication or disconnection between the first first node and the second first node under the control of a first on-off control signal provided by the first on-off control end.

2. The pixel circuit of claim 1, wherein, The first control node is the first second node, and the second control node is the second second node.

3. The pixel circuit of claim 1, wherein, The first control node is the first third node, and the second control node is the second third node.

4. The pixel circuit of claim 1, wherein, Further comprising a first reset circuit and a second reset circuit; the first reset circuit is electrically connected with a first reset control end, a reference voltage end and the first second node respectively, and is used for writing a reference voltage provided by the reference voltage end into the first second node under the control of a first reset control signal provided by the first reset control end; the second reset circuit is electrically connected with a second reset control end, a first initial voltage end and the second control node respectively, and is used for writing a first initial voltage provided by the first initial voltage end into the second control node under the control of a second reset control signal provided by the second reset control end.

5. The pixel circuit of claim 1, wherein, Further comprising a first reset circuit and a second reset circuit; the first reset circuit is electrically connected with a first reset control end, a reference voltage end and the second second node respectively, and is used for writing a reference voltage provided by the reference voltage end into the second second node under the control of a first reset control signal provided by the first reset control end; the second reset circuit is electrically connected with a second reset control end, a first initial voltage end and the first control node respectively, and is used for writing a first initial voltage provided by the first initial voltage end into the first control node under the control of a second reset control signal provided by the second reset control end. ​ 6. The pixel circuit of claim 1, wherein, The first reset circuit and the second reset circuit are further included. The first reset circuit is electrically connected with the first reset control end, the reference voltage end and the first second node respectively, and is used for writing the reference voltage provided by the reference voltage end into the first second node under the control of the first reset control signal provided by the first reset control end. The second reset circuit is electrically connected with the second reset control end, the first initial voltage end and the first control node respectively, and is used for writing the first initial voltage provided by the first initial voltage end into the first control node under the control of the second reset control signal provided by the second reset control end.

7. The pixel circuit of claim 1, wherein, The first reset circuit and the second reset circuit are further included. The first reset circuit is electrically connected with the first reset control end, the reference voltage end and the second second node respectively, and is used for writing the reference voltage provided by the reference voltage end into the second second node under the control of the first reset control signal provided by the first reset control end. The second reset circuit is electrically connected with the second reset control end, the first initial voltage end and the second control node respectively, and is used for writing the first initial voltage provided by the first initial voltage end into the second control node under the control of the second reset control signal provided by the second reset control end.

8. The pixel circuit of claim 1, wherein, The first reset circuit and the second reset circuit are further included. The first reset circuit is electrically connected with the first reset control end, the reference voltage end and the second second node respectively, and is used for writing the reference voltage provided by the reference voltage end into the second second node under the control of the first reset control signal provided by the first reset control end. The second reset circuit is electrically connected with the second reset control end, the first initial voltage end and the first second node respectively, and is used for writing the first initial voltage provided by the first initial voltage end into the first second node under the control of the second reset control signal provided by the second reset control end.

9. The pixel circuit of any one of claims 4 to 8, wherein, The second on-off control circuit is further included. The second on-off control circuit is electrically connected with the second on-off control end, the first second node and the second second node respectively, and is used for controlling the first second node and the second second node to be connected or disconnected under the control of the second on-off control signal provided by the second on-off control end.

10. The pixel circuit of claim 9, wherein, The transistor included in the first compensation control circuit, the transistor included in the second compensation control circuit and the transistor included in the first on-off control circuit are oxide transistors; and the transistor included in the second on-off control circuit is an oxide transistor.

11. The pixel circuit of claim 2, wherein, The pixel circuit further includes a first reset circuit, a second reset circuit and a third reset circuit; The first reset circuit is electrically connected with the first reset control end, the reference voltage end and the first second node respectively, and is used for writing the reference voltage provided by the reference voltage end into the first second node under the control of the first reset control signal provided by the first reset control end. The reference voltage is written into the first second node under the control of the first reset control signal provided by the first reset control end. The second reset circuit is electrically connected with the second reset control end, the first initial voltage end and the second second node respectively, and is used for writing the first initial voltage provided by the first initial voltage end into the second second node under the control of a second reset control signal provided by the second reset control end; The third reset circuit is electrically connected with the first reset control end, the reference voltage end and the second second node respectively, and is used for writing the reference voltage provided by the reference voltage end into the second second node under the control of a first reset control signal provided by the first reset control end.

12. The pixel circuit of claim 2, wherein, The pixel circuit further comprises a first data writing circuit and a second data writing circuit; The first data writing circuit is electrically connected with a scanning end, a first data line and a first third node respectively, and is used for writing a first data voltage provided by the first data line into the first third node under the control of a scanning signal provided by the scanning end; The second data writing circuit is electrically connected with the scanning end, a second data line and a second third node respectively, and is used for writing a second data voltage provided by the second data line into the second third node under the control of the scanning signal provided by the scanning end.

13. The pixel circuit of claim 3, wherein, The pixel circuit further comprises a first data writing circuit and a second data writing circuit; The first data writing circuit is electrically connected with a scanning end, a first data line and a first second node respectively, and is used for writing a first data voltage provided by the first data line into the first second node under the control of a scanning signal provided by the scanning end; The second data writing circuit is electrically connected with the scanning end, a second data line and a second second node respectively, and is used for writing a second data voltage provided by the second data line into the second second node under the control of the scanning signal provided by the scanning end.

14. The pixel circuit of any one of claims 1 to 8, wherein, Further comprising a first first light emitting control circuit, a first second light emitting control circuit, a second first light emitting control circuit and a second second light emitting control circuit; The first first light emitting control circuit is electrically connected with a first light emitting control end, a power voltage end and a first second node respectively, and is used for controlling the power voltage end and the first second node to be connected or disconnected under the control of a first light emitting control signal provided by the first light emitting control end; The first second light emitting control circuit is electrically connected with a second light emitting control end, a first third node and a first electrode of the first light emitting element respectively, and is used for controlling the first third node and the first electrode of the first light emitting element to be connected or disconnected under the control of a second light emitting control signal provided by the second light emitting control end; The second first light emitting control circuit is electrically connected with a first light emitting control end, a power voltage end and a second second node respectively, and is used for controlling the power voltage end and the second second node to be connected or disconnected under the control of a first light emitting control signal provided by the first light emitting control end; The second second light-emitting control circuit is electrically connected with the second light-emitting control terminal, the second third node and the first electrode of the second light-emitting element respectively, and is configured to control the second third node to be in communication or disconnected with the first electrode of the second light-emitting element under the control of a second light-emitting control signal provided by the second light-emitting control terminal.

15. The pixel circuit of claim 14, wherein, The first initialization circuit, the second initialization circuit, the first energy storage circuit and the second energy storage circuit are further included. The first initialization circuit is electrically connected with the initial control terminal, the second initial voltage terminal and the first electrode of the first light-emitting element respectively, and is configured to write a second initial voltage provided by the second initial voltage terminal into the first electrode of the first light-emitting element under the control of an initial control signal provided by the initial control terminal. The second initialization circuit is electrically connected with the initial control terminal, the third initial voltage terminal and the first electrode of the second light-emitting element respectively, and is configured to write a third initial voltage provided by the third initial voltage terminal into the first electrode of the second light-emitting element under the control of an initial control signal provided by the initial control terminal. The first energy storage circuit is electrically connected with the first first node, and is configured to maintain the potential of the first first node. The second energy storage circuit is electrically connected with the second first node, and is configured to maintain the potential of the second first node.

16. The pixel circuit of claim 1, wherein, The first drive circuit includes a first drive transistor, the second drive circuit includes a second drive transistor, the first compensation control circuit includes a first transistor, the second compensation control circuit includes a second transistor, and the first on-off control circuit includes a third transistor. The gate of the first drive transistor is electrically connected with the first first node, the first electrode of the first drive transistor is electrically connected with the first second node, and the second electrode of the first drive transistor is electrically connected with the first third node. The gate of the second drive transistor is electrically connected with the second first node, the first electrode of the second drive transistor is electrically connected with the second second node, and the second electrode of the second drive transistor is electrically connected with the second third node. The gate of the first transistor is electrically connected with the compensation control terminal, the first electrode of the first transistor is electrically connected with the first first node, and the second electrode of the first transistor is electrically connected with the first control node. The gate of the second transistor is electrically connected with the compensation control terminal, the first electrode of the second transistor is electrically connected with the second first node, and the second electrode of the second transistor is electrically connected with the second control node. The gate of the third transistor is electrically connected with the first on-off control terminal, the first electrode of the third transistor is electrically connected with the first first node, and the second electrode of the third transistor is electrically connected with the second first node.

17. The pixel circuit of claim 9, wherein, The second on-off control circuit includes a sixth transistor. The gate of the sixth transistor is electrically connected with the second on-off control terminal, the first electrode of the sixth transistor is electrically connected with the first second node, and the second electrode of the sixth transistor is electrically connected with the second second node.

18. The pixel circuit of claim 15, wherein, The first initialization circuit comprises a fourteenth transistor, the second initialization circuit comprises a fifteenth transistor, the first energy storage circuit comprises a first capacitor, and the second energy storage circuit comprises a second capacitor; The gate of the fourteenth transistor is electrically connected with the initial control end, the first electrode of the fourteenth transistor is electrically connected with the second initial voltage end, and the second electrode of the fourteenth transistor is electrically connected with the first electrode of the first light-emitting element; The gate of the fifteenth transistor is electrically connected with the initial control end, the first electrode of the fifteenth transistor is electrically connected with the third initial voltage end, and the second electrode of the fifteenth transistor is electrically connected with the first electrode of the second light-emitting element; The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the first direct current voltage end; The first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with the second direct current voltage end.

19. The pixel circuit of claim 11, wherein, The first reset circuit comprises a fourth transistor, the second reset circuit comprises a fifth transistor, and the third reset circuit comprises a seventh transistor; The gate of the fourth transistor is electrically connected with the first reset control end, the first electrode of the fourth transistor is electrically connected with the reference voltage end, and the second electrode of the fourth transistor is electrically connected with the first second node; The gate of the fifth transistor is electrically connected with the second reset control end, the first electrode of the fifth transistor is electrically connected with the first initial voltage end, and the second electrode of the fifth transistor is electrically connected with the second second node; The gate of the seventh transistor is electrically connected with the first reset control end, the first electrode of the seventh transistor is electrically connected with the reference voltage end, and the second electrode of the seventh transistor is electrically connected with the second second node; The pixel circuit further comprises a first data write-in circuit, a second data write-in circuit, a first light-emitting control circuit, a second light-emitting control circuit, a second light-emitting control circuit, and a second light-emitting control circuit; The first data write-in circuit comprises an eighth transistor, and the second data write-in circuit comprises a ninth transistor; The gate of the eighth transistor is electrically connected with the scanning end, the first electrode of the eighth transistor is electrically connected with the first data line, and the second electrode of the eighth transistor is electrically connected with the first third node; The gate of the ninth transistor is electrically connected with the scanning end, the first electrode of the ninth transistor is electrically connected with the second data line, and the second electrode of the ninth transistor is electrically connected with the second third node; The first light-emitting control circuit comprises a tenth transistor, the first second light-emitting control circuit comprises an eleventh transistor, the second light-emitting control circuit comprises a twelfth transistor, and the second light-emitting control circuit comprises a thirteenth transistor; The gate of the tenth transistor is electrically connected with the first light-emitting control end, the first electrode of the tenth transistor is electrically connected with the power voltage end, and the second electrode of the tenth transistor is electrically connected with the first second node; A gate of the eleventh transistor is electrically connected with the second light-emitting control end, a first electrode of the eleventh transistor is electrically connected with the first third node, and a second electrode of the eleventh transistor is electrically connected with the first electrode of the first light-emitting element; A gate of the twelfth transistor is electrically connected with the first light-emitting control end, a first electrode of the twelfth transistor is electrically connected with the power voltage end, and a second electrode of the twelfth transistor is electrically connected with the second second node; A gate of the thirteenth transistor is electrically connected with the second light-emitting control end, a first electrode of the thirteenth transistor is electrically connected with the second third node, and a second electrode of the thirteenth transistor is electrically connected with the first electrode of the second light-emitting element.

20. A pixel driving method applied to the pixel circuit according to any one of claims 1 to 19, a display period comprising a reset stage and a compensation stage arranged in sequence; the pixel driving method comprising: in the reset stage, the first on-off control circuit controls the first first node and the second first node to be in communication under the control of the first on-off control signal, the first compensation control circuit controls the first first node and the first control node to be in communication under the control of the compensation control signal, and the second compensation control circuit controls the second first node and the second control node to be in communication under the control of the compensation control signal; in the compensation stage, the first compensation control circuit controls the first first node and the first control node to be in communication under the control of the compensation control signal, and the second compensation control circuit controls the second first node and the second control node to be in communication under the control of the compensation control signal.

21. A display device comprising the pixel circuit according to any one of claims 1 to 19.

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