Power conversion device

Abstract

A power conversion device (1) is provided with: a plurality of semiconductor packages (P1-P4, N1-N4) having built-in power semiconductor elements electrically connected between a high-potential-side terminal (4P) and a low-potential-side terminal (4N); and a stacked wiring (2) including high-potential-side wiring (UP, LP) connected to the high-potential-side terminal of each of the plurality of semiconductor packages, and low-potential-side wiring (UN, LN) connected to the low-potential-side terminal of each of the plurality of semiconductor packages. The first semiconductor package and the second semiconductor package, which are adjacent to each other, are disposed such that the respective low-potential-side terminals are sandwiched between the respective high-potential-side terminals, and the low-potential-side wiring has an integrated connection terminal section (50). The connection terminal part (50) is formed by connecting the connection part of the low potential side terminal of the first semiconductor package and the connection part of the low potential side terminal of the second semiconductor package.

Description

Technical Field

[0001] This invention relates to an electric power conversion device. Background Technology

[0002] Power conversion devices that convert DC to AC power are used in various devices and require high efficiency, small size, and low heat generation. The semiconductor elements constituting the power conversion device are connected in parallel in multiples according to the required current magnitude. Patent Document 1 discloses a semiconductor unit characterized by comprising: a plurality of transistor chips, each having a first main electrode on one side and a second main electrode on the other side, arranged in parallel columns; a first conductor layer electrically connected to the first main electrode of the transistor chips and protruding at two corners of one side along the extending direction of the columns of the transistor chips; a second conductor layer disposed between the two corners of the first conductor layer; and a wiring substrate having a wiring layer disposed on the side of the second main electrode of the plurality of transistor chips and electrically connected to the second main electrode and the second conductor layer of the plurality of transistor chips.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-047656 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] When the current flowing through multiple semiconductor elements deviates, heat generation becomes unbalanced, requiring additional heat dissipation measures, which is undesirable. During switching, deviations in the source inductance of each semiconductor element cause current deviations. In the invention described in Patent Document 1, the source inductance is deviated.

[0008] Methods for solving problems

[0009] The power conversion device according to the first aspect of the present invention includes: a plurality of semiconductor packages having a power semiconductor element internally connected between a high-potential side terminal and a low-potential side terminal; and a stacked wiring including a high-potential side wiring connected to the high-potential side terminal of each of the plurality of semiconductor packages and a low-potential side wiring connected to the low-potential side terminal of each of the plurality of semiconductor packages. In the plurality of semiconductor packages, adjacent first semiconductor packages and second semiconductor packages are arranged such that their respective low-potential side terminals are sandwiched between their respective high-potential side terminals. The low-potential side wiring has an integral connection terminal portion, which is formed by connecting a connection portion to the low-potential side terminal of the first semiconductor package and a connection portion to the low-potential side terminal of the second semiconductor package.

[0010] The effects of the invention

[0011] According to the present invention, the source inductance can be equalized. Attached Figure Description

[0012] Figure 1 This is a plan view of the power conversion device.

[0013] Figure 2 This is a diagram showing the polarity of the DC terminals of a semiconductor package.

[0014] Figure 3 It is a diagram showing the structure of the layers in a cascaded wiring diagram.

[0015] Figure 4 It is a diagram representing the equivalent circuit of a power conversion device.

[0016] Figure 5 It is a diagram showing the direction of current flow in a power conversion device.

[0017] Figure 6 This is a detailed diagram of a semiconductor package.

[0018] Figure 7 This is a diagram showing the shape of the semiconductor package in Variation 1.

[0019] Figure 8 This is a schematic diagram of the power conversion device in Variation Example 2.

[0020] Figure 9 This is a schematic diagram of the power conversion device in Variation Example 3. Detailed Implementation

[0021] (First Embodiment)

[0022] The following is for reference Figures 1-6 The first embodiment of the power conversion device of the present invention will be described.

[0023] Figure 1 This is a plan view of a power conversion device 1. The power conversion device 1 includes a multilayer wiring 2 and a semiconductor package group 4. The multilayer wiring 2 has multiple layers in the depth direction shown in the figure, that is, in the thickness direction of the power conversion device 1. Specifically, the multilayer wiring 2 is a four-layer structure consisting of a first layer 21, a second layer 22, a third layer 23, and a fourth layer 24. Figure 1 Only layer 1 21 is shown in the diagram. The structure of each layer of the stacked routing 2 will be described later. The stacked routing 2 includes region 1 2L, region 2C, and region 3 2R.

[0024] Semiconductor package group 4 is composed of multiple semiconductor packages 4c, specifically consisting of upper bridge arm first package P1, upper bridge arm second package P2, upper bridge arm third package P3, upper bridge arm fourth package P4, lower bridge arm first package N1, lower bridge arm second package N2, lower bridge arm third package N3, and lower bridge arm fourth package N4. That is, semiconductor package group 4 includes four semiconductor packages 4c constituting the upper bridge arm and four semiconductor packages 4c constituting the lower bridge arm. Identical semiconductor packages 4c are connected only in the first layer 21 of the stack-up wiring 2. Furthermore, each semiconductor package 4c is physically identical in configuration, differing only in its arrangement.

[0025] Each semiconductor package 4c has a high-potential side terminal 4P and a low-potential side terminal 4N as two parallel DC terminals, and a high-potential side signal terminal, a low-potential side signal terminal, and a high-potential side terminal as three parallel terminals. Each semiconductor package 4c is configured such that the high-potential side terminal 4P and the low-potential side terminal 4N face towards one side of the stacked wiring 2, i.e., towards the inside. See below for details. Figure 2 Please provide an explanation.

[0026] Figure 2 This is a diagram showing the polarity of the DC terminal of a 4C semiconductor package. Figure 1 The diagram after removing the stacked wiring 2 is shown. Focus on the two in the upper left corner, namely the first package P1 and the second package P2 of the upper bridge arm. A low-potential terminal 4N is arranged between the high-potential side terminal 4P of these two semiconductor packages 4c. Figure 2 The upper bridge arm third package P3 and upper bridge arm fourth package P4 shown in the lower left also have a low potential side terminal 4N disposed between the high potential side terminal 4P of these two semiconductor packages 4c. Figure 2 The same applies to the lower bridge arm packages N1 to N4 shown on the right. That is, the semiconductor package group 4 is configured such that the high-potential side terminals 4P of two adjacent semiconductor packages 4c are sandwiched between their respective low-potential side terminals 4N.

[0027] Figure 3This diagram illustrates the structure of each layer in the stacked wiring 2. Layer 1 21 and Layer 3 23 have approximately the same structure, and Layer 2 22 and Layer 4 24 have the same structure. In this embodiment, the stacked wiring 2 uses hatching to represent the same electrical potential. Figure 3 The via (V) indicated by the circle runs through layers 1 21 to 4 24, electrically connecting each layer. For example, the via V in the upper left of the figure exists in the area where the diagonal profile line is applied in any of layers 1 21 to 4 24, so that the potential of the stacked wiring 2 is the same in the stacking direction.

[0028] The stacked wiring 2 includes an upper high wiring UP, which is a high-potential side wiring in the upper arm; an upper low wiring UN, which is a low-potential side wiring in the upper arm; a lower high wiring LP, which is a high-potential side wiring in the lower arm; and a lower low wiring LN, which is a low-potential side wiring in the lower arm. In this embodiment, the upper high wiring UP is represented by a diagonal cross-section line, the upper low wiring UN is represented by a grid cross-section line, the lower high wiring LP is represented by a diagonal grid cross-section line, and the lower low wiring LN is represented by a grid cross-section line. However, since the upper low wiring UN and the lower high wiring LP have the same potential, the same cross-section line can also be used.

[0029] Layer 1 21 includes a first connection terminal portion 51, a second connection terminal portion 52, a third connection terminal portion 53, and a fourth connection terminal portion 54. Hereinafter, these will be collectively referred to as connection terminal portions 50. Connection terminal portions 50 are portions integrally connected to the low-potential side terminals 4N of two adjacently arranged semiconductor packages 4c. Specifically: The first connection terminal portion 51 is connected to the low-potential side terminals 4N of the upper bridge arm first package P1 and the upper bridge arm second package P2. The second connection terminal portion 52 is connected to the upper bridge arm third package P3 and the upper bridge arm fourth package P4. The third connection terminal portion 53 is connected to the lower bridge arm first package N1 and the lower bridge arm second package N2. The fourth connection terminal portion 54 is connected to the lower bridge arm third package N3 and the lower bridge arm fourth package N4.

[0030] Figure 4 This is a diagram showing the equivalent circuit of power conversion device 1. Figure 4 The lower part schematically illustrates the corresponding positions of the inductive elements in the equivalent circuit. The P and N shown at the upper and lower ends of the equivalent circuit are connected, for example, to the high-potential side terminal 4P and the low-potential side terminal 4N of the capacitor connected to the power conversion device 1.

[0031] Figure 5 This is a diagram showing the current flow direction in power conversion device 1. Specifically, Figure 5The upper section indicates the current flow direction of the first layer 21 and the third layer 23 of the stacked wiring 2; the middle section indicates the current flow direction of the second layer 22 and the fourth layer 24 of the stacked wiring 2; and the lower section indicates the current flow direction in the cross-section. The cross-sectional diagram shown in the lower section is the cross-section at the single-dotted line positions of the upper and middle sections. In the cross-sectional diagram, an "X" surrounded by a circle indicates current flowing inwards, and a "black dot surrounded by a circle" indicates current flowing outwards.

[0032] For example, focusing on region 1 (2L), current flows inward in layer 1 (21), outward in layer 2 (22), inward in layer 3 (23), and outward in layer 4 (24). That is, in region 1 (2L), the current direction is opposite in each layer. This tendency is also present in regions 2C and 3R, and even within the same layer, the current direction is different in each adjacent region. Thus, the inductance of the stacked wiring 2 is reduced due to the flow of opposing currents.

[0033] Figure 5 The four dashed circles shown represent busbars 60. A busbar 60 is a location where currents flowing through two connection terminal sections 50 with the same potential converge. The busbar 60 is located approximately at the center of these two connection terminal sections 50. Specifically, the first busbar 61 is a location where currents flowing through the first connection terminal section 51 and the second connection terminal section 52 converge after moving from the first layer 21 to the second layer 22 and the fourth layer 24 via the via V. Furthermore, the second busbar 62 is a location where currents flowing through the third connection terminal section 53 and the fourth connection terminal section 54 converge after moving from the first layer 21 to the second layer 22 and the fourth layer 24 via the via V.

[0034] First confluence section 61 Figure 5 In the vertical direction, it is located approximately at the center of the first connection terminal projection portion 51a after the first connection terminal portion 51 is moved in the thickness direction, and the second connection terminal projection portion 52a after the second connection terminal portion 52 is projected in the thickness direction. Therefore, the distance from the first connection terminal portion 51 to the first busbar 61 and the distance from the second connection terminal portion 52 to the first busbar 61 are approximately equal, and even if the paths are different, the inductance value is approximately the same. The second busbar 62 is located at... Figure 5 In the vertical direction, it is located approximately at the center of the third connection terminal projection portion 53a after the third connection terminal portion 53 is moved in the thickness direction and the fourth connection terminal projection portion 54a after the fourth connection terminal portion 54 is projected in the thickness direction. Therefore, the distance from the third connection terminal portion 53 to the second bus portion 62 is approximately equal to the distance from the fourth connection terminal portion 54 to the second bus portion 62, and even if the paths are different, the inductance value is approximately the same.

[0035] Figure 6 This is a detailed structural diagram of a 4C semiconductor package. Additionally, Figure 6 The cross-sectional pattern in the diagram is independent of the overlay wiring 2. From Figure 6 After removing the molding compound 41, the semiconductor package 4c shown in (a) appears as... Figure 6 The state shown in (b). Figure 6 (b) shows a low-potential body 4NB with a low-potential side terminal 4N formed at the front end. Figure 6 The DD and EE sections in (b) will be described later. Figure 6 After removing the low-potential body 4NB, the state shown in (b) is as follows: Figure 6 The state shown in (c). Figure 6 (c) shows a bonding line 44 extending from the power semiconductor element 43 and a high-potential body 4PB with a high-potential side terminal 4P formed at its front end.

[0036] Figure 6 (d) and Figure 6 (e) is Figure 6 The DD cross-section and EE cross-section are shown in (b). Figure 6 (d) and Figure 6 (e) shows the power semiconductor element 43 connected to the low-potential body 4NB and the high-potential body 4PB via solder 45. Furthermore, the upper bridge arm first package P1 and the upper bridge arm third package P3 employ... Figure 6 As shown in (a), the upper bridge arm second package P2 and the upper bridge arm fourth package P4 are in an up-down flip configuration.

[0037] According to the first embodiment described above, the following effects can be obtained.

[0038] (1) The power conversion device 1 includes: a plurality of semiconductor packages 4c having a power semiconductor element 43 internally connected between a high-potential side terminal 4P and a low-potential side terminal 4N; and a stacked wiring 2, which includes an upper high wiring UP and a lower high wiring LP connected to the high-potential side terminal 4P of each of the plurality of semiconductor packages 4c, and an upper low wiring UN and a lower low wiring LN connected to the low-potential side terminal 4N of each of the plurality of semiconductor packages 4c. In the power conversion device 1, adjacent first semiconductor packages and second semiconductor packages, such as upper bridge arm first package P1 and upper bridge arm second package P2, are arranged such that their respective low-potential side terminals 4N are sandwiched between their respective high-potential side terminals 4P. The upper low wiring UN and the lower low wiring LN, which are low-potential side wirings, have an integral connection terminal portion 50, such as a first connection terminal portion 51, which connects the connection portion to the low-potential side terminal 4N of the first semiconductor package and the connection portion to the low-potential side terminal 4N of the second semiconductor package. Therefore, the source inductance in each power semiconductor element 43 can be made equal.

[0039] (2) The power conversion device 1 comprises an upper bridge arm and a lower bridge arm, each having N connection terminals 50 for 2N or 2N+1 semiconductor packages 4c, where N is a natural number. For example Figure 1 The upper and lower bridge arms of the power conversion device 1 shown each contain four semiconductor packages 4c. Since 4 is 2x2, "N=2". The upper and lower bridge arms each have two connection terminal portions 50.

[0040] (3) A busbar 60, in which currents flowing through two connection terminal portions 50 with the same potential converge, is provided approximately at the center of the two connection terminal portions 50. For example, the first busbar 61, in which currents flowing through the first connection terminal portion 51 and the second connection terminal portion 52 with the same potential converge, is provided approximately at the center of the first connection terminal portion 51 and the second connection terminal portion 52 in the long side direction of the stacked wiring 2. Therefore, the source inductance in each power semiconductor element 43 can be further equalized.

[0041] (4) For a semiconductor package 4c with 2N or 2N+1 semiconductor packages 4c having N connection terminal portions 50 and located at both ends in the long side direction, the low potential side terminal 4N is arranged on the inner side.

[0042] (5) The stacked wiring 2 has a first region 2L, a second region 2C, and a third region 2R. The second region 2C exists between the first region 2L and the third region 2R. The connecting terminal portion 50 exists in the first region 2L and the third region 2R. In the first region 2L, the high-potential side wiring of the upper bridge arm and the low-potential side wiring of the upper bridge arm are stacked. In the second region 2C, the high-potential side wiring of the upper bridge arm and the low-potential side wiring of the lower bridge arm are stacked. In the third region 2R, the high-potential side wiring of the lower bridge arm and the low-potential side wiring of the lower bridge arm are stacked. Therefore, as Figure 5 As shown in the next section, the inductance is reduced because opposing currents flow through the stacked wiring 2.

[0043] (6) The adjacent upper bridge arm first package P1 and upper bridge arm second package P2 have the same configuration and are connected to the stacked wiring 2 in opposite orientations. Therefore, the number of components constituting the power conversion device 1 can be reduced.

[0044] (Variation Example 1)

[0045] Figure 7 This is a diagram showing the shape of the semiconductor package 4c in Modified Example 1. In the first embodiment, the positions of the high-potential side terminal 4P and the low-potential side terminal 4N in the thickness direction of the semiconductor package 4c are not specified. However, as... Figure 7As shown, the high-potential side terminal 4P and the low-potential side terminal 4N can also be positioned approximately at the center of the semiconductor package 4c in the thickness direction. In other words, the distance T1 from the end of the low-potential body 4NB to the high-potential side terminal 4P and the low-potential side terminal 4N in the thickness direction is equal to the distance T2 from the end of the high-potential body 4PB to the high-potential side terminal 4P and the low-potential side terminal 4N in the thickness direction. In this case, regardless of the orientation of the semiconductor package 4c, the upper and lower ends in the thickness direction are flush. Therefore, as Figure 7 As shown in (b), when the upper cooling path 8U and the lower cooling path 8D are configured in a manner that sandwiches the semiconductor package group 4, the gap between the cooling path and the semiconductor package 4c can be eliminated.

[0046] Based on this modified example, the following effects can be achieved.

[0047] (7) The semiconductor package 4c has a high-potential side terminal 4P and a low-potential side terminal 4N approximately at the center in the thickness direction. Therefore, the cooling structure can be simplified.

[0048] (Variation Example 2)

[0049] The number of semiconductor packages 4c in each of the upper and lower bridge arms constituting the power conversion device 1 is not limited to four. Each of the upper and lower bridge arms can be composed of two or more semiconductor packages 4c, with no upper limit. Let N be a natural number. In the cases where the number of semiconductor packages 4c constituting the upper and lower bridge arms is 2N or 2N+1, N connection terminal sections 50 are provided. For the odd number cases, please refer to the attached diagram for explanation.

[0050] Figure 8 This is a configuration diagram of the power conversion device 1a in Modified Example 2. The upper and lower bridge arms of the power conversion device 1a each contain five semiconductor packages 4c. Since a connection terminal 50 is provided for each of the two semiconductor packages 4c, the third package P3 of the upper bridge arm and the third package N3 of the lower bridge arm, which are located in the center, are not connected to the connection terminal 50.

[0051] (Variation Example 3)

[0052] Figure 9 This is a configuration diagram of the power conversion device 1b in Variation Example 3. The difference between power conversion device 1b and power conversion device 1 lies in the arrangement of the upper arm third package P3 and upper arm fourth package P4. With this change in arrangement, the stacked wiring 2 is also changed. Specifically, the upper arm third package P3 and upper arm fourth package P4 are moved downwards relative to power conversion device 1. This movement makes the distance from the first connection terminal 51 to the first busbar 61 more equal to the distance from the second connection terminal 52 to the first busbar 61.

[0053] (Variation Example 4)

[0054] In the first embodiment described above, the stacked wiring 2 has layers 1 to 4, 24. However, the number of layers in the stacked wiring 2 is not limited to 4 layers, as long as it is an even number. It is not limited to the number of sheets, each of the even-numbered layers has the same configuration, and each of the odd-numbered layers has the same configuration.

[0055] The above-described embodiments and modifications can also be combined separately. Various embodiments and modifications have been described above, but the present invention is not limited to these. Other methods conceivable without departing from the spirit of the present invention are also included within the scope of the present invention.

[0056] Figure Labels

[0057] 1: Power conversion device

[0058] 2: Layered wiring

[0059] 2C: Region 2

[0060] 2L: Zone 1

[0061] 2R: Area 3

[0062] 4: Semiconductor Packaging Group

[0063] 4N: Low-potential side terminal

[0064] 4NB: Low Potential Body

[0065] 4P: High-potential side terminal

[0066] 4PB: High potential body

[0067] 4c: Semiconductor Packaging

[0068] 21: Level 1

[0069] 22: Level 2

[0070] 23: The 3rd floor

[0071] 24: 4th floor

[0072] 50: Connecting terminal section

[0073] 60: Convergence section

[0074] 61: First Convergence Section

[0075] 62: Second confluence section

[0076] LN: Lower routing

[0077] LP: Bottom High Wiring

[0078] UN: Upper Low Wiring

[0079] UP: Upper wiring.

Claims

1. A power conversion device, characterized by, Possessing: a plurality of semiconductor packages that have a power semiconductor element electrically connected between a high potential side terminal and a low potential side terminal built in; and a laminated wiring that includes a high potential side wiring connected to the high potential side terminal possessed by each of the plurality of semiconductor packages, and a low potential side wiring connected to the low potential side terminal possessed by each of the plurality of semiconductor packages, in the plurality of semiconductor packages, a first semiconductor package and a second semiconductor package that are adjacent to each other are arranged with the low potential side terminals of each being sandwiched between the high potential side terminals possessed by each, the low potential side wiring has an integrated connection terminal portion that is formed by joining a connection portion to the low potential side terminal of the first semiconductor package and a connection portion to the low potential side terminal of the second semiconductor package.

2. The power conversion device according to claim 1, wherein an upper bridge arm and a lower bridge arm are constituted, each of the upper bridge arm and the lower bridge arm has N connection terminal portions for 2N or 2N+1 semiconductor packages, where N is a natural number.

3. The power conversion device according to claim 2, wherein a bus portion at which currents flowing through two connection terminal portions having the same potential converge is provided at substantially the center of the two connection terminal portions.

4. The power conversion device according to claim 2, wherein N connection terminal portions are provided for 2N or 2N+1 semiconductor packages, and the low potential side terminals of the semiconductor packages located at the uppermost and lowermost portions in the vertical direction are arranged inward.

5. The power conversion device according to claim 1, wherein the laminated wiring has a first region, a second region, and a third region, the second region is present between the first region and the third region, the connection terminal portions are present in the first region and the third region, in the first region, a high potential side wiring of an upper bridge arm and a low potential side wiring of the upper bridge arm are laminated, in the second region, a high potential side wiring of an upper bridge arm and a low potential side wiring of a lower bridge arm are laminated, in the third region, a high potential side wiring of a lower bridge arm and a low potential side wiring of the lower bridge arm are laminated.

6. The power conversion device according to claim 1, wherein the first semiconductor package and the second semiconductor package have the same constitution and are connected to the laminated wiring in a state in which the front and back are reversed.

7. The power conversion device according to claim 6, wherein the semiconductor packages have the high potential side terminal and the low potential side terminal at substantially the center in the thickness direction.

Images