Capacitor

Abstract

The capacitor according to one embodiment of the present invention comprises: a base substrate including a plurality of through holes penetrating from a first surface to a second surface opposite to the first surface; a base electrode disposed on the first surface to cover at least two adjacent through holes of the plurality of through holes; a first electrode layer disposed on an upper surface edge and a side surface of the base electrode; a dielectric layer disposed on the first electrode layer; a second electrode layer disposed on the dielectric layer; an insulating layer disposed on the second electrode layer; and a first electrode pad disposed on an upper surface of the base electrode, in which the insulating layer extends from an upper surface of the second electrode layer to the upper surface of the base electrode along a side surface of the second electrode layer, a side surface of the dielectric layer, and a side surface of the first electrode layer, and a second electrode pad disposed between a side surface of the first electrode pad and a side surface of the first electrode layer, a side surface of the dielectric layer, and a side surface of the second electrode layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a capacitor. BACKGROUND

[0002] Semiconductor packages are applied to various fields (e.g., vehicles, communications, and computers), and generally include a printed circuit board, a semiconductor chip disposed on the printed circuit board, and a passive element disposed on the printed circuit board. The passive element can include, for example, a resistor, an inductor, a capacitor, etc.

[0003] As semiconductor packages become more advanced, there is an increasing demand for capacitors having high performance, high reliability, and ultra-small size. To meet this demand, silicon-based capacitors and anode aluminum oxide (AAO)-based capacitors have been proposed. The silicon-based capacitor includes electrode layers, dielectric layers, and electrode layers stacked in sequence on a silicon substrate, and the AAO-based capacitor includes electrode layers, dielectric layers, and electrode layers stacked in sequence on an AAO substrate.

[0004] The AAO substrate can be a porous substrate manufactured through a metal anodization process. Because the porous substrate has a large surface area, the capacitance of the capacitor can be increased. However, there is a problem in that a process of disposing an electrode pad on the porous substrate is very difficult. SUMMARY

[0005] TECHNICAL PROBLEM

[0006] The technical object to be achieved by the present application is to provide a capacitor that is ultra-small and has a large capacity.

[0007] TECHNICAL SOLUTION

[0008] A capacitor according to an embodiment of the present application includes a base substrate including a plurality of through holes passing through from a first surface to a second surface opposite to the first surface; a base electrode disposed on the first surface to cover at least two adjacent through holes among the plurality of through holes; a first electrode layer disposed on an upper surface edge and a side surface of the base electrode; a dielectric layer disposed on the first electrode layer; a second electrode layer disposed on the dielectric layer; an insulating layer disposed on the second electrode layer; and a first electrode pad disposed on an upper surface of the base electrode, wherein the insulating layer extends from an upper surface of the second electrode layer along a side surface of the second electrode layer, a side surface of the dielectric layer, and a side surface of the first electrode layer to the upper surface of the base electrode, and is disposed between the side surface of the first electrode pad and the side surface of the first electrode layer, the side surface of the dielectric layer, and the side surface of the second electrode layer.

[0009] The side surface of the base electrode can be disposed to be inclined with respect to the first surface, and the first electrode layer disposed on the side surface of the base electrode can be disposed to be inclined with respect to the first surface.

[0010] The side surface of the base electrode can include a recessed area, and the first electrode layer can be disposed along the recessed area on the side surface of the base electrode.

[0011] The lower surface of the base electrode can include a protrusion protruding in a direction from the first surface toward the second surface within the at least two through-holes.

[0012] The at least two through-holes disposed below the base electrode can be hollow.

[0013] The remaining through-holes other than the at least two through-holes among the plurality of through-holes can be filled with the first electrode layer, the dielectric layer, the electrode layer, and the insulating layer.

[0014] The first electrode layer, the dielectric layer, the second electrode layer, and the insulating layer can be sequentially disposed on inner wall surfaces of the remaining through-holes other than the at least two through-holes among the plurality of through-holes.

[0015] The first electrode layer, the dielectric layer, and the second electrode layer can be sequentially disposed on the first surface of the base substrate in a second area surrounding a first area in which the base electrode is disposed, and can further include a second electrode pad disposed on the second electrode layer in the second area.

[0016] The thickness of the base electrode can be 0.9 times to 1.1 times the thickness of the first electrode layer, the dielectric layer, and the second electrode layer disposed in the second area.

[0017] The thickness of the base electrode can be 10 nm to 100 µm.

[0018] The diameter of each of the plurality of through-holes can be 10 nm to 500 nm, the shortest distance between two of the through-holes can be 10 nm to 500 nm, and the aspect ratio of each of the through-holes can be 20 or more.

[0019] The base substrate can be an anodized substrate of at least one of aluminum (Al), magnesium (Mg), zinc (Zn), titanium (Ti), tantalum (Ta), hafnium (Hf), or niobium (Nb).

[0020] Advantageous Effects

[0021] According to embodiments of the present application, a capacitor of an ultra-small size and a large capacity can be provided. Further, according to embodiments of the present application, a capacitor of a simple manufacturing process, low cost, and high reliability can be provided. Specifically, according to embodiments of the present application, a capacitor of a simple process for connecting electrode pads can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1is a perspective view of a capacitor according to an embodiment of the present application.

[0023] Figure 2 is a perspective view of a base substrate included in a capacitor according to an embodiment of the present application.

[0024] Figure 3 is a top view of a base substrate included in a capacitor according to an embodiment of the present application.

[0025] Figure 4 is a cross-sectional view of a base substrate included in a capacitor according to an embodiment of the present application.

[0026] Figure 5 is a top view of a base substrate and a base electrode included in a capacitor according to an embodiment of the present application.

[0027] Figure 6 is a cross-sectional view of a base substrate and a base electrode included in a capacitor according to an embodiment of the present application.

[0028] Figures 7 to 12 is a cross-sectional view of a capacitor according to an embodiment of the present application.

[0029] Figure 13 is an example of a manufacturing method of a base substrate according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] Hereinafter, exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0031] However, the technical spirit of the present application is not limited to the embodiments described below, and the present application can be implemented in various forms. One or more components of the embodiments can be selectively combined with each other or replaced within the technical spirit or scope of the present application.

[0032] Further, unless explicitly defined otherwise, the terms used in the embodiments of the present application, including technical and scientific terms, will be interpreted the same as commonly understood by one of ordinary skill in the art to which the present application pertains, and the terms, such as terms defined in a dictionary, will be interpreted in the context of the relevant technology.

[0033] Further, the terms used in the embodiments of the present application are merely used to describe the embodiments and are not intended to limit the scope of the present application.

[0034] In the present specification, unless stated otherwise, the singular forms are intended to include the plural forms and the expression "at least one of A, B, and / or C" is intended to include any combination of A, B, and C.

[0035] Also, expressions such as "first", "second", "A", "B", "(a)", "(b)", etc. can be used to describe components of the embodiments of the present application.

[0036] These expressions are used only to distinguish one component from another component, and do not limit the nature, order, or arrangement of the corresponding components.

[0037] Also, when a component is described as being "connected", "engaged", or "coupled" to another component, the description should be understood to include both direct "connection", "engagement", or "coupling" between the components and indirect "connection", "engagement", or "coupling" between the components through one or more intermediate components.

[0038] In the expression "formed or disposed on (over) or under (under) another component", the terms "on (over)" and "under (under)" include not only direct contact between the two components, but also formation or disposition with one or more other components interposed between the two components. Also, the terms "on (over)" and "under (under)" can refer to the upward and downward directions with respect to one component.

[0039] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings. In all the drawings, the same reference numerals refer to the same or corresponding components, and repetitive description thereof will be omitted.

[0040] Figure 1 is a perspective view of a capacitor according to an embodiment of the present application, Figure 2 is a perspective view of a base substrate included in a capacitor according to an embodiment of the present application, Figure 3 is a plan view of a base substrate included in a capacitor according to an embodiment of the present application, Figure 4 is a cross-sectional view of a base substrate included in a capacitor according to an embodiment of the present application, Figure 5 is a plan view of a base substrate and a base electrode included in a capacitor according to an embodiment of the present application, Figure 6 is a cross-sectional view of a base substrate and a base electrode included in a capacitor according to an embodiment of the present application, Figures 7 to 12 is a cross-sectional view of a capacitor according to an embodiment of the present application.

[0041] Referring to Figures 1 to 12 , the capacitor 100 includes a base substrate 110, a first electrode layer 120, a first dielectric layer 130, and a second electrode layer 140.

[0042] As Figures 2 to 4As shown, the base substrate 110 includes a first surface 111, a second surface 112 opposite to the first surface 111, and a third surface 113 disposed between the first surface 111 and the second surface 112. The first surface 111, the second surface 112, and the third surface 113 can be respectively referred to as an upper surface, a lower surface, and a side surface. The base substrate 110 is shown as a hexahedron, but is not limited thereto. The substrate 110 can be a cylinder, an elliptic cylinder, a prism, or the like.

[0043] The base substrate 110 can include a semiconductor material or a non-conductor material. For example, the base substrate 110 can include an anodized metal. For example, the base substrate 110 can be an anodized substrate of at least one of aluminum (Al), magnesium (Mg), zinc (Zn), titanium (Ti), tantalum (Ta), hafnium (Hf), or niobium (Nb). For example, the base substrate 110 can include anodized aluminum oxide (AAO). Alternatively, the base substrate 110 can be a silicon (Si) substrate. For example, the base substrate 110 can be a doped silicon substrate. For example, the base substrate 110 can be an n-type doped silicon substrate or a p-type doped silicon substrate.

[0044] According to an embodiment of the present application, the base 110 includes a plurality of through holes TH penetrating from the first surface 111 to the second surface 112. That is, the plurality of through holes TH extend from the first surface 111 to the second surface 112 of the base 110. In this case, at least some of the plurality of through holes TH can be parallel to each other. For example, an imaginary line of one of the plurality of through holes TH connecting from the center of the bottom surface to the center of the upper surface can be parallel to an imaginary line of another of the plurality of through holes TH connecting from the center of the upper surface to the center of the upper surface. According to this embodiment, since the electrode layer can be easily deposited on the inner wall surfaces of the plurality of through holes TH with a uniform thickness, a capacitor with high reliability can be obtained. The plurality of through holes TH can be regularly arranged. For example, as shown in FIG. 1, the plurality of through holes TH can be arranged in a matrix form. Figure 3As shown, the distance from the center point P1 of one via to the center points P2-P7 of six vias arranged around it is constant, and when the center points P2-P7 of the six vias are imaginarily connected, they can be arranged in a hexagonal shape. In this case, the deviation of the diameter d1 of the multiple vias TH can be within 25%. Optionally, the deviation of the distance d2 between the center points of adjacent vias TH can be within 25%. Here, deviation can refer to the deviation between the minimum and maximum values. That is, the maximum value of the via diameter or the distance between the center points can mean that it is less than 1.25 times the minimum value of the via diameter or the distance between the center points. Optionally, deviation can refer to the deviation from the average value. That is, the distance between the diameter of the via or the distance between the center points can mean that it is within 75% to 125% of the average value of the diameter of the via or the distance between the center points. In this way, when multiple vias TH are arranged regularly, the surface area of ​​the substrate 110 remains constant, thereby obtaining a capacitor with uniform quality.

[0045] According to an embodiment of the invention, the average diameter d1 of the plurality of vias TH can be from 1 nm to 1 μm, preferably from 10 nm to 500 nm, and more preferably from 50 nm to 300 nm. Alternatively, the average shortest distance d3 between two adjacent vias TH can be from 1 nm to 1 μm, preferably from 10 nm to 500 nm, and more preferably from 50 nm to 300 nm. According to this embodiment, the possibility of damage to the substrate 110 can be minimized and durability increased, while ensuring sufficient specific surface area required to achieve the capacitor.

[0046] In this case, the aspect ratio of each via TH can be 20 or more, preferably 40 or more, more preferably 60 or more, and even more preferably 80 or more. Here, the aspect ratio can refer to the ratio of the height H of the via TH relative to the second surface 112 of the substrate 110 to the diameter d1 of the via TH. According to this embodiment, a capacitor with a large capacitance can be obtained by maximizing the surface area of ​​the substrate 110.

[0047] At the same time, such as Figures 5 to 6 As shown, the capacitor 100 according to an embodiment of the present invention further includes a base electrode 600. The base electrode 600 is disposed on a first surface 111 of a base substrate 110 to cover at least two adjacent vias TH of a plurality of adjacent vias. According to this embodiment, external electrodes can be easily connected even on the first surface 111 of the base substrate 110, in which vias are formed with a diameter in nm or a distance between center points in nm.

[0048] More specifically, such as Figures 7 to 12As shown, according to an embodiment of the present application, the first electrode layer 120 is disposed on the first surface 111 and the second surface 112 of the substrate 110 and the inner wall surface of the plurality of through holes TH2; the first dielectric layer 130 is disposed on the first electrode layer 120 on the first surface 111 and the second surface 112 of the substrate 110 and the inner wall surface of the plurality of through holes TH2; the second electrode layer 140 is disposed on the first dielectric layer 130 on the first surface 111 and the second surface 112 of the substrate 110 and the inner wall surface of the plurality of through holes TH2; the first electrode pad 150 is connected to the first electrode layer 120; and the second electrode pad 160 is connected to the second electrode layer 140.

[0049] The capacitance of the capacitor can follow Equation 1 below.

[0050]

Equation 1

[0051] In Equation 1 above, C is the capacitance, ε is the dielectric constant, S is the area of the electrode layer, and d is the distance between the electrode layers. Thus, the capacitance can increase as the area of the electrode layer increases.

[0052] In this case, the first electrode layer 120 can include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), or indium tin. For example, the first electrode layer 120 can include at least one of TiN, TiO2, MoO x , WO x , ITO, or ITGO, where x is a positive integer.

[0053] In this way, when the first electrode layer 120 is disposed on the first surface 111 and the second surface 112 of the substrate 110 and the inner wall surface of the through hole TH2, the specific surface area of the capacitor increases, and thus a large capacity can be obtained. In addition, since gas can flow through the through hole TH2 during deposition of the first electrode layer 120, easy and uniform deposition can be achieved.

[0054] Next, the first dielectric layer 130 can include at least one of SiO2, Si3N3, SiN4, ZAZ, HfO2, ZrO2, Hf x Zr y O z , or Al2O3, where x, y, and z are positive integers. When the material of the first dielectric layer 130 satisfies these conditions, it is easy to deposit the first dielectric layer 130 having a uniform thickness on the first electrode layer 120.

[0055] Next, the second electrode layer 140 can include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium tin, copper (Cu), or aluminum (Al). For example, the second electrode layer 140 can include TiN, TiO2, MoOx , WO x , ITO, ITGO, Cu or Al, wherein x is a positive integer.

[0056] The material of the second electrode layer 140 can be the same as that of the first electrode layer 120, but is not limited thereto. That is, the material of the second electrode layer 140 can be different from that of the first electrode layer 120. For example, the first electrode layer 120 can be deposited by at least one of titanium (Ti), molybdenum (Mo), tungsten (W), or indium tin, and the second electrode layer 140 can be plated by copper or aluminum.

[0057] In this case, the first electrode layer 120 is disposed on the edge and the side surface 630 of the upper surface 610 of the base electrode 600, the first dielectric layer 130 is disposed on the first electrode layer 120, and the second electrode layer 140 is disposed on the first dielectric layer 130. Here, the first electrode layer 120 is in direct contact with the edge and the side surface 630 of the upper surface 610 of the base electrode 600, and the first electrode pad 150 is disposed on the upper surface 610 of the base electrode 600. According to this embodiment, the first electrode pad 150 can be easily disposed on the first surface 111 of the base substrate 110 in which the diameter of the via hole is formed in nm or the distance between the center points is formed in nm without a complicated process, and the first electrode layer 120 can be directly electrically connected to the first electrode pad 150 through the base electrode 600.

[0058] Here, the base electrode 600 can include the same material as the first electrode layer 120, or can include a different material. For example, the base electrode 600 can include at least one of chromium (Cr), copper (Cu), titanium (Ti), aluminum (Al), silver (Ag), or gold (Au), and can be disposed on the first surface 111 of the base substrate 110 by a deposition method. The base electrode 600 can be deposited on the first surface 111 of the base substrate 110 by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0059] According to an embodiment of the present application, the capacitor 100 further includes an insulating layer 400 disposed on the second electrode layer 140, the insulating layer 400 extending from an upper surface of the second electrode layer 140 along a side surface of the second electrode layer 140, a side surface of the first dielectric layer 130, a side surface of the first electrode layer 120 to an upper surface 610 of the base electrode 600 to be disposed between a side surface of the first electrode pad 150 and the side surface of the first electrode layer 120, the side surface of the first dielectric layer 130, and the side surface of the second electrode layer 140. According to an embodiment, the first electrode layer 120 is electrically connected to the first electrode pad 150 through the base electrode 600, and the second electrode layer 140 can be electrically insulated from the first electrode pad 150 by the insulating layer 400.

[0060] Meanwhile, according to an embodiment of the present application, the capacitor 100 further includes a second electrode pad 160 disposed on the second electrode layer 140 and electrically connected to the second electrode layer 140. When an area of the first surface 111 of the base substrate 110 in which the base electrode 600 is disposed is referred to as a first area 111A, an area of the first surface 111 of the base substrate 110 other than the first area, i.e., an area around the first area can be referred to as a second area. That is, when an area of the first surface 111 of the base substrate 110 in which the base electrode 600 is disposed is referred to as a first area, an area of the first surface 111 of the base substrate 110 in which the base electrode 600 is not disposed can be referred to as a second area. According to an embodiment of the present application, the second electrode pad 160 is disposed on the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 disposed in the second area in order. As described above, the insulating layer 400 is disposed on the second electrode layer 140. In order for the second electrode layer 140 and the second electrode pad 160 to be electrically connected, an opening can be formed in the insulating layer 400 disposed in the second area, and the second electrode pad 160 can be disposed in the opening so as to be in direct contact with the second electrode layer 140.

[0061] According to an embodiment of the present application, the thickness of the base electrode 600 can be 0.9 to 1.1 times, preferably 0.95 to 1.05 times, more preferably 0.975 to 1.025 times, of the sum of the thicknesses of the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 disposed in the second area. According to an embodiment, the first electrode pad 150 and the second electrode pad 160 can be disposed to have the same height with reference to the first surface 111 of the base substrate 110. According to this embodiment, when the capacitor 100 according to an embodiment of the present application is mounted on a printed circuit board, since it is not necessary to separately adjust the heights of the first electrode pad 150 and the second electrode pad 160, the assembly process can be improved, and in addition, the bonding force between the first electrode pad 150 and the second electrode pad 160 and the printed circuit board can be improved.

[0062] To achieve this, the thickness of the base electrode 600 can be 10 nm to 100 µm, preferably 10 nm to 50 µm, and more preferably 10 nm to 10 µm. According to this embodiment, when the capacitor 100 is mounted on a printed circuit board while stably supporting the first electrode pad 150 disposed on the base electrode 600, a high bonding force with the printed circuit board can be maintained.

[0063] According to an embodiment of the present application, in a state where the base electrode 600 is disposed on the first surface 111 of the base substrate 110, a material of the first electrode layer 120 can be deposited such that the first electrode layer 120 is disposed on the upper and side surfaces of the base electrode 600, the surface of the base substrate 110, and the inner wall surface of the through-hole TH2. The first electrode layer 120 can be deposited using, for example, an atomic layer deposition (ALD) process. When the ALD process is used, the material of the first electrode layer 120 can be conformally deposited on the upper and side surfaces of the base electrode 600, the surface of the base substrate 110, and the inner wall surface of the through-hole TH2 in atomic units. Accordingly, the first electrode layer 120 can be uniformly deposited on the upper and side surfaces of the base electrode 600, the surface of the base substrate 110, and the inner wall surface of the through-hole TH2.

[0064] Similarly, the first dielectric layer 130 can be deposited using, for example, an ALD process. According to an embodiment, the material of the first dielectric layer 130 can be conformally and uniformly deposited on the surface of the first electrode layer 120 in atomic units.

[0065] Further, the second electrode layer 140 can be deposited using, for example, an ALD process. According to an embodiment, the material of the second electrode layer 140 can be conformally deposited on the surface of the first dielectric layer 130 in atomic units. Alternatively, the second electrode layer 140 can be formed on the first dielectric layer 130 by an electroplating process. In this case, the second electrode layer 140 can include Cu or Al.

[0066] Further, the insulating layer 400 can be disposed on the second electrode layer 140.

[0067] As described above, with the base electrode 600 disposed on the first surface 111 of the substrate 110, since the first electrode layer 120, the first dielectric layer 130, the second electrode layer 130, and the insulating layer 400 are disposed, the via TH1 disposed below the base electrode 600 is hollow, and except for the via TH1 disposed below the base electrode 600, the other vias TH2 can be filled by the first electrode layer 120, the first dielectric layer 130, the second electrode layer 130, and the insulating layer 400. For example, the first electrode layer 120, the first dielectric layer 130, the second electrode layer 130, and the insulating layer 400 can be sequentially disposed on the inner wall surface of the other vias TH2 except for the via TH1 disposed below the base electrode 600.

[0068] Thus, when the insulating layer 400 is disposed on the second electrode layer 130, the thickness of the second electrode layer 130 can remain constant, thereby providing a capacitor with uniform electrical characteristics. Furthermore, when the insulating layer 400 is disposed on the second electrode layer 130 and fills the interior of the through-holes TH2, even if the temperature of the capacitor 100 increases, the multiple through-holes TH2 will not undergo thermal expansion, thereby providing a highly reliable capacitor 100. Optionally, the insulating layer 400 can be used as a passivation layer. For this purpose, the insulating layer 400 can contain Al2O3 or SiO2, or can include a resin composition with thermal and electrical insulating properties.

[0069] According to embodiments of the present invention, such as Figure 8 As shown, the lower surface 620 of the substrate electrode 600 may include a protrusion 622 that protrudes within the through-hole TH where the substrate electrode 600 is disposed, in a direction from the first surface 111 toward the second surface 112. According to this embodiment, since the substrate electrode 600 is stably fixed to the substrate 110, high reliability can be maintained even when the capacitor 100 is applied to an environment with frequent shaking or vibration. At least one of the shape or thickness of the protrusion 622 may vary depending on the deposition process conditions of the PVD or CVD method or the deposition material.

[0070] According to embodiments of the present invention, such as Figure 9As shown, the side surface 630 of the base electrode 600 can be disposed to be inclined with respect to the first surface 111 of the base substrate 110. Here, being disposed to be inclined with respect to the first surface 111 of the base substrate 110 can mean that the first surface 111 of the base substrate 110 and the side surface 630 of the base electrode 600 form an angle greater than 90° and less than 180°. For example, the first surface 111 of the base substrate 110 and the side surface 630 of the base electrode 600 can form an angle greater than 90° and less than 180°, greater than 100° and less than 150°, or greater than 110° and less than 130°. The angle between the first surface 111 of the base substrate 110 and the side surface 630 of the base electrode 600 can vary depending on the deposition process conditions or the deposition material of the PVD method or the CVD method of the base electrode 600. According to an embodiment, the first electrode layer 120 disposed on the side surface 630 of the base electrode 600 can also be disposed to be inclined with respect to the first surface 111 of the base substrate 110. Similarly, the first dielectric layer 130 and the second electrode layer 140 disposed on the side surface 630 of the base electrode 600 can also be disposed to be inclined with respect to the first surface 111 of the base substrate 110. According to this embodiment, since the areas of the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 disposed on the side surface 630 of the base electrode 600 increase, the capacitance can be improved, and the adhesion between the side surface 630 of the base electrode 600 and the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 can be improved. In addition, the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 can be deposited at a uniform thickness at the junction between the upper surface 610 of the base electrode 600 and the side surface 630 and at the junction between the side surface 630 of the base electrode 600 and the first surface 111 of the base substrate 110. When the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 are deposited at a uniform thickness, the resistance of the first electrode layer 120 and the second electrode layer 140 can be uniform, and a uniform capacitance can be obtained.

[0071] According to an embodiment of the present application, as Figure 10As shown, the side surface 630 of the base electrode 600 can include a recessed area. The shape of the side surface 630 of the base electrode 600 can vary depending on the deposition process conditions or deposition materials of the PVD method or the CVD method of the base electrode 600. According to an embodiment, the first electrode layer 120 disposed on the side surface 630 of the base electrode 600 can also be disposed along the recessed area of the side surface 630 of the base electrode 600. Similarly, the first dielectric layer 130 and the second electrode layer 140 disposed on the side surface 630 of the base electrode 600 can also be disposed along the recessed area of the side surface 630 of the base electrode 600. According to an embodiment, since the areas of the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 disposed on the side surface 630 of the base electrode 600 increase, the capacitance can increase, and the bonding force between the side surface 630 of the base electrode 600 and the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 can increase. In addition, the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 can be deposited at a uniform thickness at the junction between the upper surface 610 and the side surface 630 of the base electrode 600 and at the junction between the side surface 630 of the base electrode 600 and the first surface 111 of the base substrate 110.

[0072] According to an embodiment of the present application, as Figure 11 As shown, the side surface 630 of the base electrode 600 can include a recessed area, and the lower surface 620 of the base electrode 600 can include a protrusion 622 protruding from the first surface 111 toward the second surface 112 in the through-hole TH1. Although not shown, the side surface 630 of the base electrode 600 can be disposed to be inclined with respect to the first surface 111 of the base substrate 110, and the lower surface 620 of the base electrode 600 can include a protrusion 622 protruding from the first surface 111 toward the second surface 112 in the through-hole TH.

[0073] According to an embodiment of the present application, as Figure 12 As shown, a dielectric layer and an electrode layer can be alternately and additionally disposed on the second electrode layer 140. A second dielectric layer 180 is disposed on the second electrode layer 140.

[0074] In this case, the second dielectric layer 180 can include at least one of SiO2, Si3N3, SiN4, ZAZ, HfO2, ZrO2, Hf x Zr y O z or Al2O3, where x, y, and z are positive integers. When the material of the second dielectric layer 180 satisfies these conditions, it is easy to deposit the second dielectric layer 140 of a uniform thickness on the second electrode layer 140.

[0075] Next, a third electrode layer 190 is disposed on the second dielectric layer 180.

[0076] In this case, the third electrode layer 190 can include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium tin, copper (Cu), or aluminum (Al). For example, the third electrode layer 190 can include at least one of TiN, TiO2, MoO x , WO x , ITO, ITGO, Cu, or Al, where x is a positive integer.

[0077] The material of the third electrode layer 190 can be the same as that of the first electrode layer 120 and the second electrode layer 140, but is not limited thereto. That is, the material of the third electrode layer 190 can be different from that of the first electrode layer 120 and the second electrode layer 140. For example, the first electrode layer 120 and the second electrode layer 140 can include titanium (Ti), molybdenum (Mo), tungsten (W), and indium tin, and the third electrode layer 190 can include Cu or Al.

[0078] Figure 13 is an example of a method of manufacturing a base substrate according to an embodiment of the present application.

[0079] Referring to Figure 13 (a), an aluminum substrate is prepared. Here, the content of aluminum of the aluminum substrate can be 90% or more, preferably 99% or more, and more preferably 99.999% or more. In this case, the aluminum substrate can have a rough surface.

[0080] Referring to Figure 13 (b), the surface of the aluminum substrate is electrochemically polished. Accordingly, the surface of the aluminum substrate can be planarized.

[0081] Referring to Figure 13 (c), a first anodization process is performed on the planarized surface of the aluminum substrate. Accordingly, AAO can be grown on the aluminum substrate. In this case, the AAO can be grown through a wet process. According to this embodiment, AAO having a hole of a predetermined width can be grown on the aluminum substrate. In this case, the AAO grown through the first anodization process can not be uniform.

[0082] Referring to Figure 13 (d), the AAO on the aluminum substrate is removed through a wet etching process.

[0083] Referring to Figure 13(e) performing a secondary anodization process on the aluminum substrate from which the AAO has been removed by the primary anodization process. Accordingly, the AAO can be grown more uniformly on the aluminum substrate than the AAO grown in the primary anodization process. In this case, by controlling the solvent, temperature, time, and voltage of the secondary anodization process, the pore diameter of the AAO, the length of the AAO, etc. can be adjusted.

[0084] Referring to Figure 13 (f) removing the aluminum substrate by wet etching.

[0085] Referring to Figure 13 (g) removing the lower portion of the AAO, that is, the region in contact with the aluminum substrate, by wet etching.

[0086] Accordingly, the base substrate 110 including a plurality of through holes TH penetrating from the first surface 111 to the second surface 112 can be provided.

[0087] Thereafter, the base electrode 600 is provided on the first surface 111 of the base substrate 110; the first electrode layer 120, the first dielectric layer 130, and the second electrode layer 140 are sequentially deposited; the insulating layer 400 is provided; the first electrode pad 150 is connected to the base electrode 600 electrically connected to the first electrode layer 120; and the second electrode pad 160 is connected to the second electrode layer 140.

[0088] Here, a method of manufacturing a capacitor in which the base includes AAO has been mainly described, but embodiments of the present application are not limited thereto. The capacitor according to embodiments of the present application can also be a silicon-based capacitor in which the base includes silicon.

[0089] Although the foregoing description has been provided with reference to exemplary embodiments of the present application, it will be understood by those of ordinary skill in the art that various modifications and changes can be made without departing from the technical spirit and scope of the present application as set forth in the appended claims.

Claims

1. A capacitor, comprising: The substrate includes a plurality of through holes extending from a first surface to a second surface opposite to the first surface; A base electrode is disposed on the first surface to cover at least two adjacent through holes among the plurality of through holes; The first electrode layer is disposed on the upper surface edge and side surface of the substrate electrode; A dielectric layer is disposed on the first electrode layer; A second electrode layer is disposed on the dielectric layer; An insulating layer is disposed on the second electrode layer; as well as The first electrode pad is disposed on the upper surface of the substrate electrode. The insulating layer extends from the upper surface of the second electrode layer along the side surface of the second electrode layer, the side surface of the dielectric layer, and the side surface of the first electrode layer to the upper surface of the substrate electrode, and is disposed between the side surface of the first electrode pad and the side surface of the first electrode layer, the side surface of the dielectric layer, and the side surface of the second electrode layer.

2. The capacitor according to claim 1, wherein, The side surface of the base electrode is configured to be inclined relative to the first surface, and The first electrode layer disposed on the side surface of the substrate electrode is configured to be inclined relative to the first surface.

3. The capacitor according to claim 1, wherein, The side surface of the base electrode includes a recessed region, and The first electrode layer is disposed along the recessed region on the side surface of the substrate electrode.

4. The capacitor according to claim 1, wherein, The lower surface of the base electrode includes a protrusion that protrudes within the at least two through holes in a direction from the first surface toward the second surface.

5. The capacitor according to claim 1, wherein, The at least two through holes located below the substrate electrode are hollow.

6. The capacitor according to claim 5, wherein, The remaining vias, except for the at least two vias, are filled by the first electrode layer, the dielectric layer, the electrode layer, and the insulating layer.

7. The capacitor according to claim 6, wherein, The first electrode layer, the dielectric layer, the second electrode layer, and the insulating layer are sequentially disposed on the inner wall surface of the remaining through holes, excluding the at least two through holes.

8. The capacitor according to claim 1, wherein, The first electrode layer, the dielectric layer, and the second electrode layer are sequentially disposed on the first surface of the substrate in a second region surrounding the first region in which the substrate electrode is disposed. It also includes a second electrode pad disposed on the second electrode layer in the second region.

9. The capacitor according to claim 8, wherein, The thickness of the base electrode is 0.9 to 1.1 times the thickness of the first electrode layer, the dielectric layer, and the second electrode layer disposed in the second region.

10. The capacitor according to claim 1, wherein, The substrate is an anodized substrate of at least one of aluminum (Al), magnesium (Mg), zinc (Zn), titanium (Ti), tantalum (Ta), hafnium (Hf) or niobium (Nb).

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