Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate includes: a pixel driving circuit; the pixel driving circuit comprises a driving transistor and a compensation control transistor, and the display substrate comprises a first semiconductor layer, a second semiconductor layer and a fourth conductive layer which are arranged in sequence; an active layer of the driving transistor is located on the first semiconductor layer, an active layer of the compensation control transistor is located on the second semiconductor layer, and the active layer of the compensation control transistor comprises a middle part; the display substrate further comprises a second conductive connecting part and a first scanning signal line; the second conductive connecting part is used for connecting the first electrode of the compensation control transistor and the first electrode of the driving transistor; the first scanning signal line is electrically connected with the control electrode of the compensation control transistor; the overlapping width of the orthographic projection of the first scanning signal line and the second conductive connection part on the substrate in the second direction is smaller than the overlapping width of the orthographic projection of the first scanning signal line and the middle part of the compensation control transistor on the substrate in the second direction.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost, making them widely used in wearable display products. Optimizing pixel driving circuits to achieve low-frequency refresh rates and reduce power consumption in display products is one of the important research topics for developers.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising: a substrate; and a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, at least one of the sub-pixels including a pixel driving circuit and a light-emitting element, the light-emitting element emitting light under the drive of the pixel driving circuit, wherein the pixel driving circuit includes a driving transistor and a compensation control transistor; the display substrate includes: a first semiconductor layer disposed on the substrate, and a second semiconductor layer disposed on the side of the first semiconductor layer away from the substrate; the active layer of the driving transistor is located on the first semiconductor layer, and the active layer of the compensation control transistor is located on the second semiconductor layer; the active layer of the compensation control transistor includes a first end, a middle portion and a second end, the middle portion being located between the first end and the second end, the first end being electrically connected to a first electrode of the driving transistor, the second end being electrically connected to a control electrode of the driving transistor, and at least a portion of the middle portion being a channel region of the compensation control transistor;

[0006] The display substrate further includes: a fourth conductive layer disposed on the side of the second semiconductor layer away from the substrate; and a second conductive connection portion located in the fourth conductive layer;

[0007] One end of the second conductive connection is electrically connected to the first electrode of the compensation control transistor, and the other end of the second conductive connection is electrically connected to the first electrode of the driving transistor; and

[0008] The display substrate further includes a first scan signal line extending along a first direction, the first scan signal line being electrically connected to the control electrode of the compensation control transistor.

[0009] Wherein, the orthographic projection of the first scan signal line on the substrate at least partially overlaps with the orthographic projection of the second conductive connection portion on the substrate, and the overlapping portion of the orthographic projections of the first scan signal line and the second conductive connection portion on the substrate has a first overlap width in a second direction; and the orthographic projection of the first scan signal line on the substrate at least partially overlaps with the orthographic projection of the middle portion of the compensation control transistor on the substrate, and the overlapping portion of the orthographic projections of the first scan signal line and the middle portion of the compensation control transistor on the substrate has a second overlap width in a second direction.

[0010] Wherein, the first overlap width is smaller than the second overlap width.

[0011] According to some exemplary embodiments, the pixel driving circuit further includes a data writing transistor;

[0012] The display substrate further includes: a first conductive layer disposed between the first semiconductor layer and the second semiconductor layer; and a second scan signal line located in the first conductive layer and extending along a first direction, wherein the control electrode of the data writing transistor is electrically connected to the second scan signal line; and

[0013] The orthographic projection of the second conductive connection portion on the substrate overlaps at least partially with the orthographic projection of the second scanning signal line on the substrate.

[0014] According to some exemplary embodiments, the orthographic projection of the middle portion of the active layer of the compensation control transistor on the substrate at least partially overlaps with the orthographic projection of the second scan signal line on the substrate.

[0015] According to some exemplary embodiments, the display substrate includes: a first conductive portion located in the first conductive layer, and a first conductive connection portion located in the fourth conductive layer; the orthographic projection of the first conductive portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate, one end of the first conductive connection portion is electrically connected to the first conductive portion, and the other end of the first conductive connection portion is electrically connected to the second electrode of the compensation control transistor.

[0016] According to some exemplary embodiments, the orthographic projection of the second conductive connection portion on the substrate is spaced apart from the orthographic projection of the middle portion of the active layer of the compensation control transistor on the substrate.

[0017] According to some exemplary embodiments, the display substrate includes: a second conductive layer disposed on the side of the second semiconductor layer near the substrate, and a third conductive layer disposed on the side of the second semiconductor layer away from the substrate; the display substrate includes: a first sub-scan signal line located in the second conductive layer, and a second sub-scan signal line located in the third conductive layer; the first sub-scan signal line includes a first sub-body portion and a first sub-widening portion, the dimension of the first sub-widening portion in a second direction being larger than the dimension of the first sub-body portion in a second direction; the second sub-scan signal line includes a second sub-body portion and a second sub-widening portion, the dimension of the second sub-widening portion in a second direction being larger than the dimension of the second sub-body portion in a second direction; and the orthographic projection of the first sub-widening portion on the substrate at least partially overlaps with the orthographic projection of the channel region of the compensation control transistor on the substrate, and the orthographic projection of the second sub-widening portion on the substrate at least partially overlaps with the orthographic projection of the channel region of the compensation control transistor on the substrate.

[0018] According to some exemplary embodiments, the orthographic projection of the second conductive connection portion on the substrate overlaps with the orthographic projection of the first sub-part of the first sub-scan signal line on the substrate, and the first sub-part is spaced apart from the first sub-widening portion; and / or, the orthographic projection of the second conductive connection portion on the substrate overlaps with the orthographic projection of the second sub-scan signal line on the substrate, and the second sub-part is spaced apart from the second sub-widening portion.

[0019] According to some exemplary embodiments, the display substrate further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate; the display substrate includes: a first power signal line located in the fifth conductive layer, the first power signal line extending along a second direction; and a power signal connection portion located in the fourth conductive layer, the power signal connection portion being electrically connected to the first power signal line; and the power signal connection portion includes a connection body portion, a first branch portion, a second branch portion, and a third branch portion, the first branch portion extending from the connection body portion along a first direction, the second branch portion extending from the connection body portion along a direction parallel to the first conductive connection portion, and the third branch portion extending from the connection body portion along a second direction.

[0020] According to some exemplary embodiments, the first pole of the driving transistor includes a first sub-pole region located in the first semiconductor layer, the first sub-pole region extending along a second direction; and the orthographic projection of the first branch on the substrate at least partially overlaps with the orthographic projection of the first sub-pole region on the substrate.

[0021] According to some exemplary embodiments, the first power signal line includes a widened portion, the orthographic projection of the widened portion of the first power signal line on the substrate overlays the orthographic projection of the middle portion of the active layer of the compensation control transistor on the substrate.

[0022] According to some exemplary embodiments, the widened portions of the first power signal lines of two adjacent sub-pixels located in the same row are spaced apart in a first direction.

[0023] According to some exemplary embodiments, the plurality of sub-pixels includes a first sub-pixel located in the i-th row and j-th column, a second sub-pixel located in the i-th row and j+1-th column, and a third sub-pixel located in the i-th row and j+2-th column. The first sub-pixel, the second sub-pixel, and the third sub-pixel each include the pixel driving circuit, wherein i and j are both positive integers greater than or equal to 1. The display substrate includes a plurality of data signal lines disposed on the substrate. The plurality of data signal lines include a first data signal line for providing data signals to the first sub-pixel, a second data signal line for providing data signals to the second sub-pixel, and a third data signal line for providing data signals to the third sub-pixel. The first data line, the second data line, and the third data line extend along a second direction. In a first direction, the active layer of the compensation control transistor of the pixel driving circuit of the first sub-pixel is located between the first data line and the second data line, and the active layer of the compensation control transistor of the pixel driving circuit of the second sub-pixel is located between the second data line and the third data line.

[0024] According to some exemplary embodiments, the pixel driving circuit further includes a data writing transistor, the data writing transistor including a first electrode; the first data line is electrically connected to the first electrode of the data writing transistor of the pixel driving circuit of the first sub-pixel through a first via, the second data line is electrically connected to the first electrode of the data writing transistor of the pixel driving circuit of the second sub-pixel through a second via; and in a first direction, the active layer of the compensation control transistor of the pixel driving circuit of the first sub-pixel is spaced apart from the first via by a first distance, the active layer of the compensation control transistor of the pixel driving circuit of the first sub-pixel is spaced apart from the second via by a second distance, the ratio of the first distance to the second distance being between 0.8 and 1.2.

[0025] According to some exemplary embodiments, the display substrate includes: a first reset signal line located in the first conductive layer; and a second initialization signal line located in the fourth conductive layer; the pixel driving circuit includes a first initialization transistor and a second initialization transistor, the first initialization transistor including an active layer and a control electrode, the second initialization transistor including a first electrode, the orthographic projection of the first reset signal line on the substrate at least partially overlapping the orthographic projection of the active layer of the first initialization transistor on the substrate, the portion of the first reset signal line overlapping the active layer of the first initialization transistor forming the control electrode of the first initialization transistor, the first electrode of the second initialization transistor being electrically connected to the second initialization signal line; and the first reset signal line extending along a first direction, the second initialization signal line including a main body sub-part extending along the first direction and a transition sub-part extending along a second direction, the orthographic projection of the main body sub-part of the second initialization signal line on the substrate at least partially overlapping the orthographic projection of the first reset signal line on the substrate.

[0026] According to some exemplary embodiments, the display substrate includes: a second reset signal line located in the first conductive layer; and a third initialization signal line located in the third conductive layer; the pixel driving circuit includes a third initialization transistor, the third initialization transistor including an active layer, a control electrode and a first electrode, the orthographic projection of the second reset signal line on the substrate at least partially overlaps with the orthographic projection of the active layer of the third initialization transistor on the substrate, the portion of the second reset signal line overlapping with the active layer of the third initialization transistor forms the control electrode of the third initialization transistor, the first electrode of the third initialization transistor is electrically connected to the third initialization signal line; and the orthographic projection of the second reset signal line on the substrate at least partially overlaps with the orthographic projection of the third initialization signal line on the substrate.

[0027] According to some exemplary embodiments, the display substrate further includes a sixth conductive layer located on the side of the first semiconductor layer near the substrate; and the display substrate includes a main light-shielding portion located in the sixth conductive layer, wherein the orthographic projection of the main light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate, and the orthographic projection of the main light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the connection main portion of the power signal connection portion on the substrate.

[0028] According to some exemplary embodiments, the display substrate includes a first light-shielding portion located in the sixth conductive layer, the first light-shielding portion extending from the main light-shielding portion along a first direction, and the orthographic projection of the first light-shielding portion on the substrate at least partially overlapping the orthographic projection of the first branch of the power signal connection portion on the substrate; and / or, the display substrate includes a second light-shielding portion located in the sixth conductive layer, the second light-shielding portion extending from the main light-shielding portion along a second direction, and the orthographic projection of the second light-shielding portion on the substrate at least partially overlapping the orthographic projection of the second conductive connection portion on the substrate.

[0029] According to some exemplary embodiments, the pixel driving circuit includes a data writing transistor and a third initialization transistor, the data writing transistor including a second electrode, the third initialization transistor including a second electrode; the display substrate includes a third conductive connection portion located in the fourth conductive layer; one end of the third conductive connection portion is electrically connected to the second electrode of the data writing transistor, and the other end of the third conductive connection portion is electrically connected to the second electrode of the third initialization transistor; and the display substrate includes a third light-shielding portion located in the sixth conductive layer, the third light-shielding portion extending from the main light-shielding portion along a second direction, the orthographic projection of the third light-shielding portion on the substrate at least partially overlapping the orthographic projection of the third conductive connection portion on the substrate.

[0030] According to some exemplary embodiments, the data signal line includes a first sub-line, a second sub-line, and a third sub-line, the first sub-line and the third sub-line both extending along a second direction, the second sub-line located between the first sub-line and the third sub-line, the second sub-line extending along a third direction, the third direction intersecting both the first direction and the second direction; and the orthographic projection of the first sub-line on the substrate at least partially overlaps with the orthographic projection of the connection body portion of the power signal connection portion on the substrate; and / or, the orthographic projection of the first sub-line on the substrate at least partially overlaps with the orthographic projection of the third branch portion of the power signal connection portion on the substrate.

[0031] According to some exemplary embodiments, the pixel driving circuit includes a first initialization transistor, the first initialization transistor including an active layer; and the orthographic projection of the third sub-line on the substrate at least partially overlaps with the orthographic projection of the active layer of the first initialization transistor on the substrate.

[0032] According to some exemplary embodiments, the display substrate includes: a first power signal line and a data signal line located in the fifth conductive layer, both the first power signal line and the data signal line extending along a second direction; the display substrate includes a seventh conductive layer located on the side of the fifth conductive layer away from the substrate, the light-emitting element includes a first electrode located in the seventh conductive layer; and for sub-pixels located in the same column, the first electrode of the light-emitting element of each sub-pixel includes a first end and a second end, the first end and the second end being opposite ends of the first electrode in a first direction, the orthographic projection of one of the first power signal line and the data signal line on the substrate at least partially overlaps with the orthographic projection of the first end of the first electrode on the substrate, and the orthographic projection of the other of the first power signal line and the data signal line on the substrate at least partially overlaps with the orthographic projection of the second end of the first electrode on the substrate.

[0033] According to some exemplary embodiments, the display substrate includes an eighth conductive layer located on the side of the seventh conductive layer away from the substrate, and the display substrate includes touch traces located in the eighth conductive layer; the touch traces include a first touch sub-trace extending along a first direction, and the orthographic projection of the first touch sub-trace on the substrate at least partially overlaps with the orthographic projection of the second initialization signal line on the substrate; and / or, the touch traces include a second touch sub-trace extending along the first direction, and the orthographic projection of the second touch sub-trace on the substrate at least partially overlaps with the orthographic projection of the power signal connection portion on the substrate.

[0034] According to some exemplary embodiments, the touch trace includes a third touch sub-trace extending along a second direction, the orthographic projection of the third touch sub-trace on the substrate at least partially overlapping the orthographic projection of the second conductive connection portion on the substrate; and / or, the touch trace includes a fourth touch sub-trace extending along the second direction, the orthographic projection of the fourth touch sub-trace on the substrate at least partially overlapping the orthographic projection of the first sub-polar region on the substrate.

[0035] According to some exemplary embodiments, the first semiconductor layer comprises a polycrystalline silicon semiconductor material, and the second semiconductor layer comprises an oxide semiconductor material.

[0036] In another aspect, a display substrate is provided, wherein the display substrate includes: a substrate; a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, at least one of the sub-pixels including a pixel driving circuit and a light-emitting element, the light-emitting element emitting light under the drive of the pixel driving circuit; a plurality of data signal lines disposed on the substrate, the plurality of data signal lines being used to provide data signals to N columns of sub-pixels respectively, wherein N is a positive integer greater than or equal to 2, wherein the pixel driving circuit includes a driving transistor and a compensation control transistor, the driving transistor including an active layer, a control electrode and a first electrode, the compensation control transistor including an active layer, a first electrode and a second electrode, the control electrode of the driving transistor being connected to the compensation control transistor. The second electrode of the driving transistor is electrically connected, and the first electrode of the driving transistor is electrically connected to the first electrode of the compensation control transistor. The display substrate includes: a first semiconductor layer disposed on the substrate, and a second semiconductor layer disposed on the side of the first semiconductor layer away from the substrate. The active layer of the driving transistor is located on the first semiconductor layer, and the active layer of the compensation control transistor is located on the second semiconductor layer. For multiple sub-pixels located in the same row, the active layers of the compensation control transistors of the pixel driving circuit of the j-th column sub-pixel are all located in the first direction between one data signal line providing data signal lines to the j-th column sub-pixel and another data signal line providing data signal lines to the (j+1)-th column sub-pixel, where j is a positive integer greater than or equal to 1 and less than N.

[0037] In another aspect, a display device is provided, comprising a display substrate as described in any of the preceding claims. Attached Figure Description

[0038] The features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0039] Figure 1 is a plan view of a display device according to some embodiments of the present disclosure;

[0040] Figure 2 is a schematic diagram of the structure of a sub-pixel according to some embodiments of the present disclosure;

[0041] Figure 3 is an equivalent circuit of a pixel driving circuit according to some embodiments of the present disclosure;

[0042] Figure 4 is a schematic diagram of the structure of a single pixel driving circuit according to some exemplary embodiments of the present disclosure;

[0043] Figure 5 is a schematic planar structure of the sixth conductive layer in the pixel driving circuit of the exemplary embodiment of Figure 4;

[0044] Figure 6 is a schematic planar structure of the first semiconductor layer in the pixel driving circuit of the exemplary embodiment of Figure 4;

[0045] Figure 7 is a schematic planar structure of the first conductive layer in the pixel driving circuit of the exemplary embodiment of Figure 4;

[0046] Figure 8 is a schematic planar structure of the second conductive layer in the pixel driving circuit of the exemplary embodiment of Figure 4;

[0047] Figure 9 is a schematic planar structure of the combined film layer of the second semiconductor layer and the third conductive layer in the pixel driving circuit of the exemplary embodiment of Figure 4.

[0048] Figure 10 is a schematic planar structure diagram of the fourth conductive layer in the pixel driving circuit of the exemplary embodiment of Figure 4;

[0049] Figure 11 is a schematic planar structure of the fifth conductive layer in the pixel driving circuit of the exemplary embodiment of Figure 4;

[0050] Figure 12 is a partial structural schematic diagram of a plurality of pixel driving circuits according to some exemplary embodiments of the present disclosure;

[0051] Figure 13A is a partial planar schematic diagram of the film layers of two pixel driving circuits located in the same row according to an embodiment of the present disclosure, including a first semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;

[0052] Figure 13B is a partial planar schematic diagram of the film layers of two pixel driving circuits located in the same row according to an embodiment of the present disclosure, including a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;

[0053] Figure 14 is a partial planar schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, including a first conductive layer, a third conductive layer and a fourth conductive layer;

[0054] Figure 15 is a partial planar schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, including a second conductive layer, a fourth conductive layer and a sixth conductive layer;

[0055] Figure 16 is a partial planar schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, including a first semiconductor layer, a fourth conductive layer and a fifth conductive layer;

[0056] Figure 17 is a partial planar schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, including a fifth conductive layer and a seventh conductive layer;

[0057] Figure 18 is a partial planar schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0059] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0060] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0061] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0062] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0063] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0064] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0065] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimensions along the light-emitting direction of the display substrate, or the dimensions along the normal direction of the display device.

[0066] In this document, the term "transistor" can refer to a bipolar junction transistor (BJT), a thin-film transistor (TFT), a field-effect transistor (FET), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of a transistor other than the control terminal, one terminal is referred to as the first terminal, and the other as the second terminal. In actual operation, when the transistor is a TFT or a FET, the first terminal can be the drain, and the second terminal can be the source; alternatively, the first terminal can be the source, and the second terminal can be the drain.

[0067] This disclosure provides at least one display substrate. The display substrate includes: a substrate; and a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction. At least one sub-pixel includes a pixel driving circuit and a light-emitting element. The light-emitting element emits light under the drive of the pixel driving circuit. The pixel driving circuit includes a driving transistor, a compensation control transistor, and a data writing transistor. The driving transistor includes an active layer, a control electrode, and a first electrode. The compensation control transistor includes an active layer, a first electrode, and a second electrode. The control electrode of the driving transistor is electrically connected to the second electrode of the compensation control transistor, and the first electrode of the driving transistor is electrically connected to the first electrode of the compensation control transistor. The display substrate includes: a first semiconductor layer disposed on the substrate, and a second semiconductor layer disposed on the side of the first semiconductor layer away from the substrate. The active layer of the driving transistor is located on the first semiconductor layer, and the active layer of the compensation control transistor is located on the second semiconductor layer. The active layer of the compensation control transistor includes a first end, a middle portion, and a second end, with the middle portion located between the first and second ends. The first end is electrically connected to the first electrode of the driving transistor, and the second end is electrically connected to the control electrode of the driving transistor. At least a portion of the middle portion forms the channel region of the compensation control transistor. The display substrate further includes a first conductive layer disposed between a first semiconductor layer and a second semiconductor layer, and a fourth conductive layer disposed on the side of the second semiconductor layer away from the substrate. The display substrate includes a second scan signal line located in the first conductive layer and extending along a first direction, and a second conductive connection portion located in the fourth conductive layer. The control electrode of the data writing transistor is electrically connected to the second scan signal line. One end of the second conductive connection portion is electrically connected to the first electrode of the compensation control transistor, and the other end of the second conductive connection portion is electrically connected to the first electrode of the driving transistor. The orthographic projection of the second conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the second scan signal line on the substrate.

[0068] By connecting the first electrode of the compensation control transistor and the first electrode of the driving transistor using the second conductive connection, the active layer of the compensation control transistor can be designed more flexibly. For example, by placing the active layer of the compensation control transistor at the center of the pixel and designing the channel region in the active layer of the compensation control transistor in a vertical shape, the parasitic capacitance near the compensation control transistor can be reduced, resulting in a lower black state voltage value for the display substrate, better low grayscale image quality, and improved display effect of the display substrate.

[0069] Figure 1 is a plan view of a display device according to some embodiments of the present disclosure. For example, the display device may be an OLED display device.

[0070] Referring to FIG1, the display device 1000 may include a display substrate 1100, a gate driver 1200, a data driver 1300, a controller 1400, and a voltage generator 1500. The display substrate 1100 may include a substrate 1, wherein the substrate 1 includes a display area AA and a non-display area NA. The display substrate 1100 may further include a plurality of sub-pixels PX disposed on the substrate 1. The plurality of sub-pixels PX are arranged in an array along a first direction X and a second direction Y in the display area AA. At least one sub-pixel PX includes a pixel driving circuit 101 and a light-emitting element L, the light-emitting element L emitting light under the drive of the pixel driving circuit 101. The signal generated by the gate driver 1200 can be applied to the sub-pixel PX through, for example, a scan signal line GL, and the signal generated by the data driver 1300 can be applied to the sub-pixel PX through, for example, a data signal line DL. For example, a first voltage VDD and a second voltage VSS can be applied to the sub-pixel PX. For example, the first voltage VDD may be higher than, for example, the second voltage VSS. Optionally, a first voltage, such as VDD, can be applied to the anode of the light-emitting element (e.g., OLED), and a second voltage, such as VSS, can be applied to the cathode of the light-emitting element, so that the light-emitting element can emit light.

[0071] For example, multiple sub-pixels PX can include red sub-pixels, green sub-pixels, and blue sub-pixels. Alternatively, multiple sub-pixels PX can include white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels.

[0072] It should be noted that the figure exemplifies a rectangular shape for the orthographic projection of a subpixel onto the substrate. However, the embodiments of this disclosure are not limited to this. For example, the shape of the orthographic projection of a subpixel onto the substrate can be a rounded rectangle, hexagon, pentagon, square, circle, or other shapes. Although in the illustrated embodiment, the first direction X and the second direction Y are perpendicular to each other, the embodiments of this disclosure are not limited to this.

[0073] It should be understood that in the embodiments of this disclosure, each sub-pixel includes a pixel driving circuit and a light-emitting element. For example, the light-emitting element may be an OLED light-emitting element, including a stacked anode, a light-emitting layer, and a cathode. The pixel driving circuit may include a plurality of thin-film transistors and at least one storage capacitor.

[0074] Figure 2 is a schematic diagram of the structure of a sub-pixel according to some embodiments of the present disclosure.

[0075] As shown in Figure 2, each sub-pixel PX may include: a light-emitting element L and a pixel driving circuit 101 coupled to the light-emitting element L. The pixel driving circuit 101 is configured to provide a driving current to the light-emitting element L to drive the light-emitting element L to operate (i.e. emit light).

[0076] For example, continuing to refer to FIG2, the first electrode of the light-emitting element L is coupled to the pixel driving circuit 101, and the second electrode of the light-emitting element L is coupled to the second power signal line VSS. The second power signal line VSS is configured to transmit a second voltage. The second voltage can be a DC reference voltage, for example, the second voltage VSS is -3V. Alternatively, the second voltage VSS is 0V, that is, the second power signal line VSS is grounded. The second power signal line VSS only needs to provide a 0V or negative voltage to the second electrode of the light-emitting element L.

[0077] Exemplarily, the light-emitting element L includes a current-driven element. Further, the light-emitting element L can be a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), a quantum light-emitting diode (QLED), or an organic light-emitting diode (OLED). Exemplarily, the first electrode and the second electrode of the light-emitting element L are the anode and cathode of the light-emitting diode, respectively.

[0078] Figure 3 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. It should be noted that in the following description, an 8T1C pixel driving circuit is used as an example to describe the structure of the pixel driving circuit in detail. However, the embodiments of the present disclosure are not limited to the 8T1C pixel driving circuit, and other known pixel driving circuit structures can be applied to the embodiments of the present disclosure unless otherwise specified.

[0079] As shown in Figure 3, the pixel driving circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst.

[0080] The pixel driving circuit is connected to 10 signal lines (first scan signal line GL1, second scan signal line GL2, first reset signal line Re1, second reset signal line Re2, light emission signal line EM, first initial signal line Vi1, second initial signal line Vi2, third initial signal line Vi3, data signal line DL, and first power signal line VDD).

[0081] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second terminal of the second transistor T2, the control terminal of the third transistor T3, and the first terminal of the storage capacitor Cst. The second node N2 is connected to the second terminals of the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8. The third node N3 is connected to the second terminals of the first transistor T1, the second transistor T2, the third transistor T3, and the sixth transistor T6. The fourth node N4 is connected to the second terminals of the sixth transistor T6 and the seventh transistor T7, and is also connected to the anode of the light-emitting device L.

[0082] In an exemplary embodiment, the first end of the storage capacitor Cst is connected to the first node N1, and the second end of the storage capacitor Cst is connected to the first power signal line VDD.

[0083] In an exemplary embodiment, the first transistor T1 may be referred to as the first initialization transistor. The control electrode of the first transistor T1 is connected to the first reset signal line Re1, the first electrode of the first transistor T1 is connected to the first initial signal line Vi1, and the second electrode of the first transistor T1 is connected to the third node N3.

[0084] The second transistor T2 can be called a compensation control transistor. The control electrode of the second transistor T2 is connected to the first scan signal line GL1, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1.

[0085] The third transistor T3 can be called the driving transistor. The control electrode of the third transistor T3 is connected to the first node N1, that is, the control electrode of the third transistor T3 is connected to the first terminal of the storage capacitor Cst. The second electrode of the third transistor T3 is connected to the second node N2, and the first electrode of the third transistor T3 is connected to the third node N3.

[0086] The fourth transistor T4 can be called the data write transistor. Its control electrode is connected to the second scan signal line GL2, its first electrode is connected to the data signal line DL, and its second electrode is connected to the second node N2. The fifth transistor T5 can be called the first light-emitting control transistor. Its control electrode is connected to the light-emitting control signal line EM, its first electrode is connected to the first power supply signal line VDD, and its second electrode is connected to the second node N2. The sixth transistor T6 can be called the second light-emitting control transistor. Its control electrode is connected to the light-emitting control signal line EM, its first electrode is connected to the third node N3, and its second electrode is connected to the fourth node N4. The seventh transistor T7 can be called the second initialization transistor. Its control electrode is connected to the second reset signal line Re2, its first electrode is connected to the second initialization signal line Vi2, and its second electrode is connected to the fourth node N4. The eighth transistor T8 can be called the third initialization transistor. The control electrode of the eighth transistor T8 is connected to the second reset signal line Re2, the first electrode of the eighth transistor T8 is connected to the third initial signal line Vi3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0087] In an exemplary embodiment, the light-emitting device L may be an OLED, including a stacked anode (first electrode), an organic light-emitting layer, and a cathode (second electrode), or it may be a QLED, including a stacked anode (first electrode), a quantum dot light-emitting layer, and a cathode (second electrode).

[0088] In an exemplary embodiment, the first electrode of the light-emitting device L is connected to the fourth node N4, and the second electrode of the light-emitting device L is connected to the second power signal line VSS. The signal of the second power signal line VSS can be a continuously provided low-level signal, and the signal of the first power signal line VDD can be a continuously provided high-level signal.

[0089] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include both P-type and N-type transistors.

[0090] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be a low-temperature polysilicon transistor (LTPS), an oxide transistor, or a combination of LTPS and metal-oxide transistors. The active layer of the LTPS transistor is made of low-temperature polysilicon (LTPS), while the active layer of the metal-oxide transistor is made of metal-oxide semiconductor (Oxide). LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and metal-oxide transistors onto a single display substrate to form a LTPS display substrate allows for the utilization of both advantages, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0091] FIG4 is a schematic diagram of the structure of a single pixel driving circuit according to some exemplary embodiments of the present disclosure; FIG5 is a schematic diagram of the planar structure of the sixth conductive layer in the pixel driving circuit of the exemplary embodiment of FIG4; FIG6 is a schematic diagram of the planar structure of the first semiconductor layer in the pixel driving circuit of the exemplary embodiment of FIG4; FIG7 is a schematic diagram of the planar structure of the first conductive layer in the pixel driving circuit of the exemplary embodiment of FIG4; FIG8 is a schematic diagram of the planar structure of the second conductive layer in the pixel driving circuit of the exemplary embodiment of FIG4; FIG9 is a schematic diagram of the planar structure of the combined film layer of the second semiconductor layer and the third conductive layer in the pixel driving circuit of the exemplary embodiment of FIG4; FIG10 is a schematic diagram of the planar structure of the fourth conductive layer in the pixel driving circuit of the exemplary embodiment of FIG4; FIG11 is a schematic diagram of the planar structure of the fifth conductive layer in the pixel driving circuit of the exemplary embodiment of FIG4; FIG12 is a partial structural schematic diagram of multiple pixel driving circuits according to some exemplary embodiments of the present disclosure.

[0092] For example, referring to Figures 4-11, the display substrate may include: a first semiconductor layer 3 disposed on a substrate 1 (as shown in Figure 6), and a second semiconductor layer 6 disposed on the side of the first semiconductor layer 3 away from the substrate 1 (as shown in Figure 9). Multiple transistors in the pixel driving circuit may include active layers. For example, the driving transistor T3 includes an active layer ACT3, and the compensation control transistor T2 includes an active layer ACT2.

[0093] For example, the first semiconductor layer 3 may include a polycrystalline silicon semiconductor material, and the second semiconductor layer 6 may include an oxide semiconductor material.

[0094] The active layer ACT3 of the driving transistor T3 is located in the first semiconductor layer 3, and the active layer ACT2 of the compensation control transistor T2 is located in the second semiconductor layer 6. The active layer ACT2 of the compensation control transistor T2 includes a first end ACT21, a middle portion ACT22, and a second end ACT23. The middle portion ACT22 is located between the first end ACT21 and the second end ACT23. The first end ACT21 is electrically connected to the first electrode S3 of the driving transistor T3, and the second end ACT23 is electrically connected to the control electrode G3 of the driving transistor T3. At least a portion of the middle portion ACT22 forms the channel region of the compensation control transistor T2. The middle portion of the active layer ACT2 of the compensation control transistor T2 extends linearly along the second direction Y.

[0095] For example, in an embodiment of this disclosure, referring to FIG12, a plurality of sub-pixels PX may include a first sub-pixel SP1 located in the i-th row and j-th column, a second sub-pixel SP2 located in the i-th row and j+1-th column, and a third sub-pixel SP3 located in the i-th row and j+2-th column. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 each include a pixel driving circuit, wherein i and j are both positive integers greater than or equal to 1.

[0096] The display substrate may include a plurality of data signal lines disposed on the substrate. For example, the plurality of data signal lines may include a first data signal line DL1 for providing a data signal to a first sub-pixel SP1, a second data signal line DL2 for providing a data signal to a second sub-pixel SP2, and a third data signal line DL3 for providing a data signal to a third sub-pixel SP3. The first data line DL1, the second data line DL2, and the third data line DL3 extend along a second direction.

[0097] In the first direction X, the active layer ACT2-1 of the compensation control transistor T2-1 of the pixel driving circuit of the first sub-pixel SP1 is located between the first data line DL1 and the second data line DL2. The active layer ACT2-2 of the compensation control transistor T2-2 of the pixel driving circuit of the second sub-pixel SP2 is located between the second data line DL2 and the third data line DL3.

[0098] Exemplarily, in embodiments of this disclosure, the pixel driving circuit may further include a data writing transistor. The data writing transistor includes a first terminal. Referring to FIG12, the first data line DL1 is electrically connected to the first terminal S41 of the data writing transistor T4-1 of the pixel driving circuit of the first sub-pixel SP1 through a first via VH1. The second data line DL2 is electrically connected to the first terminal S42 of the data writing transistor T4-2 of the pixel driving circuit of the second sub-pixel SP2 through a second via VH2.

[0099] For example, in the first direction X, the active layer ACT2-1 of the compensation control transistor T2-1 of the pixel driving circuit of the first sub-pixel SP1 is spaced by a first distance d1 from the first via VH1. The active layer ACT2-1 of the compensation control transistor T2-1 of the pixel driving circuit of the first sub-pixel SP1 is spaced by a second distance d2 from the second via VH2. The ratio of the first distance d1 to the second distance d2 is between 0.8 and 1.2.

[0100] In some exemplary embodiments, the first distance d1 can be equal to the second distance d2. By placing the active layer of the compensation control transistor at the center of the pixel and designing the channel region in the active layer of the compensation control transistor to be vertical, the parasitic capacitance near the compensation control transistor can be reduced, resulting in a lower black state voltage value for the display substrate, better low grayscale image quality, and improved display effect of the display substrate.

[0101] Exemplary, in embodiments of this disclosure, referring to Figures 4-10, the display substrate may include a first conductive layer 4 disposed between a first semiconductor layer 3 and a second semiconductor layer 6, and a fourth conductive layer 8 disposed on the side of the second semiconductor layer away from the substrate. The display substrate may include a first conductive portion 41 located in the first conductive layer 4, and a first conductive connection portion 81 located in the fourth conductive layer 8. The orthographic projection of the first conductive portion 41 onto the substrate at least partially overlaps with the orthographic projection of the active layer ACT3 of the driving transistor T3 onto the substrate. One end of the first conductive connection portion 81 is electrically connected to the first conductive portion 41, and the other end of the first conductive connection portion 81 is electrically connected to the second electrode D2 of the compensation control transistor T2. The orthographic projection of the active layer ACT2 of the compensation control transistor T2 onto the substrate is at least partially aligned with the orthographic projection of the first conductive connection portion 81 onto the substrate in the second direction Y. By designing the active layer of the compensation control transistor at the center of the pixel, the first conductive connection part electrically connected to the active layer of the compensation control transistor can also be designed at the center of the pixel. This can increase the distance between the first conductive connection part and the data signal line, reduce parasitic capacitance, prevent crosstalk between signal lines, and thus improve the driving effect of the pixel unit.

[0102] By way of example, in an embodiment of this disclosure, continuing to refer to Figures 4-10, the display substrate may include a second conductive connection portion 82 located in the fourth conductive layer 8. One end of the second conductive connection portion 82 is electrically connected to the first electrode S2 of the compensation control transistor T2, and the other end of the second conductive connection portion 82 is electrically connected to the first electrode S3 of the driving transistor T3.

[0103] The data writing transistor T4 includes an active layer ACT4 and a control electrode G4. The display substrate includes a second scan signal line GL2 located in the first conductive layer 4, and the second scan signal line GL2 extends along a first direction. The orthographic projection of the active layer ACT4 of the data writing transistor T4 onto the substrate at least partially overlaps with the orthographic projection of the second scan signal line GL2 onto the substrate. The portion of the second scan signal line GL2 overlapping with the active layer ACT4 of the data writing transistor T4 constitutes the control electrode G4 of the data writing transistor T4.

[0104] The orthographic projection of the second conductive connection portion 82 on the substrate at least partially overlaps with the orthographic projection of the second scan signal line GL2 on the substrate. The orthographic projection of the second conductive connection portion 82 on the substrate is spaced apart from the orthographic projection of the middle portion ACT22 of the active layer of the compensation control transistor T2 on the substrate. The fact that the second conductive connection portion and the middle portion ACT22 of the active layer of the compensation control transistor T2 do not overlap reduces the impact of parasitic capacitance on the control electrode G3 (i.e., the first node N1) of the driving transistor T3, thus improving the stability of the pixel driving circuit.

[0105] By using the second conductive connection portion 82 to connect the first electrode S2 of the compensation control transistor T2 and the first electrode S3 of the driving transistor T3, the active layer ACT2 of the compensation control transistor T2 can be designed more flexibly. For example, by placing the active layer ACT2 of the compensation control transistor T2 at the center of the pixel and designing the channel region in the active layer ACT2 of the compensation control transistor T2 in a vertical shape, the parasitic capacitance near the compensation control transistor can be reduced, resulting in a lower black state voltage value for the display substrate, better low grayscale image quality, and improved display effect of the display substrate.

[0106] Exemplarily, in embodiments of this disclosure, referring to Figures 4 and 6-9, the display substrate may include: a second conductive layer 5 disposed on the side of the second semiconductor layer 6 near the substrate, and a third conductive layer 7 disposed on the side of the second semiconductor layer 6 away from the substrate. The display substrate may also include a first scan signal line GL1. The first scan signal line GL1 may include: a first sub-scan signal line gl11 located in the second conductive layer 5, and a second sub-scan signal line gl12 located in the third conductive layer 7. The first sub-scan signal line gl11 and the second sub-scan signal line gl12 can be used to transmit a first scan signal. The first sub-scan signal line gl11 includes a first sub-body portion 51 and a first sub-widening portion 52. The dimension d4 of the first sub-widening portion 52 in the second direction is greater than the dimension d3 of the first sub-body portion 51 in the second direction. The second sub-scan signal line gl12 includes a second sub-body portion 71 and a second sub-widening portion 72, and the dimension d6 of the second sub-widening portion in the second direction is greater than the dimension d5 of the second sub-body portion in the second direction.

[0107] For example, the orthographic projection of the first scan signal line GL1 on the substrate at least partially overlaps with the orthographic projection of the second conductive connection portion 82 on the substrate, and the overlapping portion of the projections of the first scan signal line GL1 and the second conductive connection portion 82 on the substrate has a first overlap width in the second direction. For example, referring to Figures 4, 8, and 9, the first scan signal line GL1 includes a first sub-scan signal line gl11 and a second sub-scan signal line gl12. The orthographic projection of the first sub-body portion 51 of the first sub-scan signal line gl11 on the substrate partially overlaps with the orthographic projection of the second conductive connection portion 82 on the substrate, and the overlapping portion of the projections of the first sub-body portion 51 and the second conductive connection portion 82 on the substrate has an overlap width in the second direction equal to the dimension d3 of the first sub-body portion 51 in the second direction. The orthographic projection of the second sub-body portion 71 of the second sub-scan signal line gl12 onto the substrate overlaps with the orthographic projection of the second conductive connection portion 82 onto the substrate. The overlap width of the projections of the second sub-body portion 71 and the second conductive connection portion 82 onto the substrate in the second direction is equal to the width d5 ​​of the second sub-body portion 71 in the second direction.

[0108] Referring again to Figures 4, 8, and 9, the orthographic projection of the first scan signal line GL1 on the substrate at least partially overlaps with the orthographic projection of the middle portion ACT22 of the compensation control transistor T2 on the substrate. The overlapping portion of the orthographic projections of the first scan signal line GL1 and the middle portion ACT2 of the compensation control transistor on the substrate has a second overlap width in the second direction. For example, the first sub-widened portion 52 of the first sub-scan signal line GL11 overlaps with the orthographic projection of the middle portion ACT22 of the compensation control transistor T2 on the substrate, and the overlap width of the projections of the first sub-widened portion 52 and the middle portion ACT22 of the compensation control transistor T2 on the substrate in the second direction is equal to the dimension d4 of the first sub-widened portion 52 in the second direction. The orthographic projection of the second sub-widening portion 72 of the second sub-scan signal line gl12 onto the substrate overlaps with the orthographic projection of the middle portion ACT22 of the compensation control transistor T2 onto the substrate. The overlapping width of the projection of the second sub-widening portion 72 and the orthographic projection of the middle portion ACT22 of the compensation control transistor T2 onto the substrate in the second direction is equal to the width d6 of the second sub-widening portion 72 in the second direction.

[0109] For example, the first overlap width is equal to the dimension d3 of the first sub-body portion 51 in the second direction; or, the first overlap width is equal to the width d5 ​​of the second sub-body portion 71 in the second direction. The second overlap width is equal to the dimension d4 of the first sub-widened portion 52 in the second direction; or, the second overlap width is equal to the width d6 of the second sub-widened portion 72 in the second direction. Wherein, d3 is less than d4, and d5 is less than d6. That is, the first overlap width is less than the second overlap width.

[0110] This design reduces the parasitic capacitance between the first scan signal line and the third node N3, improving reliability ripples.

[0111] The compensation control transistor T2 can adopt a dual-gate design. By designing the first sub-widening section and the second sub-widening section, the area of ​​the control electrode of the compensation control transistor T2 is increased, which is beneficial to improving the stability of the compensation control transistor.

[0112] For example, referring to Figures 4, 7, and 9, the orthographic projection of the middle portion ACT22 of the active layer of the compensation control transistor T2 onto the substrate at least partially overlaps with the orthographic projection of the second scan signal line GL2 onto the substrate. At least a portion of the middle portion ACT22 of the active layer of the compensation control transistor T2 constitutes the channel region of the active layer of the compensation control transistor T2. That is, the channel region of the active layer of the compensation control transistor T2 can overlap with the first sub-scan signal line gl11, the second sub-scan signal line gl12, and the second scan signal line GL2. The first sub-scan signal line gl11 and the second sub-scan signal line gl12 provide a first scan signal, and the second scan signal line GL2 provides a second scan signal. The first scan signal and the second scan signal can be inversely related signals, thereby canceling out the parasitic capacitance acting on the channel of the compensation control transistor T2, which is beneficial for improving the stability of the compensation control transistor.

[0113] By way of example, in an embodiment of this disclosure, referring to Figures 4, 8 and 9, the first sub-scan signal line gl11 may further include a first sub-part 511. The orthographic projection of the second conductive connection portion 82 on the substrate overlaps with the orthographic projection of the first sub-part 511 of the first sub-scan signal line on the substrate, and the first sub-part 511 and the first sub-widening portion 52 are spaced apart.

[0114] The second sub-scan signal line gl12 may further include a second sub-part 711. The orthographic projection of the second conductive connection portion 82 on the substrate overlaps with the orthographic projection of the second sub-part 711 of the second sub-scan signal line gl12 on the substrate, and the second sub-part 711 and the second sub-widening portion 72 are spaced apart. The third node N3 may be located in the second conductive connection portion 82.

[0115] The projections of the second conductive connection portion and the channel region of the compensation control transistor onto the substrate do not overlap. This results in a smaller overlap capacitance between the second conductive connection portion and the first and second sub-scan signal lines, improving reliability ripples and optimizing temperature drift. Furthermore, the second conductive connection portion can serve as the second electrode (source) of the compensation control transistor, and the reduced overlap capacitance further enhances the stability of the compensation control transistor.

[0116] Exemplary, in embodiments of this disclosure, referring to Figures 4, 10, and 11, the display substrate may further include a fifth conductive layer 9 located on the side of the fourth conductive layer 8 away from the substrate. The display substrate may include a first power signal line VDD located in the fifth conductive layer 9. The first power signal line VDD extends along a second direction Y. The display substrate may further include a power signal connection portion 83 located in the fourth conductive layer, the power signal connection portion 83 being electrically connected to the first power signal line VDD. The power signal connection portion 83 includes a connection body portion 831, a first branch portion 832, a second branch portion 833, and a third branch portion 834. The first branch portion 832 extends from the connection body portion 831 along a first direction, the second branch portion 833 extends from the connection body portion along a direction parallel to the first conductive connection portion 81, and the third branch portion 834 extends from the connection body portion along the second direction Y.

[0117] Exemplarily, in an embodiment of this disclosure, referring to Figures 4, 6, and 10, the first electrode S3 of the driving transistor T3 includes a first sub-electrode region ACT31 located in the first semiconductor layer 3, the first sub-electrode region ACT31 extending along a second direction. The orthographic projection of the first branch 832 on the substrate at least partially overlaps with the orthographic projection of the first sub-electrode region ACT31 on the substrate.

[0118] Exemplary, in an embodiment of this disclosure, referring to Figures 4, 9, and 11, the first power signal line VDD includes a widened portion 91. The orthographic projection of the widened portion 91 of the first power signal line VDD onto the substrate covers the orthographic projection of the middle portion ACT22 of the active layer of the compensation control transistor onto the substrate.

[0119] Figure 13A is a partial planar schematic diagram of the film layers of two pixel driving circuits located in the same row according to an embodiment of the present disclosure, including a first semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. Exemplarily, in an embodiment of the present disclosure, referring to Figures 4, 11, and 13A, the orthographic projection of the second conductive connection portion 82 and the channel region ACT22 of the compensation control transistor on the substrate does not overlap. For example, the second conductive connection portion 82 and the channel region ACT22 of the compensation control transistor can both extend along a second direction and be spaced apart in a first direction. This design reduces the overlap capacitance between the second conductive connection portion and the first and second sub-scan signal lines, improving reliability stripes. Continuing to refer to Figure 13A, the power signal connection portions 83 in the pixel driving circuits of adjacent sub-pixels located in the same row are laterally connected in the first direction. The power signal connection portions 83 can also be electrically connected to the first power signal line VDD; therefore, the power signal connection portion 83 located in the fourth conductive layer can form a mesh structure with the first power signal line VDD located in the fifth conductive layer. The lateral VDD signal line is designed in the fourth conductive layer, which allows the third node N3 to have a lower capacitance. The reduction in the total capacitance of the third node N3 is beneficial for optimizing temperature drift. On the other hand, the second conductive connection 82 can serve as the second electrode S2 (source) of the compensation control transistor T2. The reduction in overlap capacitance is beneficial for improving the stability of the compensation control transistor.

[0120] Figure 13B is a partial planar schematic diagram of the partial film layers of two pixel driving circuits located in the same row according to an embodiment of the present disclosure, including a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer.

[0121] Exemplarily, in embodiments of this disclosure, two adjacent sub-pixels in the same row can have their first power signal lines widened uniformly, or the widened portions of the first power signal lines of two adjacent sub-pixels in the same row can be spaced apart in the first direction. For example, referring to FIG13B, the widened portion 911 of the first power signal line VDD1 of the first sub-pixel SP1 in the i-th row and j-th column and the widened portion 912 of the first power signal line VDD2 of the second sub-pixel SP2 in the i-th row and j+1-th column are spaced apart in the first direction. The first power signal lines that are blocked above the two compensation control transistors in two adjacent sub-pixels in the same row can be disconnected, thereby improving the transmittance of the pixel unit and facilitating the placement of the photosensitive sensor module under the display substrate. At the same time, the large area of ​​the first power signal lines covering the first node N1 can stabilize the voltage of the first node N1 and prevent crosstalk. On the other hand, the spaced arrangement of the first power signal lines can be matched with the position of the anode placement to ensure uniform routing of the fifth conductive layer below the anode, ensuring the flatness of the anode and facilitating the optimization of color shift.

[0122] Referring again to Figure 13B, the routing layout of the first power signal lines for different sub-pixels can be different. For example, the first power signal line VDD1 of the first sub-pixel SP1 located in the i-th row and j-th column has a different shape than the first power signal line VDD2 of the second sub-pixel SP2 located in the i-th row and j+1-th column. Different first power signal line designs can be adopted according to different sub-pixel types. By flexibly designing the routing layout of the first power signal lines according to the arrangement of different sub-pixels, the sub-pixels can have higher transmittance.

[0123] In the same pixel unit, the driving pixel circuits located on different layers can be designed to overlap in the direction perpendicular to the substrate, thereby improving the transmittance of the pixel unit. Different types of traces between the driving circuits of adjacent sub-pixels can also be designed to overlap in the direction perpendicular to the substrate, making full use of the vertical space, which is beneficial to improving the transmittance of the pixel unit.

[0124] For example, the pixel driving circuit may further include a first light-emitting control transistor T5 and a second light-emitting control transistor T6. The first light-emitting control transistor T5 includes an active layer ACT5 and a control electrode G5, and the second light-emitting control transistor T6 includes an active layer ACT6, a control electrode G6, and a second electrode D6. The display substrate also includes a light-emitting control signal line EM located in the first conductive layer. The portion of the orthographic projection of the light-emitting control signal line EM on the substrate that overlaps with the active layer ACT5 of the first light-emitting control transistor T5 is the control electrode G5 of the first light-emitting control transistor T5, and the portion of the orthographic projection of the light-emitting control signal line EM on the substrate that overlaps with the active layer ACT6 of the second light-emitting control transistor T6 is the control electrode G6 of the second light-emitting control transistor T6. The display substrate also includes a seventh conductive connection portion 88 located in the fourth conductive layer, through which the second electrode D6 of the second light-emitting control transistor T6 can be electrically connected to the first electrode of the light-emitting element.

[0125] For example, the pixel driving circuit may also store a capacitor. The storage capacitor may include a first electrode C1a located in the first conductive layer and a second electrode C1b located in the second conductive layer.

[0126] Figure 14 is a partial planar schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, including a first conductive layer, a third conductive layer and a fourth conductive layer.

[0127] Exemplary, in embodiments of this disclosure, referring to Figures 4-10 and 14, the display substrate may include a first reset signal line Re1 located in the first conductive layer 4 and a second initialization signal line Vi2 located in the fourth conductive layer 8. The pixel driving circuit includes a first initialization transistor T1 and a second initialization transistor T7. The first initialization transistor T1 includes an active layer ACT1 and a control electrode G1, and the second initialization transistor T7 includes a first electrode S7. The orthographic projection of the first reset signal line Re1 onto the substrate at least partially overlaps with the orthographic projection of the active layer ACT1 of the first initialization transistor T1 onto the substrate. The overlapping portion of the first reset signal line Re1 and the active layer ACT1 of the first initialization transistor T1 forms the control electrode G1 of the first initialization transistor. The first electrode S7 of the second initialization transistor T7 is electrically connected to the second initialization signal line Vi2.

[0128] The first initialization transistor T1 also includes a first electrode S1. The display substrate includes a first initial signal line Vi1 located in the second conductive layer and a sixth conductive connection portion 87 located in the fourth conductive layer. The first electrode S1 of the first initialization transistor T1 is electrically connected to the first initialization signal line Vi1 through the sixth conductive connection portion 87.

[0129] The first reset signal line Re1 extends along a first direction. The second initialization signal line Vi2 includes a main body sub-part Vi21 extending along the first direction and a transition sub-part Vi22 extending along a second direction. The orthographic projection of the main body sub-part Vi21 of the second initialization signal line on the substrate at least partially overlaps with the orthographic projection of the first reset signal line Re1 on the substrate. Specifically, the main body sub-part Vi21 of the second initialization signal line can be a signal trace in the pixel driving circuit of a sub-pixel located in the i-th row, and the first reset signal line Re1 can be a signal trace in the pixel driving circuit of a sub-pixel located in the (i+1)-th row. That is, in the scenario where the orthographic projection of the main body sub-part Vi21 of the second initialization signal line on the substrate at least partially overlaps with the orthographic projection of the first reset signal line Re1 on the substrate, the second initialization signal line Vi2 and the first reset signal line Re1 do not necessarily have to be signal traces in the same pixel driving circuit.

[0130] By designing that at least a portion of the signal traces in the pixel driving circuits of different pixel units overlap at least partially in the orthographic projection of the substrate, the total area occupied by the opaque traces in the plane formed by the first and second directions can be reduced, which is beneficial to improving the transmittance of the pixel units and enhancing the display effect of the display substrate.

[0131] For example, continuing to refer to Figures 4-10 and 14, the display substrate may include a second reset signal line Re2 located in a first conductive layer and a third initialization signal line Vi3 located in a third conductive layer. The pixel driving circuit includes a third initialization transistor T8, which includes an active layer ACT8, a control electrode G8, and a first electrode S8. The orthographic projection of the second reset signal line Re2 onto the substrate at least partially overlaps with the orthographic projection of the active layer ACT8 of the third initialization transistor T8 onto the substrate. The overlapping portion of the second reset signal line Re2 and the active layer ACT8 of the third initialization transistor T8 forms the control electrode G8 of the third initialization transistor. The first electrode S8 of the third initialization transistor is electrically connected to the third initialization signal line Vi3. The orthographic projection of the second reset signal line Re2 onto the substrate at least partially overlaps with the orthographic projection of the third initialization signal line Vi3 onto the substrate. The second reset signal line Re2 and the third initialization signal line Vi3 may be signal traces in the pixel driving circuit of the same sub-pixel.

[0132] By designing that at least a portion of the signal traces in the pixel driving circuit of the same pixel unit overlap at least partially in the orthographic projection of the substrate, the total area occupied by the opaque traces in the plane formed by the first and second directions can be reduced, which is beneficial to improving the transmittance of the pixel unit and enhancing the display effect of the display substrate.

[0133] Figure 15 is a partial planar schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, including a second conductive layer, a fourth conductive layer and a sixth conductive layer.

[0134] For example, continuing to refer to Figures 4-10 and 15, the display substrate may further include a sixth conductive layer 2 located on the side of the first semiconductor layer 3 near the substrate.

[0135] The display substrate may include a main light-shielding portion 21 located in the sixth conductive layer 2. The orthographic projection of the main light-shielding portion 21 on the substrate at least partially overlaps with the orthographic projection of the active layer ACT3 of the driving transistor T3 on the substrate. The orthographic projection of the main light-shielding portion 21 on the substrate at least partially overlaps with the orthographic projection of the connection main portion 831 of the power signal connection portion 83 on the substrate.

[0136] For example, the display substrate may include a first light-shielding portion 211 located in the sixth conductive layer 2. The first light-shielding portion 211 extends from the main light-shielding portion 21 along the first direction X, and the orthographic projection of the first light-shielding portion 211 on the substrate at least partially overlaps with the orthographic projection of the first branch 832 of the power signal connection portion 83 on the substrate.

[0137] For example, the display substrate may further include a second light-shielding portion 212 located in the sixth conductive layer 2. The second light-shielding portion 212 extends from the main light-shielding portion 21 along the second direction Y, and the orthographic projection of the second light-shielding portion 212 on the substrate at least partially overlaps with the orthographic projection of the second conductive connection portion 82 on the substrate.

[0138] For example, the pixel driving circuit may include a data writing transistor T4 and a third initialization transistor T8. The data writing transistor T4 includes a first terminal S4 and a second terminal D4, and the third initialization transistor T8 includes a first terminal S8 and a second terminal D8. The display substrate includes a third conductive connection portion 84 located in the fourth conductive layer 8. One end of the third conductive connection portion 84 is electrically connected to the second terminal D4 of the data writing transistor T4, and the other end of the third conductive connection portion 84 is electrically connected to the second terminal D8 of the third initialization transistor T8. The display substrate includes a third light-shielding portion 213 located in the sixth conductive layer, and the third light-shielding portion 213 extends from the main light-shielding portion 21 along the second direction Y. The orthographic projection of the third light-shielding portion 213 on the substrate at least partially overlaps with the orthographic projection of the third conductive connection portion 84 on the substrate.

[0139] The sixth conductive layer can serve as a light-shielding layer for the pixel driving circuit. The traces in this light-shielding layer can be designed to be positioned below the existing metal traces above. For example, the existing metal traces above can include one or more of the power signal connection portions, second conductive connections, or third conductive connections located in the fourth conductive layer. By designing the light-shielding layer as far below the upper metal traces as possible, the transmittance of the pixel units can be improved, which is beneficial for enhancing the display effect of the display substrate.

[0140] The data writing transistor T4 also includes an active layer ACT4 and a control electrode G4. The display substrate includes a second scan signal line GL2 located in the first conductive layer 4, and the second scan signal line GL2 extends along a first direction. The orthographic projection of the active layer ACT4 of the data writing transistor T4 onto the substrate at least partially overlaps with the orthographic projection of the second scan signal line GL2 onto the substrate. The portion of the second scan signal line GL2 overlapping with the active layer ACT4 of the data writing transistor T4 constitutes the control electrode G4 of the data writing transistor T4.

[0141] By way of example, referring to Figures 4, 9, and 11, the display substrate may further include a fourth conductive connection portion 85 and a fifth conductive connection portion 86 located in the fourth conductive layer 8. The display substrate may also include a third initialization signal line Vi located in the third conductive layer 7 and a data signal line DL located in the fifth conductive layer 9. The third initialization signal line Vi extends along a first direction X, and the data signal line DL extends along a second direction Y. The first terminal S4 of the data writing transistor T4 is electrically connected to the data signal line DL through the fourth conductive connection portion 85. The first terminal S8 of the third initialization transistor T8 is electrically connected to the third initialization signal line Vi3 through the fifth conductive connection portion 86.

[0142] Figure 16 is a partial planar schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, including a first semiconductor layer, a fourth conductive layer and a fifth conductive layer.

[0143] Exemplary, in an embodiment of this disclosure, referring to Figures 4, 6, and 16, the data signal line DL includes a first sub-line dl1, a second sub-line dl2, and a third sub-line dl3. Both the first sub-line dl1 and the third sub-line dl3 extend along a second direction Y, and the second sub-line dl2 is located between the first sub-line dl1 and the third sub-line dl3. The second sub-line dl2 extends along a third direction Z, which intersects both the first direction X and the second direction Y. The orthographic projection of the first sub-line dl1 onto the substrate at least partially overlaps with the orthographic projection of the connection body portion 831 of the power signal connection portion 83 onto the substrate.

[0144] For example, the orthographic projection of the first sub-line dl1 on the substrate at least partially overlaps with the orthographic projection of the third branch 834 of the power signal connection portion 83 on the substrate.

[0145] For example, the pixel driving circuit may include a first initialization transistor T1, which includes an active layer ACT1. The orthographic projection of the third sub-line dl3 onto the substrate at least partially overlaps with the orthographic projection of the active layer ACT1 of the first initialization transistor T1 onto the substrate.

[0146] The data signal lines are located in the fifth conductive layer and are designed with vertical traces. They also overlap with some of the metal traces in the underlying film layer, which helps to improve the transmittance of the display substrate.

[0147] Figure 17 is a partial planar schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, including a fifth conductive layer and a seventh conductive layer.

[0148] Exemplary, in an embodiment of this disclosure, referring to FIG17, the display substrate may include a first power signal line VDD and a data signal line DL located in the fifth conductive layer 9. Both the first power signal line VDD and the data signal line DL extend along the second direction Y. The display substrate may further include a seventh conductive layer 10 located on the side of the fifth conductive layer away from the substrate. The light-emitting element may include a first electrode L1 located in the seventh conductive layer 10. For sub-pixels located in the same column, the first electrode of the light-emitting element of each sub-pixel includes a first end L11 and a second end L12, respectively. The first end L11 and the second end L12 are the ends of the first electrode L1 opposite each other in the first direction X. The orthographic projection of one of the first power signal line VDD and the data signal line DL on the substrate at least partially overlaps with the orthographic projection of the first end L11 of the first electrode on the substrate, and the orthographic projection of the other of the first power signal line VDD and the data signal line DL on the substrate at least partially overlaps with the orthographic projection of the second end L12 of the first electrode on the substrate.

[0149] By optimizing the routing layout below the first electrode, metal traces in the fifth conductive layer are provided below both ends of the first electrode along the first direction. These lower metal traces, such as the first power signal line VDD and the data signal line DL, can be designed to extend along the second direction, thereby improving the flatness of the first electrode and enhancing the uniformity of light emission from the pixel unit.

[0150] Figure 18 is a partial planar schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0151] For example, in an embodiment of this disclosure, referring to FIG18, the display substrate may include an eighth conductive layer 11 located on the side of the seventh conductive layer away from the substrate, and the display substrate may include touch traces TMB located in the eighth conductive layer.

[0152] The touch trace TMB may include a first touch sub-trace TMB1, which extends along a first direction X. The orthographic projection of the first touch sub-trace TMB1 on the substrate at least partially overlaps with the orthographic projection of the second initialization signal line Vi2 on the substrate.

[0153] The touch trace TMB may include a second touch sub-trace TMB2, which extends along a first direction X. The orthographic projection of the second touch sub-trace TMB2 on the substrate at least partially overlaps with the orthographic projection of the power signal connection portion 83 on the substrate.

[0154] The touch trace TMB may include a third touch sub-trace TMB3, which extends along the second direction Y, and the orthographic projection of the third touch sub-trace TMB3 on the substrate at least partially overlaps with the orthographic projection of the second conductive connection portion 82 on the substrate.

[0155] The touch trace TMB may include a fourth touch sub-trace TMB4, which extends along the second direction Y. The orthographic projection of the fourth touch sub-trace TMB4 on the substrate at least partially overlaps with the orthographic projection of the first sub-polar region ACT31 on the substrate.

[0156] The touch traces may include portions extending along a first direction and portions extending along a second direction. By designing the touch traces above existing metal traces, and ensuring that at least a portion of the touch traces' orthogonal projection on the substrate overlaps with the orthogonal projection of the metal traces in the underlying film layer on the substrate, the transmittance of the display substrate is improved.

[0157] Exemplary, in an embodiment of this disclosure, a display substrate is provided. Referring to FIG1, the display substrate includes: a substrate; a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, at least one sub-pixel including a pixel driving circuit and a light-emitting element, the light-emitting element emitting light under the drive of the pixel driving circuit.

[0158] The display substrate may further include multiple data signal lines disposed on the substrate, which are used to provide data signals to N columns of sub-pixels respectively, where N is a positive integer greater than or equal to 2. The pixel driving circuit includes a driving transistor and a compensation control transistor. The driving transistor includes an active layer, a control electrode, and a first electrode. The compensation control transistor includes an active layer, a first electrode, and a second electrode. The control electrode of the driving transistor is electrically connected to the second electrode of the compensation control transistor, and the first electrode of the driving transistor is electrically connected to the first electrode of the compensation control transistor.

[0159] The display substrate may include: a first semiconductor layer disposed on a substrate, and a second semiconductor layer disposed on the side of the first semiconductor layer away from the substrate, wherein the active layer of the driving transistor is located on the first semiconductor layer, and the active layer of the compensation control transistor is located on the second semiconductor layer. As shown in Figure 12, for multiple sub-pixels located in the same row, the active layers of the compensation control transistors of the pixel driving circuit of the j-th column sub-pixel are all located in the first direction between one data signal line providing data signal lines to the j-th column sub-pixel and another data signal line providing data signal lines to the (j+1)-th column sub-pixel, where j is a positive integer greater than or equal to 1 and less than N.

[0160] By placing the active layer of the compensation control transistor at the center of the pixel, the parasitic capacitance near the compensation control transistor can be reduced, resulting in a lower black state voltage value for the display substrate, better low grayscale image quality, and improved display effect of the display substrate.

[0161] Referring to FIG1, at least some embodiments of the present disclosure also provide a display device. The display device may include the display substrate described above.

[0162] The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0163] It should be understood that the display panel and display device according to the embodiments of this disclosure have all the features and advantages of the display substrate described above, as detailed in the above description, which will not be repeated here. Although some embodiments of the overall technical concept of this disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the overall technical concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate comprises: a substrate substrate; and a plurality of sub-pixels disposed on the substrate substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, at least one of the sub-pixels comprising a pixel driving circuit and a light emitting element, the light emitting element emitting light under the driving of the pixel driving circuit, wherein the pixel driving circuit comprises a driving transistor and a compensation control transistor; The display substrate comprises: a first semiconductor layer disposed on the substrate substrate, and a second semiconductor layer disposed on the side of the first semiconductor layer away from the substrate substrate; The active layer of the driving transistor is located in the first semiconductor layer, and the active layer of the compensation control transistor is located in the second semiconductor layer; The active layer of the compensation control transistor comprises a first end portion, a middle portion and a second end portion, the middle portion is located between the first end portion and the second end portion, the first end portion is electrically connected with the first electrode of the driving transistor, the second end portion is electrically connected with the control electrode of the driving transistor, and at least a part of the middle portion is the channel region of the compensation control transistor; The display substrate further comprises: a fourth conductive layer disposed on the side of the second semiconductor layer away from the substrate substrate; and a second conductive connection portion located in the fourth conductive layer; One end of the second conductive connection portion is electrically connected with the first electrode of the compensation control transistor, and the other end of the second conductive connection portion is electrically connected with the first electrode of the driving transistor; and The display substrate further comprises a first scan signal line extending along the first direction, the first scan signal line being electrically connected with the control electrode of the compensation control transistor, wherein the orthogonal projection of the first scan signal line on the substrate substrate at least partially overlaps with the orthogonal projection of the second conductive connection portion on the substrate substrate, the overlapping part of the orthogonal projection of the first scan signal line and the second conductive connection portion on the substrate substrate has a first overlapping width in the second direction; and the orthogonal projection of the first scan signal line on the substrate substrate at least partially overlaps with the orthogonal projection of the middle portion of the compensation control transistor on the substrate substrate, the overlapping part of the orthogonal projection of the first scan signal line and the middle portion of the compensation control transistor on the substrate substrate has a second overlapping width in the second direction, wherein the first overlapping width is smaller than the second overlapping width. 2.The display substrate of claim 1, wherein, The pixel driving circuit further comprises a data writing transistor; The display substrate further comprises: a first conductive layer disposed between the first semiconductor layer and the second semiconductor layer; and a second scan signal line located in the first conductive layer and extending along the first direction, the control electrode of the data writing transistor being electrically connected with the second scan signal line; and The orthogonal projection of the second conductive connection portion on the substrate substrate at least partially overlaps with the orthogonal projection of the second scan signal line on the substrate substrate. 3.The display substrate of claim 2, wherein, The orthogonal projection of the middle portion of the active layer of the compensation control transistor on the substrate substrate at least partially overlaps with the orthogonal projection of the second scan signal line on the substrate substrate. 4.The display substrate of claim 2, wherein, The display substrate includes a first conductive portion in the first conductive layer, and a first conductive connection portion in the fourth conductive layer; A normal projection of the first conductive portion on the substrate substrate at least partially overlaps a normal projection of an active layer of the drive transistor on the substrate substrate, one end of the first conductive connection portion is electrically connected with the first conductive portion, and the other end of the first conductive connection portion is electrically connected with a second electrode of the compensation control transistor. 5.The display substrate of claim 4, wherein, A normal projection of the second conductive connection portion on the substrate substrate is spaced apart from a normal projection of a middle portion of the active layer of the compensation control transistor on the substrate substrate. 6.The display substrate of claim 5, wherein, The display substrate includes a second conductive layer provided on a side of the second semiconductor layer close to the substrate substrate, and a third conductive layer provided on a side of the second semiconductor layer away from the substrate substrate; The display substrate includes a first sub-scanning signal line in the second conductive layer, and a second sub-scanning signal line in the third conductive layer; The first sub-scanning signal line includes a first sub-main body portion and a first sub-widened portion, a size of the first sub-widened portion in the second direction is greater than a size of the first sub-main body portion in the second direction; the second sub-scanning signal line includes a second sub-main body portion and a second sub-widened portion, a size of the second sub-widened portion in the second direction is greater than a size of the second sub-main body portion in the second direction; and A normal projection of the first sub-widened portion on the substrate substrate at least partially overlaps a normal projection of a channel region of the compensation control transistor on the substrate substrate, and a normal projection of the second sub-widened portion on the substrate substrate at least partially overlaps a normal projection of the channel region of the compensation control transistor on the substrate substrate. A normal projection of the second conductive connection portion on the substrate substrate overlaps a normal projection of a first sub-portion of the first sub-scanning signal line on the substrate substrate, and the first sub-portion is spaced apart from the first sub-widened portion; 7.The display substrate of claim 6, wherein, And / or, A normal projection of the second conductive connection portion on the substrate substrate overlaps a normal projection of a second sub-portion of the second sub-scanning signal line on the substrate substrate, and the second sub-portion is spaced apart from the second sub-widened portion. The display substrate further includes a fifth conductive layer on a side of the fourth conductive layer away from the substrate substrate; 8.The display substrate of claim 7, wherein, The display substrate includes a first power signal line in the fifth conductive layer, the first power signal line extending along a second direction; and a power signal connection portion in the fourth conductive layer, the power signal connection portion being electrically connected with the first power signal line; and The power signal connection portion includes a connection main body portion, a first branch portion, a second branch portion, and a third branch portion, the first branch portion extending from the connection main body portion along a first direction, the second branch portion extending from the connection main body portion along a direction parallel to the first conductive connection portion, and the third branch portion extending from the connection main body portion along a second direction. The first electrode of the drive transistor includes a first sub-electrode region in the first semiconductor layer, the first sub-electrode region extending along a second direction; and 9.The display substrate of claim 8, wherein, And ​ A projection of the first branch on the substrate substrate at least partially overlaps with a projection of the first sub-pixel region on the substrate substrate. 10.The display substrate according to claim 8 or 9, wherein The first power signal line includes a widened portion, and a projection of the widened portion of the first power signal line on the substrate substrate covers a projection of a middle portion of an active layer of the compensation control transistor on the substrate substrate.

11. The display substrate according to any one of claims 8-10, wherein, The widened portions of the first power signal lines of two adjacent sub-pixels in the same row are arranged at intervals in the first direction. 12.The display substrate of claim 8, wherein, The plurality of sub-pixels includes a first sub-pixel in an i-th row and a j-th column, a second sub-pixel in the i-th row and a j+1-th column, and a third sub-pixel in the i-th row and a j+2-th column, the first sub-pixel, the second sub-pixel, and the third sub-pixel each including the pixel driving circuit, where i and j are each a positive integer greater than or equal to 1. The display substrate includes a plurality of data signal lines disposed on the substrate substrate, the plurality of data signal lines including a first data signal line for providing a data signal to the first sub-pixel, a second data signal line for providing a data signal to the second sub-pixel, and a third data signal line for providing a data signal to the third sub-pixel, the first data line, the second data line, and the third data line each extending along a second direction; and In the first direction, an active layer of a compensation control transistor of the pixel driving circuit of the first sub-pixel is located between the first data line and the second data line, and an active layer of a compensation control transistor of the pixel driving circuit of the second sub-pixel is located between the second data line and the third data line. 13.The display substrate of claim 12, wherein, The data write transistor includes a first electrode; The first data line is electrically connected to a first electrode of a data write transistor of the pixel driving circuit of the first sub-pixel through a first via, and the second data line is electrically connected to a first electrode of a data write transistor of the pixel driving circuit of the second sub-pixel through a second via; In the first direction, an active layer of a compensation control transistor of the pixel driving circuit of the first sub-pixel is spaced apart from the first via by a first distance, and an active layer of a compensation control transistor of the pixel driving circuit of the first sub-pixel is spaced apart from the second via by a second distance, and a ratio of the first distance to the second distance is between 0.8 and 1.

2. The display substrate includes a first reset signal line in the first conductive layer and a second initialization signal line in the fourth conductive layer. 14.The display substrate of claim 11, wherein, The pixel driving circuit includes a first initialization transistor and a second initialization transistor, the first initialization transistor includes an active layer and a control electrode, the second initialization transistor includes a first electrode, a projection of the first reset signal line on the substrate substrate at least partially overlaps with a projection of the active layer of the first initialization transistor on the substrate substrate, and a portion of the first reset signal line overlapping with the active layer of the first initialization transistor forms the control electrode of the first initialization transistor, the first electrode of the second initialization transistor is electrically connected to the second initialization signal line; and The pixel driving circuit includes a first initialization transistor and a second initialization transistor, the first initialization transistor includes an active layer and a control electrode, the second initialization transistor includes a first electrode, a projection of the first reset signal line on the substrate substrate at least partially overlaps with a projection of the active layer of the first initialization transistor on the substrate substrate, and a portion of the first reset signal line overlapping with the active layer of the first initialization transistor forms the control electrode of the first initialization transistor, the first electrode of the second initialization transistor is electrically connected to the second initialization signal line; and ​ The first reset signal line extends in a first direction, and the second initialization signal line includes a main sub-portion extending in the first direction and a switching sub-portion extending in a second direction, and a projection of the main sub-portion of the second initialization signal line on the substrate substrate at least partially overlaps a projection of the first reset signal line on the substrate substrate.

15. The display substrate according to any one of claims 8-10, wherein, The display substrate includes a second reset signal line in the first conductive layer, and a third initialization signal line in the third conductive layer. The pixel driving circuit includes a third initialization transistor including an active layer, a control electrode, and a first electrode, a projection of the second reset signal line on the substrate substrate at least partially overlaps a projection of the active layer of the third initialization transistor on the substrate substrate, a portion of the second reset signal line overlapping the active layer of the third initialization transistor forms the control electrode of the third initialization transistor, and the first electrode of the third initialization transistor is electrically connected with the third initialization signal line; and A projection of the second reset signal line on the substrate substrate at least partially overlaps a projection of the third initialization signal line on the substrate substrate. 16.The display substrate of claim 15, wherein, The display substrate further includes a sixth conductive layer on a side of the first semiconductor layer close to the substrate substrate; and The display substrate includes a main light shielding portion in the sixth conductive layer, a projection of the main light shielding portion on the substrate substrate at least partially overlaps a projection of the active layer of the driving transistor on the substrate substrate, and a projection of the main light shielding portion on the substrate substrate at least partially overlaps a projection of the connection main portion of the power signal connection portion on the substrate substrate. 17.The display substrate of claim 16, wherein, The display substrate includes a first light shielding portion in the sixth conductive layer, the first light shielding portion extends in a first direction from the main light shielding portion, and a projection of the first light shielding portion on the substrate substrate at least partially overlaps a projection of the first branch portion of the power signal connection portion on the substrate substrate. And / or, The display substrate includes a second light shielding portion in the sixth conductive layer, the second light shielding portion extends in a second direction from the main light shielding portion, and a projection of the second light shielding portion on the substrate substrate at least partially overlaps a projection of the second conductive connection portion on the substrate substrate. 18.The display substrate of claim 17, wherein, The pixel driving circuit includes a data writing transistor including a second electrode and a third initialization transistor including a second electrode; The display substrate includes a third conductive connection portion in the fourth conductive layer, one end of the third conductive connection portion is electrically connected with the second electrode of the data writing transistor, and the other end of the third conductive connection portion is electrically connected with the second electrode of the third initialization transistor; and The display substrate includes a third light shielding portion in the sixth conductive layer, the third light shielding portion extends in a second direction from the main light shielding portion, and a projection of the third light shielding portion on the substrate substrate at least partially overlaps a projection of the third conductive connection portion on the substrate substrate. 19.The display substrate of claim 12, wherein, The data signal line includes a first sub-line, a second sub-line and a third sub-line, the first sub-line and the third sub-line both extend along a second direction, the second sub-line is located between the first sub-line and the third sub-line, and the second sub-line extends along a third direction, the third direction intersects both the first direction and the second direction; and The orthogonal projection of the first sub-line on the substrate substrate at least partially overlaps with the orthogonal projection of the connection main body part of the power signal connection part on the substrate substrate; And / or, the orthogonal projection of the first sub-line on the substrate substrate at least partially overlaps with the orthogonal projection of the third branch part of the power signal connection part on the substrate substrate. 20.The display substrate of claim 19, wherein, The pixel driving circuit includes a first initialization transistor, and the first initialization transistor includes an active layer; and The orthogonal projection of the third sub-line on the substrate substrate at least partially overlaps with the orthogonal projection of the active layer of the first initialization transistor on the substrate substrate. 21.The display substrate of claim 19, wherein, The display substrate includes a first power signal line and a data signal line located in the fifth conductive layer, and the first power signal line and the data signal line both extend along a second direction; The display substrate includes a seventh conductive layer located on the side of the fifth conductive layer away from the substrate substrate, and the light emitting element includes a first electrode located in the seventh conductive layer; and For the sub-pixels located in the same column, the first electrode of the light emitting element of each sub-pixel respectively includes a first end part and a second end part, the first end part and the second end part are opposite end parts of the first electrode in the first direction, the orthogonal projection of one of the first power signal line and the data signal line on the substrate substrate at least partially overlaps with the orthogonal projection of the first end part of the first electrode on the substrate substrate, and the orthogonal projection of the other of the first power signal line and the data signal line on the substrate substrate at least partially overlaps with the orthogonal projection of the second end part of the first electrode on the substrate substrate.

22. The display substrate of claim 21, wherein, The display substrate includes an eighth conductive layer located on the side of the seventh conductive layer away from the substrate substrate, and the display substrate includes a touch trace located in the eighth conductive layer; The touch trace includes a first touch sub-trace, the first touch sub-trace extends along a first direction, and the orthogonal projection of the first touch sub-trace on the substrate substrate at least partially overlaps with the orthogonal projection of the second initialization signal line on the substrate substrate; And / or, the touch trace includes a second touch sub-trace, the second touch sub-trace extends along a first direction, and the orthogonal projection of the second touch sub-trace on the substrate substrate at least partially overlaps with the orthogonal projection of the power signal connection part on the substrate substrate. 23.The display substrate of claim 22, wherein, The touch trace includes a third touch sub-trace, the third touch sub-trace extends along a second direction, and the orthogonal projection of the third touch sub-trace on the substrate substrate at least partially overlaps with the orthogonal projection of the second conductive connection part on the substrate substrate; And / or, The touch wire includes a fourth touch sub-wire, the fourth touch sub-wire extends along a second direction, and a projection of the fourth touch sub-wire on the substrate substrate at least partially overlaps with a projection of the first sub-polar region on the substrate substrate.

24. The display substrate according to any one of claims 1-23, wherein, The first semiconductor layer includes a polysilicon semiconductor material, and the second semiconductor layer includes an oxide semiconductor material.

25. A display substrate, wherein, The display substrate includes: a substrate substrate; a plurality of sub-pixels disposed on the substrate substrate, the plurality of sub-pixels are arranged in an array along a first direction and a second direction, at least one of the sub-pixels includes a pixel driving circuit and a light emitting element, the light emitting element emits light under the drive of the pixel driving circuit; a plurality of data signal lines disposed on the substrate substrate, the plurality of data signal lines are used to provide data signals to N columns of sub-pixels respectively, wherein N is a positive integer greater than or equal to 2, The pixel driving circuit includes a driving transistor and a compensation control transistor, the driving transistor includes an active layer, a control electrode and a first electrode, the compensation control transistor includes an active layer, a first electrode and a second electrode, the control electrode of the driving transistor is electrically connected to the second electrode of the compensation control transistor, and the first electrode of the driving transistor is electrically connected to the first electrode of the compensation control transistor, The display substrate includes a first semiconductor layer disposed on the substrate substrate, and a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate substrate, The active layer of the driving transistor is located in the first semiconductor layer, and the active layer of the compensation control transistor is located in the second semiconductor layer, For a plurality of sub-pixels located in the same row, the active layer of the compensation control transistor of the pixel driving circuit of the jth column of sub-pixels is located between one data signal line providing data signals to the jth column of sub-pixels and another data signal line providing data signals to the j+1th column of sub-pixels in the first direction, wherein i is a positive integer greater than or equal to 1 and less than N.

26. A display device comprising: The display device includes the display substrate according to any one of claims 1-25.

Images