Method, device, equipment and storage medium for testing interface conductivity of multiphase material

Abstract

This application discloses a method, apparatus, equipment, and storage medium for testing the interfacial conductivity of multiphase materials, including: preparing test samples with various gold plating schemes based on the package structure under test to obtain a set of test samples; performing state statistics on each test sample in the test sample set to obtain a set of gold plating quality-thickness data; performing interfacial current tests on each test sample in the test sample set to obtain a set of interfacial current test results; performing analysis and calculation based on a preset interfacial conductivity formula and the set of interfacial current test results to obtain a set of interfacial conductivity to be verified; and performing data fitting verification based on the set of interfacial conductivity to be verified and the set of gold plating quality-thickness data to obtain the interfacial conductivity. This application achieves accurate measurement of interfacial conductivity by using samples with different gold plating schemes and combining data fitting verification.

Description

Technical Field

[0001] This application relates to the technical field of electronic manufacturing, and in particular to a method, apparatus, equipment and storage medium for testing the interfacial conductivity of multiphase materials. Background Technology

[0002] Currently, although silicon carbide (SiC) electronic devices have driven the development of high-power devices due to their excellent performance, their packaging still uses the traditional wire bonding method, which leads to electric field concentration at the three junction points of silicon gel, copper layer and ceramic substrate, becoming a weak link for insulation failure.

[0003] However, existing research has focused on the bulk resistivity of materials, while the resistivity of the silicon gel / ceramic substrate interface, which is crucial for the calculation of the three-phase point electric field, has long been neglected. Furthermore, due to the extremely thin interface thickness and the difficulty of testing, there is a lack of effective experimental methods.

[0004] Therefore, there is an urgent need to develop a method that can accurately test the resistivity of the silicon gel / ceramic substrate interface in order to achieve accurate measurement of the conductivity of the silicon gel / ceramic substrate interface. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for testing the interfacial conductivity of multiphase materials to solve the aforementioned technical problems.

[0006] The first aspect of this application provides a method for testing the interfacial conductivity of multiphase materials, including:

[0007] Test samples with various gold plating schemes were prepared based on the package structure under test, resulting in a test sample set of the package structure under test;

[0008] The gold plating status of each test sample in the test sample set of the packaged structure under test is statistically analyzed to obtain a set of gold plating quality-thickness data.

[0009] Each test sample of the packaged structure under test in the test sample set is subjected to interface current test to obtain a set of interface current test results.

[0010] Based on the preset interface conductivity formula and the set of interface current test results, the set of interface conductivity to be verified is obtained by analysis and calculation.

[0011] The interface conductivity is obtained by performing data fitting verification based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data.

[0012] In some embodiments, test samples with various gold plating schemes are prepared based on the package structure under test to obtain a test sample set of the package structure under test, including:

[0013] Design a corresponding mask based on the package structure under test;

[0014] The mask is placed over the package structure to be tested, and the covered package structure to be tested is gold-plated according to a variety of different gold plating schemes to obtain the corresponding gold-plated package structure to be tested.

[0015] Test samples are prepared based on all the gold-plated packaging structures under test, resulting in a set of test samples for the packaging structures under test.

[0016] In some embodiments, the mask is applied over the package structure under test, and the covered package structure under test is gold-plated according to various different gold plating schemes to obtain the corresponding gold-plated package structure under test, including:

[0017] The mask is placed over the package structure to be tested to obtain the covered package structure to be tested.

[0018] Based on various different gold plating qualities, corresponding gold plating schemes are designed to obtain a set of gold plating schemes;

[0019] Based on the set of gold plating schemes, the covered test package structure is gold-plated to obtain the corresponding gold-plated test package structure.

[0020] In some embodiments, test samples are prepared based on all the gold-plated package structures under test to obtain a set of test samples of the package structures under test, including:

[0021] First, aluminum foil is pasted onto the gold plating layer of all the gold-plated packaging structures under test as test electrodes. Then, silicone gel is covered onto all the gold-plated packaging structures under test. Finally, all the gold-plated packaging structures under test are dried to obtain a test sample set of the packaging structures under test.

[0022] In some embodiments, the interface conductivity to be verified is obtained by analysis and calculation based on a preset interface conductivity formula and the set of interface current test results, including:

[0023] The preset interface conductivity formula is read, and the preset interface conductivity formula is:

[0024]

[0025] In the formula, ρ int It is the preset interface conductivity, ρ v It is a thickness of h v Volume resistivity of phase at time ρ test It is the resistivity of the test area, h int h is the thickness of the interface to be verified, and h is the thickness of the gold plating layer.

[0026] The interface current test results are substituted into the preset interface conductivity formula for analysis and calculation to obtain the interface conductivity set to be verified.

[0027] In some embodiments, data fitting verification is performed based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data to obtain the interface conductivity, including:

[0028] Get the preset interface thickness threshold range;

[0029] Based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data, data fitting analysis is performed to obtain the interface thickness fitting result.

[0030] Data verification is performed based on the preset interface thickness threshold range and the interface thickness fitting result to obtain the data verification result;

[0031] If the data verification result is qualified, the interface conductivity is obtained based on the interface thickness fitting result.

[0032] In some embodiments, after performing data verification based on the preset interface thickness threshold range and the interface thickness fitting result, the method further includes:

[0033] If the data verification result is unqualified, at least two test samples with different thicknesses than the existing gold layer are prepared first, and their interface resistivity is tested to expand the set of interface conductivity to be verified. Then, based on the expanded set of interface conductivity to be verified, a refit is performed. If the secondary interface thickness fitting result obtained by refitting falls within the preset interface thickness threshold range, the data verification result is determined to be qualified and the interface resistivity is output.

[0034] The second aspect of this application proposes a testing device for the interfacial conductivity of multiphase materials, comprising a sample preparation module, a gold plating statistics module, a current testing module, an analysis and calculation module, and a fitting verification module, wherein...

[0035] The sample preparation module is used to prepare test samples with various gold plating schemes based on the package structure under test, and obtain a set of test samples of the package structure under test.

[0036] The gold plating statistics module is used to perform gold plating status statistics on each test sample of the test package structure in the test sample set to obtain a gold plating quality-thickness data set.

[0037] The current testing module is used to perform interface current testing on each test sample of the packaged structure under test in the test sample set, and obtain a set of interface current test results.

[0038] The analysis and calculation module is used to perform analysis and calculation based on the preset interface conductivity formula and the set of interface current test results to obtain the set of interface conductivity to be verified.

[0039] The fitting verification module is used to perform data fitting verification based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data to obtain the interface conductivity.

[0040] A third aspect of this application provides an electronic device comprising: a memory; a processor; and one or more computer programs stored in the memory, the one or more computer programs including instructions that, when executed by the processor, enable the testing method for the interfacial conductivity of multiphase materials as described above.

[0041] A fourth aspect of this application provides a computer-readable storage medium storing a computer program, wherein the storage medium stores a test program for the interfacial conductivity of a multiphase material, and when the test program for the interfacial conductivity of a multiphase material is executed by a processor, it implements the steps of the test method for the interfacial conductivity of a multiphase material as described above.

[0042] This application provides a method, apparatus, equipment, and storage medium for testing the interfacial conductivity of multiphase materials. The method includes: preparing test samples with various gold plating schemes based on the package structure under test to obtain a test sample set; statistically analyzing the gold plating state of each test sample in the test sample set to obtain a gold plating quality-thickness data set; performing interfacial current tests on each test sample in the test sample set to obtain an interfacial current test result set; analyzing and calculating based on a preset interfacial conductivity formula and the interfacial current test result set to obtain a set of interfacial conductivity to be verified; and performing data fitting verification based on the set of interfacial conductivity to be verified and the gold plating quality-thickness data set to obtain the interfacial conductivity. This application, by designing samples with different gold layer thicknesses and combining data fitting verification, achieves accurate measurement of the interfacial conductivity of silicon gel / ceramic substrates, solving the technical problem that traditional methods cannot separate the interfacial contribution due to the extremely thin interfacial thickness. This provides key data support for accurately analyzing the three-phase point electric field distribution and improving the insulation reliability of SiC power modules. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of the testing device for the interfacial conductivity of multiphase materials provided in the embodiments of this application.

[0044] Figure 2 This is a flowchart illustrating the method for testing the interfacial conductivity of multiphase materials provided in the embodiments of this application.

[0045] Figure 3 yes Figure 2 A schematic diagram of the sub-process of step S10.

[0046] Figure 4 yes Figure 3 A schematic diagram of the sub-process of step S12.

[0047] Figure 5 yes Figure 2 A schematic diagram of the sub-process of step S40.

[0048] Figure 6 yes Figure 2 A schematic diagram of the sub-process of step S50.

[0049] Figure 7 This is a structural block diagram of the multiphase material interface conductivity testing device provided in the embodiments of this application.

[0050] Figure 8 This is another structural block diagram of the testing device for the interfacial conductivity of multiphase materials provided in the embodiments of this application. Detailed Implementation

[0051] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0052] Currently, silicon carbide (SiC), as a representative of third-generation wide-bandgap semiconductor materials, has become the core foundation for building next-generation high-power-density electronic devices due to its excellent properties such as high critical breakdown electric field, high thermal conductivity, and high temperature resistance, greatly promoting technological innovation in fields such as new energy, rail transportation, and smart grids. However, despite the leap in chip material performance, commercial SiC power devices still generally use traditional silicon-based packaging forms represented by wire bonding at the packaging level. The limitations of this packaging structure lead to a high concentration of electric field intensity in the "three-phase point" region where the silicon gel encapsulant, metal wiring layer, and ceramic substrate meet under long-term high voltage stress. This makes it the weakest link in the module insulation system, which is very prone to partial discharge, ultimately leading to insulation aging or even breakdown failure of the device.

[0053] However, a critical blind spot has long existed in academic research on this reliability issue. Existing technologies mostly focus on the influence of the macroscopic resistivity of the silica gel or ceramic substrate on the electric field distribution, while the microscopic "silica gel / ceramic substrate interface resistivity" parameter, which plays a decisive role in the calculation of the three-phase point electric field, has been severely neglected. In fact, due to complex physicochemical effects such as material surface morphology, process residues, and interfacial diffusion, a transition layer with a thickness on the nanometer scale is formed at the interface. Its electrical properties (especially resistivity) differ from those of the bulk material by orders of magnitude, directly determining the degree of electric field distortion. Even more challenging is that, because this interface layer is extremely thin (typically between 25-50 nanometers) and tightly encapsulated by the upper and lower layers, traditional four-probe methods or bulk resistivity testing methods are completely ineffective in separating and extracting its intrinsic resistivity. This has made the testing of this key parameter a huge technical challenge, with related experimental data almost nonexistent.

[0054] Therefore, this application provides a method, apparatus, device, and storage medium for testing the interfacial conductivity of multiphase materials. The method includes: preparing test samples with various gold plating schemes based on the package structure under test to obtain a test sample set; statistically analyzing the gold plating state of each test sample in the test sample set to obtain a gold plating quality-thickness data set; performing interfacial current tests on each test sample in the test sample set to obtain an interfacial current test result set; analyzing and calculating based on a preset interfacial conductivity formula and the interfacial current test result set to obtain a set of interfacial conductivity to be verified; and performing data fitting verification based on the set of interfacial conductivity to be verified and the gold plating quality-thickness data set to obtain the interfacial conductivity. This application, by designing samples with different gold layer thicknesses and combining data fitting verification, achieves accurate measurement of the interfacial conductivity of silicon gel / ceramic substrates, solving the technical problem that traditional methods cannot separate the interfacial contribution due to the extremely thin interfacial thickness. This provides key data support for accurately analyzing the three-phase point electric field distribution and improving the insulation reliability of SiC power modules.

[0055] Reference Figure 1 , Figure 1 This is a schematic diagram of the electronic device structure according to an embodiment of this application. Figure 1As shown, the electronic device 1000 may include: a processor 1001, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The processor 1001 may be, for example, a Central Processing Unit (CPU). The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard. Optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wireless-Fidelity (Wi-Fi) interface). The memory 1005 may be high-speed random access memory (RAM) or stable non-volatile memory (NVM), such as a disk storage device. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0056] Those skilled in the art will understand that Figure 1 The structure shown does not constitute a limitation on the electronic device 1000, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0057] like Figure 1 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a test program for the interfacial conductivity of multiphase materials.

[0058] Understandable, Figure 1 In the illustrated electronic device 1000, the network interface 1004 is mainly used for data communication with a network server. The user interface 1003 is mainly used for data interaction with the user. In this application, the electronic device 1000 uses the processor 1001 to call the control program stored in the memory 1005 to execute the multiphase material interface conductivity testing method provided in this application embodiment.

[0059] Please refer to Figure 2 , Figure 2 This is a schematic flowchart of a method for testing the interfacial conductivity of multiphase materials provided in an embodiment of this application. In some embodiments, the method for testing the interfacial conductivity of multiphase materials may be performed by... Figure 1 The electronic device 1000 in the system performs this operation. Specifically, for example... Figure 2 As shown, the method for testing the interfacial conductivity of multiphase materials includes the following steps:

[0060] Step S10: Prepare test samples with various gold plating schemes based on the package structure under test to obtain a set of test samples of the package structure under test.

[0061] It is understood that in some embodiments, the package structure under test refers to an electronic package containing a substrate and a packaging material layer, such as a silicone gel / ceramic substrate, wherein the ceramic substrate provides mechanical support and insulation, and the silicone gel, as a packaging material, covers the surface of the ceramic substrate to form the interface under test.

[0062] Please refer to this as well. Figure 3 , Figure 3 yes Figure 2 A schematic diagram of the sub-process of step S10. In some embodiments, a test sample set of the package structure under test can be obtained based on the following steps S11 to S13.

[0063] Step S11: Design the corresponding mask based on the package structure to be tested.

[0064] It is understandable that the mask designs for different package structures under test are not the same. Therefore, it is necessary to design a mask with a specific opening pattern based on the surface morphology of the package structure under test and the requirements of the test area, so as to limit the gold layer to be deposited only on the interface area under test in the subsequent gold plating process.

[0065] It should be noted that, in some embodiments, the process of designing a mask based on the package structure under test includes, but is not limited to, first determining the shape and size of the mask opening pattern according to the test area requirements of the package structure under test, matching the substrate geometry and setting alignment marks, then selecting the mask material and thickness in combination with the shadow effect of the vapor deposition process, verifying the rationality of the mask pattern design through simulation, and finally using photolithography to manufacture a high-precision mask and complete defect detection, thus obtaining the corresponding mask.

[0066] Step S12: Cover the package structure under test with a mask, and perform gold plating on the covered package structure under test according to a variety of different gold plating schemes to obtain the corresponding gold-plated package structure under test.

[0067] It is understood that in some embodiments, a pre-designed mask is first applied to the surface of the packaged structure under test. Then, by controlling the mass parameters of the evaporation source (pure gold), various gold plating schemes are implemented to deposit gold layers, ultimately resulting in a series of gold-plated packaged structures under test with different gold layer thicknesses. The various gold plating schemes are achieved by controlling the mass of the evaporation source (pure gold) in the gold plating process, so that each scheme corresponds to a specific gold layer mass gradient, thereby preparing a series of samples with different gold layer thicknesses. For example, 0.1g, 0.2g, 0.3g, and 0.4g of gold can be evaporated and deposited onto the covered packaged structure under test, respectively, to obtain four different gold-plated packaged structures under test corresponding to the four different gold plating schemes.

[0068] Please refer to this as well. Figure 4 , Figure 4 yes Figure 3 A schematic diagram of the sub-process of step S12. In some embodiments, the corresponding gold-plated package structure to be tested can be obtained based on steps S121 to S123.

[0069] Step S121: Cover the package structure under test with a mask to obtain the covered package structure under test.

[0070] It is understood that, in some embodiments, when covering the packaged structure under test with a mask, it is necessary to ensure that the opening pattern of the mask is precisely aligned with the area to be tested to obtain the covered packaged structure under test. Furthermore, the number of covered packaged structures under test prepared must meet the requirements for implementing various subsequent gold plating schemes.

[0071] Step S122: Design corresponding gold plating schemes based on various different gold plating qualities to obtain a set of gold plating schemes.

[0072] It is understood that in some embodiments, various gold plating qualities are typically set as gradient gold layer qualities, such as 0.1g, 0.2g, 0.3g, and 0.4g. Furthermore, to ensure the reliability of data fitting, at least three gold plating schemes are required to form a uniformly distributed gradient sequence, thereby effectively capturing the variation between gold layer thickness and interface resistance and avoiding fitting errors due to insufficient data points.

[0073] It should be noted that, in some embodiments, the gold plating schemes included in the gold plating scheme set may be: Scheme A, depositing 0.1g of pure gold onto the covered test package structure; Scheme B, depositing 0.2g of pure gold onto the covered test package structure; Scheme C, depositing 0.3g of pure gold onto the covered test package structure; and Scheme D, depositing 0.4g of pure gold onto the covered test package structure.

[0074] Step S123: Based on the set of gold plating schemes, perform gold plating on the covered package structure to obtain the corresponding gold-plated package structure to be tested.

[0075] It is understood that in some embodiments, the process of performing gold plating on the covered package-to-test (PTS) structure according to different gold plating schemes in the gold plating scheme set involves depositing pure gold of corresponding mass from different gold plating schemes onto the covered PTS structure to obtain gold-plated PTS structures with different (gold plating layer) thicknesses. For example, in scheme A, 0.1g of pure gold is deposited onto the covered PTS structure to obtain a gold plating layer thickness of 26nm; in scheme B, 0.2g of pure gold is deposited onto the covered PTS structure to obtain a gold plating layer thickness of 52nm; in scheme C, 0.3g of pure gold is deposited onto the covered PTS structure to obtain a gold plating layer thickness of 78nm; and in scheme D, 0.4g of pure gold is deposited onto the covered PTS structure to obtain a gold plating layer thickness of 104nm.

[0076] Step S13: Prepare test samples based on the fully gold-plated package structure to be tested, and obtain a set of test samples of the package structure to be tested.

[0077] It is understood that, in some embodiments, the process of preparing test samples based on the fully gold-plated package structure under test includes, but is not limited to, first attaching aluminum foil as test electrodes to the gold-plated surface of the fully gold-plated package structure under test, then covering it with a silicone gel encapsulation layer, and finally performing a drying process to obtain a set of test samples of the package structure under test.

[0078] Furthermore, test samples are prepared based on the fully gold-plated package structure to be tested, resulting in a test sample set of the package structure to be tested. This includes: firstly, attaching aluminum foil as a test electrode to the gold-plated layer of the fully gold-plated package structure to be tested; then covering the fully gold-plated package structure to be tested with silicone gel; and finally drying the fully gold-plated package structure to be tested, resulting in a test sample set of the package structure to be tested.

[0079] It is understood that in some embodiments, the process of drying the entire gold-plated package structure to be tested includes, but is not limited to, placing the entire gold-plated package structure to be tested in a vacuum drying oven and then evacuating it for 1 hour, then drying it in an oven at 100°C for 1 hour, and finally cooling it down to obtain a set of test samples of the package structure to be tested.

[0080] Step S20: Perform gold plating status statistics on each test sample of the packaged structure to be tested in the test sample set to obtain a gold plating quality-thickness data set.

[0081] It is understood that in some embodiments, the statistical analysis of the gold plating status of each test sample of the packaged structure under test is achieved by AFM (Atomic Force Microscope). The process includes, but is not limited to, first confirming the gold plating quality of each test sample of the packaged structure under test, then measuring the thickness of the gold layer on each test sample of the packaged structure under test by AFM and recording the thickness value, forming a gold plating quality-thickness data pair with the corresponding gold layer thickness data of each test sample of the packaged structure under test, and finally integrating all the gold plating quality-thickness data pairs to obtain a gold plating quality-thickness data set.

[0082] Step S30: Perform interface current tests on each test sample of the package structure under test in the test sample set to obtain the interface current test result set.

[0083] It is understood that in some embodiments, the process of performing interface current testing on each test sample of the packaged structure under test in the test sample set includes, but is not limited to, first applying a test voltage to the interface between the gold plating layer and the silicon gel through the aluminum foil electrode of each test sample under constant voltage source drive, and at the same time using a high-precision ammeter to measure the current value flowing through the interface, and finally recording the current data of all samples to form an interface current test result set.

[0084] Step S40: Analyze and calculate based on the preset interface conductivity formula and the set of interface current test results to obtain the set of interface conductivity to be verified.

[0085] It is understood that in some embodiments, the interface current test results of each test sample of the package structure under test can be substituted into the preset interface conductivity formula to obtain the corresponding interface conductivity to be verified. Finally, all the interface conductivity to be verified are integrated to obtain the set of interface conductivity to be verified.

[0086] Please refer to this as well. Figure 5 , Figure 5 yes Figure 2 A schematic diagram of the sub-process of step S40. In some embodiments, the set of interface conductivity to be verified can be obtained based on steps S41 to S42.

[0087] Step S41: Read the preset interface conductivity formula. The preset interface conductivity formula is:

[0088]

[0089] In the formula, ρ int It is the preset interface conductivity, ρ v It is a thickness of h v Volume resistivity of phase at time ρtest It is the resistivity of the test area, h int h is the thickness of the interface to be verified, and h is the thickness of the gold plating layer.

[0090] It is understood that in some embodiments, the preset interface conductivity formula is based on a physical model derived from Ohm's law and the interface geometry, and the process is as follows:

[0091]

[0092] In the above formula, R w1 It is the resistance of the high-voltage electrode, R. w2 It is the resistance of the low-voltage electrode, R. v It is the volume resistivity, R int It is the interface resistance, R test It is a test resistor. Where R... test The resistance value is the volume resistance R. v and interface resistance R int The parallel value; and compared to insulating polymers, gold is conductive, therefore, R w1 and R w2 It can be ignored.

[0093]

[0094]

[0095]

[0096]

[0097]

[0098] Integrating and calculating the above formulas, we can find that the interface resistivity is:

[0099]

[0100] In the formula, ρ v It is a thickness of h v Volume phase resistivity, ρ test It is the resistivity of the test area, h int d is the thickness of the interface, l is the distance between the high and low voltage electrodes, d is the width of the electrode, and h is the gold plating thickness.

[0101] Step S42: Substitute the interface current test results into the preset interface conductivity formula for analysis and calculation to obtain the interface conductivity set to be verified.

[0102] It is understood that in some embodiments, each interface current data in the interface current test result set is substituted into a preset interface conductivity formula to calculate the corresponding interface conductivity value, and finally a set of interface conductivity to be verified is formed.

[0103] Step S50: Perform data fitting verification based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data to obtain the interface conductivity.

[0104] It is understood that in some embodiments, the interfacial conductivity and gold layer thickness data corresponding to different gold plating qualities are substituted into a preset fitting model (such as a linear model), and the interfacial thickness parameters are fitted by algorithms such as the least squares method. The thickness is then verified to determine whether it is within a preset reasonable range (such as 25-50nm) in order to judge the reliability of the interfacial conductivity data and finally obtain the interfacial conductivity.

[0105] Please refer to this as well. Figure 6 , Figure 6 yes Figure 2 A schematic diagram of the sub-process of step S50. In some embodiments, the interface conductivity can be obtained based on steps S51 to S54.

[0106] Step S51: Obtain the preset interface thickness threshold range.

[0107] It is understood that in some embodiments, the preset interface thickness threshold range is a reasonable interface thickness range (such as 25-50nm) of the packaging structure pre-set by the user based on the physical properties of the material interface, process experience and experimental data. It is used to determine whether the interface thickness obtained by data fitting is physically reasonable. If the fitted thickness falls within this range, the corresponding interface conductivity test result is determined to be valid.

[0108] Step S52: Perform data fitting analysis based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data to obtain the interface thickness fitting results.

[0109] It is understood that in some embodiments, data fitting analysis is performed based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data to obtain the interface thickness fitting result. This result is usually presented in the form of a data relationship graph, where the horizontal axis is the gold layer thickness (or gold plating quality) and the vertical axis is the interface conductivity. The fitting curve reflects the influence of the interface thickness parameter on the electrical properties, and the interface thickness value can be extracted from the curve slope or intercept. The fitting analysis process includes, but is not limited to, matching the interface conductivity to be verified and the gold plating quality-thickness data points to a preset physical model through optimization algorithms (such as the least squares method), then iteratively adjusting the model parameters (such as interface thickness) to make the model curve best fit the experimental data, and finally extracting the interface thickness value from the fitting curve to obtain the interface thickness fitting result.

[0110] Step S53: Perform data verification based on the preset interface thickness threshold range and interface thickness fitting results to obtain data verification results.

[0111] It is understood that, in some embodiments, the process of data verification based on a preset interface thickness threshold range and interface thickness fitting results refers to comparing the fitted interface thickness value (interface thickness fitting result) with a preset threshold range (such as 25-50nm). If the thickness falls within this range, the data verification result is deemed qualified, indicating that the interface conductivity test data is reliable; otherwise, the data verification result is deemed unqualified, indicating that there is a problem with the interface conductivity test data.

[0112] Step S54: If the data verification result is qualified, obtain the interface conductivity based on the interface thickness fitting result.

[0113] It is understood that in some embodiments, if the data verification result is qualified, that is, the interface thickness fitting result is within the preset threshold range, the interface conductivity can be calculated based on the fitted thickness and the known interface resistivity formula.

[0114] Furthermore, data verification is performed based on the preset interface thickness threshold range and the interface thickness fitting results. After obtaining the data verification results, the process also includes: if the data verification results are unqualified, at least two test samples with different thicknesses from the existing gold layer are prepared and their interface resistivity is tested to expand the set of interface conductivity to be verified. Then, the interface conductivity to be verified is refitted based on the expanded set of interface conductivity to be verified. If the secondary interface thickness fitting result obtained by refitting falls within the preset interface thickness threshold range, the data verification result is determined to be qualified and the interface resistivity is output.

[0115] It is understood that in some embodiments, if the data verification result is unqualified, a self-correction process needs to be executed, which includes, but is not limited to, first expanding the dataset by adding test samples with different gold layer thicknesses, and optimizing the fitting model using richer data points. If the refitted interface thickness falls within a reasonable range, the verification is passed and a reliable interface resistivity is output.

[0116] Reference Figure 7 , Figure 7 This is a structural block diagram of the testing device for the interfacial conductivity of multiphase materials provided in an embodiment of this application. Figure 7 As shown, the testing device for the interfacial conductivity of multiphase materials includes a sample preparation module 10, a gold plating statistics module 20, a current testing module 30, an analysis and calculation module 40, and a fitting verification module 50.

[0117] The sample preparation module 10 is used to prepare test samples with various gold plating schemes based on the package structure under test, and obtain a set of test samples of the package structure under test.

[0118] The gold plating statistics module 20 is used to perform gold plating status statistics on each test sample of the packaged structure under test in the test sample set, and obtain a gold plating quality-thickness data set.

[0119] The current testing module 30 is used to perform interface current testing on each test sample of the packaged structure under test in the test sample set, and obtain a set of interface current test results.

[0120] The analysis and calculation module 40 is used to perform analysis and calculation based on the preset interface conductivity formula and the interface current test result set to obtain the interface conductivity set to be verified.

[0121] The fitting verification module 50 is used to perform data fitting verification based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data to obtain the interface conductivity.

[0122] This embodiment provides a method, apparatus, device, and storage medium for testing the interfacial conductivity of multiphase materials. The method includes: preparing test samples with various gold plating schemes based on the package structure under test, obtaining a test sample set for the package structure under test; statistically analyzing the gold plating state of each test sample in the test sample set, obtaining a gold plating quality-thickness data set; performing interfacial current tests on each test sample in the test sample set, obtaining an interfacial current test result set; analyzing and calculating based on a preset interfacial conductivity formula and the interfacial current test result set, obtaining a set of interfacial conductivity to be verified; and performing data fitting verification based on the set of interfacial conductivity to be verified and the gold plating quality-thickness data set to obtain the interfacial conductivity. This embodiment, by designing samples with different gold layer thicknesses and combining data fitting verification, achieves accurate measurement of the interfacial conductivity of silicon gel / ceramic substrates, solving the technical problem that traditional methods cannot separate the interfacial contribution due to the extremely thin interfacial thickness. It provides key data support for accurately analyzing the three-phase point electric field distribution and improving the insulation reliability of SiC power modules.

[0123] In addition, refer to Figure 8 , Figure 8 This is another structural block diagram of the multiphase material interface conductivity testing device provided in this application embodiment. The multiphase material interface conductivity testing device 2000 includes a processor 1001 and a memory 1005. The memory 1005 stores programs, instructions, or code for executing the aforementioned multiphase material interface conductivity testing method. The processor 1001 executes the programs, instructions, or code stored in the memory 1005. The programs, instructions, or code stored in the memory 1005 are executable. Figures 2 to 6The embodiments shown include some or all of the steps of the method for testing the interfacial conductivity of multiphase materials.

[0124] Since this storage medium adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.

[0125] Furthermore, embodiments of this application also propose a computer-readable storage medium storing a computer program, wherein the storage medium stores a test program for the interfacial conductivity of multiphase materials, and when the test program for the interfacial conductivity of multiphase materials is executed by a processor, it implements the steps of the test method for the interfacial conductivity of multiphase materials as described above.

[0126] It should be understood that the above are merely illustrative examples and do not constitute any limitation on the technical solution of this application. In specific applications, those skilled in the art can make settings as needed, and this application does not impose any restrictions on this.

[0127] It should be noted that the workflow described above is merely illustrative and does not limit the scope of protection of this application. In practical applications, those skilled in the art can select some or all of it to achieve the purpose of this embodiment according to actual needs, and no restrictions are imposed here.

[0128] In addition, for technical details not described in detail in this embodiment, please refer to the test method for the interfacial conductivity of multiphase materials provided in any embodiment of this application, which will not be repeated here.

[0129] Furthermore, it should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0130] The sequence numbers of the embodiments in this application are for description only and do not represent the superiority or inferiority of the embodiments.

[0131] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as read-only memory (ROM) / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0132] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for testing the interfacial conductivity of multiphase materials, characterized in that, The method includes: Test samples with various gold plating schemes were prepared based on the package structure under test, resulting in a test sample set of the package structure under test; The gold plating status of each test sample in the test sample set of the packaged structure under test is statistically analyzed to obtain a set of gold plating quality-thickness data. Each test sample of the packaged structure under test in the test sample set is subjected to interface current test to obtain a set of interface current test results. Based on the preset interface conductivity formula and the set of interface current test results, the set of interface conductivity to be verified is obtained by analysis and calculation. The interface conductivity is obtained by performing data fitting verification based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data.

2. The method for testing the interfacial conductivity of multiphase materials according to claim 1, characterized in that, Test samples with various gold plating schemes were prepared based on the package structure under test, resulting in a test sample set of the package structure under test, including: Design a corresponding mask based on the package structure under test; The mask is placed over the package structure to be tested, and the covered package structure to be tested is gold-plated according to a variety of different gold plating schemes to obtain the corresponding gold-plated package structure to be tested. Test samples are prepared based on all the gold-plated packaging structures under test, resulting in a set of test samples for the packaging structures under test.

3. The method for testing the interfacial conductivity of multiphase materials according to claim 2, characterized in that, The mask is placed over the package structure under test, and gold plating is performed on the covered package structure according to various different gold plating schemes to obtain the corresponding gold-plated package structure under test, including: The mask is placed over the package structure to be tested to obtain the covered package structure to be tested. Based on various different gold plating qualities, corresponding gold plating schemes are designed to obtain a set of gold plating schemes; Based on the set of gold plating schemes, the covered test package structure is gold-plated to obtain the corresponding gold-plated test package structure.

4. The method for testing the interfacial conductivity of multiphase materials according to claim 2, characterized in that, Test samples were prepared based on all the gold-plated packaging structures under test, resulting in a set of test samples for the packaging structures under test, including: First, aluminum foil is pasted onto the gold plating layer of all the gold-plated packaging structures under test as test electrodes. Then, silicone gel is covered onto all the gold-plated packaging structures under test. Finally, all the gold-plated packaging structures under test are dried to obtain a test sample set of the packaging structures under test.

5. The method for testing the interfacial conductivity of multiphase materials according to claim 1, characterized in that, Based on the preset interface conductivity formula and the set of interface current test results, the interface conductivity to be verified is obtained through analysis and calculation, including: The preset interface conductivity formula is read, and the preset interface conductivity formula is: In the formula, ρ int It is the preset interface conductivity, ρ v It is a thickness of h v Volume resistivity of phase at time ρ test It is the resistivity of the test area, h int h is the thickness of the interface to be verified, and h is the thickness of the gold plating layer. The interface current test results are substituted into the preset interface conductivity formula for analysis and calculation to obtain the interface conductivity set to be verified.

6. The method for testing the interfacial conductivity of multiphase materials according to any one of claims 1 to 5, characterized in that, Based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data, data fitting verification is performed to obtain the interface conductivity, including: Get the preset interface thickness threshold range; Based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data, data fitting analysis is performed to obtain the interface thickness fitting result. Data verification is performed based on the preset interface thickness threshold range and the interface thickness fitting result to obtain the data verification result; If the data verification result is qualified, the interface conductivity is obtained based on the interface thickness fitting result.

7. The method for testing the interfacial conductivity of multiphase materials according to claim 6, characterized in that, After performing data verification based on the preset interface thickness threshold range and the interface thickness fitting result, the process further includes: If the data verification result is unqualified, at least two test samples with different thicknesses than the existing gold layer are prepared first, and their interface resistivity is tested to expand the set of interface conductivity to be verified. Then, based on the expanded set of interface conductivity to be verified, a refit is performed. If the secondary interface thickness fitting result obtained by refitting falls within the preset interface thickness threshold range, the data verification result is determined to be qualified and the interface resistivity is output.

8. A testing device for the interfacial conductivity of multiphase materials, characterized in that, The device includes: Sample preparation module: Based on the package structure under test, test samples with various gold plating schemes are prepared to obtain a set of test samples of the package structure under test; Gold plating statistics module: Perform gold plating status statistics on each test sample of the packaged structure under test in the test sample set to obtain a gold plating quality-thickness data set. Current testing module: Performs interface current testing on each test sample of the packaged structure under test in the test sample set to obtain a set of interface current test results; Analysis and calculation module: Based on the preset interface conductivity formula and the set of interface current test results, it performs analysis and calculation to obtain the set of interface conductivity to be verified; Fitting and verification module: Based on the set of interface conductivity to be verified and the set of gold plating quality-thickness data, data fitting and verification are performed to obtain the interface conductivity.

9. An electronic device, characterized in that, The electronic device includes: a memory; a processor; and one or more computer programs stored in the memory, the one or more computer programs including instructions that, when executed by the processor, enable the method for testing the interfacial conductivity of multiphase materials as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes instructions that, when executed by a processor, enable the method for testing the interfacial conductivity of multiphase materials as described in any one of claims 1 to 7.

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