Capacitor loss test circuit and test method thereof
By designing a capacitor loss test circuit that supports both unipolar and bipolar modes, and utilizing a freewheeling inductor and three energy flow paths, the problem of simulating operating conditions in three-pulse cycle tests in existing capacitor loss test circuits is solved, achieving fast, stable, and efficient capacitor loss testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-22
- Publication Date
- 2026-04-14
AI Technical Summary
Existing capacitor loss test circuits are difficult to simulate the unipolar and bipolar modulation conditions of converters in three-pulse cycle tests, and the transition time required for the test is too long, making it difficult to achieve steady-state collection of high-frequency data.
A capacitor loss test circuit was designed, including a half-bridge circuit, a power supply module, an absorption capacitor, and a capacitor under test. It supports unipolar and bipolar modes. The half-bridge circuit is connected to the midpoint through a freewheeling inductor. It utilizes three energy flow paths to achieve a rapid transition to a stable state. Combined with a three-pulse cycle test method, it can automatically test capacitor loss.
It enables a rapid transition to a stable state during three-pulse cyclic testing, supports capacitance loss testing under various modulations, improves testing efficiency and accuracy, and is suitable for capacitance loss testing under unipolar and bipolar modulation.
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Figure CN121856646A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of capacitor loss testing technology, and particularly relates to a capacitor loss testing circuit and its testing method. Background Technology
[0002] In the rapid development of modern power electronics technology, capacitors, as key passive components, are widely used in various power converters and drive systems, undertaking important functions such as energy storage, power balancing, and voltage ripple suppression. As systems evolve towards higher frequencies, higher voltages, and higher power densities, capacitors need to suppress even greater current ripple. Simultaneously, the resistance of the plates, wires, and dielectric, as well as the repeated polarization of the dielectric, generate additional losses, thus affecting the lifespan of the devices and the reliability of the system. Therefore, it is urgent to characterize capacitor losses under different operating conditions to improve the performance and reliability of converters.
[0003] A previous method for testing capacitor loss utilized a three-pulse cycle test to characterize capacitor losses during actual operation of a pulse-width modulation converter from the perspective of the switching cycle. However, the full-bridge test circuit used previously could only simulate the excitation waveform of the DC-side capacitor under bipolar modulation of the converter, making it difficult to simulate the operating conditions of the DC-side capacitor under unipolar modulation. Furthermore, when establishing the test current at the initial stage of the test, this structure needs to draw a significant amount of energy from the capacitor under test, resulting in an excessively long transition time (the time required for the system and the capacitor under test to reach a steady state). This problem is particularly pronounced when collecting high-frequency data, making it difficult for the system to reach a steady state.
[0004] Therefore, a capacitor loss testing circuit suitable for three-pulse cycle testing is needed to realize capacitor loss testing under various modulations. Summary of the Invention
[0005] The purpose of this invention is to provide a capacitor loss testing circuit and a testing method thereof to solve the problems mentioned in the background art.
[0006] To address the aforementioned technical problems, the present invention provides the following technical solution: a capacitance loss testing circuit, characterized in that the testing circuit includes...
[0007] Half-bridge circuit: includes a first half-bridge circuit and a second half-bridge circuit connected together; Power supply module: includes a first power supply connected to the first half-bridge circuit and a second power supply connected to the second half-bridge circuit; Absorption capacitor bank: includes a first capacitor connected to the DC side of the first half-bridge circuit and a second capacitor connected to the DC side of the second half-bridge circuit. The capacitor under test is selectively connected between the first power supply and the first capacitor or between the second power supply and the second capacitor. The test circuit operates in two modes: unipolar and bipolar. In unipolar mode, the capacitor under test is located between the first power supply and the first capacitor. This mode simulates the energy flow of the DC-side capacitor during one switching cycle when the pulse width modulation converter is in unipolar modulation. In bipolar mode, the capacitor under test is located between the second power supply and the second capacitor. This mode simulates the energy flow of the DC-side capacitor during one switching cycle when the pulse width modulation converter is in bipolar modulation.
[0008] Furthermore, the midpoints of the first and second half-bridge circuits are connected by a freewheeling inductor.
[0009] Furthermore, the first half-bridge circuit includes a first power switching device and a second power switching device connected to each other, and the second half-bridge circuit includes a second power switching assembly and a second power switching device connected to each other.
[0010] Furthermore, the test circuit also includes a fifth power switching device, the source of which is connected to the positive DC input of the second half-bridge circuit through a reverse protection diode, and the drain is connected to the midpoint of the first half-bridge circuit.
[0011] Furthermore, the first power switch, the second power switch, the third power switch, the fourth power switch, the fifth power switch, and the anti-reverse diode are all wide-bandgap semiconductor devices to provide higher test bandwidth.
[0012] Furthermore, the test circuit includes three energy flow paths: the first path is from the positive terminal of the first power supply to the first power switch device to the freewheeling inductor to the fourth power switch device to the negative terminal of the first power supply; the second path is from the negative terminal of the second power supply to the second power switch device to the freewheeling inductor to the third power switch device to the positive terminal of the second power supply; and the third path is from the positive terminal of the second power supply to the fifth power switch device to the freewheeling inductor to the fourth power switch device to the negative terminal of the second power supply.
[0013] Furthermore, both the first capacitor and the second capacitor are high-frequency capacitors, used to absorb the spikes generated during the switching of the switching devices.
[0014] In another aspect, the present invention provides a method for testing a capacitor loss test circuit, comprising the following steps: S1: Controls the first and second power supplies to be at preset voltages; S2: Apply control pulse P1, wherein, in unipolar mode, a third energy flow path is constructed during the high-level phase of P1, and the current is established through the second power supply using the freewheeling inductor. After the current reaches the preset current value, the test circuit switches to the second energy flow path during the low-level phase of P1 so that the system reaches the preset test operating point. In bipolar mode operation, a first energy flow path is constructed during the P1 high-level phase. The freewheeling inductor is used to establish current through the first power supply. After the current reaches the preset current value, the test circuit switches to the second energy flow path during the P1 low-level phase so that the system reaches the preset test operating point. S3: Apply control pulse P2. In unipolar mode, the first energy flow path and the second energy flow path are constructed during the high-level and low-level phases of P2, respectively. Switching between the two is performed for multiple switching cycles to connect the capacitor under test into the test circuit and transition to a stable state. In bipolar mode, a third energy flow path and a second energy flow path are constructed during the high-level and low-level phases of P2, respectively. Switching between the two is performed for multiple switching cycles to connect the capacitor under test into the test circuit and transition to a stable state. S4: Continue to apply control pulse P3. In unipolar mode, the test circuit is placed in the first energy flow path during the high-level phase of P3 and in the second energy flow path during the low-level phase of P3, in order to obtain the electrical quantity data required under this test condition. In bipolar mode, the test circuit is placed in the third energy flow path during the P3 high level phase and in the second energy flow path during the P3 low level phase, in order to obtain the electrical quantity data required under the test condition. S5: Construct a second energy flow path until the freewheeling inductor current drops to 0, then turn off all power switching devices and power supplies to stop the equipment from operating; S6: Use the electrical quantity data obtained in S4 to establish a loss model of the measured capacitor, which is used to calculate the loss of the DC-side capacitor of the PWM converter in each switching cycle under different modulation methods.
[0015] Furthermore, the high-level duration of P1 is determined by the preset current value and freewheeling inductance value to be 1ms to 100ms. Its low-level pulse duration is consistent with the low-level pulse duration of the control pulse P2. P2 and P3 pulses are consistent, which are square waves with a duty cycle of 50%. Their period is determined by the test conditions to be 1us to 1ms. Multiple sets of P2 are used to transition the test system to a stable state, and P3 is used to measure the data required for loss calculation and modeling.
[0016] Furthermore, in the preset voltage, the relationship between the first power supply voltage and the second power supply voltage is as follows, used to maintain the absolute value of the freewheeling inductor voltage being equal when switching between the first energy flow path and the second energy flow path: ; In the formula V Q+ V is the forward voltage drop of the power switching device used under the corresponding current. Q- To correspond to the reverse freewheeling voltage drop of the tube, V dc1 V is the first power supply voltage. dc2 This is the second power supply voltage.
[0017] Compared with the prior art, the beneficial effects achieved by the present invention are: The capacitance loss test circuit of this application includes two operating modes: unipolar mode and bipolar mode. The unipolar mode simulates the energy flow of the DC-side capacitor of the capacitor under test during one switching cycle when the pulse width modulation converter is in unipolar modulation. The bipolar mode simulates the energy flow of the DC-side capacitor of the capacitor under test during one switching cycle when the pulse width modulation converter is in bipolar modulation. Compared to traditional circuits, this circuit can transition the capacitor under test to a stable state more quickly in three-pulse cycle testing, requiring fewer transition pulses and eliminating the need to adjust the number of transition pulses according to the test conditions. This allows for better automation of three-pulse cycle testing. Furthermore, the circuit operation method, when used in conjunction with the three-pulse cycle testing method, can achieve discrete capacitance loss testing and simultaneously perform DC-side capacitance loss testing under both unipolar and bipolar modulation conditions of the converter. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a power path diagram of a single-phase inverter provided in an embodiment of the present invention; Figure 2 A schematic diagram of a full-bridge-based test circuit structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the capacitor loss testing circuit structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the control pulse timing of the test circuit provided in an embodiment of the present invention; Figure 5A schematic diagram of a GaN HEMT-based test platform provided in an embodiment of the present invention; Figure 6 A typical waveform diagram for unipolar testing provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the MATLAB simulation circuit provided in the embodiment of the present invention; Figure 8 Estimated and measured losses of the CUT under each operating condition are provided for embodiments of the present invention. Figure 9 The diagram shows the prediction error of the loss model at different frequencies provided in the embodiments of the present invention. Detailed Implementation
[0020] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. These embodiments are implemented based on the technical solution of the present invention and provide detailed implementation methods and specific operation processes. However, the scope of protection of the present invention is not limited to the following embodiments.
[0021] According to an embodiment of the present invention: To accurately characterize the power loss of the DC-side capacitor during each switching cycle of the power electronic converter, this embodiment discloses a DC-side capacitor loss test circuit.
[0022] For a single-phase full-bridge inverter, the energy flow path of its DC-side capacitor differs depending on the modulation method during continuous operation. When the single-phase full-bridge inverter uses bipolar modulation, its power flow path is as follows: Figure 1 As shown in Figure (a), it can be seen from the figure that, regardless of whether it is in the positive or negative half-cycle of the sine cycle, in a complete switching cycle, the AC side will both draw energy from and feed energy back to the DC side capacitor. When the single-phase full-bridge inverter adopts unipolar modulation, its power flow path is as follows: Figure 1 As shown in Figure (b), it can be seen from the figure that during the positive and negative half-cycles of the sine cycle, the AC side only draws energy from the DC side capacitor and does not feed energy back to it. All the energy of the DC side capacitor comes from the DC side power supply.
[0023] For capacitor loss testing under bipolar modulation, a single-phase full-bridge circuit can be directly used as the test circuit, with the load inductor L passing through the midpoint of the outputs of the two half-bridges. load Connections, such as Figure 2 As shown. In order to maintain the test current at a relatively constant level during the test, L loadThe selected values can be as large as possible. This reduces the current drop caused by device voltage drops in different power paths and also reduces the fluctuation of the test current within a switching cycle. When transistors Q1 and Q4 are turned on, it can be used to simulate the scenario where the AC side draws energy from the DC side capacitor in a real circuit. When transistors Q2 and Q3 are turned on, it can be used to simulate the scenario where the AC side feeds energy back from the DC side capacitor in a real circuit. This method can be used to obtain the loss data generated when the capacitor releases or absorbs energy at a real operating point. For unipolar modulation mode, since the energy release path is limited during the current freewheeling stage, directly using the above circuit can easily lead to a continuous rise in current, affecting the test stability.
[0024] Therefore, this embodiment discloses as follows: Figure 3 The circuit structure shown has a first half-bridge circuit (Phase 1) composed of the first power switching device (Q1) and the second power switching device (Q2), and a second half-bridge circuit (Phase 2) composed of the third power switching device (Q3) and the fourth power switching device (Q4). The negative DC input terminals of Phase 1 and Phase 2 are connected to each other, and the midpoints of the half-bridges of Phase 1 and Phase 2 are connected through a freewheeling inductor (L). The inductance of the freewheeling inductor is 10mH, which is used to maintain the test current.
[0025] The power supply module includes a first power supply (V dc1 ) and second power supply (V dc2 ), V dc1 and V dc2 It is an adjustable two-phase DC source, which can be adjusted by adjusting V dc1 With V dc2 It can achieve flexible control of voltage and current operating points, and realize energy extraction and freewheeling processes through different combinations of switching devices.
[0026] V dc1 V dc2 Connected to the DC input sides of Phase 1 and Phase 2 respectively; the fifth power switching device (Q 1_1 The source of the circuit is connected to the positive DC input of Phase 2 via a reverse protection diode (D1), and the drain is connected to the midpoint of the half-bridge of Phase 1. In this embodiment, both the power switching device and the reverse protection diode are wide-bandgap semiconductor devices such as GaN HEMTs to provide a high test bandwidth. The first and second power supplies are adjustable DC sources and both are bidirectional DC sources with an output voltage of 0–800V, used to provide power to the test circuit.
[0027] The absorption capacitor bank includes a first capacitor (C1) and a second absorption capacitor (C2), with C1 and C2 located on the DC side of Phase 1 and Phase 2, respectively. Both the first and second capacitors are high-frequency capacitors with a capacitance of 8μF, used to absorb the spikes generated during the turn-on and turn-off of the power switching devices. The capacitor under test (CUT) can be placed at V according to the circuit's operating mode. dc1 Between C1 or V dc2 Between C2 and C2. In this embodiment, the capacitance loss test circuit includes two modes: unipolar mode and bipolar mode. When placed at V... dc1 When connected to C1, it enters unipolar mode. This mode is used to simulate the energy flow of the DC-side capacitor of the capacitor under test during one switching cycle when the pulse width modulation converter is in unipolar modulation. When placed at V dc2 When connected to C2, it enters bipolar mode, which is used to simulate the energy flow of the DC-side capacitor of the capacitor under test during one switching cycle when the pulse width modulation converter is in bipolar modulation.
[0028] The capacitor loss test circuit contains three energy flow paths. The first energy flow path (Path1) is V dc1 From positive electrode to Q1 to L to Q4 to V dc1 The negative electrode has a second energy flow path (Path2) of V. dc2 negative electrode to Q2 to L to Q3 to V dc2 At the positive electrode, the third energy flow path (Path 3) is V dc2 From positive electrode to Q 1_1 To L to Q4 to V dc2 negative electrode.
[0029] like Figure 4 As shown, according to the control pulse timing diagram of the test circuit in this embodiment, the test process can be divided into four stages: the test current establishment stage, the transition stage, the test stage, and the energy release stage.
[0030] Specifically for unipolar mode: Test current setup phase: Apply a high-level signal for a duration of T. 1+ The low-level time is T 1- The control pulse at T 1+ During this period, control Q 1_1 Connect to Q4, establish Path3, and in T 1- The timing controls Q2 and Q3 to turn on, establishing Path2 to establish the target inductor current I. L To simulate AC current measurement conditions. The initial pulse high-level duration T... 1+ It can be determined by the following formula: ; Transition phase: Apply 3 to 4 sets of high-level signals for a duration of T. 2+ The low-level time is T 2- The control pulse at T 2+ During the period, Q1 and Q4 are turned on, Path1 is established, and in T 2- During this period, Q2 and Q3 are turned on to establish Path 2. This stage is used to allow the system and the capacitor under test to transition to a steady state under test conditions in preparation for data collection.
[0031] Test phase: Apply a set of high-level signals for a duration of T. 2+ The low-level time is T 2- The control pulse at T 2+ During the period, Q1 and Q4 are turned on, Path1 is established, and in T 2- During this period, Q2 and Q3 are turned on to establish Path2. This stage is used to collect relevant data, including capacitor voltage V. C Capacitor current I C Inductor current I L and the duration T of the high-level pulse 2+ It is worth noting that T 2+ With T 2- The duty cycle of the control pulse should be kept constant during the test, that is, the duty cycle of the control pulse should be 50% during both the transition phase and the test phase.
[0032] Energy release phase: Control Q2 and Q3 to conduct, establish Path2, and block all control pulses until the inductor energy is completely released.
[0033] For bipolar mode: Test current setup phase: Apply a high-level signal for a duration of T. 1+ The low-level time is T 1- The control pulse at T 1+ During this period, control the conduction of Q1 and Q4, establish Path1, and in T 1- The timing controls Q2 and Q3 to turn on, establishing Path2 to establish the target inductor current I. L To simulate AC current measurement conditions.
[0034] Transition phase: Apply 3 to 4 sets of high-level signals for a duration of T. 2+ The low-level time is T 2- The control pulse at T 2+ Period control Q 1_1 Connect to Q4, establish Path3, and in T 2- During this period, Q2 and Q3 are turned on to establish Path 2. This stage is used to allow the system and the capacitor under test to transition to a steady state under test conditions in preparation for data collection.
[0035] Test phase: Apply a set of high-level signals for a duration of T. 2+ The low-level time is T 2- The control pulse at T 2+ Period control Q 1_1 Connect to Q4, establish Path3, and in T 2- During this period, Q2 and Q3 are turned on to establish Path2. This stage is used to collect relevant data, including capacitor voltage V. C Capacitor current I C Inductor current I L and the duration T of the high-level pulse 2+ .
[0036] Energy release phase: Control Q2 and Q3 to conduct, establish Path2, and block all control pulses until the inductor energy is completely released.
[0037] The testing system also includes a host computer, a high-speed router, and a high-speed controller to automate testing and reduce testing time. The adjustable DC power supply and oscilloscope are connected to the high-speed router via wired connections; the host computer is connected to the high-speed router wirelessly; and the high-speed controller is connected to the host computer.
[0038] The host computer performs core control and data processing, communicating and coordinating with various instruments on the test bench through multiple interfaces. First, the host computer establishes connections with the DC power supply and oscilloscope, used to control the power supply's output voltage and current parameters, and to acquire voltage and current waveform data during the test. Dynamic power management is achieved through gradual adjustments to the DC power supply during the test. Simultaneously, the oscilloscope's multi-channel high-speed sampling function acquires the voltage and current waveforms on the inductor and downloads them to the host computer. Furthermore, the host computer controls the start and stop of the three-pulse cyclic test program via serial communication.
[0039] The automated testing process consists of four main stages: Pre-test phase: In capacitor loss testing, the test current is maintained by an inductor. A high-current test is performed before the three-pulse cycle test to ensure that the system is fully functional and available.
[0040] Test preparation phase: Load the capacitor parameters into the test module and preset the target operating point to complete the initialization settings before the test.
[0041] Automatic Testing Phase: Combining the three-pulse cyclic test, the program controls the test circuit to operate in the corresponding mode within each test cycle, determining whether the DC bias has reached the preset conditions based on real-time acquired data. If the test conditions are not met, the system will automatically adjust the DC voltage and test pulses until the system reaches the preset voltage and current state. Once the test conditions are met, the test system will record the volt-ampere data acquired at the current test point and save it as a CSV file, then continuously cycle to the next test point. Throughout the entire testing process, the average test time for each test point is approximately 5 seconds.
[0042] Post-processing stage: The loss data of the preset target operating point can be obtained by simply calculating based on the three-pulse automatic test inductor voltage and current data stored in the computer.
[0043] Regarding the experimental platform setup, a test platform based on gallium nitride high electron mobility transistors (GaN HEMTs) was built, such as... Figure 5 As shown. The selected gallium nitride device is the Infineon GS66508T. To maintain a constant load current during the test, two inductors with a rated inductance of 10 mH are connected in series as the load inductance. The main instruments used in the experiment include: a current probe (Keysight N2783B), a voltage probe (Keysight N2790A), an oscilloscope (Keysight DSOX3024T), and an electrolytic capacitor (450MXG100MEFCSN25X25) manufactured by Rubycon. A typical waveform of its unipolar test is shown below. Figure 6 As shown.
[0044] Taking unipolarity testing as an example, based on the V obtained from the test... C I C Calculate separately at T 2+ With T 2- The loss E generated by the capacitor during the time period Loss After that, V C I L I L T is the input, E Loss A loss model is established for the output, and its model expression is shown in the following equation: ; In the formula, T represents the duration of the pulse high or low level. The test conditions are shown in Table 1. During the test, the original dataset is obtained by combining the described circuit operation method with the three-pulse cycle test method.
[0045] Table 1. Test Conditions
[0046] Subsequently, 15 different operating conditions were set up for MATLAB / Simulink simulation to obtain the input variables used to estimate the loss of the capacitor under test. Specifically, the DC-side voltage was set to 20 V, 30 V, 40 V, 50 V, and 60 V, and the switching frequencies were 10 kHz, 15 kHz, and 20 kHz, respectively. The filter inductor was 20 mH, and the load was a 20 Ω resistor. During the simulation, the voltage V under each operating condition was recorded. C I load The pulses from the A-phase bridge arm and the B-phase bridge arm are then input into a trained loss model to calculate the CUT loss. The simulation circuit is shown below. Figure 7 As shown. In actual operation, the converter's operating conditions are set to match the simulation. During operation, a WT5000 power analyzer is used to measure the actual losses of the CUT under each operating condition and compare them with the predicted results. Figure 8 This demonstrates how to estimate and measure loss. From... Figure 9 It can be seen that at switching frequencies of 10kHz and 15kHz, the loss model exhibits good predictive performance for different operating conditions, with prediction errors within 10%. At a switching frequency of 20kHz, the model's prediction error is approximately 17%. These results indicate that the circuit is well-suited for the three-pulse cycle test method, enabling this method to be used for capacitor loss testing under both unipolar and bipolar modulation, and giving the three-pulse cycle test method the potential to calculate the DC-side capacitor loss of a three-phase converter.
[0047] According to another embodiment of the present invention: This embodiment discloses a testing method for a capacitance loss testing circuit. Using the capacitance loss testing circuit of Embodiment 1, in unipolar mode, the method includes the following steps: S1 controls the adjustable DC source V dc1 V dc2 Under a preset voltage; preset voltage V dc1 With V dc2 The voltage relationship is shown in the following formula, which is used to maintain the absolute value of the freewheeling inductor voltage equal when switching between energy path Path1 and energy path Path2: ; In the formula V Q+ V is the forward voltage drop of the power device used under the corresponding current. Q- This represents the tube voltage drop under reverse freewheeling current.
[0048] S2 applies a control pulse P1, and during the high-level phase of P1, an energy path Path3 is constructed, utilizing the freewheeling inductor L to supply an adjustable DC source V. dc2Once the current is established and reaches the preset current value, the test circuit switches to energy path Path2 during the low-level phase of P1 so that the system reaches the preset test operating point. S3 applies control pulse P2, constructing energy path Path1 and energy path Path2 during the high-level and low-level phases of P2 respectively, and switching between the two for 3 to 5 switching cycles to connect the capacitor under test into the test circuit and transition to a stable state. S4 continues to apply control pulse P3. During the high-level phase of P3, the test circuit is placed in energy path Path1, and during the low-level phase of P3, the test circuit is placed in energy path Path2, in order to obtain the data of the electrical quantities required under this test condition. S5 constructs energy path Path2 until the freewheeling inductor current drops to 0, after which it blocks all energy paths, causing the device to stop operating. S6 uses the electrical quantity data obtained from A4 to establish a loss model of the measured capacitor, which is used to calculate the loss of the DC-side capacitor of the PWM converter in each switching cycle under unipolar modulation.
[0049] In bipolar mode, the following steps are included: S1 controls the adjustable DC source V dc1 V dc2 Under preset voltage; S2 applies a control pulse P1, establishing an energy path Path1 during the high-level phase of P1, utilizing the freewheeling inductor to supply an adjustable DC source V. dc1 Once the current is established and reaches the preset current value, the test circuit switches to energy path Path2 during the low-level phase of P1 so that the system reaches the preset test operating point. S3 applies control pulse P2, constructing energy path Path3 and energy path Path2 respectively during the high-level and low-level phases of P2, and switching between the two for 3 to 5 switching cycles to connect the capacitor under test into the test circuit and transition to a stable state. S4 continues to apply control pulse P3. During the high-level phase of P3, the test circuit is in energy path Path1. During the high-level phase of P3, the test circuit is in energy path Path2, which is used to obtain the data of the electrical quantities required under this test condition. S5 constructs the energy path Path2 until the freewheeling inductor current drops to 0, after which it shuts down all power devices and DC power sources, causing the equipment to stop operating. S6 uses the electrical quantity data obtained from B4 to establish a loss model of the capacitor under test, which is used to calculate the loss of the DC-side capacitor of the PWM converter in each switching cycle under bipolar modulation.
[0050] Control pulses P1, P2, and P3 are used. The duration of the high-level pulse of P1 is determined by the preset current value and the freewheeling inductance value, ranging from 1ms to 100ms. The duration of its low-level pulse is the same as that of the low-level pulse of control pulse P2. P2 and P3 are the same, which are square waves with a duty cycle of 50%. Their period is determined by the test conditions, ranging from 1us to 1ms. Multiple sets of P2 are used to transition the test system to a stable state, and P3 is used to measure the data required for loss calculation and modeling.
[0051] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.
Claims
1. A capacitor loss testing circuit, characterized in that, The test circuit includes Half-bridge circuit: includes a first half-bridge circuit and a second half-bridge circuit connected together; Power supply module: includes a first power supply connected to the first half-bridge circuit and a second power supply connected to the second half-bridge circuit; Absorption capacitor bank: includes a first capacitor connected to the DC side of the first half-bridge circuit and a second capacitor connected to the DC side of the second half-bridge circuit. The capacitor under test is selectively connected between the first power supply and the first capacitor or between the second power supply and the second capacitor. The test circuit operates in two modes: unipolar and bipolar. In unipolar mode, the capacitor under test is located between the first power supply and the first capacitor. This mode simulates the energy flow of the DC-side capacitor during one switching cycle when the pulse width modulation converter is in unipolar modulation. In bipolar mode, the capacitor under test is located between the second power supply and the second capacitor. This mode simulates the energy flow of the DC-side capacitor during one switching cycle when the pulse width modulation converter is in bipolar modulation.
2. The capacitance loss testing circuit according to claim 1, characterized in that, The midpoints of the first and second half-bridge circuits are connected by a freewheeling inductor.
3. The capacitance loss testing circuit according to claim 1, characterized in that, The first half-bridge circuit includes a first power switch and a second power switch connected to each other, and the second half-bridge circuit includes a second power switch and a fourth power switch connected to each other.
4. The capacitance loss testing circuit according to any one of claims 1 to 3, characterized in that, The test circuit also includes a fifth power switching device, the source of which is connected to the positive DC input of the second half-bridge circuit through a reverse protection diode, and the drain is connected to the midpoint of the first half-bridge circuit.
5. The capacitance loss testing circuit according to claim 4, characterized in that, The first power switch, the second power switch, the third power switch, the fourth power switch, the fifth power switch, and the anti-reverse diode are all wide-bandgap semiconductor devices, used to provide higher test bandwidth.
6. The capacitance loss testing circuit according to claim 4, characterized in that, The test circuit includes three energy flow paths: the first path is from the positive terminal of the first power supply to the first power switch device to the freewheeling inductor to the fourth power switch to the negative terminal of the first power supply; the second path is from the negative terminal of the second power supply to the second power switch device to the freewheeling inductor to the third power switch device to the positive terminal of the second power supply; and the third path is from the positive terminal of the second power supply to the fifth power switch interval to the freewheeling inductor to the fourth power switch device to the negative terminal of the second power supply.
7. The capacitance loss testing circuit according to claim 1, characterized in that, Both the first capacitor and the second capacitor are high-frequency capacitors, used to absorb the spikes generated during the switching of the switching devices.
8. A test method for the capacitance loss test circuit according to claim 6, characterized in that, Includes the following steps: S1: Controls the first and second power supplies to be at preset voltages; S2: Apply control pulse P1, wherein, in unipolar mode, a third energy flow path is constructed during the high-level phase of P1, and the current is established through the second power supply using the freewheeling inductor. After the current reaches the preset current value, the test circuit switches to the second energy flow path during the low-level phase of P1 so that the system reaches the preset test operating point. In bipolar mode operation, a first energy flow path is constructed during the P1 high-level phase. The freewheeling inductor is used to establish current through the first power supply. After the current reaches the preset current value, the test circuit switches to the second energy flow path during the P1 low-level phase so that the system reaches the preset test operating point. S3: Apply control pulse P2. In unipolar mode, the first energy flow path and the second energy flow path are constructed during the high-level and low-level phases of P2, respectively. Switching between the two is performed for multiple switching cycles to connect the capacitor under test into the test circuit and transition to a stable state. In bipolar mode, a third energy flow path and a second energy flow path are constructed during the high-level and low-level phases of P2, respectively. Switching between the two is performed for multiple switching cycles to connect the capacitor under test into the test circuit and transition to a stable state. S4: Continue to apply control pulse P3. In unipolar mode, the test circuit is placed in the first energy flow path during the high-level phase of P3 and in the second energy flow path during the low-level phase of P3, in order to obtain the electrical quantity data required under this test condition. In bipolar mode, the test circuit is placed in the third energy flow path during the P3 high level phase and in the second energy flow path during the P3 low level phase, in order to obtain the electrical quantity data required under the test condition. S5: Construct a second energy flow path until the freewheeling inductor current drops to 0, then turn off all power switching devices and power supplies to stop the equipment from operating; S6: Use the electrical quantity data obtained in S4 to establish a loss model of the measured capacitor, which is used to calculate the loss of the DC-side capacitor of the PWM converter in each switching cycle under different modulation methods.
9. The test method according to claim 8, characterized in that, The high-level duration of P1 is determined by the preset current value and freewheeling inductance value, ranging from 1ms to 100ms. Its low-level pulse duration is consistent with the low-level pulse duration of the control pulse P2. P2 and P3 pulses are consistent, being square waves with a 50% duty cycle. Their period is determined by the test conditions, ranging from 1μs to 1ms. Multiple sets of P2 are used to transition the test system to a stable state, while P3 is used to measure the data required for loss calculation and modeling.
10. The test method according to claim 8, characterized in that, The relationship between the first power supply voltage and the second power supply voltage in the preset voltage is as follows, used to maintain the absolute value of the freewheeling inductor voltage being equal when switching between the first energy flow path and the second energy flow path: ； In the formula V Q+ V is the forward voltage drop of the power switching device used under the corresponding current. Q- To correspond to the reverse freewheeling voltage drop of the tube under the current, V dc1 V is the first power supply voltage. dc2 This is the second power supply voltage.