Temperature-compensated band-gap reference circuit

Abstract

The invention discloses a temperature compensation band-gap reference circuit, relates to the technical field of analog integrated circuits, and aims to solve the problem that a traditional band-gap reference circuit is large in temperature drift due to the fact that the traditional band-gap reference circuit is affected by a VBE nonlinear high-order term within a wide temperature range. The circuit comprises a bias circuit module, a starting circuit module, a temperature compensation circuit module and a band gap core circuit module. Wherein the bias circuit module provides temperature-insensitive bias current for the system through the current mirror network; the starting circuit module realizes power-on quick starting, normal working zero static power consumption and power-down quick reset by utilizing the synergistic effect of a capacitor and a switch; according to the band-gap core circuit module and the temperature compensation circuit module, nonlinear voltage characteristics are extracted through triode emitter voltage difference, reverse compensation current is introduced through a feedback loop, and a high-order temperature drift item in reference voltage is accurately offset. In addition, the circuit adopts a composite resistor structure in which polycrystalline silicon and diffusion resistors are connected in series, so that process deviation and resistance temperature drift are further inhibited.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a temperature-compensated bandgap reference circuit. Background Technology

[0002] In modern integrated circuit design, the reference voltage source is the internal reference voltage source for all analog and mixed-signal systems. It is responsible for providing a stable reference voltage that is independent of the voltage level (PVT). The accuracy of the reference voltage directly determines the conversion accuracy of ADCs / DACs, the output stability of linear regulators, and the measurement accuracy of various sensors.

[0003] The most classic reference voltage source is the traditional BJT bandgap reference. Its basic principle utilizes the negative temperature coefficient of the base-emitter voltage of a BJT and the positive temperature coefficient of the base-emitter voltage difference between two BJTs operating at different current densities. By adding VBE to the amplified ΔVBE, zero temperature coefficient can be achieved at a specific temperature; this is called first-order temperature compensation. However, with advancements in semiconductor technology and increasing application demands, traditional first-order compensated bandgap references face significant challenges. Physics research shows that the relationship between VBE and temperature is not strictly linear. According to the Shockley equation and the physical characteristics of transistors, the complete expression for VBE includes a high-order nonlinear term TlnT. In traditional first-order compensation circuits, this term cannot be eliminated, causing the output voltage to exhibit a downward-opening parabolic shape as it changes with temperature. Within a wide temperature range of -40℃ to 125℃, this curvature error typically results in a temperature drift of 10~40ppm / ℃, which is unacceptable for high-end applications that require <5ppm / ℃.

[0004] Furthermore, the startup problem of the bandgap reference circuit is also a design challenge. Bandgap core circuits typically have two stable operating points: one is a normal non-zero current operating point, and the other is a degenerate point where all branch currents are zero. A startup circuit must be introduced to break the degenerate point when the system powers on. However, traditional startup circuit designs often face two extremes: either strong startup capability but high static power consumption, affecting low-power performance; or low power consumption but startup failure under extreme process corners or slow power-up slopes. More seriously, some startup circuits may experience leakage current injection into the core circuit at high temperatures, causing the reference voltage to deviate.

[0005] Against this backdrop, this invention proposes an innovative high-order temperature-compensated bandgap reference circuit. This circuit not only extracts and eliminates nonlinear terms through topological structure but also integrates a low-power, high-reliability startup circuit and resistance temperature compensation technology, meeting the operational requirements of bandgap reference circuits. Summary of the Invention

[0006] The purpose of this invention is to provide a high-order temperature-compensated bandgap reference circuit. By introducing a specific compensation current for the TlnT term, combined with composite resistor technology and an optimized startup circuit, the problems of large temperature drift, unreliable startup, and high power consumption in the prior art are solved.

[0007] This invention provides a temperature-compensated bandgap reference circuit, comprising: a bias circuit module, a startup circuit module, a bandgap core circuit module, and a temperature compensation circuit module connected to each other. The bias circuit module is used to provide bias voltage for the bandgap core circuit module and the temperature compensation circuit module; it is also used to start itself up and generate a reference current based on the primary reference voltage. The startup circuit module is used to power itself on; during its power-on phase, it generates a startup current that is transmitted to the bandgap core circuit module; and it is also used to control itself to stop working based on the stable operation. The bandgap core circuit module is used to generate a primary reference voltage containing positive and negative temperature coefficient terms based on the bias voltage and transmit it to the bias circuit module; it gets rid of its degeneracy point based on the startup current and then enters a stable operating state; based on the stable operating state, it generates a stable operating signal and sends it to the startup circuit module. The temperature compensation circuit module is used to couple with the bandgap core circuit module to detect its own internal nonlinear voltage characteristics; based on the nonlinear voltage characteristics, it generates a compensation current to form its own compensation voltage.

[0008] Preferably, the bias circuit module includes: PMOS transistors M7, M8, M9, M10, M15, and M16; NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N11, NMOS transistor N12, NMOS transistor N13, NMOS transistor N14, NMOS transistor N17 and NMOS transistor N18; The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8, the drain of PMOS transistor M7 is connected to the source of PMOS transistor M9, and the drain of PMOS transistor M8 is connected to the source of PMOS transistor M10, forming the input stage of the current mirror; the gate of PMOS transistor M9 and the gate of PMOS transistor M10 form a common source and common gate structure, which is used to improve the output impedance and matching accuracy of the current mirror. The drain of the PMOS transistor M9 is connected to the drain and gate of the NMOS transistor N11; the source of the NMOS transistor N11 is connected to the drain and gate of the NMOS transistor N12. The NMOS transistors N1, N3, and N5 are connected in series to form a first bias branch; the NMOS transistors N2, N4, and N6 are connected in series to form a second bias branch; wherein the gates of NMOS transistors N5 and N6 are interconnected and connected in the form of a diode, which is used to provide the underlying bias voltage for the first bias branch and the second bias branch; The gate of the PMOS transistor M15 is connected to the drain of the PMOS transistor M16; the drain of the PMOS transistor M16 is connected to the drain of the NMOS transistor N17; the NMOS transistor N17 and the NMOS transistor N18 form a cascaded current branch on the right side, and the source of the NMOS transistor N17 and the drain of the NMOS transistor N18 are connected to the power supply VDD.

[0009] Preferably, the gate of the PMOS transistor M15 is used as the first port, and the first port is connected to the gate of the PMOS transistor M27 and the gate of the PMOS transistor M28 in the bandgap core circuit module, as well as the gate of the PMOS transistor M39 in the temperature compensation circuit module. The gate of the NMOS transistor N18 serves as the second port, which is connected to the gates of the NMOS transistors N25 and N26 in the bandgap core circuit module, as well as the gates of the NMOS transistors N49 and N50 in the temperature compensation circuit module. The first port and the second port jointly output a bias voltage; they are also used to generate a reference current after the bias circuit module is started.

[0010] Preferably, the startup circuit module includes: PMOS transistor M57, PMOS transistor M58, PMOS transistor M59 and NMOS transistor N56; The sources of PMOS transistors M57 and M58 are both connected to the power supply VDD. The gates of PMOS transistors M57 and M58 are connected, and then connected to the source of PMOS transistor M59. The gate of PMOS transistor M56 is connected to the drain of PMOS transistor M57. The drain of PMOS transistor M58 is connected to the source of PMOS transistor M59. When the source voltage of PMOS transistor M59 increases, the gate voltages of PMOS transistors M57 and M58 also increase, enabling the startup circuit module to operate stably. When PMOS transistors M57 and M58 disconnect, the startup circuit module itself stops operating. The drain of the NMOS transistor N56 is connected to the drain of the PMOS transistor M34 in the bandgap core circuit module, and is used to output the startup current to the bandgap core circuit module.

[0011] Preferably, the startup circuit module further includes: a resistor R9 and a capacitor C1. The drain of the PMOS transistor M58 is connected to the positive terminal of capacitor C1; the negative terminal of capacitor C1 is grounded.

[0012] Preferably, the bandgap core circuit module includes: PMOS transistors M19, M20, M22, M27, M28, M29, M30, M31, M32, M33, M34, M35, M36, M37, and M38; NMOS transistors N23, NMOS transistor N24, NMOS transistor N25, and NMOS transistor N26; The PMOS transistors M27, M28, and M35 are connected in series, and the PMOS transistors M29, M30, and M36 are connected in series to form the top structure of the current mirror. The PMOS transistors M31 and M32 form a differential input pair. The sources of PMOS transistors M31 and M32 are connected to the drains of PMOS transistor M29, and the source of PMOS transistor M29 is connected to the drain of PMOS transistor M27. The cascaded current mirror group formed by NMOS transistors N23, N24, N25, and N26 provides bias current for the differential input pair.

[0013] Preferably, the bandgap core circuit module further includes: resistors R5, R6, and R7, transistors Q1 and Q2; resistor R5 connects the gate of PMOS transistor M32 to one end of resistor R7, and the other end of resistor R7 connects to the emitter of transistor Q1; one end of resistor R6 connects the gate of PMOS transistor M31 to the emitter of transistor Q2; the other ends of resistors R5 and R6 connect to the output node VBG; furthermore, the source of PMOS transistor M33 is connected to power supply VDD, the gate of PMOS transistor M33 is connected to the drain of PMOS transistor M22, and the drain of PMOS transistor M34 is connected to the output node VBG, forming a closed-loop feedback; capacitor Cc is connected between the gate of PMOS transistor M33 and the drain of PMOS transistor M30 for frequency compensation; PMOS transistors M37 and M38 constitute the protection or startup auxiliary branch of the output stage; The drain of the PMOS transistor M34 and the upper end of the resistor R6 are connected to the output node VBG to generate a primary reference voltage that includes both positive and negative temperature coefficient terms. The drain of the PMOS transistor M34 in the bandgap core circuit module is connected to the startup circuit module, and is used to generate a stable working signal and send it to the startup circuit module when it is in a stable working state.

[0014] Preferably, the temperature compensation circuit module includes: PMOS transistor M41, PMOS transistor M42, transistor Q3, and a current mirror output stage; The emitter of transistor Q3 is connected to the gate of PMOS transistor M38 in the bandgap core circuit module; the gate of PMOS transistor M41 is connected to the emitter of transistor Q2 in the bandgap core circuit module; PMOS transistor M41 and PMOS transistor M42 form a differential pair, and the gate of PMOS transistor M41 is connected to the gate of PMOS transistor M31 in the bandgap core module. The output of the current mirror is composed of PMOS transistors M43, M44, M45, M46, M51, M52, M53, NMOS transistors N47, NMOS transistors N48, NMOS transistors N49, NMOS transistors N50, and NMOS transistors N55. The temperature compensation circuit module detects the nonlinear voltage characteristics of its internal transistor Q3; based on these nonlinear voltage characteristics, it generates a compensation current to form its own compensation voltage.

[0015] In this invention, high-order curvature correction of the reference voltage is achieved through a specific port connection between the temperature compensation circuit module and the bandgap core circuit module. Specifically, the temperature compensation circuit module utilizes the emitter of transistor Q3 and the gate of PMOS transistor M38, and the connection between the gate of PMOS transistor M41 and the emitter of transistor Q2, to not only accurately sense the nonlinear potential characteristics inside the core circuit, but also to feed the generated compensation current back to the core circuit through a current mirror. This design allows the compensation current to dynamically cancel the high-order nonlinear terms of the bipolar transistor VBE voltage in both low and high temperature ranges, thereby solving the technical problem of large temperature drift coefficient and limited accuracy of traditional first-order compensated bandgap reference circuits over a wide temperature range, and significantly improving the flatness and stability of the reference voltage source across the entire temperature range. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a high-order temperature-compensated bandgap reference circuit according to the present invention. Figure 2 This is a detailed schematic diagram of a high-order temperature-compensated bandgap reference circuit according to the present invention. Figure 3 The simulation waveform of the reference voltage VREF of the bandgap reference circuit of this invention is shown. Figure 4 This is the startup waveform diagram of the bandgap reference circuit of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] Referring to the accompanying drawings, embodiments of the present invention provide a high-order temperature-compensated bandgap reference circuit, comprising: a bias circuit module, a startup circuit module, a bandgap core circuit module, and a temperature compensation circuit module interconnected with each other; The bias circuit module is used to provide bias voltage for the bandgap core circuit module and the temperature compensation circuit module; it is also used to start itself up and generate a reference current based on the primary reference voltage. The startup circuit module is used to power itself on; during its power-on phase, it generates a startup current that is transmitted to the bandgap core circuit module; and it is also used to control itself to stop working based on the stable operation. The bandgap core circuit module is used to generate a primary reference voltage containing positive and negative temperature coefficient terms based on the bias voltage and transmit it to the bias circuit module; it gets rid of its degeneracy point based on the startup current and then enters a stable operating state; based on the stable operating state, it generates a stable operating signal and sends it to the startup circuit module. The temperature compensation circuit module is used to couple with the bandgap core circuit module to detect its own internal nonlinear voltage characteristics; based on the nonlinear voltage characteristics, it generates a compensation current to form its own compensation voltage.

[0020] Furthermore, the bias circuit module includes: PMOS transistors M7, M8, M9, M10, M15, and M16; NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N11, NMOS transistor N12, NMOS transistor N13, NMOS transistor N14, NMOS transistor N17 and NMOS transistor N18; The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8, the drain of PMOS transistor M7 is connected to the source of PMOS transistor M9, and the drain of PMOS transistor M8 is connected to the source of PMOS transistor M10, forming the input stage of the current mirror; the gate of PMOS transistor M9 and the gate of PMOS transistor M10 form a common source and common gate structure, which is used to improve the output impedance and matching accuracy of the current mirror. The drain of the PMOS transistor M9 is connected to the drain and gate of the NMOS transistor N11; the source of the NMOS transistor N11 is connected to the drain and gate of the NMOS transistor N12, and the source of the NMOS transistor N12 is grounded. The NMOS transistors N1, N3, and N5 are connected in series to form a first bias branch; the NMOS transistors N2, N4, and N6 are connected in series to form a second bias branch; wherein the gates of NMOS transistors N5 and N6 are interconnected and connected in the form of a diode, which is used to provide the underlying bias voltage for the first bias branch and the second bias branch; The gate of NMOS transistor N1 is connected to the gate of NMOS transistor N2, the gate of NMOS transistor N3 is connected to the gate of NMOS transistor N4, and the gate of NMOS transistor N5 is interconnected with the gate of NMOS transistor N6 and connected in a diode configuration to provide the underlying bias voltage. The gate of the PMOS transistor M15 is connected to the drain of the PMOS transistor M16; the drain of the PMOS transistor M16 is connected to the drain of the NMOS transistor N17; the NMOS transistor N17 and the NMOS transistor N18 form a cascaded current branch on the right side; the source of the NMOS transistor N17 and the drain of the NMOS transistor N18 are connected to the power supply VDD. The aforementioned bias circuit module is used to generate bias voltage and bias current based on the input power supply VDD. PMOS transistors M11, M12, M13, and M14, along with resistor R3, constitute a self-biased cascode current mirror structure to generate a bias current independent of the power supply voltage.

[0021] The bias circuit module provides stable bias voltage and bias current to each module, ensuring the accuracy of the circuit's static operating point. The startup circuit module assists the bandgap core circuit module in quickly establishing its operating state and preventing degeneracy. The temperature compensation circuit module acquires the node voltage difference that changes nonlinearly with temperature within itself and generates a high-order compensation current based on this voltage difference. The bandgap core circuit module generates and outputs a curvature-corrected reference voltage based on the input power supply and the adjustment signals of each module.

[0022] The gate of the PMOS transistor M15 serves as the first port, which is connected to the gates of the PMOS transistors M27 and M28 in the bandgap core circuit module, as well as the gate of the PMOS transistor M39 in the temperature compensation circuit module. The gate of the NMOS transistor N18 serves as the second port, which is connected to the gates of the NMOS transistors N25 and N26 in the bandgap core circuit module, as well as the gates of the NMOS transistors N49 and N50 in the temperature compensation circuit module. The first port and the second port jointly output a bias voltage; they are also used to generate a reference current after the bias circuit module is started.

[0023] The sources of PMOS transistors M7, M8, and M15 are all connected to the power supply VDD. The bias circuit module further includes: resistor R1 and resistor R2, wherein resistor R1 and resistor R2 are connected in series and connected between the power supply VDD and the drain of the NMOS transistor N1.

[0024] Furthermore, the startup circuit module includes: PMOS transistor M57, PMOS transistor M58, PMOS transistor M59 and NMOS transistor N56; The sources of PMOS transistors M57 and M58 are both connected to the power supply VDD. The gates of PMOS transistors M57 and M58 are connected, and then connected to the source of PMOS transistor M59. The gate of PMOS transistor M56 is connected to the drain of PMOS transistor M57. The source of PMOS transistor M56 is grounded. The drain of PMOS transistor M58 is connected to the source of PMOS transistor M59. When the source voltage of PMOS transistor M59 increases, the gate voltages of PMOS transistors M57 and M58 also increase, enabling the startup circuit module to operate stably. When PMOS transistors M57 and M58 disconnect, the startup circuit module stops operating. The drain of PMOS transistor M59 is grounded. The drain of the NMOS transistor N56 is connected to the drain of the PMOS transistor M34 in the bandgap core circuit module, and is used to output the startup current to the bandgap core circuit module.

[0025] Furthermore, the startup circuit module also includes: resistor R9 and capacitor C1. The drain of the PMOS transistor M58 is connected to the positive terminal of capacitor C1; the negative terminal of capacitor C1 is grounded.

[0026] As described above, in the startup circuit module, the voltage across capacitor C1 does not change abruptly upon power-up, keeping PMOS transistor M59 in the off state. PMOS transistor M57 then conducts, pulling up the gate potential of PMOS transistor M56, causing M56 to conduct. The conducting PMOS transistor M56 injects startup current into the bandgap core circuit module, forcing it to move away from its zero-current degeneracy point. As capacitor C1 charges, it lowers the gate voltage of PMOS transistor M56, turning it off, and the startup circuit module automatically shuts down, no longer affecting the normal operation of the bandgap core circuit module.

[0027] Furthermore, the bandgap core circuit module includes: PMOS transistors M19, M20, M22, M27, M28, M29, M30, M31, M32, M33, M34, M35, M36, M37, and M38; NMOS transistors N23, NMOS transistor N24, NMOS transistor N25, and NMOS transistor N26; The PMOS transistors M27, M28, and M35 are connected in series, and the PMOS transistors M29, M30, and M36 are connected in series to form the top structure of the current mirror. The sources of PMOS transistors M27, M28, and M35 are connected to the power supply VDD; the gates of PMOS transistors M27, M28, and M35 are connected to each other; and the gates of PMOS transistors M29, M30, and M36 are connected to each other. These components together form the top structure of the common-source cascode current mirror.

[0028] PMOS transistors M29, M30, and M36 serve as common-source, common-gate transistors, connected to the drains of PMOS transistors M27, M28, and M35, respectively. PMOS transistors M31 and M32 form a differential input pair, with the sources of M31 and M32 connected to the drain of PMOS transistor M29, and the source of M29 connected to the drain of PMOS transistor M27. A cascaded current mirror group consisting of NMOS transistors N23, N24, N25, and N26 provides bias current for the differential input pair.

[0029] Furthermore, the bandgap core circuit module further includes: resistors R5, R6, and R7, transistors Q1 and Q2; resistor R5 connects the gate of the PMOS transistor M32 to one end of resistor R7, and the other end of resistor R7 connects to the emitter of transistor Q1; one end of resistor R6 connects the gate of the PMOS transistor M31 to the emitter of transistor Q2; the base and collector of transistor Q1 are grounded; the base and collector of transistor Q2 are grounded; resistor R5 and... The other end of resistor R6 is connected to output node VBG; in addition, the source of PMOS transistor M33 is connected to power supply VDD, the gate of PMOS transistor M33 is connected to the drain of PMOS transistor M22, and the drain of PMOS transistor M34 is connected to output node VBG, forming a closed-loop feedback; capacitor Cc is connected between the gate of PMOS transistor M33 and the drain of PMOS transistor M30 for frequency compensation; PMOS transistors M37 and M38 constitute the protection or startup auxiliary branch of the output stage; The drain of the PMOS transistor M34 and the upper end of the resistor R6 are connected to the output node VBG to generate a primary reference voltage that includes both positive and negative temperature coefficient terms. The drain of the PMOS transistor M34 in the bandgap core circuit module is connected to the startup circuit module, and is used to generate a stable working signal and send it to the startup circuit module when it is in a stable working state. As described above, the emitter of transistor Q2 in the bandgap core circuit module is connected to the gate of PMOS transistor M41 in the temperature compensation circuit module, and the drain of PMOS transistor M34 is connected to the drain of NMOS transistor N56 in the startup circuit module and the upper end of resistor R6.

[0030] The aforementioned bandgap core circuit module is used to generate and output the primary reference voltage; the negative feedback clamp makes the collector potential of transistor Q1 equal to that of transistor Q2, thereby generating a current in resistor R7 that is proportional to the absolute temperature.

[0031] The aforementioned temperature compensation circuit module includes: PMOS transistor M41, PMOS transistor M42, transistor Q3, and a current mirror output stage; The emitter of transistor Q3 is connected to the gate of PMOS transistor M38 in the bandgap core circuit module; the gate of PMOS transistor M41 is connected to the emitter of transistor Q2 in the bandgap core circuit module, and the lower end of resistor R6 inside the bandgap core circuit module; PMOS transistor M41 and PMOS transistor M42 form a differential pair, and the gate of PMOS transistor M41 is connected to the gate of PMOS transistor M31 in the bandgap core module; The output of the current mirror is composed of PMOS transistors M43, M44, M45, M46, M51, M52, M53, NMOS transistors N47, NMOS transistors N48, NMOS transistors N49, NMOS transistors N50, and NMOS transistors N55.

[0032] The sources of PMOS transistors M43, M44, M51, and M52 are connected to the power supply VDD. The drain of PMOS transistor M43 is connected to the source of PMOS transistor M45. The drain of PMOS transistor M43 is connected to the drain of NMOS transistor N47. The source of NMOS transistor N47 is connected to the drain of NMOS transistor N49. The drain of PMOS transistor M44 is connected to the source of PMOS transistor M46. The drain of PMOS transistor M46 is connected to the drain of NMOS transistor N48. The source of NMOS transistor N48 is connected to the drain of NMOS transistor N50. The drain of PMOS transistor M51 is connected to the source of PMOS transistor M53. The drain of PMOS transistor M53 is connected to the drain of NMOS transistor N55. The drain of PMOS transistor M52 is connected to the source of PMOS transistor M54.

[0033] The temperature compensation circuit module detects the nonlinear voltage characteristics of its internal transistor Q3; based on these nonlinear voltage characteristics, it generates a compensation current to form its own compensation voltage.

[0034] The aforementioned temperature compensation circuit module is used to perform high-order curvature correction on the reference voltage. Specifically, its working principle is as follows: by utilizing the nonlinear voltage difference between the internal nodes of the bandgap core circuit module and the internal nodes of the compensation circuit module, a nonlinear compensation current is generated by controlling the differential pair, and then fed back to the core circuit through current mirror injection or extraction to cancel the high-order nonlinear terms of the reference voltage at high or low temperatures.

[0035] Figure 2 shows the simulation results of the output voltage of the temperature-compensated bandgap reference circuit of the present invention under different process angles. Figure 2 As can be seen, the temperature drift coefficient of the reference voltage is 2.5574 ppm / ℃ within the temperature range of -40 to 125℃. The temperature drift coefficients of most traditional bandgap references are in the tens or higher, so the temperature compensation of this invention has a significant effect on improving temperature drift performance.

[0036] Figure 3 shows the signal performance of the startup circuit module during startup. It can be seen that the reference voltage at the VBG point tends to stabilize when the time is less than 20us, and the static current of the startup circuit module is almost negligible, saving power consumption.

[0037] In summary, this invention achieves a high-precision, low-power bandgap reference circuit with high-order temperature compensation characteristics through a unique inter-module port connection design, particularly utilizing the bias circuit module to provide bias voltage and current, and the dual-port closed-loop feedback between the temperature compensation circuit module and the core bandgap module. The circuit includes a bias circuit module, a startup circuit module, a temperature compensation circuit module, and a bandgap core circuit module. The bias circuit module provides a temperature-insensitive bias current to the system through a current mirror network; the startup circuit module utilizes the synergistic effect of capacitors and switches to achieve rapid power-on startup, zero static power consumption during normal operation, and rapid power-off reset; the bandgap core circuit module and the temperature compensation circuit module extract nonlinear voltage characteristics using the transistor emitter voltage difference and introduce reverse compensation current through a feedback loop to accurately offset the high-order temperature drift term in the reference voltage. Furthermore, the circuit employs a composite resistor structure with polysilicon and a diffusion resistor in series to further suppress process deviations and resistor temperature drift. Simulation results show that this invention, through the startup core circuit unit and the temperature compensation unit, can guarantee a low temperature drift coefficient and stable startup performance.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit its protection scope. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that after reading the present invention, they can still make various changes, modifications or equivalent substitutions to the specific implementation of the application, but these changes, modifications or equivalent substitutions are all within the protection scope of the claims pending approval.

Claims

1. A temperature-compensated bandgap reference circuit, characterized in that, include: The interconnected bias circuit module, startup circuit module, bandgap core circuit module, and temperature compensation circuit module; The bias circuit module is used to provide bias voltage for the bandgap core circuit module and the temperature compensation circuit module; it is also used to start itself up and generate a reference current based on the primary reference voltage. The startup circuit module is used to power itself on; during its power-on phase, it generates a startup current that is transmitted to the bandgap core circuit module; and it is also used to control itself to stop working based on the stable operation. The bandgap core circuit module is used to generate a primary reference voltage containing a positive temperature coefficient term and a negative temperature coefficient term based on the bias voltage and transmit it to the bias circuit module. Based on the starting current, it gets rid of its own degeneracy point and then enters a stable working state; based on the stable working state, a stable working signal is generated and sent to the starting circuit module; The temperature compensation circuit module is used to couple with the bandgap core circuit module to detect its own internal nonlinear voltage characteristics; based on the nonlinear voltage characteristics, it generates a compensation current to form its own compensation voltage.

2. The circuit according to claim 1, characterized in that, The bias circuit module includes: PMOS transistors M7, M8, M9, M10, M15, and M16; NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N11, NMOS transistor N12, NMOS transistor N13, NMOS transistor N14, NMOS transistor N17 and NMOS transistor N18; The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8, the drain of PMOS transistor M7 is connected to the source of PMOS transistor M9, and the drain of PMOS transistor M8 is connected to the source of PMOS transistor M10, forming the input stage of the current mirror; the gate of PMOS transistor M9 and the gate of PMOS transistor M10 form a common source and common gate structure, which is used to improve the output impedance and matching accuracy of the current mirror. The drain of the PMOS transistor M9 is connected to the drain and gate of the NMOS transistor N11; the source of the NMOS transistor N11 is connected to the drain and gate of the NMOS transistor N12. The NMOS transistors N1, N3, and N5 are connected in series to form a first bias branch; the NMOS transistors N2, N4, and N6 are connected in series to form a second bias branch; wherein the gates of NMOS transistors N5 and N6 are interconnected and connected in the form of a diode, which is used to provide the underlying bias voltage for the first bias branch and the second bias branch; The gate of the PMOS transistor M15 is connected to the drain of the PMOS transistor M16; the drain of the PMOS transistor M16 is connected to the drain of the NMOS transistor N17; the NMOS transistor N17 and the NMOS transistor N18 form a cascaded current branch on the right side, and the source of the NMOS transistor N17 and the drain of the NMOS transistor N18 are connected to the power supply VDD.

3. The circuit according to claim 2, characterized in that, The gate of the PMOS transistor M15 serves as the first port, which is connected to the gates of the PMOS transistors M27 and M28 in the bandgap core circuit module, as well as the gate of the PMOS transistor M39 in the temperature compensation circuit module. The gate of the NMOS transistor N18 serves as the second port, which is connected to the gates of the NMOS transistors N25 and N26 in the bandgap core circuit module, as well as the gates of the NMOS transistors N49 and N50 in the temperature compensation circuit module. The first port and the second port jointly output a bias voltage; they are also used to generate a reference current after the bias circuit module is started.

4. The circuit according to claim 1, characterized in that, The startup circuit module includes: PMOS transistor M57, PMOS transistor M58, PMOS transistor M59 and NMOS transistor N56; The sources of PMOS transistors M57 and M58 are both connected to the power supply VDD. The gates of PMOS transistors M57 and M58 are connected, and then connected to the source of PMOS transistor M59. The gate of PMOS transistor M56 is connected to the drain of PMOS transistor M57. The drain of PMOS transistor M58 is connected to the source of PMOS transistor M59. When the source voltage of PMOS transistor M59 increases, the gate voltages of PMOS transistors M57 and M58 also increase, enabling the startup circuit module to operate stably. When PMOS transistors M57 and M58 disconnect, the startup circuit module itself stops operating. The drain of the NMOS transistor N56 is connected to the drain of the PMOS transistor M34 in the bandgap core circuit module, and is used to output the startup current to the bandgap core circuit module.

5. The circuit according to claim 4, characterized in that, The startup circuit module also includes: resistor R9 and capacitor C1. The drain of the PMOS transistor M58 is connected to the positive terminal of capacitor C1; the negative terminal of capacitor C1 is grounded.

6. The circuit according to claim 1, characterized in that, The bandgap core circuit module includes: PMOS transistors M19, M20, M22, M27, M28, M29, M30, M31, M32, M33, M34, M35, M36, M37, and M38; NMOS transistors N23, NMOS transistor N24, NMOS transistor N25, and NMOS transistor N26; The PMOS transistors M27, M28, and M35 are connected in series, and the PMOS transistors M29, M30, and M36 are connected in series to form the top structure of the current mirror. The PMOS transistors M31 and M32 form a differential input pair. The sources of PMOS transistors M31 and M32 are connected to the drains of PMOS transistor M29, and the source of PMOS transistor M29 is connected to the drain of PMOS transistor M27. The cascaded current mirror group formed by NMOS transistors N23, N24, N25, and N26 provides bias current for the differential input pair.

7. The circuit according to claim 6, characterized in that, The bandgap core circuit module further includes: resistors R5, R6, and R7, transistors Q1 and Q2; resistor R5 connects the gate of PMOS transistor M32 to one end of resistor R7, and the other end of resistor R7 connects to the emitter of transistor Q1; one end of resistor R6 connects the gate of PMOS transistor M31 to the emitter of transistor Q2; the other ends of resistors R5 and R6 connect to the output node VBG; furthermore, the source of PMOS transistor M33 is connected to the power supply VDD, the gate of PMOS transistor M33 is connected to the drain of PMOS transistor M22, and the drain of PMOS transistor M34 is connected to the output node VBG, forming a closed-loop feedback; capacitor Cc is connected between the gate of PMOS transistor M33 and the drain of PMOS transistor M30 for frequency compensation; PMOS transistors M37 and M38 constitute the protection or startup auxiliary branch of the output stage. The drain of the PMOS transistor M34 and the upper end of the resistor R6 are connected to the output node VBG to generate a primary reference voltage that includes both positive and negative temperature coefficient terms. The drain of the PMOS transistor M34 in the bandgap core circuit module is connected to the startup circuit module, and is used to generate a stable working signal and send it to the startup circuit module when it is in a stable working state.

8. The circuit according to claim 1, characterized in that, The temperature compensation circuit module includes: PMOS transistor M41, PMOS transistor M42, transistor Q3, and current mirror output stage; The emitter of transistor Q3 is connected to the gate of PMOS transistor M38 in the bandgap core circuit module; the gate of PMOS transistor M41 is connected to the emitter of transistor Q2 in the bandgap core circuit module; PMOS transistor M41 and PMOS transistor M42 form a differential pair, and the gate of PMOS transistor M41 is connected to the gate of PMOS transistor M31 in the bandgap core module. The output of the current mirror is composed of PMOS transistors M43, M44, M45, M46, M51, M52, M53, NMOS transistors N47, NMOS transistors N48, NMOS transistors N49, NMOS transistors N50, and NMOS transistors N55. The temperature compensation circuit module detects the nonlinear voltage characteristics of its internal transistor Q3; based on these nonlinear voltage characteristics, it generates a compensation current to form its own compensation voltage.

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