Power supply control system and method based on multimode heterogeneous processing system

Abstract

The invention discloses a power supply control system and method based on a multimode heterogeneous processing system, and belongs to the technical field of embedded power supply control. The power supply control system comprises an input interface, a plurality of power supply modules, an adjustable capacitor array, a programmable power supply controller and a multi-path output interface; the input interface is electrically connected with the input side of each power supply module and is used for accessing external power supply; the adjustable capacitor array is electrically connected with the rise time configuration interface of each power supply module and is used for adjusting the rise time of the output voltage of the power supply module; the programmable power supply controller is electrically connected with the enabling interface and the output state interface of each power supply module and is also electrically connected with the control end of the adjustable capacitor array, the programmable power supply controller is provided with a sampling interface, the sampling interface is electrically connected with the output side of each power supply module, and the adjustable capacitor array is electrically connected with the output side of each power supply module. The output voltage and the output current of the power supply module are collected.

Description

Technical Field

[0001] This invention belongs to the field of embedded power control technology, and relates to a power supply control system and method based on a multi-mode heterogeneous processing system. Background Technology

[0002] In cutting-edge fields such as artificial intelligence, high-performance computing, and industrial control, multi-mode heterogeneous processing systems have become core hardware supports due to their efficient adaptability to different workloads. These systems typically integrate processors with various architectures, such as CPUs, GPUs, DSPs, and FPGAs, as well as large-scale complex integrated circuits. The various core components differ significantly in their computational precision, data throughput, and power consumption characteristics, which determines the system's power supply requirements, exhibiting distinct characteristics of "multi-specification, high dynamism, and strict timing." In terms of power supply specifications, the system not only needs to provide a high-precision core voltage as low as 0.8V for the core processor and a standard voltage of 3.3V for interface circuits, but also requires dedicated configuration and logic voltages for programmable devices such as FPGAs. Some high-performance modules even require dynamically adjustable power outputs to adapt to load changes. In terms of timing requirements, the power-on and power-off sequences of various power supplies have strict logical relationships—for example, the processor's reset circuit must be powered first to ensure the reset signal is stable before starting the core power supply; the FPGA can only be connected to the core operating power supply after the configuration power supply is ready, otherwise there is a risk of configuration data loss or hardware damage. Precise power timing control directly determines the startup reliability and long-term operational stability of a multi-mode heterogeneous processing system. Disordered power-up sequence during power-up may cause core components to lock up due to initialization anomalies, preventing the system from booting normally. Inappropriate voltage shutdown timing during power-down may lead to data being incorrectly written to or remaining in storage units, resulting in the loss of critical information. In scenarios with extremely high reliability requirements, such as industrial control and aerospace, uncontrolled power timing can trigger cascading failures, leading to serious safety accidents or economic losses.

[0003] To address the timing control problem of multiple power supplies, existing technologies have developed various solutions. However, when adapting to the complex requirements of multi-mode heterogeneous processing systems, numerous shortcomings have gradually emerged. Traditional solutions partially rely on dedicated timing control chips for centralized management. The control logic of these chips is relatively fixed; when power modules are added or removed, or timing parameters are adjusted, the chip model needs to be changed and the peripheral circuit redesigned, resulting in extremely poor configuration flexibility and difficulty in adapting to the personalized needs of heterogeneous systems. Another approach uses discrete electronic components to construct delay or logic control circuits, achieving timing control through the RC charging and discharging characteristics of resistors and capacitors or logical combinations of diodes. While this approach reduces hardware costs, it suffers from significant performance defects: firstly, the parameters of components such as resistors and capacitors are easily affected by environmental factors such as temperature and humidity, leading to decreased timing delay accuracy and potential deviations from the design value in power supply startup intervals; secondly, this type of control is essentially open-loop control, unable to monitor the output voltage rise of each power module in real time, nor respond to abnormal conditions such as overvoltage, overcurrent, or startup failure, exhibiting weak fault tolerance. When a power supply fails to start up properly, the system cannot trigger its protection mechanism in time, potentially causing the fault to spread to other core modules. Furthermore, existing solutions generally lack a closed-loop feedback mechanism for the processor's power supply completion status. Most systems rely solely on the power module's output voltage reaching a threshold as the basis for timing, neglecting the time lag between the processor's connection to power and its completion of internal initialization and entry into a ready state. This "voltage threshold equals readiness" logic can lead to subsequent modules starting prematurely, causing data interaction anomalies. These issues collectively make it difficult for existing technologies to balance reliability, flexibility, and fault tolerance when facing the complex power supply requirements of multi-mode heterogeneous processing systems, becoming a key bottleneck restricting the full realization of system performance. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problems of open-loop control, timing accuracy being easily affected by the environment, and low fault tolerance in the prior art, and to provide a power supply control system and method based on a multi-mode heterogeneous processing system.

[0005] To achieve the above objectives, the present invention employs the following technical solution: In a first aspect, the present invention discloses a power supply control system based on a multi-mode heterogeneous processing system, including an input interface, several power modules, an adjustable capacitor array, a programmable power controller, and multiple output interfaces. The input interfaces are electrically connected to the input side of each power module for external power supply. The adjustable capacitor array is electrically connected to the rise time configuration interface of each power module for adjusting the rise time of the power module output voltage. The programmable power controller is electrically connected to the enable interface and output status interface of each power module, and also to the control terminal of the adjustable capacitor array. The programmable power controller is equipped with a sampling interface, which is electrically connected to the output side of each power module for collecting the output voltage and output current of the power module. The output side of each power module is electrically connected to the corresponding multi-output interface, which is used to supply power to the load of the multi-mode heterogeneous processing system.

[0006] Further improvements are made in the following aspects: The power module is equipped with an input interface, an output interface, an enable interface, an output status interface, and a rise time configuration interface. The enable interface is the output control terminal of the power module. When the input of the enable interface is high, the power module starts up and outputs voltage. The output status interface is used to output a high level when the output voltage of the power module reaches a preset judgment voltage. The preset judgment voltage is 90% or more of the rated voltage of the power module.

[0007] The adjustable capacitor array consists of multiple electronic switches and multiple corresponding capacitors. The switching on and off of each capacitor is controlled by a corresponding electronic switch. The control terminal of the electronic switch is electrically connected to the output interface of the programmable power controller. The programmable power controller adjusts the overall capacitance value of the capacitor array by controlling the switching on and off of the electronic switches.

[0008] The total capacitance of the adjustable capacitor array is greater than the capacitance value corresponding to the expected rise time of the power module output voltage and a preset margin is reserved. The margin is determined based on the electronic component tolerance and device offset parameters.

[0009] The number of electronic switches and capacitors is determined by the adjustment granularity of the voltage rise time, and the adjustment granularity is inversely correlated with the corresponding number of electronic switches and capacitors.

[0010] Secondly, this invention discloses a power supply control method for a multi-mode heterogeneous processing system based on the above-mentioned power supply control system, comprising: System initialization: Configure the basic operating parameters of the multi-mode heterogeneous processing system through the programmable power controller; the basic operating parameters include the expected rise time, preset judgment voltage, minimum load start-up current and power-on timeout threshold of each power module; Power sequence startup control: The programmable power controller outputs control signals to the enable interface of each power module in a preset order, triggering the corresponding power module to start and begin outputting voltage; Voltage rise time adjustment: The programmable power controller collects the output voltage of the power module in real time through the sampling interface, and combines the deviation between the accumulated rise time and the desired rise time to control the electronic switching of the adjustable capacitor array to adjust the capacitor value, thereby adjusting the rise slope of the output voltage of the power module. Power-on status judgment: The programmable power controller determines whether the power output has reached the preset judgment voltage through the output status interface of the power module, and at the same time collects the power output current through the sampling interface to determine whether the load has reached the minimum starting current. If both conditions are met, the power supply and the corresponding load are determined to be powered on. Anomaly Handling and Timing Flow: If the current power supply and load complete power-on within the preset power-on timeout threshold, the startup control process of the next power module will be initiated until all power modules and loads are powered on. If power-on is not completed after the power-on timeout threshold is exceeded, anomaly handling operations such as restart or fault reporting will be performed.

[0011] The configuration of the basic operating parameters is based on the load type of the multi-mode heterogeneous processing system, the power supply requirements of each processor and FPGA, and the tolerance and device offset parameters of electronic components. The principle for determining the preset order is: according to the core status and power supply dependence of the load in the multi-mode heterogeneous processing system, power is first started on the power module corresponding to the core control unit, and then power is started on the power module corresponding to the peripheral functional unit.

[0012] The specific slope of the rising voltage of the power supply module output includes: Determine if the current power module is in a state where the enable has been triggered but the power-on is not complete. If not, restore the adjustable capacitor array to its initial capacitance value; if yes, proceed to the next step. Calculate the expected remaining time t2, where t2 = the preset expected rise time t0 - the accumulated rise time t1; Calculate the real-time voltage change rate du / dt, where du / dt = voltage difference between two adjacent sampling periods ΔU1 / sampling period Δt; Calculate the remaining voltage rise time t3, t3 = (expected output voltage - current real-time output voltage) / du / dt; Comparing t3 and t2, if t3 > t2, the adjustable capacitor array is controlled to reduce the input capacitance value to increase the rising slope; if t3 < t2, the adjustable capacitor array is controlled to increase the input capacitance value to decrease the rising slope.

[0013] The preset judgment voltage is 90%~95% of the rated output voltage of the corresponding power module; the specific logic for judging whether the load has reached the minimum starting current is as follows: continuously collect the load end current 3~5 times. If all collected values ​​are greater than the minimum starting current of the load, the load current is determined to meet the requirements; if there is at least one collected value that is less than or equal to the minimum starting current of the load, the load current is determined to not meet the requirements.

[0014] The exception handling operations specifically include: Upon first detection of a power-on timeout, the programmable power controller resets the enable interface of the current power module and re-triggers the power-on process of the power module. If the same power module triggers a power-on timeout three times in a row, it is determined that the power module or the corresponding load is faulty. The programmable power controller stops the startup process of subsequent power modules and reports the fault information to the main controller of the multi-mode heterogeneous processing system. The fault information includes the faulty power module number, the number of timeouts, and the voltage and current data of the last power-on.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention discloses a power supply control system based on a multi-mode heterogeneous processing system. The programmable power controller is configured to manage the power startup sequence by controlling the enable interfaces of each power module, adjust the output voltage rise slope through the adjustable capacitor array, determine the power-on status of the power supply and load through the output status interface and sampling interface, and execute an abnormal handling process of restart or fault reporting in case of power supply anomalies. The output current data collected by the sampling interface of the programmable power controller is used to determine whether there is overshoot during the power module power-on process and the operating status of each load unit in the multi-mode heterogeneous processing system. This power supply control system uses the programmable power controller to manage the power supply startup sequence of each power module. The enable interface of the power supply module is controlled in an orderly manner, realizing the sequential startup of multiple power supply modules. This avoids the problem of core components (such as processors and FPGAs) of the multi-mode heterogeneous processing system failing to initialize properly due to chaotic power supply timing. At the same time, the programmable power controller, combined with the voltage data collected by the sampling interface, dynamically adjusts the rise time of the power supply output voltage through an adjustable capacitor array. This effectively offsets the impact of electronic component tolerances and device offsets on the voltage rise time, keeping the deviation between the actual rise time and the preset expected rise time within a very small range. This significantly improves the accuracy and consistency of the power supply timing, ensuring that each device in the multi-mode heterogeneous processing system completes the power-on preparation according to the predetermined timing. The adjustable capacitor array can flexibly adjust the overall capacitance value through the switching of electronic switches, thereby realizing multi-level adjustment of the voltage rise slope of the power module output voltage. It can not only meet the differentiated voltage rise rate requirements of different types of loads (such as processor cores and peripheral interfaces) in multi-mode heterogeneous processing systems, but also adapt to new power supply parameters without replacing hardware components when the system load type or power supply requirements are slightly adjusted. This is achieved by simply adjusting the switching logic of the capacitor array through the programmable power controller, reducing the hardware modification cost of the system and improving the flexible adaptability of the power supply system. On the one hand, the programmable power controller can accurately determine whether the power module itself has reached the preset supply voltage through the output status interface of the power module. At the same time, with the help of the current data collected by the sampling interface, it can determine whether the processor and other loads have reached the minimum start-up current. This achieves dual monitoring of the power module and load power-on status, ensuring that the power supply process of the next power module will only start after the previous power supply and the corresponding load are fully powered on and ready, avoiding device damage caused by powering on the load before it is ready. On the other hand, after the system is powered on, it can still continuously monitor the voltage and current data of each power module through the sampling interface. Once abnormalities such as voltage drift and current overshoot occur, they can be identified and warned in time, thus building a solid defense for the stable operation of the multi-mode heterogeneous processing system from the power supply level.The system has a built-in comprehensive fault handling mechanism. When a power module or its corresponding load fails to power on within a preset timeout threshold, the programmable power controller can first trigger the power module enable terminal to reset and retry the power-on process. If multiple retries still fail, the startup of subsequent power modules will be stopped immediately, and the fault module number, timeout count, and abnormal voltage and current data will be reported. This will help maintenance personnel quickly locate the fault source and reduce troubleshooting time. This fault tolerance mechanism avoids the situation where a single power module failure causes the entire multi-mode heterogeneous processing system to be paralyzed by power supply failure, greatly improving the system's fault tolerance and fault handling efficiency, and reducing downtime losses caused by power supply failures.

[0016] Furthermore, considering the characteristics of multi-mode heterogeneous processing systems, which include multiple processors, FPGAs, and a wide variety of power supplies, the system can achieve precise power supply to different types and specifications of loads through multiple output interfaces. At the same time, the programmable power controller can flexibly configure the operating parameters of each power module to meet the differentiated control requirements of 56 or more different power supplies. After multiple power-on and power-off tests in three temperature environments (high temperature, low temperature, and normal temperature), the system can ensure that all processors and FPGAs can work normally and stably, fully adapting to the complex power supply scenarios of multi-mode heterogeneous processing systems, and providing a solid power supply guarantee for the system to realize core functions such as big data intelligent analysis and processing.

[0017] This invention discloses a power supply control method for a multi-mode heterogeneous processing system. During system initialization, it precisely configures core parameters such as the expected rise time and power-on timeout threshold for each power module, laying a unified standard for subsequent timing control. In the power timing startup control stage, a programmable power controller triggers each power module in a preset sequence, achieving orderly start-up and shutdown of multiple power modules and avoiding initialization failures of core devices such as processors and FPGAs due to disordered power supply timing. Simultaneously, in the voltage rise time adjustment step, the controller dynamically adjusts the capacitance value of the adjustable capacitor array based on real-time collected voltage data, effectively offsetting the interference of electronic component tolerances and device offsets on the voltage rise time, keeping the deviation between the actual rise time and the expected rise time within a minimal range. This significantly improves the accuracy and consistency of the multi-power supply timing, ensuring that each device in the multi-mode heterogeneous processing system completes power-on preparation according to predetermined logic. This control method requires no hardware modifications; it adjusts the basic operating parameters of each power module using only a programmable power controller. It adapts to the varying voltage rise rate and startup current requirements of different types of loads (such as processor cores and FPGA peripherals) in multi-mode heterogeneous processing systems. In the voltage rise time adjustment stage, multi-level capacitor value adjustment is achieved through electronic switching, flexibly changing the voltage rise slope. This satisfies the need for slow power-up of sensitive devices to avoid voltage overshoot damage, while also adapting to the rapid power-up requirements of conventional devices. This improves the power supply system's adaptability to different loads, reduces hardware modification costs, and shortens the system parameter iteration cycle. The method constructs a dual monitoring logic of "power supply output voltage + load startup current" in the power-on status judgment stage. On one hand, it confirms whether the power supply itself has reached the preset judgment voltage (90% or above of the rated voltage) through the power module output status interface, ensuring stable power output. On the other hand, it collects the load current through the sampling interface to determine whether it has reached the minimum startup current, confirming that the load is ready for power-on. This dual monitoring mode avoids the hidden fault of "power supply completed but load not ready," ensuring that each power supply level and its corresponding load meet power requirements before proceeding to the next stage of the sequence, thus guaranteeing the integrity and effectiveness of the power supply link from the source. The method's built-in exception handling and sequence flow mechanism sets up a hierarchical handling logic for power supply faults: when a single power module or load experiences a power-on timeout, the power enable terminal is first reset for retry, ensuring the system's fault tolerance margin; only after multiple failed retries is subsequent sequence execution stopped and the fault reported, with the reported information including the faulty module number, timeout count, and voltage and current data, facilitating rapid fault location by maintenance personnel and significantly shortening troubleshooting time. This mechanism prevents a single module failure from causing a complete system power supply paralysis, improves the system's anti-interference capability and fault handling efficiency, and reduces system downtime losses due to power supply faults.Addressing the challenges of multi-mode heterogeneous processing systems that include various processors, FPGAs, and diverse power supplies, this method enables unified management of dozens of different power supplies. A standardized control process ensures that each power module receives power sequentially and stably. After multiple power-on and power-off verifications in three temperature environments (high temperature, low temperature, and normal temperature), this method ensures that all processors and FPGAs within the system can start normally and operate stably, meeting the high-reliability power supply requirements for intelligent big data analysis and processing in multi-mode heterogeneous processing systems. Furthermore, after power-on, the method continuously monitors voltage and current status through a sampling interface, providing timely warnings of power supply anomalies and strengthening the power supply defenses for the long-term stable operation of the system. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the power supply control system based on a multi-mode heterogeneous processing system in an embodiment of the present invention; Figure 2 This is a timing diagram of the logic control of each interface of the power supply in a power supply control system based on a multi-mode heterogeneous processing system according to an embodiment of the present invention. Figure 3 This is a schematic diagram of the adjustable capacitor array structure in an embodiment of the present invention; Figure 4 This is a control logic diagram of a power supply control method based on a multi-mode heterogeneous processing system in an embodiment of the present invention; Figure 5 This is a rise time adjustment logic diagram of a power supply control method based on a multi-mode heterogeneous processing system in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0025] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0026] The present invention will now be described in further detail with reference to the accompanying drawings: See Figure 1 and Figure 2This invention discloses a power supply control system based on a multi-mode heterogeneous processing system, including an input interface, several power modules, an adjustable capacitor array, a programmable power controller, and multiple output interfaces. The input interface is electrically connected to the input side of each power module for external power supply. The adjustable capacitor array is electrically connected to the rise time configuration interface of each power module for adjusting the rise time of the power module's output voltage. The programmable power controller is electrically connected to the enable interface and output status interface of each power module, and also electrically connected to the control terminal of the adjustable capacitor array. The programmable power controller has a sampling interface electrically connected to the output side of each power module for collecting the output voltage and output current of the power modules. The output side of each power module is electrically connected to the corresponding multiple output interfaces, which are used to supply power to the load of the multi-mode heterogeneous processing system. The power module is equipped with an input interface, an output interface, an enable interface, an output status interface, and a rise time configuration interface. The enable interface is the output control terminal of the power module. When the input of the enable interface is high, the power module starts up and outputs voltage. The output status interface is used to output a high level when the output voltage of the power module reaches a preset judgment voltage. The preset judgment voltage is 90% or more of the rated voltage of the power module.

[0027] See Figure 3 The adjustable capacitor array consists of multiple electronic switches and multiple corresponding capacitors. The switching of each capacitor is controlled by a corresponding electronic switch. The control terminal of the electronic switch is electrically connected to the output interface 2 of the programmable power controller. The programmable power controller adjusts the overall capacitance value of the capacitor array by controlling the switching of the electronic switches. The total capacitance of the adjustable capacitor array is greater than the capacitance value corresponding to the expected rise time of the power module output voltage, with a preset margin. This margin is determined based on the electronic component tolerances and device offset parameters. The number of electronic switches and capacitors is determined by the adjustment granularity of the voltage rise time, and the adjustment granularity is inversely correlated with the corresponding number of electronic switches and capacitors.

[0028] This invention discloses a power supply control system based on a multi-mode heterogeneous processing system. The programmable power controller is configured to manage the power startup sequence by controlling the enable interfaces of each power module, adjust the output voltage rise slope through the adjustable capacitor array, determine the power-on status of the power supply and load through the output status interface and sampling interface, and execute an abnormal handling process of restart or fault reporting in case of power supply anomalies. The output current data collected by the sampling interface of the programmable power controller is used to determine whether there is overshoot during the power module power-on process and the operating status of each load unit in the multi-mode heterogeneous processing system. This power supply control system uses the programmable power controller to manage the power supply startup sequence of each power module. The enable interface of the power supply module is controlled in an orderly manner, realizing the sequential startup of multiple power supply modules. This avoids the problem of core components (such as processors and FPGAs) of the multi-mode heterogeneous processing system failing to initialize properly due to chaotic power supply timing. At the same time, the programmable power controller, combined with the voltage data collected by the sampling interface, dynamically adjusts the rise time of the power supply output voltage through an adjustable capacitor array. This effectively offsets the impact of electronic component tolerances and device offsets on the voltage rise time, keeping the deviation between the actual rise time and the preset expected rise time within a very small range. This significantly improves the accuracy and consistency of the power supply timing, ensuring that each device in the multi-mode heterogeneous processing system completes the power-on preparation according to the predetermined timing. The adjustable capacitor array can flexibly adjust the overall capacitance value through the switching of electronic switches, thereby realizing multi-level adjustment of the voltage rise slope of the power module output voltage. It can not only meet the differentiated voltage rise rate requirements of different types of loads (such as processor cores and peripheral interfaces) in multi-mode heterogeneous processing systems, but also adapt to new power supply parameters without replacing hardware components when the system load type or power supply requirements are slightly adjusted. This is achieved by simply adjusting the switching logic of the capacitor array through the programmable power controller, reducing the hardware modification cost of the system and improving the flexible adaptability of the power supply system. On the one hand, the programmable power controller can accurately determine whether the power module itself has reached the preset supply voltage through the output status interface of the power module. At the same time, with the help of the current data collected by the sampling interface, it can determine whether the processor and other loads have reached the minimum start-up current. This achieves dual monitoring of the power module and load power-on status, ensuring that the power supply process of the next power module will only start after the previous power supply and the corresponding load are fully powered on and ready, avoiding device damage caused by powering on the load before it is ready. On the other hand, after the system is powered on, it can still continuously monitor the voltage and current data of each power module through the sampling interface. Once abnormalities such as voltage drift and current overshoot occur, they can be identified and warned in time, thus building a solid defense for the stable operation of the multi-mode heterogeneous processing system from the power supply level.The system has a built-in comprehensive fault handling mechanism. When a power module or its corresponding load fails to power on within a preset timeout threshold, the programmable power controller can first trigger the power module enable terminal to reset and retry the power-on process. If multiple retries still fail, the startup of subsequent power modules will be stopped immediately, and the fault module number, timeout count, and abnormal voltage and current data will be reported. This will help maintenance personnel quickly locate the fault source and reduce troubleshooting time. This fault tolerance mechanism avoids the situation where a single power module failure causes the entire multi-mode heterogeneous processing system to be paralyzed by power supply failure, greatly improving the system's fault tolerance and fault handling efficiency, and reducing downtime losses caused by power supply failures.

[0029] See Figure 4 The present invention also discloses a power supply control method based on a multi-mode heterogeneous processing system, comprising: System initialization: Configure the basic operating parameters of the multi-mode heterogeneous processing system through the programmable power controller; the basic operating parameters include the expected rise time of each power module, the preset judgment voltage, the minimum load start-up current and the power-on timeout threshold; the configuration of the basic operating parameters is based on the load type of the multi-mode heterogeneous processing system, the power supply requirements of each processor and FPGA, and the tolerance and device offset parameters of electronic components. Power sequence startup control: The programmable power controller outputs control signals to the enable interface of each power module in a preset order to trigger the corresponding power module to start and begin outputting voltage; the principle for determining the preset order is: according to the core status of the load and the power supply dependence in the multi-mode heterogeneous processing system, the power module corresponding to the core control unit is started to supply power first, and then the power module corresponding to the peripheral functional unit is started to supply power.

[0030] Voltage rise time adjustment: The programmable power controller collects the output voltage of the power module in real time through the sampling interface, and combines the deviation between the accumulated rise time and the desired rise time to control the electronic switching of the adjustable capacitor array to adjust the capacitor value, thereby adjusting the rise slope of the output voltage of the power module. Power-on status judgment: The programmable power controller determines whether the power output has reached the preset judgment voltage through the output status interface of the power module, and simultaneously collects the power output current through the sampling interface to determine whether the load has reached the minimum starting current. If both are satisfied, the power supply and the corresponding load are determined to be powered on successfully. The preset judgment voltage is 90% to 95% of the rated output voltage of the corresponding power module. The specific logic for determining whether the load has reached the minimum starting current is as follows: the load end current is collected 3 to 5 times continuously. If all collected values ​​are greater than the minimum starting current of the load, the load current is determined to meet the requirements. If at least one collected value is less than or equal to the minimum starting current of the load, the load current is determined to not meet the requirements.

[0031] Anomaly Handling and Timing Flow: If the current power supply and load complete power-on within the preset power-on timeout threshold, the startup control process of the next power module will be initiated until all power modules and loads are powered on. If power-on is not completed after the power-on timeout threshold is exceeded, anomaly handling operations such as restart or fault reporting will be performed.

[0032] The exception handling operations specifically include: Upon first detection of a power-on timeout, the programmable power controller resets the enable interface of the current power module and re-triggers the power-on process of the power module. If the same power module triggers a power-on timeout three times in a row, it is determined that the power module or the corresponding load is faulty. The programmable power controller stops the startup process of subsequent power modules and reports the fault information to the main controller of the multi-mode heterogeneous processing system. The fault information includes the faulty power module number, the number of timeouts, and the voltage and current data of the last power-on.

[0033] See Figure 5 The specific steps include adjusting the rise slope of the power supply module output voltage: Determine if the current power module is in a state where the enable has been triggered but the power-on is not complete. If not, restore the adjustable capacitor array to its initial capacitance value; if yes, proceed to the next step. Calculate the expected remaining time t2, where t2 = the preset expected rise time t0 - the accumulated rise time t1; Calculate the real-time voltage change rate du / dt, where du / dt = voltage difference between two adjacent sampling periods ΔU1 / sampling period Δt; Calculate the remaining voltage rise time t3, t3 = (expected output voltage - current real-time output voltage) / du / dt; Comparing t3 and t2, if t3 > t2, the adjustable capacitor array is controlled to reduce the input capacitance value to increase the rising slope; if t3 < t2, the adjustable capacitor array is controlled to increase the input capacitance value to decrease the rising slope.

[0034] This invention discloses a power supply control method for a multi-mode heterogeneous processing system. During system initialization, it precisely configures core parameters such as the expected rise time and power-on timeout threshold for each power module, laying a unified standard for subsequent timing control. In the power timing startup control stage, a programmable power controller triggers each power module in a preset sequence, achieving orderly start-up and shutdown of multiple power modules and avoiding initialization failures of core devices such as processors and FPGAs due to disordered power supply timing. Simultaneously, in the voltage rise time adjustment step, the controller dynamically adjusts the capacitance value of the adjustable capacitor array based on real-time collected voltage data, effectively offsetting the interference of electronic component tolerances and device offsets on the voltage rise time, keeping the deviation between the actual rise time and the expected rise time within a minimal range. This significantly improves the accuracy and consistency of the multi-power supply timing, ensuring that each device in the multi-mode heterogeneous processing system completes power-on preparation according to predetermined logic. This control method requires no hardware modifications; it adjusts the basic operating parameters of each power module using only a programmable power controller. It adapts to the varying voltage rise rate and startup current requirements of different types of loads (such as processor cores and FPGA peripherals) in multi-mode heterogeneous processing systems. In the voltage rise time adjustment stage, multi-level capacitor value adjustment is achieved through electronic switching, flexibly changing the voltage rise slope. This satisfies the need for slow power-up of sensitive devices to avoid voltage overshoot damage, while also adapting to the rapid power-up requirements of conventional devices. This improves the power supply system's adaptability to different loads, reduces hardware modification costs, and shortens the system parameter iteration cycle. The method constructs a dual monitoring logic of "power supply output voltage + load startup current" in the power-on status judgment stage. On one hand, it confirms whether the power supply itself has reached the preset judgment voltage (90% or above of the rated voltage) through the power module output status interface, ensuring stable power output. On the other hand, it collects the load current through the sampling interface to determine whether it has reached the minimum startup current, confirming that the load is ready for power-on. This dual monitoring mode avoids the hidden fault of "power supply completed but load not ready," ensuring that each power supply level and its corresponding load meet power requirements before proceeding to the next stage of the sequence, thus guaranteeing the integrity and effectiveness of the power supply link from the source. The method's built-in exception handling and sequence flow mechanism sets up a hierarchical handling logic for power supply faults: when a single power module or load experiences a power-on timeout, the power enable terminal is first reset for retry, ensuring the system's fault tolerance margin; only after multiple failed retries is subsequent sequence execution stopped and the fault reported, with the reported information including the faulty module number, timeout count, and voltage and current data, facilitating rapid fault location by maintenance personnel and significantly shortening troubleshooting time. This mechanism prevents a single module failure from causing a complete system power supply paralysis, improves the system's anti-interference capability and fault handling efficiency, and reduces system downtime losses due to power supply faults.Addressing the challenges of multi-mode heterogeneous processing systems that include various processors, FPGAs, and diverse power supplies, this method enables unified management of dozens of different power supplies. A standardized control process ensures that each power module receives power sequentially and stably. After multiple power-on and power-off verifications in three temperature environments (high temperature, low temperature, and normal temperature), this method ensures that all processors and FPGAs within the system can start normally and operate stably, meeting the high-reliability power supply requirements for intelligent big data analysis and processing in multi-mode heterogeneous processing systems. Furthermore, after power-on, the method continuously monitors voltage and current status through a sampling interface, providing timely warnings of power supply anomalies and strengthening the power supply defenses for the long-term stable operation of the system.

[0035] The working principle of this invention is as follows: like Figure 1 The diagram shows a power supply control system based on a multi-mode heterogeneous processing system. Its main power supply system consists of one input interface, multiple power modules, an adjustable capacitor array, a power controller, and multiple output interfaces.

[0036] I. Power Module The power module (taking power module N in the figure as an example, 1~N are the same) has the following main interfaces: 1) input interface, 2) output interface, 3) enable interface, 4) output status interface, and 5) rise time configuration interface. like Figure 2 The diagram shown is the timing diagram for interface control from 3) to 5), where: 3) Enable Interface: The enable interface is the output control terminal of the power module. When this interface is set to 1, the power module outputs voltage starting from zero. 4) Output Status Interface: The output status interface is used by the power module to determine whether the output voltage reaches a certain threshold (this value varies depending on the power module model, such as 90% of the rated voltage). If the threshold is reached or higher, this interface will be set to 1. 5) Rise Time Configuration Interface: The rise time configuration interface adjusts the slope by configuring a variable capacitor. Generally, the larger the capacitor value, the longer the rise time, and the relationship is linear.

[0037] II. Adjustable Capacitor Array The adjustable capacitor array mainly consists of multiple capacitors controlled by electronic switches. When the electronic switch Sn is closed, capacitor Cn is engaged; when the electronic switch is open, the capacitor is disengaged. The capacitor value can be adjusted by switching on and off via switch Sn, thereby controlling the rise time of the power module's output voltage. Generally, the sum of the configured capacitances will be greater than the desired rise time plus a certain margin (the margin is mainly based on factors such as tolerance and component offset). The number of switches and capacitors can be determined according to the adjustment granularity; the smaller the granularity, the more switches and capacitors are required.

[0038] III. Power Controller The main interfaces of the power controller are: 1) Power supply interface; 2) Output interface 1: can control the enable terminal of the power module; 3) Output interface 2: can control the on and off of the electronic switch, thereby controlling the capacitor value; 4) Input interface: receives and judges the output status of the power module; 5) Sampling interface: collects the output voltage and output current of the power module, and can judge whether there is overshoot during power-on and the working status of each unit of the processor through the current. like Figure 4 As shown, the output control logic of the multi-power supply system is implemented in the power controller, and its power control logic is as follows; Initialize and configure basic operating parameters; Startup judgment: Startup timeout check; if timeout occurs, exit and determine timeout fault. When the control module is enabled, the module begins output. Ascent time adjustment: such as Figure 5 As shown, The first step is to determine whether to adjust the module based on whether it is enabled and not yet started. If the condition is not met, restore the initial value; otherwise, proceed to the next step. The second step is to obtain the real-time voltage value, the expected rise time t0, and the cumulative rise time t1. The third step is to calculate the expected remaining time: t2 = t0 - t1 (If the expected time is 30ms, the cumulative rise time is 10ms, and the expected remaining time is 20ms). Calculate the rate of change of voltage: du / dt = ΔU1 / Δt (ΔU1 is the difference between the sampled voltages of the two consecutive sampling periods, and Δt is the sampling time. For example, if the previous sampled voltage was 2V and the current sampled voltage is 2.1V, with a sampling period of 1ms (the sampling period can generally be set to more than 1 / 10 of the desired period as needed), then the voltage change rate is 0.1V / ms). Calculate the remaining time: t3 = ΔU2 / (du / dt) (ΔU2 is the difference between the desired output voltage and the current voltage. For example, if the desired output voltage is 5V, then ΔU2 is 2.9V, and the remaining time t3 = 2.9V / (0.1V / ms) = 29ms). The fourth step is to determine the relationship between t3 and t2 to decide whether to adjust Sn; Module status judgment: If the module status is 1, proceed to the next process; if it is not 1, check if the module output has timed out. If it has timed out, the timeout count is incremented. Check again if the number of timeouts has exceeded the limit. If the number of times has not exceeded the limit, the enable terminal is reset. If the limit has been exceeded, a timeout fault is judged. The processor status determination is similar to the module status determination, except that the processor status determination is determined by whether the current reaches the minimum start-up current. If it is greater than the minimum start-up current, the status is considered to be 1. Proceed to the startup sequence of the next module; until all modules have started. This invention mainly realizes a power supply and control method for a multi-mode heterogeneous processing system. The power supply system and control method utilize functions such as power module enable, voltage rise time monitoring, power module output status judgment, processor power supply completion status monitoring, and abnormal handling mechanism to achieve high-reliability power supply capability for the multi-mode heterogeneous system.

[0039] This power supply system and its control method have been successfully applied to a multi-mode heterogeneous big data intelligent analysis and processing system. This system includes two processors and three FPGAs, involving a total of 56 power supply types. Based on the power supply and control method of this invention, through 50 power-on and power-off tests at three temperatures (high temperature, low temperature, and room temperature), the normal and reliable operation of all processors and FPGAs was achieved, meeting the 100% pre-design evaluation requirement and providing a basis for the application of power supply and control methods in multi-mode heterogeneous processing systems.

[0040] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A power supply control system based on a multi-mode heterogeneous processing system, characterized in that, It includes an input interface, several power modules, an adjustable capacitor array, a programmable power controller, and multiple output interfaces; The input interfaces are electrically connected to the input side of each power module for external power supply. The adjustable capacitor array is electrically connected to the rise time configuration interface of each power module for adjusting the rise time of the power module output voltage. The programmable power controller is electrically connected to the enable interface and output status interface of each power module, and also to the control terminal of the adjustable capacitor array. The programmable power controller is equipped with a sampling interface, which is electrically connected to the output side of each power module for collecting the output voltage and output current of the power module. The output side of each power module is electrically connected to the corresponding multi-output interface, which is used to supply power to the load of the multi-mode heterogeneous processing system.

2. The power supply control system based on a multi-mode heterogeneous processing system according to claim 1, characterized in that, The power module is equipped with an input interface, an output interface, an enable interface, an output status interface, and a rise time configuration interface. The enable interface is the output control terminal of the power module. When the input of the enable interface is high, the power module starts up and outputs voltage. The output status interface is used to output a high level when the output voltage of the power module reaches a preset judgment voltage. The preset judgment voltage is 90% or more of the rated voltage of the power module.

3. The power supply control system based on a multi-mode heterogeneous processing system according to claim 1, characterized in that, The adjustable capacitor array consists of multiple electronic switches and multiple corresponding capacitors. The switching on and off of each capacitor is controlled by a corresponding electronic switch. The control terminal of the electronic switch is electrically connected to the output interface of the programmable power controller. The programmable power controller adjusts the overall capacitance value of the capacitor array by controlling the switching on and off of the electronic switches.

4. The power supply control system based on a multi-mode heterogeneous processing system according to claim 1, characterized in that, The total capacitance of the adjustable capacitor array is greater than the capacitance value corresponding to the expected rise time of the power module output voltage and a preset margin is reserved. The margin is determined based on the electronic component tolerance and device offset parameters.

5. The power supply control system based on a multi-mode heterogeneous processing system according to claim 1, characterized in that, The number of electronic switches and capacitors is determined by the adjustment granularity of the voltage rise time, and the adjustment granularity is inversely correlated with the corresponding number of electronic switches and capacitors.

6. A power supply control method for a multi-mode heterogeneous processing system based on the power supply control system according to any one of claims 1-5, characterized in that, include: System initialization: Configure the basic operating parameters of the multi-mode heterogeneous processing system through the programmable power controller; The basic operating parameters include the expected rise time, preset judgment voltage, minimum load starting current, and power-on timeout threshold for each power module. Power sequence startup control: The programmable power controller outputs control signals to the enable interface of each power module in a preset order, triggering the corresponding power module to start and begin outputting voltage; Voltage rise time adjustment: The programmable power controller collects the output voltage of the power module in real time through the sampling interface, and combines the deviation between the accumulated rise time and the desired rise time to control the electronic switching of the adjustable capacitor array to adjust the capacitor value, thereby adjusting the rise slope of the output voltage of the power module. Power-on status judgment: The programmable power controller determines whether the power output has reached the preset judgment voltage through the output status interface of the power module, and at the same time collects the power output current through the sampling interface to determine whether the load has reached the minimum starting current. If both conditions are met, the power supply and the corresponding load are determined to be powered on. Anomaly Handling and Timing Flow: If the current power supply and load complete power-on within the preset power-on timeout threshold, the startup control process of the next power module will be initiated until all power modules and loads are powered on. If power-on is not completed after the power-on timeout threshold is exceeded, anomaly handling operations such as restart or fault reporting will be performed.

7. The power supply control method for a multi-mode heterogeneous processing system according to claim 6, characterized in that, The configuration of the basic operating parameters is based on the load type of the multi-mode heterogeneous processing system, the power supply requirements of each processor and FPGA, and the tolerance and device offset parameters of electronic components. The principle for determining the preset order is: according to the core status and power supply dependence of the load in the multi-mode heterogeneous processing system, power is first started on the power module corresponding to the core control unit, and then power is started on the power module corresponding to the peripheral functional unit.

8. The power supply control method for a multi-mode heterogeneous processing system according to claim 6, characterized in that, The specific slope of the rising voltage of the power supply module output includes: Determine if the current power module is in a state where the enable has been triggered but the power-on is not complete. If not, restore the adjustable capacitor array to its initial capacitance value; if yes, proceed to the next step. Calculate the expected remaining time t2, where t2 = the preset expected rise time t0 - the accumulated rise time t1; Calculate the real-time voltage change rate du / dt, where du / dt = voltage difference between two adjacent sampling periods ΔU1 / sampling period Δt; Calculate the remaining voltage rise time t3, t3 = (expected output voltage - current real-time output voltage) / du / dt; Comparing t3 and t2, if t3 > t2, the adjustable capacitor array is controlled to reduce the input capacitance value to increase the rising slope; if t3 < t2, the adjustable capacitor array is controlled to increase the input capacitance value to decrease the rising slope.

9. The power supply control method for a multi-mode heterogeneous processing system according to claim 6, characterized in that, The preset judgment voltage is 90%~95% of the rated output voltage of the corresponding power module; the specific logic for judging whether the load has reached the minimum starting current is as follows: continuously collect the load end current 3~5 times. If all collected values ​​are greater than the minimum starting current of the load, the load current is determined to meet the requirements; if there is at least one collected value that is less than or equal to the minimum starting current of the load, the load current is determined to not meet the requirements.

10. The power supply control method for a multi-mode heterogeneous processing system according to claim 6, characterized in that, The exception handling operations specifically include: Upon first detection of a power-on timeout, the programmable power controller resets the enable interface of the current power module and re-triggers the power-on process of the power module. If the same power module triggers a power-on timeout three times in a row, it is determined that the power module or the corresponding load is faulty. The programmable power controller stops the startup process of subsequent power modules and reports the fault information to the main controller of the multi-mode heterogeneous processing system. The fault information includes the faulty power module number, the number of timeouts, and the voltage and current data of the last power-on.

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