Writing method and reading method for hidden data and memory device thereof
By employing asymmetric programming and read operations in the memory device and adjusting the threshold voltage distribution of the memory cells, the problems of high bit error rate and limited amount of hidden data when hiding data are solved, achieving more efficient data hiding and recovery.
Patent Information
- Application Number
- CN202411456090.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-14
- Filing Date
- 2024-10-18
- Publication Date
- 2026-04-14
AI Technical Summary
Existing technologies for hiding data in memory devices suffer from high bit error rates, leading to data recovery errors, and the amount of hidden data is limited.
By employing asymmetric programming and reading operations, and applying different levels of through voltage in the memory blocks, the threshold voltage distribution of the memory cells is adjusted, making the sub-latent states of hidden data more compact and reducing the bit error rate.
It effectively reduces the bit error rate when hiding data, increases the capacity of hidden data, and reduces programming and reading latency.
Smart Images
Figure CN121858023A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a corresponding technique for use in memory devices (e.g., NAND flash memory), and more particularly to a method for writing, reading, and using hidden data in a memory device. Background Technology
[0002] High-capacity and high-performance integrated circuit memories incorporating 3D NAND flash memory are under continuous development, aiming to reduce the size of memory cells and increase data storage density by utilizing 3D stacking technology and triple-level cells (TLC). On the other hand, data can be encrypted using various methods (e.g., adjusting the read / write methods of the memory device) to embed this hidden data (also known as secret data) into a memory device used to store public images or digital data. This hidden data can then be retrieved from the memory device using corresponding decryption methods, thus protecting the hidden data. This technique is called steganography.
[0003] Since data hiding is achieved by adjusting the read / write method of the memory device, the amount of data that can be hidden is correspondingly limited. On the other hand, because the threshold voltage distributions corresponding to the values "0" and "1" will inevitably overlap during the design process, the recovery of hidden data will be hampered; that is, errors may occur when extracting some bits from the hidden data. Therefore, how to avoid or reduce errors in bit extraction during the recovery of hidden data is one direction that needs further research. Summary of the Invention
[0004] The present invention provides a writing method, a reading method, and a memory device for hiding data in a memory device, which can reduce the bit error rate when retrieving hidden data.
[0005] This invention proposes a writing method for hiding data in a memory device. The writing method includes: providing a memory block, wherein the memory block includes a plurality of memory cells, the plurality of memory cells being respectively connected to a plurality of word lines and constructed as a plurality of pages, wherein each memory cell includes an erase state and a plurality of latent states, each latent state including a first sub-latent state and a second sub-latent state for hiding the hidden data; for a specific latent state among the plurality of latent states, performing a first programming operation on a plurality of memory cells in a first portion of a specific page to move a threshold voltage of the plurality of memory cells in the first portion to the first sub-latent state of the specific latent state, wherein the plurality of pages includes the specific page; and, for the specific latent state, performing a second programming operation on a plurality of memory cells in a second portion of the specific page to move a threshold voltage of the plurality of memory cells in the second portion to the second sub-latent state of the specific latent state. The first programming operation includes: applying a first pass voltage to a first word line of a first page of the plurality of pages, wherein the first page is adjacent to one side of the specific page; and applying a second pass voltage to a second word line of a second page of the plurality of pages, wherein the second page is adjacent to the other side of the specific page, wherein the first pass voltage is lower than the second pass voltage. The second programming operation includes: applying a third pass voltage to the first word line of the first page, wherein the third pass voltage is higher than the first pass voltage; and applying a fourth pass voltage to the second word line of the second page, wherein the fourth pass voltage is lower than the third pass voltage.
[0006] This invention proposes a memory device. The memory device includes a memory array and a memory controller. The memory array includes memory blocks. Each memory block includes a plurality of memory cells, each memory cell being connected to a plurality of word lines and configured as a plurality of pages. Each memory cell includes an erase state and a plurality of latent states, each latent state including a first sub-latent state and a second sub-latent state for hiding hidden data. The memory controller is coupled to the memory array. The memory controller is configured to: for a specific latent state of the plurality of latent states, perform a first programming operation on a plurality of memory cells in a first portion of a specific page to move a threshold voltage of the plurality of memory cells in the first portion to the first sub-latent state of the specific latent state, wherein the plurality of pages includes the specific page; and, for the specific latent state, perform a second programming operation on a plurality of memory cells in a second portion of the specific page to move a threshold voltage of the plurality of memory cells in the second portion to the second sub-latent state of the specific latent state. The first programming operation includes: applying a first pass voltage to a first word line of a first page of the plurality of pages, wherein the first page is adjacent to one side of the specific page; and applying a second pass voltage to a second word line of a second page of the plurality of pages, wherein the second page is adjacent to the other side of the specific page, wherein the first pass voltage is lower than the second pass voltage. The second programming operation includes: applying a third pass voltage to the first word line of the first page, wherein the third pass voltage is higher than the first pass voltage; and applying a fourth pass voltage to the second word line of the second page, wherein the fourth pass voltage is lower than the third pass voltage.
[0007] This invention proposes a method for reading hidden data in a memory device. The method includes: providing a memory block comprising a plurality of memory cells connected to a plurality of word lines and configured as a plurality of pages, wherein each memory cell includes an erase state and a plurality of latent states, each latent state including a first sub-latent state and a second sub-latent state for hiding hidden data; and performing a read operation to read a plurality of memory cells in a specific page of the memory block. The read operation includes: applying a first read voltage to a first word line of a first page of the plurality of pages, wherein the first page is adjacent to one side of the specific page; and applying a second read voltage to a second word line of a second page of the plurality of pages, wherein the second page is adjacent to the other side of the specific page, wherein the first voltage is lower than the second voltage.
[0008] This invention proposes a memory device. The memory device includes a memory array and a memory controller. The memory array includes memory blocks. The memory block includes a plurality of memory cells, each connected to a plurality of word lines and configured as a plurality of pages, wherein each memory cell includes an erase state and a plurality of latent states, each of the plurality of latent states including a first sub-latent state and a second sub-latent state for hiding hidden data. The memory controller is coupled to the memory array. The memory controller is configured to: perform a read operation for reading a plurality of memory cells in a specific page of the memory block, wherein the plurality of pages includes the specific page. The read operation includes: applying a first read voltage to a first word line of the first page of the plurality of pages, wherein the first page is adjacent to one side of the specific page; and applying a second read voltage to a second word line of a second page of the plurality of pages, wherein the second page is adjacent to the other side of the specific page, wherein the first voltage is lower than the second voltage.
[0009] Based on the above, the writing method, reading method, and memory device for hiding data in a memory device described in this embodiment of the invention apply different levels of through voltage to two pages adjacent to a specific page during the programming operation of the writing method. This makes the threshold voltage distribution corresponding to the two sub-latent states used for hiding data in a specific latent state more compact, preventing the threshold voltage distribution corresponding to the two sub-latent states from being exposed outside the threshold voltage distribution of the specific latent state. Furthermore, in the reading method, by performing asymmetric reading operations on the two adjacent pages and the specific page, the two sub-latent states are more separated, thereby reducing the bit error rate when retrieving the hidden data. Attached Figure Description
[0010] Figure 1 This is a schematic diagram of the structure of a memory block and a memory controller in a three-dimensional memory chip according to an embodiment of the present invention.
[0011] Figure 2 This is a schematic diagram of each page (e.g., pages P0 to P95) in a memory block BLK according to an embodiment of the present invention.
[0012] Figure 3 This is a schematic diagram of the threshold voltage distribution of public data and the sub-distribution of hidden data according to an embodiment of the present invention.
[0013] Figure 4 This is a flowchart of a method for writing data to a memory device according to an embodiment of the present invention.
[0014] Figure 5A and Figure 5BThese are respectively presented in the first embodiment of the present invention. Figure 4 Schematic diagrams of steps S420 and S430.
[0015] Figure 6 It is used to explain the process. Figure 4 A schematic diagram of the sub-potential states PS11, PS11' and PS12, PS12' after the write method is executed.
[0016] Figure 7 This is a flowchart of a method for reading hidden data in a memory device according to an embodiment of the present invention.
[0017] Figure 8 This is presented in the second embodiment of the present invention. Figure 7 A schematic diagram of step S720.
[0018] Figure 9 The first embodiment and the second embodiment Figure 8 A schematic diagram of the voltage waveforms applied to multiple word lines during the write and read methods.
[0019] Figure 10A and Figure 10B It is used to explain the process. Figure 7 A schematic diagram of the potential sub-states before and after the read method.
[0020] Figure 11A and Figure 11B These are respectively presented in the third embodiment of the present invention. Figure 4 Schematic diagrams of steps S420 and S430.
[0021] Figure 12 This is presented in the fourth embodiment of the present invention. Figure 7 A schematic diagram of step S720.
[0022] Figure 13 The third and fourth embodiments Figure 12 A schematic diagram of the voltage waveforms applied to multiple word lines during the write and read methods.
[0023] Explanation of reference numerals in the attached figures:
[0024] 110: Memory controller
[0025] BLK: Memory Block
[0026] 154: String of storage units
[0027] 156. SSL: Serial Select Line
[0028] 157: Storage Unit
[0029] 158. GSL: Ground Selection Line
[0030] 159. CSL: Common Source Line
[0031] 310, 1010: Overlapping parts
[0032] S410~S440: Steps of the method for writing hidden data in a memory device
[0033] 620: Mark
[0034] S710~S724: Steps of a method for reading hidden data in a memory device
[0035] SST: Serial Select Transistor
[0036] GST: Ground Select Transistor
[0037] BL1~BLn: Bit lines
[0038] Pages P0~P95, PM-1, PM+1:
[0039] PM: Page / Specific Page
[0040] WL0~WL95, WLm-1, WLm, WLm+1: Word lines
[0041] MC: Storage Unit
[0042] PUBD: Public Data
[0043] Vr1~Vr7: Reference voltages
[0044] Vr12: Sub-reference voltage
[0045] PS0: Erasure status
[0046] PS1~PS7: Potential State
[0047] PS11~PS71, PS11A, PS12A: First Sub-Latent State
[0048] PS12~PS72: Second Sub-Potential State
[0049] Numb: The number of storage units
[0050] Vt: Threshold voltage
[0051] Vpassp: Through voltage
[0052] Vpassp1, Vpassp1': First pass voltage
[0053] Vpassp2, Vpassp2': Second pass voltage
[0054] Vpassp3, Vpassp3': Third pass voltage
[0055] Vpassp4, Vpassp4': Fourth pass voltage
[0056] dV1, dV1', dVr1, dVr1': First voltage difference
[0057] dV2, dV2', dVr2, dVr2': Second voltage difference
[0058] dV3, dV3': Third voltage difference
[0059] dV4, dV4': Fourth voltage difference
[0060] Vpgm1, Vpgm2, Vpgm1', Vpgm2': Programming voltages
[0061] Vpassr: Reads the voltage passing through
[0062] Vpassr1, Vpassr1': First read voltage
[0063] Vpassr2, Vpassr2': Second read voltage
[0064] Vread: Read voltage Detailed Implementation
[0065] Figure 1 This is a schematic diagram of the structure of a memory block BLK and a memory controller 110 in a three-dimensional memory chip according to an embodiment of the present invention. Figure 2 This is a schematic diagram of each page (e.g., pages P0 to P95) in a memory block BLK according to an embodiment of the present invention. Please also refer to... Figure 1 and Figure 2 A three-dimensional memory chip may include one or more memory blocks BLK. Each memory block BLK includes multiple memory cells, multiple word lines WL0~WL95, and bit lines BL1~BLn. These memory cells are configured in three dimensions, for example, an XYZ coordinate system. Figure 1 Taking storage cell 157 as an example, storage cell 157 is coupled to the corresponding word line WL0 and bit line BL1. Figure 1 The memory block BLK is mainly presented in a three-dimensional form. Figure 2 It mainly presents the structure of each page (e.g., pages P0~P95) in the memory block BLK.
[0066] Word lines (e.g., word lines WL0 to WL95) formed by conductive layers or word line layers, along with multiple memory cells coupled to them, are divided into multiple pages. Each page can be, for example, multiple memory cells in the XY plane connected to the same word line. For example, Figure 2 The memory block BLK comprises pages P0 to P95. Memory cells on the same level (same page) can be coupled to the same word line (e.g., word line WL0 or WL95) and receive the corresponding word line voltage. Memory cells on different levels (different pages) are coupled to different word lines (e.g., word lines WL0 and WL95) and receive different word line voltages. In other words, a page in the memory block BLK is composed of memory cells connected to one of a series of corresponding word lines (e.g., one of word lines WL0 to WL95). Each page can be connected to a corresponding contact in the drive circuit, such as a scan driver, via one of the word lines WL0 to WL95 coupled to this page. Each line has a corresponding voltage driver, and these voltage drivers can be controlled by the memory controller 110 or corresponding hardware. Figure 1 Multiple storage units in storage unit string 154 belong to different pages.
[0067] Figure 1 Each memory cell string (e.g., memory cell string 154) includes a plurality of memory cells vertically connected in series along the Z direction. The memory cell string includes a plurality of memory cells (e.g., memory cell 157), a string select transistor SST coupled to a string select line SSL 156, and a ground select transistor GST coupled to a ground select line GSL 158. Memory cell string 154 is connected to one or more drivers, such as data drivers. Memory cell 157 is connected to a common source line CSL 159 via the ground select transistor GST. The string select line SSL 156 may be a conductive line or conductive layer formed on the top of each page (or word line layer). A memory block BLK may include a plurality of string select lines SSL 156 present on the top-level page. The ground select line GSL 158 may be a conductive line or conductive layer formed on the bottom of each page (or word line layer). The common source line CSL 159 may be a conductive layer or multiple conductive lines formed below the ground select line GSL 158 and on the substrate of the 3D memory chip. Several virtual lines or corresponding layers (not shown) may also be set between the string selection line SSL 156 and the topmost page, or between the ground selection line GSL 158 and the bottommost page.
[0068] The memory device in this embodiment includes a memory array and a memory controller (e.g., ...). Figure 1 Memory controller 110). Memory array may include one or more Figure 1The aforementioned memory block (BLK). Each memory block comprises multiple memory cells, and these memory cells are divided into multiple memory regions.
[0069] The storage cells in the memory block BLK belong to multi-level storage cells. A 'multi-level storage cell' is, for example, one of a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). In this embodiment, the memory device and the storage cells in the memory block BLK are exemplified by a three-level cell (TLC).
[0070] Steganography uses intentionally added minute distortions (such as tiny differences in threshold voltage distributions) to secretly embed data into publicly available digital data (e.g., images). Assuming an attacker has physical access to the memory device and can perform basic data storage and retrieval operations, they cannot determine whether the hidden data exists, let alone retrieve it, unless they know the key to the storage unit containing the hidden data or the exact location of the hidden data.
[0071] If steganography is implemented using a single-level storage unit, the size of the hidden data can only occupy a small percentage of the total number of bits of the public data, for example, 5.64%. Furthermore, when designing steganography, it is necessary to reduce the overlap between the threshold values of the hidden data's "0" and "1" values in programming operations, as this would worsen the extraction of the secret data.
[0072] The corresponding embodiments of the present invention are based on the concept of asymmetric charge in the storage layer (e.g., nitride layer) of a memory device, which serves as a storage unit, and propose a data hiding technique with asymmetric programming and reading operations. Based on the corresponding techniques of the embodiments of the present invention, the size of the hidden data relative to the public data can be increased (e.g., it can be 10.9% of the total number of bits in the public data). The embodiments of the present invention use multi-level storage units as the basis for the data hiding technique; therefore, except for the erase state, other potential states can hide data. For a TLC storage unit, data can be hidden through 7 potential states. In the embodiments of the present invention, approximately 1 / 8 of the total number of bits in a page can be hidden through 7 potential states. Specifically, since the erase state cannot hide data, approximately less than or equal to 7 / 64 (7 / 8 × 1 / 8) of the total number of bits in a page can be hidden through 7 potential states.
[0073] The values "1" and "0" in the threshold voltage distribution can be programmed in a more overlapping manner through asymmetric programming operations, allowing the hidden data threshold voltage distribution and its sub-distributions to be better overlapped, so that the hidden data can be well hidden within the dense threshold voltage distribution of the common data. Specifically, the asymmetric programming operations of this disclosed embodiment can make the sub-distributions of the hidden data have more overlap, thereby reducing program latency. Therefore, the programming operation of the hidden data can improve program latency due to the larger program step. On the other hand, the aforementioned sub-distributions of the hidden data can be easily identified through the asymmetric read operations in this embodiment. For example, this embodiment performs the read operation by predefining a specific reference voltage for recovering the hidden data and having an adaptive through voltage, without scanning the threshold voltage distribution of values "1" / "0" within a certain read voltage span, thereby improving read latency.
[0074] To read (also known as recover or extract) hidden data based on a specific location in the memory device, embodiments of the present invention use a shared secret key to inform the memory controller of the bit location of the common data holding the aforementioned hidden data, and the method used to read the hidden data. Embodiments of the present invention primarily focus on the methods for writing and reading hidden data; therefore, the following embodiments are all presupposed to be applied to the bit location of the common data used to hide the aforementioned hidden data.
[0075] Figure 3 This is a schematic diagram of the threshold voltage distribution of public data and the sub-distribution of hidden data according to an embodiment of the present invention. Figure 3 Presentation Figure 1 The threshold voltage distribution corresponding to the potential states of memory cells represented by TLC. Figure 3 The horizontal axis represents the threshold voltage Vt, and its unit is voltage V. Figure 3 The vertical axis represents the number of storage units, Numb.
[0076] Figure 1 Storage unit includes Figure 3 Erasure state PS0 and Figure 3 Potential states PS1 to PS7. The number of potential states PS1 to PS7 corresponds to the multiple potential states of a multilevel storage cell. For example, a multilevel storage cell (MLC) has 3 potential states in addition to the erase state PS0; a three-level storage cell (TLC) has 7 potential states in addition to the erase state PS0; and a four-level storage cell (QLC) has 15 potential states in addition to the erase state PS0.
[0077] The threshold voltage distributions corresponding to latent states PS1~PS7 are used for writing and reading operations of publicly available data (PUBD). On the other hand, each latent state PS1~PS7 includes a first sub-latent state PS11~PS71 and a second sub-latent state PS12~PS72 for hiding the hidden data. For example, for latent state PS1, if one bit of metadata is hidden in the public data, that is, one of the values "1" and "0" is implanted into the latent state PS1 of the public data. The hidden value "1" can be programmed to be the lower part of the threshold voltage distribution in the latent state PS1 of the public data, for example, the first sub-latent state PS11. The hidden value "0" can be programmed to be the higher part of the threshold voltage distribution in the latent state PS1 of the public data, for example, the second sub-latent state PS12. The sub-reference voltage Vr12 can be used to distinguish between the first sub-latent state PS11 and the second sub-latent state PS12.
[0078] The embodiments of the present invention are passed through Figure 1 and Figure 2 A specific page (e.g., page PM) in the presented memory device is programmed using an asymmetric scheme to hide data within that specific page (e.g., page PM). The memory cells in adjacent pages (e.g., page PM-1 or page PM+1) must be in a latent state (e.g., erase state PS0) with a lower threshold voltage. Latent states PS1 to PS7 can be used to hide data. That is, the voltage used for programming a value "1" will be different from the voltage used for programming a value "0".
[0079] For example, in a low threshold voltage state based on a top-to-bottom approach (e.g., the first embodiment and...) Figure 5A , Figure 5B During the first programming operation of the first sub-latent states PS11~PS71, a higher programming pass voltage is applied to word line WLm-1 and a lower programming pass voltage is applied to word line WLm+1. During the second programming operation of the second sub-latent states PS12~PS72, a higher programming pass voltage is applied to word line WLm+1 and a lower programming pass voltage is applied to word line WLm-1.
[0080] Alternatively, based on a low threshold voltage state from bottom to top (e.g., the third embodiment and...) Figure 11A , Figure 11BDuring the first programming operation of the first sub-latent states PS11~PS71, a higher programming pass voltage is applied to word line WLm+1 and a lower programming pass voltage is applied to word line WLm-1. During the second programming operation of the second sub-latent states PS12~PS72, a higher programming pass voltage is applied to word line WLm-1 and a lower programming pass voltage is applied to word line WLm+1.
[0081] Compared to the first sub-latent states PS11~PS71 and the second sub-latent states PS12~PS72 with hidden data, common data using normal programming operations (e.g., programming with a voltage equal to 10V or other values) achieves a wider threshold voltage distribution with a larger voltage step. Conversely, the asymmetric programming voltage step used with hidden data requires a smaller voltage difference to obtain a tighter threshold voltage distribution. While embodiments of the present invention can still have a larger voltage step or a larger voltage difference compared to other techniques for writing hidden data, embodiments of the present invention exhibit lower program latency than other techniques for writing hidden data.
[0082] The secret key can record a specific reference voltage (e.g., Figure 3 The sub-reference voltage Vr12 is used to distinguish between the hidden data values "1" and "0".
[0083] On the other hand, besides the specific reference voltage used to read the hidden data (e.g., Figure 3 In addition to the sub-reference voltage (Vr12), embodiments of the present invention further adjust the read pass voltage to achieve an asymmetric read operation. For example, for the value "0", this embodiment applies a lower read pass voltage to the word line of the first or second page, which is a page adjacent to the specific page being programmed. In this way, the threshold voltage distribution corresponding to the value "0" in the specific page can be shifted upward, so as to separate the values "1" and "0" on the threshold voltage distribution. See the following embodiments for a detailed description.
[0084] Figure 4 This is a flowchart of a method for writing data to a memory device according to an embodiment of the present invention. Figure 4 The write method is applicable to memory devices including a memory array and a memory controller 110, wherein the memory array includes memory blocks BLK, such as Figure 1 and Figure 2 As shown.
[0085] Figure 4 In step S410, a memory block BLK is provided, such as Figure 1 and Figure 2As shown. The memory block BLK comprises multiple memory cells. These memory cells are connected to multiple word lines (e.g., word lines WL0~WL95) and are constructed as multiple pages (e.g., pages P0~P95). Each memory cell includes an erase state (e.g., ...). Figure 3 Erased state PS0) and multiple potential states (e.g., Figure 3 Latent states PS1~PS7). Each latent state includes a first sub-latent state used to hide the hidden data (e.g., ...). Figure 3 Latent states PS11~PS71) and second sub-latent states (e.g., Figure 3 Potential states PS12~PS72).
[0086] Figure 4 In step S415, before performing programming operations (e.g., first programming operation, second programming operation, and normal programming operation) on a specific page, the memory controller 110 performs an erase operation on the memory block BLK.
[0087] Figure 4 In step S420, the memory controller 110, for a specific latent state among multiple latent states PS1~PS7 (in this embodiment, latent state PS1 is taken as the specific latent state), selects a specific page (e.g., Figure 2 In the first part of page PM, multiple memory cells perform a first programming operation to move the threshold voltage of the multiple memory cells in the first part to the first sub-latent state PS11 of a specific latent state (latent state PS1). For ease of explanation, it will be referred to here as... Figure 2 Page PM is referred to as a specific page, and pages P0 to P95 include specific page PM. Figure 2 Each page P0 to P95 is coupled to the corresponding word lines WL0 to WL95. For example, page PM is coupled to word line WLm; page PM-1 is coupled to word line WLm-1; page PM+1 is coupled to word line WLm+1. The memory cells MC in page PM are all coupled to word line WLm, and so on. For example, the memory cells MC in page PM+1 are all coupled to word line WLm+1.
[0088] Step S420 mainly includes step S422. Figure 4 In step S422, the memory controller 110 applies a first pass voltage to the first word line of the first page via corresponding hardware (e.g., a voltage driver), and the memory controller 110 applies a second pass voltage to the second word line of the second page via corresponding hardware. The first page is adjacent to one side of a specific page PM. The second page is adjacent to the other side of the specific page PM. The first pass voltage is lower than the second pass voltage. For details of step S420, please refer to [link to step S420]. Figure 5A and Figure 11A Corresponding embodiments.
[0089] Figure 4In step S430, for a specific latent state (e.g., latent state PS1), the memory controller 110 assigns a specific page (e.g., ... Figure 2 Multiple memory cells in the second part of page PM perform a second programming operation to move the threshold voltage of the multiple memory cells in the second part to a second sub-latent state PS12 of a specific latent state (latent state PS1). Step S430 mainly includes step S432. Figure 4 In step S432, the memory controller 110 applies a third pass voltage to the first word line of the first page via corresponding hardware (e.g., a voltage driver), and the memory controller 110 applies a fourth pass voltage to the second word line of the second page via corresponding hardware. The third pass voltage is higher than the first pass voltage. The fourth pass voltage is lower than the third pass voltage. For details of step S430, please refer to [link to relevant documentation]. Figure 5B and Figure 11B Corresponding embodiments.
[0090] Figure 4 In step S440, for a specific latent state (e.g., latent state PS1), the memory controller 110 performs normal programming operations on multiple memory cells in the third part of the specific page PM to write public data into the third part of the specific page PM. In other words, this embodiment uses corresponding programming operations to write the first value (e.g., value "0") and the second value (e.g., value "1") of the hidden data into the first and second parts of the specific page PM respectively (steps S420 and S430), and then uses normal programming operations to write public data into the third part of the specific page PM.
[0091] The aforementioned first, second, and third parts can be configured according to the needs of applying this embodiment, and this embodiment does not limit how the aforementioned first, second, and third parts are divided. Please refer to... Figure 3 For ease of illustration, in this embodiment, the number of storage units corresponding to the potential state PS1 includes the storage units of the first, second, and third parts mentioned above. The number of storage units corresponding to the first sub-potential state PS11 includes the storage units of the first part mentioned above, and the number of storage units corresponding to the second sub-potential state PS12 includes the storage units of the second part mentioned above. The first sub-potential state PS11 and the first sub-potential state PS12 have an overlapping portion 310.
[0092] Figure 5A and Figure 5B These are respectively presented in the first embodiment of the present invention. Figure 4 Schematic diagrams for steps S420 and S430. Please refer to the diagram corresponding to step S420. Figure 5AFor a specific potential state, a first pass voltage Vpassp1 is applied to the first word line WLm+1 of the first page (e.g., page PM+1), and a second pass voltage Vpassp2 is applied to the second word line WLm-1 of the second page (e.g., page PM-1), wherein the first pass voltage Vpassp1 is lower than the second pass voltage Vpassp2. The first page (page PM+1) is adjacent to one side of the specific page PM, and the second page (page PM-1) is adjacent to the other side of the specific page PM. The first pass voltage Vpassp1 is the voltage Vpassp minus the first voltage difference dV1. The second pass voltage Vpassp2 is the voltage Vpassp plus the second voltage difference dV2. In this embodiment, the first voltage difference dV1 can be any voltage from 0.1V to 10V, and the second voltage difference dV2 can be any voltage from 0.1V to 5V.
[0093] Figure 5A In addition, a first programming voltage Vpgm1 is applied to the word line WLm of a specific page PM. The first programming voltage Vpgm1 is set according to the first sub-latent state PS11 of a specific latent state PS1. Furthermore, a pass voltage Vpassp is applied to other pages (e.g., pages P0~PM-2, PM+2~P95).
[0094] Please refer to the corresponding step S430. Figure 5B For a specific potential state, a third pass voltage Vpassp3 is applied to the first word line WLm+1 of the first page (page PM+1), and a fourth pass voltage Vpassp4 is applied to the second word line WLm-1 of the second page (e.g., page PM-1), with the third pass voltage Vpassp3 being higher than the first pass voltage Vpassp1. The third pass voltage Vpassp3 is the voltage of the third voltage difference dV3 increased by the voltage Vpassp. The fourth pass voltage Vpassp4 is the voltage of the fourth voltage difference dV4 subtracted from the voltage Vpassp. In this embodiment, the third voltage difference dV3 is 0.1V to 5V, and the fourth voltage difference dV4 is 0.1V to 10V. Figure 5B In addition, a second programming voltage Vpgm2 is applied to the word line WLm of a specific page PM. The second programming voltage Vpgm2 is set according to the second sub-latent state PS12 of a specific latent state PS1. Furthermore, a pass voltage Vpassp is applied to other pages (e.g., pages P0~PM-2, PM+2~P95).
[0095] Figure 6 It is used to explain the process. Figure 4 A schematic diagram of the sub-latent states PS11, PS11' and PS12, PS12' after the write method. In another technique for hiding data, Figure 6 The left side (A) portion allows for the use of smaller voltage steps (e.g., Figure 6 The voltage step size on the left side is 0.1V to ensure that both sub-potential states PS11 and PS12 have a close threshold voltage distribution, thus eliminating any overlap between them. Furthermore, in this embodiment of the invention, a larger voltage step size can be used (e.g., Figure 6 The voltage step on the right side is 0.2V to allow sub-latent states PS11' and PS12' to have some overlap (e.g., marked 620). The reason for this is that the asymmetric read operation in this embodiment may shift sub-latent states PS11' and PS12', making the overlap (e.g., marked 620) smaller, or even causing sub-latent states PS11' and PS12' to have no overlap after the asymmetric read operation in this embodiment.
[0096] Figure 7 This is a flowchart of a method for reading hidden data in a memory device according to an embodiment of the present invention. Figure 7 The read method is applicable to memory devices including a memory array and a memory controller 110, wherein the memory array includes memory blocks BLK, such as Figure 1 and Figure 2 As shown.
[0097] Figure 7 In step S710, a memory block BLK is provided, such as Figure 1 and Figure 2 As shown. The memory block BLK comprises multiple memory cells. These memory cells are connected to multiple word lines (e.g., word lines WL0~WL95) and are constructed as multiple pages (e.g., pages P0~P95). Each memory cell includes an erase state (e.g., ...). Figure 3 Erased state PS0) and multiple potential states (e.g., Figure 3 Latent states PS1~PS7). Each latent state includes a first sub-latent state used to hide the hidden data (e.g., ...). Figure 3 Latent states PS11~PS71) and second sub-latent states (e.g., Figure 3 Potential states PS12~PS72).
[0098] Figure 7 In step S720, the memory controller 110 performs a read operation. The read operation is used to read a specific page (e.g., ...) of the memory block BLK. Figure 2 Multiple storage units in page PM. Step S720 mainly includes steps S722 and S724. Figure 7 In step S722, the memory controller 110 applies a first read pass voltage to the first word line of the first page through corresponding hardware. Figure 7In step S724, the memory controller 110 applies a second read pass voltage to the second word line of the second page via corresponding hardware. The first read pass voltage is lower than the second read pass voltage.
[0099] Step S720 further includes sequentially applying multiple read voltages Vread to specific word lines WLM of specific page PMs. These read voltages Vread are set according to the first sub-latent states PS11-PS71 and the second sub-latent states PS12-PS72 of each of the latent states PS1-SP7. Specifically, in this embodiment, these read voltages Vread can be multiple voltage steps, thereby determining the data hidden in the memory cells of these specific page PMs one by one. For details of steps S722 and S724, please refer to [link to relevant documentation]. Figure 8 Corresponding embodiments.
[0100] Figure 8 This is presented in the second embodiment of the present invention. Figure 7 A schematic diagram of step S720. Please refer to... Figure 8 A first read pass voltage Vpassr1 is applied to the first word line WLm+1 of the first page PM+1. The first page PM+1 is adjacent to one side of the specific page PM. A second read pass voltage Vpassr2 is applied to the second word line WLm-1 of the second page PM-1. The second page PM-1 is adjacent to the other side of the specific page PM. Furthermore, read pass voltage Vpassr is applied to the word lines of other pages (e.g., pages P0~PM-2, PM+2~P95).
[0101] In this embodiment, the first read pass voltage Vpassr1 is the read pass voltage Vpassr minus the first voltage difference dVr1. The first voltage difference dVr1 can be any voltage from 0.1V to 8V. The second read pass voltage Vpassr2 is the read pass voltage Vpassr plus the second voltage difference dVr2. The second voltage difference dVr2 can be any voltage from 0.1V to 5V. Alternatively, the second read pass voltage Vpassr2 can be the read pass voltage Vpassr itself.
[0102] Figure 9 The first embodiment and the second embodiment Figure 8 A schematic diagram of the voltage waveforms applied to multiple word lines WLm-1, WLm, and WLm+1 during the write and read methods. Figure 9 When presenting steps S420, S430 and S720 Figure 8 The voltage waveforms applied to word lines WLm-1, WLm, and WLm+1. The programming voltages Vpgm1 and Vpgm2 on word line WLm will try to maintain the same potential after their potentials are increased.
[0103] In the read operation of step S720, the read pass voltages on word lines WLm+1 and WLm-1 are maintained at the corresponding first read pass voltage Vpassr1 and second read pass voltage Vpassr2. The read voltage Vread on word line WLm then exhibits voltage steps to pass through various reference voltages (e.g., ...). Figure 3 The hidden data is read from the sub-reference voltage Vr12 and other sub-reference voltages located between sub-potential states PS21-PS22, PS31-PS32, PS41-PS42, PS51-PS52, PS61-PS62 and PS71-PS72.
[0104] Figure 10A and Figure 10B It is used to explain the process. Figure 7 A schematic diagram of the sub-potential states PS11~PS71 and PS12~PS72, PS11B~PS71B and PS12B~PS72B before and after the reading method. Figure 10A The explanation is mainly based on the sub-latent states PS11 and PS12 in latent state PS1, and the sub-latent states PS21 and PS22 in latent state PS2, etc. Figure 10A Sub-latent states PS11~PS71 and PS12~PS72 presentation process Figure 7 The threshold voltage distribution prior to the reading method. After steps S722 and S724, Figure 10A Sub-potential states PS11 and PS12 move to the right and separate to form Figure 10B The sub-potential states PS11B and PS12B, Figure 10A Sub-potential states PS21 and PS22 move to the right and separate to form Figure 10B Sub-potential states PS21B and PS22B, etc. Figure 10A Sub-potential states PS71 and PS72 move to the right and separate to form Figure 10B The sub-potential states PS71B and PS72B. Figure 10B Presentation process of sub-latent states PS11B~PS71B and PS12~PS72B Figure 7 Threshold voltage distribution after reading method.
[0105] From the sub-latent states PS11 and PS12, we can see that Figure 10A There is an overlap between the sub-potential states PS11 and PS12. On the other hand, after... Figure 7 After the read method Figure 10B Sub-potential states PS11B~PS71B and PS12B~PS72B will be due to Figure 9 The voltage supplied to the corresponding word lines PM+1 and PM-1 on the first page and the second page PM-1 is used to make... Figure 10B The sub-latent states PS11B~PS71B and PS12B~PS72B are further separated to reduce or even eliminate the area of overlapping parts, thereby reducing the bit error rate when extracting hidden data.
[0106] A third embodiment of the present invention, similar to the first embodiment, is presented here. The main difference is that the first page and the second page in the first embodiment can be interchanged to form the third embodiment. Figure 11A and Figure 11B These are respectively presented in the third embodiment of the present invention. Figure 4 Schematic diagrams of steps S420 and S430.
[0107] Please refer to the corresponding step S422. Figure 11A For a specific potential state, a first pass voltage Vpassp1' is applied to the first word line WLm-1 of the first page (e.g., page PM-1), and a second pass voltage Vpassp2' is applied to the second word line WLm+1 of the second page (e.g., page PM+1), wherein the first pass voltage Vpassp1' is lower than the second pass voltage Vpassp2'. The first pass voltage Vpassp1' is the voltage Vpassp minus the first voltage difference dV1'. The second pass voltage Vpassp2' is the voltage Vpassp plus the second voltage difference dV2'. In this embodiment, the first voltage difference dV1' can be any voltage from 0.1V to 10V, and the second voltage difference dV2' can be any voltage from 0.1V to 5V.
[0108] Figure 11A In addition, a first programming voltage Vpgm1' is applied to the word line WLm of a specific page PM. The first programming voltage Vpgm1' is based on... Figure 3 The first sub-potential state PS11 of a specific potential state PS1 is set. Furthermore, a pass voltage Vpassp is applied to other pages (e.g., pages P0~PM-2, PM+2~P95).
[0109] Please refer to the corresponding step S430. Figure 11BFor a specific potential state, a third pass voltage Vpassp3' is applied to the first word line WLm-1 of the first page (page PM-1), and a fourth pass voltage Vpassp4' is applied to the second word line WLm+1 of the second page (e.g., page PM+1), wherein the third pass voltage Vpassp3' is higher than the first pass voltage Vpassp1', and the fourth pass voltage Vpassp4' is lower than the third pass voltage Vpassp3'. The third pass voltage Vpassp3' is the voltage of the third voltage difference dV3' increased by the voltage Vpassp. The fourth pass voltage Vpassp4' is the voltage of the fourth voltage difference dV4' subtracted from the voltage Vpassp. In this embodiment, the third voltage difference dV3' is 0.1V to 5V, and the fourth voltage difference dV4' is 0.1V to 10V. Figure 11B In addition, a second programming voltage Vpgm2' is applied to the word line WLm of a specific page PM. The second programming voltage Vpgm2' is based on Figure 3 The second sub-potential state PS12 of the specific potential state PS1 is set. Furthermore, a pass voltage Vpassp is applied to other pages (e.g., pages P0~PM-2, PM+2~P95).
[0110] A fourth embodiment similar to the second embodiment of the present invention is proposed here, the main difference being that the first page and the second page in the second embodiment can be interchanged to form the fourth embodiment of the present invention. Figure 12 This is presented in the fourth embodiment of the present invention. Figure 7 A schematic diagram of step S720. Please refer to... Figure 12 A first read pass voltage Vpassr1' is applied to the first word line WLm-1 of the first page PM-1. The first page PM-1 is adjacent to one side of the specific page PM. A second read pass voltage Vpassr2' is applied to the second word line WLm+1 of the second page PM+1. The second page PM+1 is adjacent to the other side of the specific page PM. Furthermore, a read pass voltage Vpassr is applied to the word lines of other pages (e.g., pages P0~PM-2, PM+2~P95).
[0111] In this embodiment, the first read pass voltage Vpassr1' is the read pass voltage Vpassr minus the first voltage difference dVr1'. The first voltage difference dVr1' can be any voltage from 0.1V to 8V. The second read pass voltage Vpassr2' can be the read pass voltage Vpassr plus the second voltage difference dVr2'. The second voltage difference dVr2' can be any voltage from 0.1V to 5V. Alternatively, the second read pass voltage Vpassr2' can be the read pass voltage Vpassr itself.
[0112] Figure 13 The third and fourth embodiments Figure 12A schematic diagram of the voltage waveforms applied to multiple word lines WLm-1, WLm, and WLm+1 during the write and read methods. Figure 13 When presenting steps S420, S430 and S720 Figure 12 The voltage waveforms applied to word lines WLm-1, WLm, and WLm+1. Figure 9 and Figure 13 Compared to other embodiments, the voltages applied to word lines WLm-1 and WLm+1 are exactly interchanged. The programming voltages Vpgm1' and Vpgm2' located on word line WLm are then kept at the same potential as much as possible after their potentials are increased.
[0113] In the read operation of step S720, the read pass voltages located on word lines WLm-1 and WLm+1 are maintained at the corresponding first read pass voltage Vpassr1' and second read pass voltage Vpassr2'. The read voltage Vread located on word line WLm then exhibits voltage steps to pass through various reference voltages (e.g., ...). Figure 3 The hidden data is read from the sub-reference voltage Vr12 and other sub-reference voltages located between sub-potential states PS21-PS22, PS31-PS32, PS41-PS42, PS51-PS52, PS61-PS62 and PS71-PS72.
[0114] In summary, the writing method, reading method, and memory device for hiding data in a memory device described in this embodiment of the invention apply different levels of through voltage to two pages adjacent to a specific page during the programming operation of the writing method. This makes the threshold voltage distributions corresponding to the two sub-latent states used for hiding data in a specific latent state more compact, preventing the threshold voltage distributions corresponding to the two sub-latent states from being exposed outside the threshold voltage distribution of the specific latent state. If the sub-latent states are not to be overlapped, the amount of data to be hidden can be reduced; if the amount of data to be hidden is to be maintained or increased, the sub-latent states can be overlapped. Furthermore, in the reading method, by performing asymmetric reading operations on the two adjacent pages and the specific page, the two sub-latent states are more separated, thereby reducing the bit error rate when retrieving the hidden data.
[0115] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A method for writing data to hide it in a memory device, comprising: A memory block is provided, wherein the memory block includes a plurality of memory cells, the plurality of memory cells being connected to a plurality of word lines and constructed as a plurality of pages, wherein each memory cell includes an erase state and a plurality of potential states, each potential state including a first sub-potential state and a second sub-potential state for hiding the hidden data; For a specific potential state among the plurality of potential states, a first programming operation is performed on a plurality of memory cells in a first portion of a specific page to move the threshold voltage of the plurality of memory cells in the first portion to a first sub-potential state of the specific potential state, wherein the plurality of pages include the specific page; as well as For the specific latent state, a second programming operation is performed on a plurality of memory cells in the second portion of the specific page to shift the threshold voltage of the plurality of memory cells in the second portion to the second sub-latent state of the specific latent state. The first programming operation includes: Apply a first voltage through a first word line to a first page of the plurality of pages, wherein the first page is adjacent to one side of the particular page; and A second pass voltage is applied to the second word line of the second page of the plurality of pages, wherein the second page is adjacent to the other side of the particular page, wherein the first pass voltage is lower than the second pass voltage. The second programming operation includes: Apply a third through voltage to the first word line of the first page, wherein the third through voltage is higher than the first through voltage; and A fourth pass voltage is applied to the second word line of the second page, wherein the fourth pass voltage is lower than the third pass voltage.
2. The method for writing data to a memory device according to claim 1, wherein the first programming operation further comprises: For the given specific latent state, a first programming voltage is applied to the corresponding word line of the given specific page, wherein the first programming voltage is set according to the first sub-latent state of the given specific latent state. The second programming operation further includes: For the given particular latent state, a second programming voltage is applied to the word line of the given particular page, wherein the second programming voltage is set according to the second sub-latent state of the given particular latent state.
3. The writing method for hiding data in a memory device according to claim 1, further comprising: For the specific potential state, normal programming operations are performed on multiple storage units in the third part of the specific page to write common data into the third part of the specific page.
4. The writing method for hiding data in a memory device according to claim 3, further comprising: Before performing the first programming operation, the second programming operation, and the normal programming operation on the specific page, an erase operation is performed on the memory block.
5. The writing method for hiding data in a memory device according to claim 1, wherein the first pass voltage is a voltage minus a first voltage difference, the second pass voltage is the pass voltage plus a second voltage difference, the third pass voltage is the pass voltage plus a third voltage difference, and the fourth pass voltage is the pass voltage minus a fourth voltage difference.
6. The writing method for hiding data in a memory device according to claim 5, wherein the first voltage difference is between 0.1 volt and 10 volts, the second voltage difference is between 0.1 volt and 5 volts, the third voltage difference is between 0.1 volt and 5 volts, and the fourth voltage difference is between 0.1 volt and 10 volts.
7. The method for writing data to a memory device according to claim 5, wherein the first programming operation further comprises: The voltage is applied to the third word line of the third page of the plurality of pages, wherein the third page is different from the specific page, the first page, and the second page.
8. A memory device, comprising: A memory array includes a memory block, wherein the memory block includes a plurality of memory cells, the plurality of memory cells being connected to a plurality of word lines and constructed as a plurality of pages, wherein each memory cell includes an erase state and a plurality of potential states, each potential state including a first sub-potential state and a second sub-potential state for hiding the hidden data. as well as The memory controller is coupled to the memory array. The memory controller is used to: For a specific potential state among the plurality of potential states, a first programming operation is performed on a plurality of memory cells in a first portion of a specific page to move the threshold voltage of the plurality of memory cells in the first portion to a first sub-potential state of the specific potential state, wherein the plurality of pages include the specific page; as well as For the specific latent state, a second programming operation is performed on a plurality of memory cells in the second portion of the specific page to shift the threshold voltage of the plurality of memory cells in the second portion to the second sub-latent state of the specific latent state. The first programming operation includes: Apply a first voltage through a first word line to a first page of the plurality of pages, wherein the first page is adjacent to one side of the particular page; and A second pass voltage is applied to the second word line of the second page of the plurality of pages, wherein the second page is adjacent to the other side of the particular page, wherein the first pass voltage is lower than the second pass voltage. The second programming operation includes: Apply a third through voltage to the first word line of the first page, wherein the third through voltage is higher than the first through voltage; and A fourth pass voltage is applied to the second word line of the second page, wherein the fourth pass voltage is lower than the third pass voltage.
9. The memory device of claim 8, wherein the memory controller is further configured to: The first programming operation further includes: For the given specific latent state, a first programming voltage is applied to the corresponding word line of the given specific page, wherein the first programming voltage is set according to the first sub-latent state of the given specific latent state. The second programming operation further includes: For the given particular latent state, a second programming voltage is applied to the word line of the given particular page, wherein the second programming voltage is set according to the second sub-latent state of the given particular latent state.
10. The memory device of claim 8, wherein the memory controller is further configured to: For the specific potential state, normal programming operations are performed on multiple storage units in the third part of the specific page to write common data into the third part of the specific page.
11. The memory device of claim 10, wherein the memory controller is further configured to: Before performing the first programming operation, the second programming operation, and the normal programming operation on the specific page, an erase operation is performed on the memory block.
12. The memory device of claim 8, wherein the first through voltage is a voltage minus a first voltage difference, the second through voltage is a through voltage plus a second voltage difference, the third through voltage is a through voltage plus a third voltage difference, and the fourth through voltage is a through voltage minus a fourth voltage difference.
13. The memory device of claim 12, wherein the first voltage difference is between 0.1 volt and 10 volts, the second voltage difference is between 0.1 volt and 5 volts, the third voltage difference is between 0.1 volt and 5 volts, and the fourth voltage difference is between 0.1 volt and 10 volts.
14. The memory device of claim 12, wherein the memory controller is further configured to: The voltage is applied to the third word line of the third page of the plurality of pages, wherein the third page is different from the specific page, the first page, and the second page.
15. A method for reading data hidden in a memory device, comprising: A memory block is provided, wherein the memory block includes a plurality of memory cells, the plurality of memory cells being connected to a plurality of word lines and constructed as a plurality of pages, wherein each memory cell includes an erase state and a plurality of potential states, each potential state including a first sub-potential state and a second sub-potential state for hiding the hidden data; A read operation is performed to read multiple memory cells from a specific page of the memory block. The read operation includes: A first read voltage is applied to the first word line of the first page of the plurality of pages, wherein the first page is adjacent to one side of the particular page; as well as A second read pass voltage is applied to the second word line of the second page of the plurality of pages, wherein the second page is adjacent to the other side of the particular page, wherein the first read pass voltage is lower than the second read pass voltage.
16. The method for reading data hidden in a memory device according to claim 15, wherein the reading operation further comprises: Multiple read voltages are sequentially applied to specific word lines of the specific page. The plurality of read voltages are set according to the first sub-potential state and the second sub-potential state of each of the plurality of potential states.
17. The method for reading data hidden in a memory device according to claim 15, wherein the first read-through voltage is a read-through voltage minus a first voltage difference. The second read pass voltage is the read pass voltage minus the second voltage difference, or the second read pass voltage is the read pass voltage.
18. A memory device, comprising: A memory array includes a memory block, wherein the memory block includes a plurality of memory cells, the plurality of memory cells being connected to a plurality of word lines and configured as a plurality of pages, wherein each memory cell includes an erase state and a plurality of potential states, each of the plurality of potential states including a first sub-potential state and a second sub-potential state for hiding the hidden data. as well as The memory controller is coupled to the memory array. The memory controller is used to: A read operation is performed to read multiple storage cells from a specific page of the memory block, wherein the multiple pages include the specific page. The read operation includes: A first read voltage is applied to the first word line of the first page of the plurality of pages, wherein the first page is adjacent to one side of the particular page; as well as A second read pass voltage is applied to the second word line of the second page of the plurality of pages, wherein the second page is adjacent to the other side of the particular page, and the first read pass voltage is lower than the second read pass voltage.
19. The memory device of claim 18, wherein the memory controller is further configured to: Multiple read voltages are sequentially applied to specific word lines of the specific page. The plurality of read voltages are set based on the first sub-potential state and the second sub-potential state of each of the plurality of potential states.
20. The memory device of claim 18, wherein the first read pass voltage is a read pass voltage minus a first voltage difference. The second read pass voltage is the read pass voltage minus the second voltage difference, or the second read pass voltage is the read pass voltage.