An on-chip ripple compensation circuit for COT BUCK

Abstract

This invention discloses an on-chip ripple compensation circuit for COT BUCK, belonging to the field of integrated circuit design technology. The on-chip ripple compensation circuit includes PMOS transistors P1~P13, NMOS transistors N1~N9, resistors R1~R4, and capacitors C1 and C2. In this on-chip ripple compensation circuit, one end of resistor R1 is connected to the switching node SW, and the other end is connected to vs10 and one end of resistors R2 and R3. The other end of resistor R2 is grounded to VSS. The other end of resistor R3 is connected to vlpf and one end of capacitors C1 and R4, as well as the gate of PMOS transistor P12. The other end of capacitor C1 is grounded to VSS. This invention generates an AC ripple compensation voltage in phase with the inductor current without adding output pins, thus completing loop compensation. Furthermore, by performing two filtering processes on the SW point, the AC ripple signal is extracted and superimposed on the feedback signal vfb, both participating in the loop operation.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, specifically to an on-chip ripple compensation circuit for COT BUCK. Background Technology

[0002] Traditional BUCK converter circuits based on COT (constant on-time) control rely on the ESR (Equivalent Series Resistance) resistor R across the load capacitor C to generate RC zero-point compensation, thus meeting loop stability requirements. When a minimum phase margin of 45° is required, the ESR resistor needs to be greater than Tsw / π*C, where Tsw is the switching period, which is a relatively large ESR value. For high-performance products requiring low output ripple, low-ESR surface-mount capacitors are chosen. However, the zero-point generated by this ESR is outside the system band and cannot compensate for loop stability. Therefore, a ripple compensation circuit is needed to provide a new compensation zero-point, ensuring loop stability and low output ripple. Summary of the Invention

[0003] The purpose of this invention is to provide an on-chip ripple compensation circuit for COT BUCK, which generates an AC ripple compensation voltage in phase with the inductor current without adding output pins, thereby completing loop compensation; and by performing two filtering processes on the SW point, the AC ripple signal is extracted and superimposed on the feedback signal vfb to participate in the loop operation, thus solving the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: an on-chip ripple compensation circuit for COT BUCK, applied to a COT BUCK circuit, characterized in that the on-chip ripple compensation circuit includes PMOS transistors P1~P13, NMOS transistors N1~N9, resistors R1~R4, and capacitors C1 and C2;

[0005] In the ripple compensation circuit of this chip, one end of resistor R1 is connected to node SW, and the other end is connected to one end of resistors R2 and R3, with the connection point being node vs10. The other end of resistor R2 is grounded to VSS. The other end of resistor R3 is connected to capacitor C1, one end of resistor R4, and the gate of PMOS transistor P12, with the connection point being node vlpf. The other end of capacitor C1 is grounded to VSS. The other end of resistor R4 is connected to one end of capacitor C2 and the gate of P13, with the connection point being node vdc. The other end of capacitor C2 is grounded to VSS.

[0006] The drains of PMOS transistors P12 and P13 are connected to resistors R6 and R8, respectively, with the other ends of resistors R6 and R8 grounded to VSS. The source of PMOS transistor P12 is connected to one end of resistor R5 and the gate of NMOS transistor N1. The source of PMOS transistor P13 is connected to one end of resistor R7 and the gate of NMOS transistor N2. The other end of resistor R5 is connected to the drain of PMOS transistor P2, and the other end of resistor R7 is connected to the drain of P3 and the gate of N3. The bias current ibias is connected to the gate and drain of PMOS transistor P1, as well as the gates of PMOS transistors P2 and P3. The sources of PMOS transistors P1~P3, P4, P6, P8, and P10 are all connected to voltage VDD. The sources of NMOS transistors N1 and N2 are connected to resistors R10 and R11, respectively, with the other ends of resistors R10 and R11 grounded to VSS.

[0007] The drain of NMOS transistor N1 is connected to resistor R9 and the gates of PMOS transistors P5 and P7. The other end of resistor R9 is connected to the drain of PMOS transistor P5 and the gates of PMOS transistors P4 and P6. The source of PMOS transistor P5 is connected to the drain of PMOS transistor P4. The drain of NMOS transistor N2 is connected to the source of NMOS transistor N3, with the connection node being vs2. The drain of NMOS transistor N3, the drain of PMOS transistor P7, and one end of resistor R12 are connected. The drain of P6 and the source of P7 are connected. The other end of resistor R12 is connected to resistor R13 and the gates of NMOS transistors N4, N6, and N8. The other end of resistor R13 is connected to the drain of NMOS transistor N4 and the gates of NMOS transistors N5, N7, and N9. The source of NMOS transistor N4... The drain of NMOS transistor N5 is connected to the drain of NMOS transistor N6. The sources of NMOS transistors N5, N7, and N9 are grounded to VSS. The drain of NMOS transistor N7 is connected to the source of NMOS transistor N6, and the drain of NMOS transistor N9 is connected to the source of NMOS transistor N8. The drain of NMOS transistor N6 is connected to resistor R14 and the gates of PMOS transistors P9 and P11. The other end of resistor R14 is connected to the drain of PMOS transistor P9 and the gates of P8 and P10. The drain of PMOS transistor P8 is connected to the source of P9, and the drain of PMOS transistor P10 is connected to the source of P11. The drain of PMOS transistor P11 is connected to one end of resistor R15, and the connection point is node vsum. The other end of resistor R15 is connected to the drain of NMOS transistor N8, and the connection point is node vfb.

[0008] Preferably, the substrates of the NMOS transistors N1 to N9 are all grounded (VSS).

[0009] Preferably, the substrates of the PMOS transistors P1 to P13 are all connected to the power supply VDD.

[0010] Preferably, the COT BUCK circuit includes a comparator and an on-chip ripple compensation circuit.

[0011] Preferably, the on-chip ripple compensation circuit includes a ripple compensation circuit and a summing circuit; wherein, the input of the ripple compensation circuit is connected to node SW, and the output is connected to one input of the summing circuit; the other input of the summing circuit is connected to node vfb, and the output is node vsum, which is connected to the inverting input of the comparator.

[0012] Compared with the prior art, the beneficial effects of the present invention are:

[0013] This invention relates to an on-chip ripple compensation circuit for COT BUCK circuits. Without adding output pins, it generates an AC ripple compensation voltage in phase with the inductor current, thus completing loop compensation. By performing two filtering processes on the SW point, the AC ripple signal is extracted and superimposed on the feedback signal Vfb, both participating in the loop operation. The low-pass filter resistor and capacitor in the first stage generate the compensation zero point, completing phase compensation. Attached Figure Description

[0014] Figure 1 This is the overall block diagram of the COT BUCK circuit.

[0015] Figure 2 This is a circuit diagram of the on-chip ripple compensation circuit of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0017] Figure 1This is the block diagram of the COT BUCK circuit. VIN is the power input voltage, and VOUT is the BUCK output voltage. The PMOS is the upper power transistor, and the NMOS is the lower power transistor. The PMOS source and substrate are connected to VIN, and the NMOS source and substrate are grounded. Their drains are connected together as SW, which is connected to one end of inductor L. The other end of inductor L is connected to the load capacitor C and the load resistor Rload, serving as the output VOUT. Rf1 and Rf2 are feedback resistors. One end of Rf1 is connected to VOUT, and the other end is connected to Rf2, forming Vfb. The other end of Rf2 is grounded. Vfb is connected to the inverting input of the error amplifier and one end of the summing circuit. The other end of the error amplifier is connected to the reference voltage VREF, and the output is VCOM and the non-inverting input of the comparator. Cc is the compensation capacitor for the error amplifier, connected between VCOM and ground. The entire dashed box contains the on-chip ripple compensation circuit, with inputs SW and Vfb, and an output Vsum, which is connected to the inverting input of the comparator. The comparator output is vpulse, which is connected to the adaptive on-time transmitter. The output of the adaptive on-time generator is connected to the driver input, and the driver output is connected to the gate of the power transistors PMOS and NMOS.

[0018] Figure 2 This is a circuit diagram of the on-chip ripple compensation circuit of the present invention. The on-chip ripple compensation circuit includes a ripple compensation circuit and a summing circuit.

[0019] Vs10 = vsw / 10, the resistance of resistor R1 is 9 times that of resistor R2, which can reduce the size of the filter capacitor.

[0020] Resistor R3 and capacitor C1 form the first-stage low-pass filter circuit, generating ripple voltage vlpf; and in the frequency domain, a compensation zero ωz=1 / R3*C1 is generated.

[0021] Resistors R4 and C2 form the second-stage filter circuit, generating a DC voltage vdc. Assuming the threshold voltage vthn of all NMOS transistors and the threshold voltage vthp of all PMOS transistors are equal, denoted as vth, and given R10=R11=R15=R, the final ripple compensation voltage is:

[0022] vsum=vfb+[(vlpf+vthp-vthn) / R10 - (vdc+vthp-vthn) / R11 】*R15=vfb+vlpf-vdc=vfb+vac.

[0023] Where vac is the AC ripple voltage proportional to sw, and vfb is the feedback voltage.

[0024] In the diagram, PMOS transistors P12 and P13, and N1, N2, and N3 are source followers. R5, R7, N3, and R12 form a current filter, which is a core protection component of this invention.

[0025] The principle is: ilpf = (vlpf + vthp - vthn) / R10, idc = (vdc + vthp - vthn) / R11, iac = iipf - idc.

[0026] Since VLPF is a high-frequency sawtooth wave signal, the voltage of VS1 is also an approximate sawtooth wave signal with high and low voltages. Since the gate voltage of N3 is a DC signal, VS2 is also a DC signal. Thus, the drain voltage of N2 and VS3 both have stable voltage values. Due to the isolation effect of N3, the AC coupling path between the source and drain voltages of N2 is eliminated, ensuring that IDC is a stable DC current. Otherwise, without the isolation of N3, IDC would also be coupled with some AC, leading to a larger error value in IAC and a larger error value in the AC compensation of Vsum.

[0027] Figure 2In the diagram, N1~N9 are NMOS transistors, and their substrates are all grounded (VSS). P1~P13 are PMOS transistors, and their substrates are all connected to the power supply (VDD). One end of R1 is connected to SW, and the other end is connected to vs10 and R2. One end of R3 and the other end of R2 are grounded. The other end of R3 is connected to VLPF and C1. One end of R4 and the gate of P12 are connected to R4, and the other end of C1 is grounded. The other end of R4 is connected to VDC, one end of C2, and the gate of P13, and the other end of C2 is grounded. The drains of P12 and P13 are connected to resistors R6 and R8, respectively, with the other ends of the resistors grounded. The source of P12 is connected to one end of R5 and the gate of N1, and the source of P13 is connected to one end of R7 and the gate of N2. The other end of R5 is connected to the drain of P2, and the other end of R7 is connected to the drain of P3 and the gate of N3. The bias current ibias is connected to the gate and drain of P1, and the gates of P2 and P3. The sources of P1~P3, P4, P6, P8, and P10 are all connected to voltage VDD. The sources of N1 and N2 are connected to resistors R10 and R11 respectively, with the other ends of R10 and R11 grounded. The drain of N1 is connected to R9 and the gates of P5 and P7. The other end of R9 is connected to the drain of P5 and the gates of P4 and P6. The source of P5 is connected to the drain of P4. The drain of N2 is connected to the source of N3, forming vs2. The drain of N3 is connected to one end of R12, and the drain of P6 is connected to the source of P7. The other end of R12 is connected to the gates of R13, N4, N6, and N8. The other end of R13 is connected to the drain of N4, the gates of N5, N7, and N9. The source of N4 is connected to the drain of N5. The sources of N5, N7, and N9 are grounded. The drain of N7 is connected to the source of N6, and the drain of N9 is connected to the source of N8. The drain of N6 is connected to the gates of R14, P9, and P11. The other end of R14 is connected to the drain of P9 and the gates of P8 and P10. The drain of P8 is connected to the source of P9, and the drain of P10 is connected to the source of P11. The drain of P11 is connected to vsum and R15. The other end of R15 is grounded to vfb and the drain of V8.

[0028] This invention generates an AC ripple compensation voltage in phase with the inductor current without adding output pins, thus completing loop compensation. The AC ripple signal is extracted by performing two filtering processes on the SW point and superimposed on the feedback signal Vfb, both participating in the loop operation. The low-pass filter resistor and capacitor in the first stage generate the compensation zero point, completing phase compensation.

[0029] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0030] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An on-chip ripple compensation circuit for COT BUCK, applied to a COT BUCK circuit, characterized in that, The on-chip ripple compensation circuit includes PMOS transistors P1~P13, NMOS transistors N1~N9, resistors R1~R4, and capacitors C1 and C2. In the ripple compensation circuit of this chip, one end of resistor R1 is connected to node SW, and the other end is connected to one end of resistors R2 and R3, with the connection point being node vs10. The other end of resistor R2 is grounded to VSS. The other end of resistor R3 is connected to capacitor C1, one end of resistor R4, and the gate of PMOS transistor P12, with the connection point being node vlpf. The other end of capacitor C1 is grounded to VSS. The other end of resistor R4 is connected to one end of capacitor C2 and the gate of P13, with the connection point being node vdc. The other end of capacitor C2 is grounded to VSS. The drains of PMOS transistors P12 and P13 are connected to resistors R6 and R8, respectively, with the other ends of resistors R6 and R8 grounded to VSS. The source of PMOS transistor P12 is connected to one end of resistor R5 and the gate of NMOS transistor N1. The source of PMOS transistor P13 is connected to one end of resistor R7 and the gate of NMOS transistor N2. The other end of resistor R5 is connected to the drain of PMOS transistor P2, and the other end of resistor R7 is connected to the drain of P3 and the gate of N3. The bias current ibias is connected to the gate and drain of PMOS transistor P1, as well as the gates of PMOS transistors P2 and P3. The sources of PMOS transistors P1~P3, P4, P6, P8, and P10 are all connected to voltage VDD. The sources of NMOS transistors N1 and N2 are connected to resistors R10 and R11, respectively, with the other ends of resistors R10 and R11 grounded to VSS. The drain of NMOS transistor N1 is connected to resistor R9 and the gates of PMOS transistors P5 and P7. The other end of resistor R9 is connected to the drain of PMOS transistor P5 and the gates of PMOS transistors P4 and P6. The source of PMOS transistor P5 is connected to the drain of PMOS transistor P4. The drain of NMOS transistor N2 is connected to the source of NMOS transistor N3, with the connection node being vs2. The drain of NMOS transistor N3, the drain of PMOS transistor P7, and one end of resistor R12 are connected. The drain of P6 and the source of P7 are connected. The other end of resistor R12 is connected to resistor R13 and the gates of NMOS transistors N4, N6, and N8. The other end of resistor R13 is connected to the drain of NMOS transistor N4 and the gates of NMOS transistors N5, N7, and N9. The source of NMOS transistor N4... The drain of NMOS transistor N5 is connected to the drain of NMOS transistor N6. The sources of NMOS transistors N5, N7, and N9 are grounded to VSS. The drain of NMOS transistor N7 is connected to the source of NMOS transistor N6, and the drain of NMOS transistor N9 is connected to the source of NMOS transistor N8. The drain of NMOS transistor N6 is connected to resistor R14 and the gates of PMOS transistors P9 and P11. The other end of resistor R14 is connected to the drain of PMOS transistor P9 and the gates of P8 and P10. The drain of PMOS transistor P8 is connected to the source of P9, and the drain of PMOS transistor P10 is connected to the source of P11. The drain of PMOS transistor P11 is connected to one end of resistor R15, and the connection point is node vsum. The other end of resistor R15 is connected to the drain of NMOS transistor N8, and the connection point is node vfb.

2. The on-chip ripple compensation circuit for COT BUCK of claim 1, wherein, The substrates of the NMOS transistors N1 to N9 are all grounded (VSS).

3. The on-chip ripple compensation circuit for COT BUCK according to claim 2, characterized in that, The substrates of the PMOS transistors P1 to P13 are all connected to the power supply VDD.

4. An on-chip ripple compensation circuit for COT BUCK according to any one of claims 1-3, characterized in that, The COT BUCK circuit includes a driver, an adaptive on-time transmitter, a comparator, an error amplifier, and an on-chip ripple compensation circuit.

5. The on-chip ripple compensation circuit for COT BUCK according to claim 4, characterized in that, The on-chip ripple compensation circuit includes a ripple compensation circuit and a summing circuit; wherein, the input of the ripple compensation circuit is connected to node SW, and the output is connected to one input of the summing circuit; the other input of the summing circuit is connected to node vfb, and the output is node vsum, which is connected to the inverting input of the comparator.

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