Fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions

Abstract

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a fractional frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions. Background Technology

[0002] Fractional frequency dividers are widely used in modern wireless communication systems, radar systems, and digital clock generation systems, and hold a particularly high position in fields such as radio frequency transceiver systems, high-performance signal sources, and clock data recovery circuits.

[0003] As the 5G technology system gradually converges, 6G research has become a global research hotspot. Sensor-communication integration is becoming a key technology in the 6G era, enabling simultaneous wireless communication and physical world sensing. Multi-antenna technology in sensor-communication integration uses multi-chip splicing to overcome the limitations of the original number of transceiver channels within a single chip. A fractional-division frequency synthesizer provides the intrinsic signal to the RF transceiver within each chip. At this point, the local oscillator signal within each chip is frequency-consistent. However, due to non-ideal factors and other conditions, it is difficult to maintain phase consistency of the local oscillator signal within each chip. This phase inconsistency between the RF channels within each chip affects beamforming effects, thus reducing the reliability of target sensing results.

[0004] To meet the demands of 6G wireless communication, utilizing waveforms to achieve integrated sensing is a dominant trend. In radar systems classified by signal waveform, the signal source is a crucial component, affecting the accuracy of target speed and distance perception, as well as core indicators such as the sensing period. Pulse radar is a common type of waveform radar, but high-precision pulse radar suffers from disadvantages such as a minimum detection range blind zone, insufficient sensitivity to low-speed targets, and generally weak anti-jamming capabilities. Summary of the Invention

[0005] To address the shortcomings of the aforementioned background technology, this invention provides a fractional-frequency divider (FFD) frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave (FMCW) functionality. In integrated sensing systems, this FMCW synthesizer can be used not only in local oscillator signal applications such as multi-antenna technology in communications, where phase synchronization is critical, but also in generating FMCW sensing signal sources within integrated sensing systems. In FMCW radar systems, the output signal can be phase-synchronized before frequency-modulated to detect target objects. Using FMCW as the sensing signal source allows for the transmission of continuous low-power signals and simultaneous acquisition of distance and velocity, resulting in high accuracy for short-range measurements and suitability for chip-based and miniaturized designs. Given the functional similarities of some modules in the synchronization loop and FMCW loop, such as the frequency and phase detector, charge pump, and voltage-controlled oscillator, these modules can be shared, significantly reducing system power consumption and area costs.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution, the present invention comprising:

[0007] A fractional-order frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions is characterized by comprising a frequency and phase detector, a charge pump I, a charge pump II, a low-pass filter, a voltage-controlled oscillator, a buffer I, a buffer II, a divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode divider, a Delta-Sigma modulator (DSM), a selector I, a selector II, a selector III, a tracking phase accumulator, a numerically controlled oscillator, an accumulated phase difference register, an atan2 logic circuit, a main phase control circuit, a phase adjustment circuit, an enable control circuit, a waveform generator, and a serial peripheral interface.

[0008] The two inputs of the frequency and phase detector are connected to the external reference clock REF and the output of the programmable multimode divider, and the two outputs of the frequency and phase detector are respectively connected to the two inputs of charge pump one.

[0009] The two input terminals of charge pump one are connected to the two output terminals of the frequency and phase detector, and the output terminal of charge pump one is connected to the input terminal of the low-pass filter;

[0010] The two input terminals of charge pump 2 are connected to the two output terminals of the enable circuit, and the output terminal of charge pump 2 is connected to the input terminal of the filter.

[0011] The input of the low-pass filter is connected to the outputs of charge pump one and charge pump two, and the output of the low-pass filter is connected to the input of the voltage-controlled oscillator.

[0012] The input terminal of the voltage-controlled oscillator is connected to the output terminal of the low-pass filter, and the two differential output terminals of the voltage-controlled oscillator are connected to the two differential input terminals of buffer one.

[0013] The two differential input terminals of buffer one are connected to the two differential output terminals of voltage-controlled oscillator. The two differential output terminals of buffer one are respectively connected to the two differential input terminals of programmable multimode divider and the two differential input terminals of divider chain.

[0014] The two differential inputs of the divider chain are connected to the two differential outputs of buffer one, and the two differential outputs of the divider chain are connected to the two differential inputs of buffer two.

[0015] The two differential input terminals of buffer two are connected to the two differential output terminals of the divider chain, and the two differential output terminals of buffer two are connected to the two differential input terminals of the IQ undersampling circuit and the two differential input terminals of the local oscillator generator, respectively.

[0016] The clock input of the IQ undersampling circuit is connected to the external reference clock REF. The two differential inputs of the IQ undersampling circuit are connected to the two differential outputs of buffer two. The two quadrature outputs of the IQ undersampling circuit are connected to the two quadrature inputs of the cumulative phase difference register.

[0017] The two differential input terminals of the local oscillator generator are connected to the two differential output terminals of buffer two, and the quadrature output terminals of the local oscillator generator are used as the two quadrature output terminals of the fractional frequency divider synthesizer.

[0018] The two differential inputs of the programmable multimode divider are respectively connected to the two differential inputs of buffer one. The 8-bit control input of the programmable multimode divider is connected to the 8-bit division ratio sequence data output of the DSM. The output of the programmable multimode divider is respectively connected to one input of the frequency and phase detector, the clock input of the DSM, and one input of the waveform generator.

[0019] The clock input of the DSM is connected to the output of the programmable multimode divider; the 8-bit integer input of the DSM is connected to the 8-bit output of selector one; the 19-bit fractional value input of the DSM is connected to the 19-bit output of selector three; and the 8-bit division ratio sequence data output of the DSM is connected to the 8-bit control input of the programmable multimode divider.

[0020] The clock input of the tracking phase accumulator is connected to an external reference clock REF, the control input of the tracking phase accumulator is connected to an external phase synchronization control signal SYNC, and the 19-bit tracking phase value output of the tracking phase accumulator is connected to the 19-bit phase value input of the numerically controlled oscillator and the tracking phase value input of the phase adjustment circuit, respectively.

[0021] The 19-bit phase value input terminal of the numerically controlled oscillator is connected to the 19-bit tracking phase value output terminal of the tracking phase accumulator, and the two 16-bit quadrature output terminals of the numerically controlled oscillator are respectively connected to the two 16-bit quadrature input terminals of the cumulative phase difference register.

[0022] The two 16-bit quadrature inputs of the cumulative phase difference register are connected to the two 16-bit quadrature outputs of the numerically controlled oscillator. The two undersampled quadrature inputs of the cumulative phase difference register are connected to the two quadrature outputs of the IQ undersampled circuit. The two 30-bit cumulative value outputs of the cumulative phase difference register are connected to the two 30-bit numerical inputs of the atan2 logic circuit.

[0023] The two 30-bit numerical input terminals of the atan2 logic circuit are connected to the two 30-bit cumulative value output terminals of the cumulative phase difference register, and the 19-bit phase difference value output terminal of the atan2 logic circuit is connected to the 19-bit phase difference value data input terminal of the phase adjustment circuit.

[0024] The numerically controlled oscillator, the accumulated phase difference register, and the atan2 logic circuit together form a phase difference detection circuit module. The clock input of the phase difference detection circuit is connected to the external reference clock REF, and the control input of the phase difference detection circuit is connected to the external phase synchronization control signal SYNC. The two pairs of quadrature inputs of the phase difference detection circuit are connected to the two quadrature outputs of the IQ undersampling circuit and the two 16-bit quadrature outputs of the numerically controlled oscillator. The output of the phase difference detection circuit is the 19-bit phase difference output of the atan2 logic circuit.

[0025] The clock input of the main phase control circuit is connected to the external reference clock REF, the control input of the main phase control circuit is connected to the external phase synchronization control signal SYNC, the 19-bit data input of the main phase control circuit is connected to the 19-bit data output of the serial peripheral interface, and the 19-bit data output of the main phase control circuit is connected to a 19-bit data input of the phase adjustment circuit.

[0026] The clock input of the phase adjustment circuit is connected to an external reference clock REF; the control input of the phase adjustment circuit is connected to an external phase synchronization control signal SYNC; the 19-bit tracking phase value input of the phase adjustment circuit is connected to the 19-bit tracking phase value output of the tracking phase accumulator; the 19-bit phase difference input of the phase adjustment circuit is connected to the 19-bit phase difference output of the phase difference detection circuit; the 19-bit main phase input of the phase adjustment circuit is connected to the 19-bit main phase output of the main phase control circuit; the 19-bit output of the phase adjustment circuit is connected to one of the 19-bit inputs of selector two; and the control output of the phase adjustment circuit is connected to the control input of selector two.

[0027] The two 19-bit inputs of selector 3 are connected to the waveform generator and the 19-bit output of selector 2, respectively. The control input of selector 3 is connected to the external phase synchronization control signal SYNC, and the 19-bit output of selector 3 is connected to the 19-bit decimal input of DSM.

[0028] The two 19-bit inputs of selector 2 are connected to the serial peripheral interface and the 19-bit output of the phase adjustment circuit, respectively. The control input of selector 2 is connected to the control output of the phase adjustment circuit. The 19-bit output of selector 2 is connected to one 19-bit input of selector 3.

[0029] The two 8-bit input terminals of selector one are connected to the serial peripheral interface and the 8-bit output terminal of the waveform generator, respectively. The control input terminal of selector one is connected to the external chirp control signal CH, and the 8-bit output terminal of selector one is connected to the 8-bit integer input terminal of the DSM.

[0030] The clock input terminal of the enable control circuit is connected to the output frequency-divided clock signal FK of the waveform generator. The three control input terminals of the enable control circuit are respectively connected to the external chirp control signal CH, the external mode control signal MODE, and the output enable control signal E of the waveform generator. The two output terminals of the enable control circuit are connected to the two input terminals of charge pump II.

[0031] The clock input of the waveform generator is connected to the output of the programmable multimode divider. The two control inputs of the waveform generator are connected to the external chirp control signal CH and the external chirp mode control signal MODE, respectively. The two 8-bit inputs of the waveform generator are connected to the two 8-bit outputs of the serial peripheral interface, respectively. The two 16-bit inputs of the waveform generator are connected to the two 16-bit outputs of the serial peripheral interface, respectively. The two 24-bit inputs of the waveform generator are connected to the two 24-bit outputs of the serial peripheral interface, respectively. The 8-bit output of the waveform generator is connected to one 8-bit input of selector one, and the 19-bit output of the waveform generator is connected to one 19-bit input of selector three. The output divided clock signal FK of the waveform generator is connected to the clock input of the enable control circuit, and the output enable control signal E of the waveform generator is connected to one control input of the enable control circuit.

[0032] The input terminal of the serial peripheral interface is connected to the external data input signal SPI. The three 8-bit output terminals of the serial peripheral interface are connected to the two 8-bit input terminals of the waveform generator and the one 8-bit input terminal of selector one, respectively. The 19-bit output terminal of the serial peripheral interface is connected to the one 19-bit input terminal of selector two. The two 16-bit output terminals of the serial peripheral interface are connected to the two 16-bit input terminals of the waveform generator. The two 24-bit output terminals of the serial peripheral interface are connected to the two 24-bit input terminals of the waveform generator.

[0033] To ensure phase consistency of the output signals of all fractional frequency dividers in a multi-channel RF transceiver system using a multi-chip splicing method, before phase synchronization of most fractional frequency dividers, all fractional frequency dividers need to be locked and share a common reference clock with the same frequency and phase. Before phase synchronization begins for each fractional frequency divider, the external phase synchronization control signal SYNC, the external chirp control signal CH, and the external chirp mode control signal MODE of each fractional frequency divider are all set to low. The phase synchronization circuit and the linear frequency modulation continuous wave circuit of each fractional frequency divider do not generate phase adjustment signals. A continuous frequency modulation signal is applied. Selector 1, under the control of the external control signal CH, selects the 8-bit output value of the serial peripheral interface as the 8-bit integer input of the DSM. Selector 2, under the control of the control signal output from the phase adjustment circuit, selects the 19-bit output value of the serial peripheral interface as a 19-bit input of selector 3. Selector 3, under the control of the external phase synchronization control signal SYNC, selects the 19-bit input value of selector 2 as the 19-bit decimal input of the DSM. The DSM operates under the drive of a frequency divider clock. The frequency division ratio sequence output by the DSM controls the programmable multi-mode frequency divider to achieve fractional frequency division, thus achieving a locked state. In each decimal... When the frequency synthesizer starts phase synchronization, the external phase synchronization control signal SYNC changes from low to high. The phase synchronization circuit operates under the drive of the reference clock. The tracking phase accumulator uses the output value of selector two before synchronization as input to generate a 19-bit tracking phase value. The numerically controlled oscillator generates two orthogonal 16-bit output values ​​from the 19-bit tracking phase value. The IQ undersampling circuit, driven by the reference clock, undersamples the two input signals and outputs two down-frequency orthogonal signals. The accumulated phase difference register cross-multiplies the two pairs of orthogonal signals and then adds or subtracts them, accumulating the resulting sine and cosine phase difference values ​​to a certain extent, and finally outputs two 30-bit accumulated phase differences. The atan2 logic circuit calculates the phase difference by arctangenting the two 30-bit cumulative phase difference values ​​and generating a 19-bit phase difference value. The main phase control circuit generates the main phase value from the 19-bit input value from the serial peripheral interface. The phase adjustment circuit performs logical operations based on the tracking phase value, phase difference value, and main phase value to generate a phase adjustment value. The phase adjustment value will be continuously assigned to the DSM through selector two and selector three within N reference clock cycles, and the DSM output frequency division ratio sequence data will be input to the programmable multi-mode divider in real time, thereby controlling the phase of the output signal of the fractional frequency divider synthesizer and realizing phase synchronization of the output signals of multiple fractional frequency dividers synthesizers.

[0034] Before chirping the fractional-order frequency synthesizer, all components of the synthesizer must be in a locked state. The synthesizer uses its internal programmable multimode divider output DIV as the clock signal with the same frequency and phase. Before chirping, the external control signals SYNC, CH, and MODE are all low. At this time, the phase synchronization circuit and linear frequency modulation continuous wave circuit of the fractional-order frequency synthesizer do not generate phase adjustment signals and continuous frequency modulation signals. The output of the serial peripheral interface is input to the DSM via selector 1, selector 2, and selector 3. The division ratio sequence data output by the DSM is input to the programmable multimode divider. In the multi-mode frequency divider, it controls the fractional frequency division function. When the fractional frequency divider starts chirping, the external control signal SYNC remains low, and the external chirp control signal CH changes from low to high. At this time, the CH signal controls the linear frequency modulation continuous wave circuit to work. The external chirp mode control signal MODE controls the linear frequency modulation continuous wave circuit to generate a sawtooth wave signal or a triangular wave signal according to the mode selection. When the external chirp control signal CH changes from low to high, and the external chirp mode control signal MODE remains low, the linear frequency modulation continuous wave... The circuit operates in sawtooth wave mode. Selector 1 selects the 8-bit value output from the waveform generator and inputs it to the DSM. Selector 3 selects the 19-bit value output from the waveform generator and inputs it to the DSM. The dynamic change of the decimal value is the frequency step. The sum of the integer and decimal values ​​increases with the frequency step. The DSM outputs a division ratio sequence based on the integer and decimal values ​​to control the programmable multi-mode divider to achieve frequency sweep. When the chirp frequency reaches its peak, the control signal E output by the waveform generator changes from low to high, controlling the enable control circuit to output an enable signal. The enable control signal output by the enable control circuit controls the charge pump II. The additional current injected by the charge pump accelerates the descent of the sawtooth wave. After the frequency reaches its peak, the integer and decimal values ​​immediately return to their initial values. When the external chirp mode control signal MODE changes from low to high, the linear frequency modulated continuous wave circuit is in triangular wave mode. The sum of the integer and decimal values ​​increases with the frequency step by step to the peak value and then decreases back to the initial value. The control signal E output by the waveform generator has no effect on the enable circuit, and the enable control circuit has no high-level enable signal output. When in chirp mode, the I and Q signals output by the fractional frequency divider are linear continuous frequency modulated waves.

[0035] The beneficial effects achieved by the present invention using the above technical solution include:

[0036] (1) This fractional frequency divider can not only provide a high-precision phase-synchronized local oscillator signal to meet the communication application requirements of phase consistency of multiple fractional frequency dividers in the integrated sensing system, but also serve as a sensing signal source for the integrated sensing system, effectively overcoming the disadvantages such as minimum detection distance blind zone, insufficient sensitivity to low-speed targets, and general anti-interference capability.

[0037] (2) This fractional frequency synthesizer can not only provide broadband and linear triangular wave and sawtooth wave signal sources for frequency modulated continuous wave radar, but also has a phase synchronization function to synchronize the initial signal, avoiding the problem of target object blurring during detection.

[0038] (3) The synchronous loop and FMCW loop modules in the fractional frequency synthesizer have similar functions, such as frequency and phase detectors, charge pumps, voltage-controlled oscillators, etc. These modules can be shared to significantly reduce the power consumption and area cost of the system.

[0039] (4) A phase difference detection circuit was designed. An undersampling circuit combining a current-mode logic trigger and a differential-to-single-ended circuit was used to convert the high-frequency output signal into a low-frequency signal, which facilitated the detection of the phase of the output signal of the fractional frequency divider synthesizer. A pipelined structure numerically controlled oscillator using the CORDIC algorithm was used to convert the accumulated reference phase signal into a digital quadrature signal with the same period as the undersampling signal, which is beneficial for phase difference calculation. The accumulated phase difference register was used to calculate and accumulate the number of sampling points accumulated in integer periods, effectively filtering out the interference of high-order harmonics, and finally obtaining an accurate phase difference value, which provided an accurate value for the high-precision synchronization of the phase of the output signal of the fractional frequency divider synthesizer.

[0040] (5) An atan2 arctangent logic algorithm was designed, which uses the reverse CORDIC rotation principle to convert the sine and cosine phase difference values ​​accumulated by the accumulated phase difference register into a 19-bit phase difference signal, so that the phase difference value can be accurately converted.

[0041] (6) A phase adjustment circuit was designed. The phase bisection method was used to adjust the phase by 360° and the total phase adjustment amount was distributed in N reference clock cycles. This prevented the output clock signal of the fractional frequency synthesizer from losing lock and improved the accuracy of phase control.

[0042] (7) After phase synchronization, the fractional frequency synthesizer proposed in this invention restores the 19-bit input fractional value of all fractional frequency synthesizers (DSM) to the initial value, making the frequency division ratio sequence of all DSMs the same, thus ensuring the synchronization of all fractional frequency synthesizers. This effectively solves the phase asynchrony problem caused by the shift of the DSM frequency division column sequence, as well as the phase asynchrony problem caused by non-ideal effects such as loop delay caused by changes in process, voltage, temperature and other conditions.

[0043] (8) A waveform generator was designed to control the integer and decimal values ​​of the DSM input, and to realize the update of 8-bit integer and 19-bit decimal values ​​during frequency sweep. The internal numerical logic control includes increase, decrease and hold, so that the linear frequency modulated continuous wave signal output by the fractional frequency divider can be converted into multiple modes such as triangular wave, sawtooth wave and frequency hold, thus expanding its application field.

[0044] (9) The frequency modulation continuous wave circuit proposed in this invention can switch between sawtooth wave and triangular wave chirp modes by controlling the high and low frequencies of the MODE signal. The chirp signal frequency can be maintained by controlling the HODE signal to jump from high level to low. Furthermore, the frequency can be accelerated to drop after the sawtooth wave chirp mode frequency reaches its peak by injecting additional current. The three modes are simple and efficient to switch. Attached Figure Description

[0045] Figure 1 This is a block diagram of a fractional-frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions, as described in an embodiment of the present invention.

[0046] Figure 2 This is a structural diagram of the phase difference detection circuit in an embodiment of the present invention.

[0047] Figure 3 This is a block diagram of the numerically controlled oscillator circuit structure and algorithm in an embodiment of the present invention.

[0048] Figure 4 This is a structural diagram of the main phase control circuit in an embodiment of the present invention.

[0049] Figure 5 This is a schematic diagram of the phase adjustment circuit in an embodiment of the present invention.

[0050] Figure 6 This is a schematic diagram illustrating the working principle of the phase adjustment circuit in this embodiment of the invention.

[0051] Figure 7 This is a structural diagram of the waveform generator in an embodiment of the present invention.

[0052] Figure 8 This is a transient simulation diagram of the tracking phase accumulator and the numerically controlled oscillator in an embodiment of the present invention.

[0053] Figure 9 This is a transient simulation diagram of the open-loop phase synchronization circuit in an embodiment of the present invention.

[0054] Figure 10 This is a transient simulation diagram of the waveform generator in an embodiment of the present invention.

[0055] Figure 11 This is a transient simulation diagram of the phase synchronization output signal of the fractional frequency synthesizer in an embodiment of the present invention.

[0056] Figure 12 This is a simulation diagram of the triangular wave signal output frequency of the fractional frequency synthesizer in this embodiment of the invention.

[0057] Figure 13 This is a frequency sweep spectrum diagram of the triangular wave signal of the fractional frequency synthesizer in an embodiment of the present invention.

[0058] Figure 14 This is a simulation diagram of the sawtooth wave signal output frequency of the fractional frequency synthesizer in this embodiment of the invention.

[0059] Figure 15 This is a frequency sweep spectrum diagram of the sawtooth wave signal of the fractional frequency synthesizer in an embodiment of the present invention. Detailed Implementation

[0060] The specific embodiments of the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings.

[0061] Example: Figure 1 This invention discloses a fractional-division frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave (FM) functions. It comprises modules including a frequency and phase detector, charge pump one, charge pump two, a low-pass filter, a voltage-controlled oscillator, buffer one, buffer two, a divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode divider, a DSM, selector one, selector two, selector three, a tracking phase accumulator, a digitally controlled oscillator, an accumulated phase difference register, an atan2 logic circuit, a main phase control circuit, a phase adjustment circuit, an enable control circuit, a waveform generator, and a serial peripheral interface. Specifically, REF is generally the externally input reference clock signal provided by the crystal oscillator; SYNC is the externally input phase synchronization control signal; CH is the externally input chirp control signal; MODE is the externally input chirp mode control signal; SPI is the externally input data signal; and the I and Q signals are the quadrature signals output by the fractional-division frequency synthesizer. The frequency and phase detector can adopt a simple, linear edge-triggered structure; the charge pump can adopt a current-directing charge pump with high current matching rate; the voltage-controlled oscillator can adopt an LC resonant voltage-controlled oscillator with a high-frequency output range; the low-pass filter is designed as a third-order low-pass filter; the programmable multimode divider can be composed of TSPC or current-mode logic; the DSM adopts a MASH structure, generally a MASH1-1-1 structure.

[0062] In normal operation of the fractional-order frequency synthesizer (FRS) without phase synchronization or continuous frequency modulation, the external control signals SYNC, CH, and MODE are all kept low. Simultaneously, selector three selects the division ratio sequence output from selector two and inputs it to the DSM; selector one selects the division ratio sequence output from the serial external interface and inputs it to the DSM; and selector two selects the division ratio sequence output from the serial external interface and inputs it to selector three. Selector three and selector one jointly control the DSM to enable the fractional-order frequency division function. The phase and frequency detector outputs a pulse signal with a pulse width proportional to the phase difference between the external reference clock signal REF and the output signal of the programmable multimode divider. The charge pump's charging and discharging switch is controlled by the pulse signal output from the phase and frequency detector. The charge and discharging current of the charge pump controls the output voltage of the low-pass filter. The output frequency of the voltage-controlled oscillator (VCO) is controlled by the filter's output voltage. The VCO output frequency is then buffered and input to the programmable multimode divider, thus forming the entire negative feedback loop. To expand the output range of the fractional frequency synthesizer and achieve quadrature signal output, a four-stage current-mode logic divider chain consisting of cascaded dividers is connected after buffer one. This chain can realize frequency division by two, four, eight, and sixteen. The output signal of the divider chain is input to buffer two, and the output signal of buffer two is input to the local oscillator to generate two quadrature signals I and Q.

[0063] Before synchronizing the phases of multiple fractional frequency dividers, all fractional frequency dividers must reach a locked state for normal operation. At this time, the external phase synchronization control signal SYNC, the chirp control signal CH, and the chirp mode control signal MODE are all at a low level. During phase synchronization, the phase synchronization control signal SYNC of all fractional frequency dividers transitions from low to high, and each module in the phase synchronization circuit starts operating. Selector 1 selects the division ratio sequence output from the serial peripheral interface and inputs it into the DSM. Selector 2 selects the fractional value output from the serial peripheral interface and inputs it into selector 3. Selector 3 selects the division ratio sequence output from selector 2 and inputs it into the DSM. Before phase adjustment, the DSM drives the programmable multimode divider to implement the fractional frequency division function. The phase synchronization circuits are all driven by the reference clock REF. During the phase difference detection phase, the tracking phase accumulator uses the small value output from selector 2 as the initial value to generate the accumulated tracking phase signal, i.e., the reference phase signal. The tracking phase signal drives the numerically controlled oscillator to generate two orthogonal reference phase signals. The IQ undersampling circuit undersamples the high-frequency clock signal output from the fractional frequency divider under the drive of the reference clock. The accumulated phase difference register performs trigonometric function operations on the orthogonal signals provided by the numerically controlled oscillator and the undersampling circuit. After cross-multiplication, the values ​​are added or subtracted to obtain the sine and cosine values ​​of the phase difference. These values ​​are then accumulated and high-order harmonics are filtered out to obtain accurate phase difference information. After accumulation, the sine and cosine values ​​are output. The atan2 logic circuit starts running after the accumulated phase difference register outputs a value. It obtains the corresponding phase difference value by arctangenting the input value. The main phase control circuit outputs the main phase signal of the fractional frequency divider to the phase adjustment circuit. During phase detection, the output of the phase adjustment circuit is zero, and the control signal P of selector two is low. When the phase difference value is input, it calculates the total phase adjustment amount based on the tracking reference phase output by the tracking phase accumulator, the main phase signal output by the main phase control circuit, and the phase difference value output by the accumulated phase difference register. This total adjustment amount is distributed over N reference clock cycles and satisfies the following formula:

[0064]

[0065] Where PS is the total phase offset, and M is the 19-bit modulus of the modulator. To achieve phase adjustment within the range of 0~360°, the product of the additional value and the number of cycles in the formula is less than or equal to M. If the DSM is 20 bits, the M corresponding to the phase is 1048575. When the value of N is 5, X... adjWhen the value is 34952, PS represents a phase offset of 60°, and the phase offset per cycle is 12°. During the phase adjustment phase, P changes from low to high. Selector 2 selects the value of the phase adjustment circuit as input to selector 3. The input value of the tracking accumulator remains unchanged. Selector 1 still selects the division ratio sequence data output from the serial peripheral interface to drive the programmable multimode divider for real-time phase control. After the phase synchronization adjustment is completed, the output value of the phase adjustment circuit is reset to zero, and the control signal P changes from high to low. Selector 2 continues to select the serial peripheral interface as input, and the fractional frequency divider synthesizer returns to normal operation. The phase synchronization control signal SYNC changes from low to high to re-enable phase synchronization. After phase synchronization, the division ratio sequence data input to the DSM in all fractional frequency dividers is the same again. Phase adjustment synchronizes the output clock signals of all fractional frequency dividers, solving the phase asynchrony problems caused by the shift of the DSM division ratio sequence and the non-ideal effects such as loop delay caused by changes in PVT and other conditions. In phase synchronization mode, both the chirp control signal CH and the chirp mode control signal MODE are kept at a low level.

[0066] Before chirping, the fractional-division frequency synthesizer operates normally in normal mode, without phase synchronization or continuous frequency modulation. In this mode, the phase synchronization control signal SYNC, the chirp control signal CH, and the chirp mode control signal MODE are all kept low. When chirping occurs, the external chirp signal CH transitions from low to high, controlling the operation of the linear frequency modulation continuous wave circuit. The external chirp mode control signal MODE can be selected as either a sawtooth wave (low level) or a triangular wave (high level) chirp mode, depending on requirements. The external signals SYNC and CH are not simultaneously high, ensuring the orderly execution of phase synchronization and chirping modes without interference. During chirping, the waveform generator of the fractional-division frequency synthesizer generates varying integer and fractional values ​​based on the input data provided by the peripheral serial interface. The internal logic of the waveform generator is as follows: Figure 7As shown, it is driven by the DIV output of a programmable multi-mode divider, preventing the clock from affecting the output value. The frequency change is mainly reflected in the small value output by the waveform generator. The small value increases or decreases with the frequency step, and the integer value output by the waveform generator only changes when it exceeds the integer modulus. For example, if the small value is 16 bits and the reference clock REF is 50MHz, the corresponding modulus is 65535. If the frequency step value is 13107 and the ratio of the frequency step to the modulus is 0.2, then for every change in the frequency step of the waveform generator output, the output clock frequency of the fractional divider frequency synthesizer changes by 10MHz (reference clock multiplied by the ratio). During chirping, selector one selects the integer value output from the waveform generator to be input into the DSM, and selector three selects the decimal value output from the waveform generator to be input into the DSM. If the chirp mode control signal MODE is low, the clock signal output by the fractional divider frequency synthesizer is a sawtooth linear frequency modulated continuous wave, with the frequency increasing within the chirp period. The integer and decimal values ​​output by the waveform generator are controlled by the frequency step and increase accordingly under the drive of the divided clock. When the chirp frequency reaches its peak value, the waveform generator outputs an enable circuit control signal E. The enable control circuit then controls the frequency divided clock signal FK and the chirp mode control signal E. Under the control of the MODE control signal and the enable circuit control signal E, the output enable signal CP2 injects additional current, accelerating the descent process and reducing the time consumed during the descent. When the chirp mode control signal MODE transitions from low to high, the clock signal output by the fractional frequency divider synthesizer is a triangular linear frequency modulated continuous wave. The frequency first increases to the peak value and then decreases to the initial frequency within the chirp period. The integer and decimal values ​​output by the waveform generator also change accordingly. In triangular chirp mode, the enable signal control circuit remains at a low level and does not operate. To change the frequency step, simply change the corresponding input of the serial peripheral interface.

[0067] Figure 2 This is a schematic diagram of the phase difference detection circuit. The circuit structure includes modules such as a numerically controlled oscillator (CNC), a cumulative phase difference register, and the arctangent function atan2 logic circuit. The input ports include: a reference clock signal input port (REF), a phase synchronization control signal input port (SYNC), an orthogonal signal input port from the undersampling circuit (S_Q and S_I), a 19-bit data value input port for the CNC oscillator (inputting the 19-bit output data signal T<18:0> generated by the tracking phase accumulator based on the fractional value F3<18:0>, i.e., F1<18:0>), two 16-bit data value input ports for the cumulative phase difference register (inputting the 16-bit orthogonal signals S<15:0> and C<15:0> generated by the CNC oscillator), and two 30-bit data value input ports for the atan2 logic circuit (inputting the two 30-bit output data signals A<0> and C<0> generated by the cumulative phase difference register).Q <29:0> and A I <29:0>, the output of the 19-bit output port of the atan2 logic circuit is the 19-bit phase difference signal A<18:0> after arctangent operation. The mutually orthogonal trigonometric function signals generated by the numerically controlled oscillator satisfy the expression:

[0068]

[0069]

[0070] Where F ref For reference clock, F is a decimal value, Φ er To track the phase error caused by the truncation of the phase accumulator output, its value is negligible, and t is time. According to the sampling theorem, the undersampled signal input to the cumulative phase difference register satisfies the expression in the time domain:

[0071]

[0072]

[0073] ∆Φ is the phase difference value. The two sets of orthogonal signals are cross-multiplied and then added together:

[0074]

[0075]

[0076] The cumulative phase difference register uses the input orthogonal trigonometric function signal and the sampled output signal to perform trigonometric function operations and accumulate the data before outputting the cumulative phase difference signal A. Q <29:0> and A I <29:0>, the atan2 logic circuit relies on the accumulated phase difference signal A Q <29:0> and A I <29:0> The phase difference value A<18:0> is obtained using the arctangent algorithm. The APD... I (t) divided by APD Q The arctangent of the ratio obtained after (t) can be used to obtain the phase difference ∆Φ:

[0077]

[0078] When the phase synchronization control signal SYNC is low, both the internal and external input / output signal values ​​of the phase difference detection circuit are zero or low, and the circuit does not work. When the phase synchronization control signal SYNC changes from low to high, the non-zero tracking phase accumulation signal T<18:0> is input to the numerically controlled oscillator to generate quadrature signals S<15:0> and C<15:0>. The quadrature signals S<15:0> and C<15:0>, along with the undersampled signals S_Q and S_I, are input to the cumulative phase difference register. After processing and accumulating a certain amount, the cumulative difference signal A is generated. Q <29:0> and A I <29:0>, Cumulative difference signal A Q <29:0> and A I The input <29:0> is fed into the atan2 logic circuit. After arctangent operation, the phase difference signal A<18:0> is output. The value of A<18:0> remains unchanged until the next phase difference calculation result is obtained.

[0079] Figure 3 This is a block diagram of the circuit structure and algorithm of a numerically controlled oscillator. Figure 3 (a) shows the circuit structure of a traditional numerically controlled oscillator. Its main structure includes a phase accumulator PA and a phase amplitude mapper PAM. PCW is the input value of the phase control word input port, and ICW is the input value of the initial control word input port. When the circuit is working, the input signal passes through the phase accumulator and the phase amplitude mapper, and the two output ports output orthogonal trigonometric function signals. The phase accumulator invented in this paper is directly replaced by a tracking phase accumulator to provide the input signal of the phase amplitude mapper. Figure 3 (b) is the schematic diagram of the CORDIC algorithm. The phase amplitude mapper can be implemented by the CORDIC algorithm. As shown in the figure, according to Givens' rotation law, the angle difference between vector A and vector B is known to be θ. When point A is given, the combination of coordinates of point B can be obtained by successively approximating according to the rotation law. Figure 3 (c) shows the CORDIC algorithm implemented with an 11-stage streamlined architecture. Each stage includes three adders / subtractors and two shift registers. x0 and y0 are two initial input values. z0 is a value generated internally by the algorithm based on the input phase to determine the rotation direction of the first stage. After the first stage rotates by an angle θ0, the resulting x1 and y1 output values ​​are used as the inputs for the second stage. The rotation direction after the first stage is determined again to generate z1, and so on until the 11-stage pipeline ends to obtain x. out y out The output is the sine and cosine values.

[0080] Figure 4This is a structural diagram of the main phase control circuit. The main phase control circuit consists of a main counter, a phase counting circuit, and a main phase accumulator. The main counter includes a phase synchronization signal input port (SYNC), a clock signal input port (REF), and a main counter output port to output the counting signal. The phase counting circuit includes a counter input port to input the counting signal, a reset signal input port (R), a 19-bit decimal value input port (F1<18:0>), and a phase counting circuit output port to output the instantaneous main phase signal. The main phase accumulator includes a phase counting circuit input port to input the instantaneous main phase signal, a 19-bit decimal value input port (also F1<18:0>), and a main phase signal output port to output the signal M<18:0>. When the phase synchronization control signal SYNC is low, none of the modules in the phase synchronization control circuit operate, and the output signals of each module are zero. When the phase synchronization control signal SYNC changes from low to high, the main phase control circuit starts working. Starting from the first rising edge of the reference clock REF, the main counter is driven by the reference clock REF to increment by +1 and output a counting signal. The phase counting circuit maintains a zero output value when the input reset signal R is low. When the reset signal changes from low to high, the phase counting circuit calculates the instantaneous main phase signal according to the function (G*F)%M, where the value of the decimal F is F1<18:0>, and G is the value of the main counter output when the reset signal R is high, adjusted by the phase counting circuit. The main phase accumulator outputs the main phase signal M<18:0> based on the non-zero instantaneous main phase signal.

[0081] Figure 5 and Figure 6 This includes the schematic diagram and operating principle diagram of the phase adjustment circuit. The structure of the phase adjustment circuit is as follows: Figure 1 As shown, the module includes a phase synchronization signal control port with the input signal SYNC; a reference clock signal input port with the input signal REF; a 19-bit tracking phase signal input port with the input signal T<18:0>; a 19-bit main phase signal input port with the input signal M<18:0>; a 19-bit phase difference signal input port with the input signal A<18:0>; a 19-bit phase adjustment signal output port with the output signal FADJ<18:0>; and a selector two control signal output port with the output signal P. Since the total adjustment amount cannot be directly output, the phase adjustment circuit uses a phase binary search method for phase adjustment. For example, assuming the total phase adjustment amount is ∆Φ-Φ M +Φ T ,∆Φ、Φ M and Φ TThese correspond to signals A<18:0>, M<18:0>, and T<18:0>, respectively. When the total phase adjustment is between 0 and π, i.e., Φ1 is greater than 0, it needs to be rotated clockwise to bring the clock signal output by the fractional frequency divider back to the origin, which is equivalent to adding 2π-Φ1 in the calculation; when it is between -π and 0, i.e., Φ2 is less than 0, it needs to be rotated counterclockwise, which is equivalent to adding -Φ2. When the phase synchronization control signal SYNC is low, the output signal FADJ<18:0> has a value of 0, and the control signal P is low. When the phase synchronization control signal SYNC changes from low to high and the input A<18:0> is non-zero, starting from the first rising edge of the clock signal REF, within N reference clock cycles REF, the output signal FADJ<18:0> equals FALL / N, where FALL is the assumed total phase adjustment amount, and the output control signal P is high. After N clock cycles REF, in each REF cycle, the output signal FADJ<18:0> returns to 0, and the control signal P is low, until the next rising edge of the phase synchronization control signal SYNC is input.

[0082] Figure 7This is a diagram of a waveform generator. The waveform generator mainly consists of a sweep circuit, a waveform selector, a register, an adder, and some logic circuits. It includes a clock signal input port (input signal DIV), three chirp signal input ports (input chirp control signal CH, chirp mode control signal MODE, and chirp hold signal H), two 8-bit data input ports (input chirp integer signal N1<8:0> and frequency divider control signal K<8:0>), two 24-bit data input ports (input initial small value signal F2<23:0> and maximum small value signal F3<23:0>), two 16-bit data input ports (input rise step signal B1<15:0> and fall step signal B2<15:0>), an 8-bit output port (output chirp integer signal FWG<8:0>), a 19-bit output port (output chirp small value signal FWG<8:0>), and an enable circuit control signal output port (output enable control signal E). When the chirp control signal CH is low, the waveform generator does not work, and the output signal is zero or low. When the chirp control signal CH changes from low to high, the waveform generator starts working. The sweep signals NWG<7:0> and FWG<18:0> output by the waveform generator are updated in real time. The frequency divider clock signal DIV is divided by a digital k-divider and used as the chirp sweep clock. The two accumulators are controlled by FS<18:0> and NS<7:0> to increase or decrease by one frequency step in each clock cycle until the sum of NWG<7:0> and FWG<18:0> reaches the peak or initial value of the required sweep frequency. The sweep module provides the accumulator with the fractional value FS<18:0> and the integer value NS<7:0> for sweeping based on the input frequency step Fstep<18:0>, the initial integer value N1<7:0>, and the initial decimal value F2<23:0>. The waveform selection module generates Fstep<18:0> for both rising and falling based on the input F2<23:0>, maximum minimum value F3<23:0>, rising steps B1<15:0>, and falling steps B2<15:0>. It then switches Fstep<18:0> and the increment / decrement state control signal Se according to the mode control signal MODE and the subtraction end signal E2. Its output signals J1<23:0> and J2<23:0> are used for the logical determination of the end of subtraction and addition. The addition end signal E, the hold signal H, and Se work together to control the state module. Its output signal ASH<1:0> controls the selection of the adder mode. At the same time, signal E also serves as an enable control signal output. When it is high, it triggers the enable control circuit of the built-in counter, which controls the charge pump to inject additional current for a short period of time.

[0083] Figure 8This is a transient simulation diagram of a tracking phase accumulator and a numerically controlled oscillator. The tracking phase accumulator and the numerically controlled oscillator are simulated together, with the reference clock signal REF frequency set to 50MHz, corresponding to a 19-bit fractional value F<18:0> of 21845. When the synchronization indicator signal SYNC is high, the tracking phase accumulator and the numerically controlled oscillator start running. Upon detecting its falling edge, the tracking phase accumulator and the numerically controlled oscillator are reset. The tracking phase accumulator outputs a 19-bit reference phase signal T<18:0> representing the range 0° to 360°. The 16-bit S<15:0> and C<15:0> are two quadrature signals generated by truncating the high 16 bits of T<18:0>. The output waveforms of the tracking phase accumulator and the numerically controlled oscillator are normal.

[0084] Figure 9 This is a transient simulation diagram of the open-loop phase synchronization circuit. To verify the correctness of the synchronization circuit algorithm, the undersampling circuit, phase difference detection circuit, main phase control circuit, and phase adjustment circuit are simulated together in an open-loop phase synchronization simulation. That is, the output signal of the phase adjustment circuit is not connected to the DSM, but only performs phase detection and phase adjustment information generation. The loop division ratio is set to 15.0416, and the reference clock signal REF is still 50MHz, so the output clock frequency of the fractional frequency synthesizer is 752.08 MHz, and the fractional value F1<18:0> is also 21845. The undersampling circuit and the fractional frequency synthesizer work simultaneously and output two quadrature signals S_Q and S_I. When the phase synchronization control signal SYNC jumps from low level to high level, the entire phase synchronization circuit starts to run, tracking the output signals T<18:0>, S<15:0>, and C<15:0> of the phase accumulator and the numerically controlled oscillator as described above; the phase difference detection circuit continuously updates the accumulated phase difference signal A. Q <29:0> and A I <29:0>, after accumulation, the arctangent signal A<18:0> is obtained, A Q <29:0> / A I The tangent of the angle after conversion between the value of <29:0> and A<18:0> is approximately -3.7, indicating normal function and reliable accuracy. When signal R is high, the main phase control circuit continuously updates the main phase signal M<18:0>, and stops outputting when R is low. The phase adjustment circuit finally outputs signal F2<18:0>, whose value switches between F1<18:0> and the value with added phase adjustment. It continuously adjusts for N reference clock signal REF cycles before switching back to the smaller value F1<18:0>.

[0085] Figure 10This is the transient simulation diagram of the waveform generator. N1<7:0>, F2<23:0>, and F3<23:0> are set to 181, 52428, and 10538188 respectively. The values ​​of F2<23:0> and F3<23:0> relative to the 19-bit values ​​are 0.1 and 20.1 respectively. B1<15:0> and B2<15:0> are both set to 150 steps, that is, the output increases by 0.133 for each time step. The frequency divider clock DIV is divided by 3 and used as the sweep clock Fk. From the waveforms of the output signals NWG<7:0> and FWG<18:0> in the diagram, it can be observed that the circuit only operates when the chirp control signal CH is high. When the chirp mode control signal MODE is high, a triangular wave control signal is output. NWG<7:0> increases to its peak value and then decreases, while FWG<18:0> increases to overflow, then increases again, and begins to decrease after reaching its peak value. When the chirp mode control signal MODE is low, a sawtooth wave control signal is output, performing only addition operations. When the hold signal H is low, the output maintains its original value. The addition end signal E remains high for one division clock cycle when the accumulation reaches its peak value. In the loop, NWG<7:0> and FWG<18:0> are respectively assigned to the division ratio sequence of the DSM through selector one and selector three for control, realizing frequency sweep.

[0086] Figure 11 This is a transient simulation diagram of the phase synchronization output signal of a fractional-division frequency synthesizer. Two identical fractional-division frequency synthesizers are used as a control group for simulation, with the same reference clock REF frequency of 50MHz, a loop division ratio of 140.0416, and an output frequency of 7.002GHz. By using different initial conditions to make the locking process of the control group different, the inconsistency of the output phase is simulated. The figure shows the transient simulation results before and after synchronization. VP1 and VP2 are the signals of the VCO in the control group after passing through the buffer. The phase synchronization control signal SYNC controls the circuit. Before synchronization, it can be seen that the phase difference between VP1 and VP2 is large, and the output clock phase is not synchronized. However, the phase adjustment is completed around 40.6μs, and the phase tracking state is entered. VP1 and VP2 are synchronized, and the synchronization time is less than 20.2μs.

[0087] Figure 12 and Figure 13 These are simulation diagrams of the triangular wave signal output frequency of the fractional frequency divider frequency synthesizer and the triangular wave signal sweep frequency spectrum. The reference clock REF is 50MHz, and the initial loop division ratio is set to 192.1. Under the modulation of the triangular signal, the output frequency of the triangular frequency modulated continuous wave changes as follows: Figure 12As shown, frequency modulation begins 9 μs after locking, and completes a total frequency modulation to 1.25 GHz within 15.1 μs, with a rise rate of 162 MHz / μs and a fall rate of 170 MHz / μs. The output spectrum within the 9.605~10.855 sweep range is shown below. Figure 13 As shown, the swept spectrum result within the 1.25 GHz frequency modulation range is approximately -99 dBc·Hz. -1 .

[0088] Figure 14 and Figure 15 These are simulation diagrams of the sawtooth wave signal output frequency from the fractional-division frequency synthesizer and the frequency sweep spectrum of the sawtooth wave signal. The reference clock REF is 50MHz, and the initial loop division ratio is set to 192.1. Under the action of the sawtooth modulation signal, the output frequency of the sawtooth frequency-modulated continuous wave changes as follows: Figure 14 As shown, frequency modulation also begins at 9μs, with a modulation period of 7.5μs and a total modulation period of 16μs. The rise rate of the 1.25GHz frequency modulation bandwidth is 166 MHz / μs, while the fall rate reaches 710 MHz / μs. The output spectrum is as follows. Figure 15 As shown, the swept frequency spectrum results are in the range of -100 dBc·Hz. -1 It exhibits good linearity with only minor fluctuations.

[0089] The above description is only a preferred embodiment of the present invention. It should be noted that the scope of protection of the present invention should not be limited thereto. Any equivalent substitutions, improvements or modifications that can be made by those skilled in the art without departing from the principle of the present invention should fall within the scope of protection of the present invention.

Claims

1. A fractional-frequency divider frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions, characterized in that, Includes a frequency and phase detector, charge pump I, charge pump II, low-pass filter, voltage-controlled oscillator, buffer I, buffer II, divider chain, IQ undersampling circuit, local oscillator generator, programmable multimode divider, Delta-Sigma modulator (DSM), selector I, selector II, selector III, tracking phase accumulator, numerically controlled oscillator, accumulated phase difference register, atan2 logic circuit, main phase control circuit, phase adjustment circuit, enable control circuit, waveform generator, and serial peripheral interface; The input of the frequency and phase detector is connected to the output of the programmable multimode divider and the external reference clock REF. The output of the frequency and phase detector is connected to the input of charge pump one. The output of charge pump one is connected to the input of a low-pass filter. The input of charge pump two is connected to the output of an enable circuit, and the output of charge pump two is connected to the input of a filter. The output of the low-pass filter is connected to the input of a voltage-controlled oscillator (VCO). The output of the VCO is connected to the input of buffer one. The output of buffer one is connected to the input of the programmable multimode divider and the input of a divider-by-two chain. The output of the divider-by-two chain is connected to the input of buffer two. The output of buffer two is connected to the input of the IQ undersampling circuit and the input of the local oscillator generator. The clock input of the IQ undersampling circuit is connected to the external reference clock REF, and the quadrature output of the IQ undersampling circuit is connected to the quadrature input of the accumulated phase difference register. The quadrature output of the local oscillator generator serves as the I and Q outputs of the fractional-division frequency synthesizer. The input of the programmable multimode divider is connected to the output of the DSM. The output of the programmable multimode divider is connected to one input of the frequency and phase detector, the clock input of the DSM, and one input of the waveform generator. The integer input of the DSM is connected to the output of selector one, and the decimal input of the DSM is connected to the output of selector three. The IQ undersampling circuit, selector two, tracking phase accumulator, phase difference detection circuit, main phase control circuit, and phase adjustment circuit constitute a phase synchronization circuit. The clock input of the phase synchronization circuit is connected to an external reference clock REF, and the control input of the phase synchronization circuit is connected to an external phase synchronization control signal SYNC. The numerically controlled oscillator, the accumulated phase difference register, and the atan2 logic circuit together constitute a phase difference detection circuit. The clock input of the phase difference detection circuit is connected to an external reference clock REF, and the control input of the phase difference detection circuit is connected to an external phase synchronization control signal SYNC. The input terminals of selector three are connected to the waveform generator and the output terminals of selector two, respectively. The control input terminal of selector three is connected to the external phase synchronization control signal SYNC, and the output terminal of selector three is connected to the decimal input terminal of the DSM. The input terminals of selector two are connected to the serial peripheral interface and the output terminal of the phase adjustment circuit, respectively. The control input terminal of selector two is connected to the control output terminal of the phase adjustment circuit, and the output terminal of selector two is connected to one input terminal of selector three. The input terminals of selector one are connected to the serial peripheral interface and the output terminal of the waveform generator, respectively. The control input terminal of selector one is connected to the external chirp control signal CH, and the output terminal of selector one is connected to the integer input terminal of the DSM. Selector one, the waveform generator, the serial peripheral interface, and the enable control circuit constitute a linear frequency modulated continuous wave circuit. The clock input terminal of the linear frequency modulated continuous wave circuit is connected to the output terminal of the programmable multimode divider, and the control input terminals of the linear frequency modulated continuous wave circuit are connected to the external chirp control signal CH and the external mode control signal MODE, respectively. The input terminal of the serial peripheral interface is connected to the external data input signal SPI.

2. A fractional-frequency divider frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions as described in claim 1, characterized in that, Before phase synchronization of most fractional frequency dividers, all fractional frequency dividers need to be locked and share a common reference clock with the same frequency and phase. Before each fractional frequency divider begins phase synchronization, the external phase synchronization control signal SYNC, the external chirp control signal CH, and the external chirp mode control signal MODE of each fractional frequency divider are all low. The phase synchronization circuit and the linear frequency modulation continuous wave circuit of each fractional frequency divider do not generate phase adjustment signals or continuous frequency modulation signals. At this time, selector one selects the serial peripheral under the control of the external control signal CH. The 8-bit output value of the interface is used as the 8-bit integer input of the DSM. At this time, selector two, under the control of the control signal output by the phase adjustment circuit, selects the 19-bit output value of the serial peripheral interface as a 19-bit input of selector three. Selector three, under the control of the external phase synchronization control signal SYNC, selects the 19-bit input value of selector two as the 19-bit decimal input of the DSM. The DSM operates under the drive of a frequency divider clock. The frequency division ratio sequence output by the DSM controls the programmable multi-mode frequency divider to achieve fractional frequency division, thus achieving a locked state. When each fractional frequency divider synthesizer begins phase synchronization, the external phase synchronization... When the SYNC control signal transitions from low to high, the phase synchronization circuit operates under the reference clock. The tracking phase accumulator uses the output value of selector two before synchronization as input to generate a 19-bit tracking phase value. The numerically controlled oscillator generates two quadrature 16-bit output values ​​from the 19-bit tracking phase value. The IQ undersampling circuit, driven by the reference clock, undersamples the two input signals and outputs two down-frequency quadrature signals. The accumulated phase difference register cross-multiplies the two pairs of quadrature signals and then adds or subtracts them, accumulating the resulting sine and cosine phase difference values ​​to a certain extent. Finally, it outputs two 30-bit accumulated phase difference values. The logic circuit generates a 19-bit phase difference value by arctangenting the two 30-bit cumulative phase difference values. The main phase control circuit generates the main phase value from the 19-bit input value from the serial peripheral interface. The phase adjustment circuit generates the phase adjustment value by performing logical operations based on the tracking phase value, phase difference value, and main phase value. The phase adjustment value will be continuously assigned to the DSM through selector two and selector three within N reference clock cycles, and the DSM output frequency division ratio sequence data will be input to the programmable multi-mode frequency divider in real time, thereby controlling the phase of the output signal of the fractional frequency divider synthesizer and realizing the phase synchronization of the output signals of multiple fractional frequency dividers synthesizers.

3. A fractional-frequency divider frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions as described in claim 1, characterized in that, Before chirping the fractional-order frequency synthesizer, all components of the fractional-order frequency synthesizer must be in a locked state. The fractional-order frequency synthesizer uses its internal programmable multimode divider output DIV as the clock for both frequency and phase synchronization. Before chirping, the external control signals SYNC, CH, and MODE are all low. At this time, the phase synchronization circuit and linear frequency modulation continuous wave circuit of the fractional-order frequency synthesizer do not generate phase adjustment signals and continuous frequency modulation signals. The output of the serial peripheral interface is input to the DSM via selector 1, selector 2, and selector 3. The division ratio sequence data output by the DSM is then input to the programmable multimode divider. The modulus divider controls the fractional frequency division function. When the fractional frequency divider synthesizer starts chirping, the external control signal SYNC remains low, while the external chirp control signal CH transitions from low to high. At this time, the CH signal controls the linear frequency modulation (LFM) continuous wave circuit. The external chirp mode control signal MODE selects the mode and controls the LFM continuous wave circuit to generate either a sawtooth or triangular wave signal. When the external chirp control signal CH transitions from low to high, and the external chirp mode control signal MODE remains low, the LFM continuous wave circuit produces a sawtooth wave. In waveform mode, selector one selects the 8-bit value output from the waveform generator and inputs it to the DSM, while selector three selects the 19-bit value output from the waveform generator and inputs it to the DSM. The dynamic change of the decimal value is the frequency step, and the sum of the integer and decimal values ​​increases with the frequency step. The DSM outputs a division ratio sequence based on the integer and decimal values ​​to control the programmable multi-mode divider to achieve frequency sweep. When the chirp frequency reaches its peak, the control signal E output by the waveform generator changes from low to high to control the enable control circuit to output an enable signal. The enable control signal output by the enable control circuit controls the charge pump, which has the same structure as the charge pump. Pump 2 outputs additional current. The additional current injected by charge pump 2 accelerates the descent process of the sawtooth wave. After the frequency reaches its peak, the integer and decimal values ​​immediately return to their initial values. When the external chirp mode control signal MODE changes from low to high, the linear frequency modulated continuous wave circuit is in triangular wave mode. The sum of the integer and decimal values ​​increases with the frequency step by step to the peak value and then decreases back to the initial value. The control signal E output by the waveform generator has no effect on the enable circuit, and the enable control circuit has no high-level enable signal output. When in chirp mode, the I and Q signals output by the fractional frequency divider frequency synthesizer are linear continuous frequency modulated waves.

4. A fractional-frequency divider frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions as described in claim 1, characterized in that, After the external phase synchronization control signal SYNC changes from low to high, the phase difference detection circuit, with the help of a numerically controlled oscillator providing a quadrature reference signal, performs phase difference calculation, accumulation, and arctangent conversion on the tracking phase signal and the undersampled signal, and outputs the phase difference value A<18:0>. The numerically controlled oscillator outputs a quadrature signal as a reference phase signal based on the tracking phase signal input by the tracking phase accumulator. The IQ undersampled circuit down-converts the high-frequency signal output by buffer two to facilitate phase detection of the high-frequency clock signal. The accumulated phase difference register performs mathematical operations on the two sets of quadrature signals and then accumulates the resulting sine and cosine phase difference values ​​to filter out high-frequency signals. The atan2 logic circuit performs an arctangent conversion on the accumulated sine and cosine phase difference values ​​to obtain the accurate phase difference signal A<18:0>. After outputting the phase difference signal, the phase difference detection circuit restarts the calculation, and the output value remains unchanged until the next accumulated value arrives.

5. A fractional-frequency divider frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions as described in claim 1, characterized in that, The main phase control circuit outputs the main phase signal M<18:0> according to the input external signal under the control of the external phase synchronization control signal SYNC. Under the control of SYNC, the main phase signal M<18:0> values ​​of the phase synchronization circuit of the fractional frequency divider synthesizer at the same time are the same. By adjusting the main phase control circuit of the fractional frequency divider synthesizer, global synchronization is achieved in multiple fractional frequency dividers synthesizers.

6. A fractional-frequency divider frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions as described in claim 1, characterized in that, The phase adjustment circuit determines whether the phase difference value A<18:0> has been accumulated after the external phase synchronization control signal SYNC changes from low to high. After the accumulation is complete, it will output FADJ<18:0> with a length of N clock cycles starting from the first rising edge of the reference clock signal REF. Its value is equivalent to distributing the total phase difference adjustment amount within N cycles. After the phase adjustment cycle ends, its output value returns to zero. During the phase adjustment cycle, the output control signal P is at a high level.

7. A fractional-frequency divider frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions according to claim 1, characterized in that, After the internal control signal P changes from low to high and the output value of the phase adjustment circuit is not zero, selector 2 outputs F1<18:0>+FADJ<18:0> for N clock cycles to DSM, i.e., F2<18:0>, F3<18:0> remains at its original value F1<18:0>, and F2<18:0> returns to its original value F1<18:0> after the phase adjustment cycle ends.

8. A fractional-frequency divider frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions according to claim 1, characterized in that, After the external chirp control signal CH transitions from low to high, the waveform generator starts outputting varying small values ​​FWG<18:0> and integer values ​​NWG<8:0> at the first rising edge of the frequency divider clock signal DIV. Under the control of the external chirp mode control signal MODE, it outputs a sawtooth or triangular changing digital signal. When the output frequency in the sawtooth chirp mode reaches its peak, it outputs a short-term high-level enable signal E and provides the frequency divider clock signal FK as a reference clock for the enable circuit. When the enable control signal E changes from low to high, and the external chirp mode control signal MODE is low, the enable control circuit outputs two identical high-level signals to control the charge pump to inject additional current. The waveform generator controls the fractional frequency synthesizer to output triangular and sawtooth linear frequency modulated continuous wave signals, and the frequency can be maintained at any frequency within the frequency range during frequency modulation.

9. A fractional-frequency divider frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions as described in claim 1, characterized in that, The phase synchronization circuit and the linear frequency modulated continuous wave (FMCW) circuit described above can be applied to the same system simultaneously, such as an integrated communication and sensing system. In communication, the phase synchronization circuit can keep the phase consistent in multi-antenna technology, resulting in better beamforming. When sensing a target object, the linear frequency modulated continuous wave can quickly detect the target's distance and speed. Furthermore, given the functional similarity of some modules in the synchronization loop and FMCW loop, such as the frequency and phase detector, charge pump, and voltage-controlled oscillator, these modules can be shared to significantly reduce the system's power consumption and area cost.

10. A fractional-frequency divider frequency synthesizer with output signal phase synchronization and frequency-modulated continuous wave functions according to claim 1, characterized in that, In a frequency-modulated continuous wave radar system, the phase synchronization circuit and the linear frequency-modulated continuous wave circuit mentioned above can perform initial phase synchronization first and then perform linear frequency modulation.

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