FPGA message flow scheduling method and system based on low-difference sequence
By adopting an FPGA message flow scheduling method based on low-difference sequences, the external memory bottleneck and time uniformity issues are resolved, achieving efficient and low-latency multi-message flow scheduling, and improving the performance and scalability of high-speed network testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING XINERTEL TECH CO LTD
- Filing Date
- 2026-01-27
- Publication Date
- 2026-04-14
AI Technical Summary
Existing FPGA-based message flow scheduling schemes suffer from external memory bandwidth bottlenecks, high configuration latency, poor flexibility, and difficulty in balancing message transmission time uniformity and hardware resource overhead, resulting in limited performance in high-speed network testing.
An FPGA message flow scheduling method based on low-difference sequences is adopted. By mapping the frame rate ratio to the unsigned integer space, a uniformly distributed sequence value is generated using a low-difference sequence generator, and the identifier of the message flow to be sent is determined by interval matching search. This achieves dynamic proportional scheduling with high uniformity and low latency, eliminating the dependence on external high-speed memory.
It achieves dynamic proportional scheduling of multiple packet streams with high uniformity and low latency without relying on external memory, reducing hardware resource consumption and scheduling latency, improving test accuracy and system scalability, and meeting the performance requirements of high-speed network testing.
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Figure CN121864262A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of high-speed network communication and testing, and in particular to an FPGA message flow scheduling method and system based on low-difference sequences. Background Technology
[0002] As Ethernet technology evolves towards 400G, 800G, and even 1.6T speeds, the performance testing of network devices and communication systems faces unprecedented challenges. In high-speed network testing scenarios, generating multiple packet streams with precise frame rate ratios is fundamental to evaluating key performance aspects such as device throughput, latency, and congestion control. Field-programmable gate arrays (FPGAs) are widely used for high-performance packet generation and scheduling due to their parallel processing capabilities and programmable characteristics.
[0003] Currently, most FPGA-based packet flow scheduling schemes rely on external high-capacity memory (such as DDR4 SDRAM) to pre-store packet sequences and control the flow ratio through sequential reading. This approach has significant drawbacks: firstly, the access bandwidth of the external memory becomes a system performance bottleneck, making it difficult to meet the line-rate requirements for packet generation throughput at speeds above 800G; secondly, dynamically adjusting the packet flow ratio requires reloading a large amount of sequence data, resulting in high configuration latency and poor flexibility. Furthermore, traditional scheduling methods based on pseudo-random sequences or polling lack uniformity in distribution at the micro-time scale, introducing significant time jitter and affecting test accuracy. In recent years, to improve scheduling performance, the industry has attempted to implement more efficient scheduling logic within FPGAs, such as using hardware pseudo-random number generators or counting-based proportional allocation mechanisms.
[0004] However, while ensuring the accuracy of multi-stream ratios, these methods often struggle to maintain the uniformity of message transmission time, and they also incur significant hardware resource overhead and limited scalability when supporting a large number of dynamic streams. Summary of the Invention
[0005] In view of this, this application provides an FPGA message stream scheduling method and system based on low-difference sequences, which realizes dynamic proportional scheduling of multiple message streams with high uniformity and low latency without relying on external high-speed memory. At the same time, it eliminates the limitation of external memory bandwidth bottleneck on high-speed network test performance, solves the problems of slow configuration response and uneven message time distribution in traditional solutions, and the shortcomings of existing on-chip scheduling methods in terms of dynamic scalability and proportional accuracy co-optimization.
[0006] This application provides an FPGA message flow scheduling method and system based on low-difference sequences, which adopts the following technical solution: An FPGA message flow scheduling method based on low-difference sequences includes: In response to the multi-message stream generation command, obtain the frame rate ratio and integer mapping bit width of each message stream; The frame rate ratio is mapped to the unsigned integer space corresponding to the integer mapping bit width, and the right boundary value of the interval and the packet stream identifier of each packet stream in the unsigned integer space are determined. Based on the right boundary value of the interval and the corresponding message stream identifier, a configuration tuple is constructed and sent to the FPGA for storage. In response to the message sending request, an FPGA-based low-difference sequence generator generates the current sequence value, which is uniformly distributed in the unsigned integer space. Based on the current sequence value and the configuration tuple, the identifier of the current message stream to be sent is determined by range matching search. Generate a message based on the current message stream identifier to be sent.
[0007] By adopting the above technical solution, the frame rate ratio of multiple message streams is mapped to a continuous interval partition in the unsigned integer space. A low-difference sequence generator produces strictly uniformly distributed sequence values, and deterministic scheduling with a high degree of consistency with the theoretical ratio is achieved through efficient interval matching search. The complex proportional scheduling problem is transformed into FPGA-friendly integer comparison and search operations. While ensuring extremely low scheduling jitter and high precision, it significantly reduces logic resource consumption and scheduling latency, achieving an optimal balance between hardware resource consumption, scheduling fairness, and real-time performance. It also enables highly uniform and low-latency dynamic proportional scheduling of multiple message streams without relying on external high-speed memory, while eliminating the limitation of external storage bandwidth bottlenecks on high-speed network testing performance.
[0008] Preferably, the frame rate ratio is mapped to an unsigned integer space corresponding to the integer mapping bit width, and the right boundary value of each packet stream in the unsigned integer space and the packet stream identifier are determined, including: Based on the frame rate ratio, calculate the proportion of each packet stream in the total frame rate; Based on the proportion and integer mapping bit width, the corresponding unsigned integer space is divided into multiple continuous numerical intervals according to the proportion. Each message stream corresponds to a numerical interval, and the width of each numerical interval is proportional to the proportion of the corresponding message stream. The end value of the interval allocated to each message flow is determined as the right boundary value of the interval of that message flow, and a predefined unique number is used as the message flow identifier of that message flow.
[0009] By adopting the above technical solution, and leveraging the deterministic characteristics of ratio-interval mapping and low-difference sequences, dual uniformity in both statistical and temporal distributions of the multi-message stream scheduling ratio is ensured. Parallelizable, low-latency hardware lookup logic and on-chip generation of scheduling sequences eliminate the dependence on external high-speed memory, overcoming the limitations of traditional solutions on scheduling rate and concurrency scale caused by storage bandwidth bottlenecks. This achieves high-throughput, low-jitter multi-stream ratio scheduling at the pure hardware logic level.
[0010] Preferably, a configuration tuple is constructed based on the right boundary value of the interval and the corresponding message flow identifier, including: The right boundary value of the interval is combined with its corresponding message flow identifier to obtain the configuration record; The configuration records of each message stream are sorted in ascending order according to the right boundary value of the interval to obtain the configuration tuple sequence.
[0011] By adopting the above technical solution, the configuration records of each message stream are arranged in ascending order according to the right boundary value of the interval, and an ordered sequence of configuration tuples is constructed. This allows for both sequential search to achieve minimal hardware overhead and binary search to cope with scenarios with a large number of message streams. It provides a flexible design choice between hardware implementation complexity and search performance, ensuring the simplicity and efficiency of the scheduling decision process. This enables the FPGA to quickly determine the identifier of the current message stream to be sent within each clock cycle.
[0012] Preferably, an FPGA-based low-discrepancy sequence generator generates current sequence values uniformly distributed in the unsigned integer space, including: The FPGA-based low-difference sequence generator calculates the next sequence value, which is uniformly distributed in the unsigned integer space, based on the pre-stored direction number and the previously generated sequence value, using a preset low-difference sequence recursion algorithm. Constrain the next sequence value within the valid range of the unsigned integer space, and use the constrained next sequence value as the current sequence value.
[0013] By adopting the above technical solution, and taking advantage of the predictable and highly uniform distribution of low-difference sequences in deterministic recursion, decision points can be generated in real time at each scheduling moment through recursive calculation and simple bit constraint operations, without the need to store a large pre-computed sequence. This greatly saves on-chip storage resources while fundamentally ensuring the accuracy of the scheduling ratio of multiple message streams on long-term time scales and the uniformity of distribution on short-term time scales.
[0014] The preferred, pre-defined low-discrepancy sequence recursion algorithm is as follows: ; in, The sequence value generated previously. For the next sequence value, Let c be the number of directions to be pre-stored, and c be the number of trailing zeros in the binary representation of n. This indicates a bitwise XOR operation.
[0015] By adopting the above technical solution, the sequence can be rapidly recursed by calculating the number of consecutive zeros at the tail and performing a simple bitwise XOR operation. Its hardware implementation only requires a counter and a small amount of combinational logic, resulting in extremely low resource consumption.
[0016] Preferably, based on the current sequence value and the configuration tuple, the identifier of the current message stream to be sent is determined by range matching lookup, including: The current sequence value is compared with the right boundary value of each message stream in turn using a binary search algorithm to obtain the sequence comparison result. Based on the sequence comparison results, the right boundary value of the minimum interval is obtained; Use the packet stream identifier corresponding to the determined minimum interval right boundary value as the current packet stream identifier to be sent.
[0017] By adopting the above technical solution, the binary search algorithm is used to perform fast interval matching in ordered configuration tuples, reducing the search time complexity from linear to logarithmic. This improves the scheduling decision speed in large-scale message flow scenarios, enabling the FPGA to complete the identifier determination within a constant and extremely short clock cycle, ensuring the real-time performance and determinism of scheduling under high throughput. Simultaneously, the hardware implementation structure of binary search is regular and easily optimized through pipelines in the FPGA, achieving a balance between search performance and hardware efficiency, ensuring that the system maintains high accuracy and low jitter even under high-concurrency flow scheduling.
[0018] Preferably, based on the sequence comparison results, the right boundary value of the minimum interval is obtained, including: Sort all right boundary values of intervals in the configuration tuple that are greater than the current sequence value in ascending order of numerical value to obtain the candidate right boundary sequence; Select the interval right boundary value with the smallest value from the candidate right boundary sequence as the minimum interval right boundary value.
[0019] By adopting the above technical solution, the comparison results are sorted and filtered to lock the minimum boundary greater than the current sequence value, thus ensuring the absolute accuracy and completeness of the interval matching logic.
[0020] An FPGA message stream scheduling system based on low-difference sequences includes: The parameter acquisition module is used to respond to the multi-message stream generation command and obtain the frame rate ratio and integer mapping bit width of each message stream; The mapping configuration module is used to map the frame rate ratio to the unsigned integer space corresponding to the integer mapping bit width, and to determine the right boundary value of the interval and the packet stream identifier of each packet stream in the unsigned integer space; The configuration storage module is used to construct configuration tuples based on the right boundary value of the interval and the corresponding message stream identifier, and send them to the FPGA for storage. The sequence generation module is used to respond to message sending requests. It is an FPGA-based low-difference sequence generator that generates current sequence values that are uniformly distributed in the unsigned integer space. The stream selection module is used to determine the current message stream identifier to be sent by range matching based on the current sequence value and the configuration tuple. The message generation module is used to generate messages based on the identifier of the current message stream to be sent.
[0021] By adopting the above technical solution, a scheduling strategy benchmark is constructed through parameter mapping and configuration. A low-difference sequence generator provides the scheduling decision point with optimal statistical characteristics, and efficient interval matching logic enables rapid flow selection, ultimately driving accurate packet generation. The modules work closely together within the FPGA, achieving end-to-end hardware acceleration and highly deterministic control from proportional configuration to packet transmission, resulting in significant comprehensive advantages in resource consumption, scheduling accuracy, processing latency, and throughput performance.
[0022] An electronic device includes a memory and a processor. The memory stores a computer program, which, when executed by the processor, causes the processor to perform steps of an FPGA message flow scheduling method based on low-difference sequences.
[0023] A computer-readable storage medium having a computer program stored thereon, which, when executed, implements an FPGA message flow scheduling method based on low-difference sequences.
[0024] In summary, this application includes at least one of the following beneficial technical effects: 1. Responding to the multi-message stream generation command, obtain the frame rate ratio and integer mapping bit width of each message stream, map the frame rate ratio to the unsigned integer space corresponding to the integer mapping bit width, and determine the right boundary value of the interval and the message stream identifier of each message stream in the unsigned integer space. Based on the right boundary value of the interval and the corresponding message stream identifier, construct a configuration tuple and send it to the FPGA for storage. Responding to the message sending request, based on the low-difference sequence generator of the FPGA, generate the current sequence value evenly distributed in the unsigned integer space. Based on the current sequence value and the configuration tuple, determine the identifier of the current message stream to be sent through interval matching search. Based on the identifier of the current message stream to be sent, generate the message. By mapping the frame rate ratio of multiple message streams to continuous intervals in the unsigned integer space, and generating highly uniformly distributed scheduling sequences in real time based on an on-chip low-difference sequence generator on the FPGA, combined with an interval matching search mechanism, dynamic proportional scheduling of multiple message streams with high uniformity and low latency is achieved without relying on external high-speed memory. At the same time, it eliminates the limitation of external storage bandwidth bottleneck on high-speed network test performance, solves the problems of slow configuration response and uneven message time distribution in traditional solutions, and the shortcomings of existing on-chip scheduling methods in terms of dynamic scalability and proportional accuracy co-optimization. 2. By constructing an ordered sequence of configuration tuples by arranging the configuration records of each message stream in ascending order according to the right boundary value of the interval, and using efficient algorithms such as binary search for interval matching, the target message stream can be located quickly with logarithmic time complexity. This improves the scheduling decision speed and system scalability in scenarios with large-scale concurrent message streams, ensures the constantness and low jitter of scheduling latency under high throughput requirements, and overcomes the performance degradation problem of traditional linear search methods when the number of streams increases. 3. An FPGA-based low-difference sequence generator uses a pre-defined recursive algorithm to generate highly uniformly distributed sequence values in real time, avoiding the consumption of on-chip storage resources by pre-storing large sequences. Through extremely simple recursive logic, it achieves deterministic and repeatable generation of sequences, ensuring the proportional accuracy of message scheduling in long periods and the uniformity of distribution in short periods, and achieving the optimal balance between hardware resource efficiency and scheduling quality. Attached Figure Description
[0025] Figure 1 This is a flowchart illustrating the steps of an FPGA message flow scheduling method based on low-difference sequences provided in an embodiment of this application.
[0026] Figure 2 This is a comparison chart showing the results of fitting the FPS 1:1:1:1 frame rate ratio between the Sobol sequence and the PRBS sequence using 25,000 samples within 1ms.
[0027] Figure 3This is a comparison chart showing the results of fitting the FPS 4:3:2:1 frame rate ratio between the Sobol sequence and the PRBS sequence using 25,000 samples within 1ms.
[0028] Figure 4 This is a comparison chart showing the results of fitting the FPS12111:11:4:5 frame rate ratio between the Sobol sequence and the PRBS sequence using 25,000 samples within 1ms.
[0029] Figure 5 This is a comparison chart showing the results of fitting the FPS 1:1:1:1 ratio between the Sobol sequence and the PRBS sequence using 25,000,000 samples within 1 second.
[0030] Figure 6 This is a comparison chart showing the results of fitting the FPS 4:3:2:1 frame rate ratio between the Sobol sequence and the PRBS sequence using 25,000,000 samples within 1 second.
[0031] Figure 7 This is a comparison chart showing the results of fitting the FPS12111:11:4:5 frame rate ratio between the Sobol sequence and the PRBS sequence using 25,000,000 samples within 1 second.
[0032] Figure 8 This is a structural block diagram of an FPGA message flow scheduling method based on low-difference sequences provided in an embodiment of this application. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It should be noted that in the optional embodiments of this application, the object information and other related data involved require the permission or consent of the object when the embodiments of this application are applied to specific products or technologies, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. That is to say, if the embodiments of this application involve data related to the object, it needs to be obtained with the authorization and consent of the object, the authorization and consent of the relevant departments, and in compliance with the relevant laws, regulations, and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information requires the consent of the individual. If sensitive information is involved, the separate consent of the information subject is required, and the embodiments also need to be implemented with the authorization and consent of the object. Example 1
[0034] Please see Figure 1 This application provides an FPGA message flow scheduling method based on low-difference sequences, comprising: Step 101: Respond to the multi-message stream generation command and obtain the frame rate ratio and integer mapping bit width of each message stream.
[0035] The multi-message stream generation command is a trigger command that controls the device to generate multiple parallel test messages with a specific rate relationship.
[0036] Frame rate ratio refers to the ratio of the expected frame transmission rates between the various message streams to be generated, and is usually expressed as a set of simplest integer ratios.
[0037] Integer mapping bit width refers to the width of the binary bits used to represent each ratio value when converting the frame rate ratio into a fixed-point or integer control parameter. This bit width determines the control precision of the frame rate ratio and the hardware resource consumption.
[0038] In this embodiment, in response to the received multi-message stream generation instruction, the identifiers of each specified message stream and their target frame rate relationships are parsed, the rate relationship is normalized to the simplest integer ratio form, and then, according to the system's preset accuracy requirements and hardware resource constraints, the integer field width used to represent the ratio value in the rate control logic, i.e., the integer mapping width, is determined. The frame rate ratio parameter corresponding to each message stream and its allocated integer mapping width are output, so that the abstract frame rate ratio relationship can be quantized into control parameters that can be directly processed by hardware logic.
[0039] Step 102: Map the frame rate ratio to the unsigned integer space corresponding to the integer mapping bit width, and determine the right boundary value of the interval and the packet stream identifier of each packet stream in the unsigned integer space.
[0040] The unsigned integer space is an abstract representation of the range of non-negative integer values defined by the bit width of the integer mapping. For example, when the integer mapping bit width is 32, this space covers all integers from 0x0000_0000 to 0xFFFF_FFFF.
[0041] The right boundary value of an interval refers to the upper limit of the continuous numerical interval divided for each message stream in the unsigned integer space. It is used as a key comparison benchmark in subsequent scheduling decisions based on low-difference sequences to determine which message stream interval the current sequence value falls into.
[0042] A message flow identifier is a number or label assigned to each message flow to be generated to uniquely distinguish different message flows. It is associated with other configuration attributes of the message flow, such as destination address and payload template.
[0043] Preferably, step 102 includes the following sub-steps: S21. Based on the frame rate ratio, calculate the proportion of each packet stream in the total frame rate.
[0044] In this embodiment, the frame rate ratio (a set of simplest integer ratios) is normalized. Specifically, the ratio value of each packet stream is divided by the sum of the ratio values of all packet streams to obtain the proportion (i.e., percentage) of each packet stream in the theoretical total number of transmitted frames.
[0045] For example, for three message streams with a rate ratio of 1:2:1, their proportions are 0.25, 0.5, and 0.25, respectively.
[0046] S22. Based on the proportion and integer mapping bit width, the corresponding unsigned integer space is divided into multiple continuous numerical intervals according to the proportion. Each message stream corresponds to a numerical interval, and the width of each numerical interval is proportional to the proportion of the corresponding message stream.
[0047] In this embodiment of the application, the total capacity of the unsigned integer space is determined to be 2 based on the integer mapping bit width N. N Based on the proportion of each message flow, the total capacity of the unsigned integer space is allocated proportionally to each message flow, assigning a continuous integer interval to each message flow. The width of the interval allocated to a given message flow (i.e., the number of integers it contains) is equal to its proportion multiplied by 2 of the total capacity. N .
[0048] Preferably, to ensure that all intervals cover the entire space and do not overlap, rounding is required (i.e., rounding down or rounding to the nearest whole number), and the accumulated error is compensated in the last interval.
[0049] For example, in a 32-bit space, for three streams with proportions of 0.25, 0.5, and 0.25, their intervals can be divided into [0x0000_0000, 0x3FFF_FFFF], [0x4000_0000, 0xBFFF_FFFF], and [0xC000_0000, 0xFFFF_FFFF], respectively.
[0050] S23. Determine the end value of the interval allocated to each message stream as the right boundary value of the interval of the message stream, and use the predefined unique number as the message stream identifier of the message stream.
[0051] In this embodiment, after the interval division is completed, the end value (maximum value) of the numerical interval corresponding to each message stream is recorded as the right boundary value of the interval for that message stream. Simultaneously, each message stream is assigned a predefined unique identifier. This information is organized in the form of information tuples and stored in the on-chip memory of the FPGA for efficient access in subsequent steps.
[0052] Through the above mapping and allocation, the complex dynamic frame rate ratio control problem is transformed into a deterministic model that divides and compares intervals within a fixed integer space. This not only simplifies the control logic, but also enables dynamic speed adjustment by simply updating the interval boundaries, thus responding to the needs of simplified configuration and reduced latency.
[0053] Preferably, taking three message streams A, B, and C with a desired frame rate ratio of 1:2:1 and an integer mapping bit width of 32 bits as an example: Calculations show that the proportions of message flows A, B, and C are 25% (0.25), 50% (0.5), and 25% (0.25), respectively.
[0054] In a 32-bit unsigned integer space (total capacity 2...) 32 In the sequence (4,294,967,296), the packets are divided proportionally: packet A is in the range [0, 1,073,741,823] (hexadecimal: 0x00000000 to 0x3FFFFFFF), packet B is in the range [1,073,741,824, 3,221,225,471] (0x40000000 to 0xBFFFFFFF), and packet C is in the range [3,221,225,472, 4,294,967,295] (0xC0000000 to 0xFFFFFFFF). This division ensures that the width of each range is proportional to its proportion and completely covers the entire 32-bit space.
[0055] Therefore, the right boundary value of the interval of message flow A is determined to be 1,073,741,823 (0x3FFFFFFF), and its message flow identifier is set to 0.
[0056] The right boundary value of the interval of message flow B is determined to be 3,221,225,471 (0xBFFFFFFF), and its message flow identifier is set to 1.
[0057] The right boundary value of the interval of message flow C is determined to be 4,294,967,295 (0xFFFFFFFF), and its message flow identifier is set to 2.
[0058] Ultimately, this information is organized into an information tuple {message stream identifier, right boundary value of interval}, or it can be represented as {strm id ,R iThe values {0, 0x3FFFFFFF}, {1, 0xBFFFFFFF}, and {2, 0xFFFFFFFF} are stored sequentially in the FPGA's on-chip Block RAM (BRAM) for rapid lookup and matching in subsequent stream selection steps based on low-difference sequences. This achieves extreme simplification of configuration information and dimensionality reduction of control logic by solidifying the frame rate ratio relationship into precise numerical range boundaries.
[0059] Preferably, the configuration tuple sequence is stored sequentially in the dual-port Block RAM (BRAM) on the FPGA chip, and its storage format can be represented as follows (taking three streams as an example), where the valid entries store the actual {strm id , R i Invalid entries can be filled with preset values (such as {0, 2}). 32-1 To simplify boundary handling: Table 1. Schematic diagram and explanation of FPGA internal storage address data illustrate 0 <![CDATA[{strm ida ,R a }]]> efficient 1 <![CDATA[{strm idb ,R b }]]> efficient 2 <![CDATA[{strm idc ,R c }]]> efficient 3 <![CDATA[{0,2 32-1 }]]> invalid … <![CDATA[{0,2 32-1 }]]> invalid In this embodiment, by combining the characteristics of dual-port BRAM, multiple comparison elements can be read in parallel efficiently during the binary search process, reducing the number of required BRAM access ports by about half, thereby further optimizing hardware resource utilization.
[0060] Step 103: Based on the right boundary value of the interval and the corresponding message flow identifier, construct the configuration tuple and send it to the FPGA for storage.
[0061] A configuration tuple is a data unit that combines a message flow identifier with the corresponding right boundary value of the interval. It is used to fully define the scheduling attributes and selection criteria of a message flow.
[0062] FPGA storage specifically refers to writing configuration tuple data into the on-chip storage resources inside a Field Programmable Gate Array (FPGA) chip to achieve high-speed, low-latency access.
[0063] Preferably, step 103 includes the following sub-steps: S31. Combine the right boundary value of the interval with its corresponding message flow identifier to obtain the configuration record.
[0064] In this embodiment of the application, for each message flow, its unique message flow identifier is paired with its calculated right boundary value of the interval to form a structured configuration record.
[0065] It should be noted that the configuration record is represented as a fixed-length data unit in the data structure, which ensures that the downstream scheduling logic can obtain both identity recognition and decision boundary information based on a single configuration record.
[0066] Preferably, three message flows A, B, and C are used, and their determined message flow identifiers (strm) are used. id ) and the right boundary value of the interval (R) i For example: The message flow identifier for message flow A is 0, and the right boundary value of the interval is 0x3FFFFFFF.
[0067] The message flow identifier for message flow B is 1, and the right boundary value of the interval is 0xBFFFFFFF.
[0068] The message flow identifier for message flow C is 2, and the right boundary value of the interval is 0xFFFFFFFF.
[0069] The configuration record combination method is: {strm id , R i In practical implementation, the format of storing the right boundary value in the high bits and the message stream identifier in the low bits can be adopted, or vice versa. For example, in a 64-bit data unit, the right boundary value (0x3FFFFFFF) can be stored in the high 32 bits, and the message stream identifier (0x00) can be stored in the low 8 bits, combined to form a complete configuration record. This configuration record will serve as the basic operation unit for subsequent FPGA lookup logic.
[0070] S32. Sort the configuration records of each message stream in ascending order according to the right boundary value of the interval to obtain the configuration tuple sequence.
[0071] In this embodiment, all generated configuration records are sorted in ascending order based on the right boundary values of their included intervals, resulting in an ordered sequence of configuration tuples. The physical storage order of this sequence is consistent with the natural order of intervals in the unsigned integer space. All information required for scheduling decisions is resided on-chip, avoiding the bandwidth bottlenecks and access latency caused by frequent access to external large-capacity memory (such as DDR4) in traditional solutions. This directly overcomes the system performance bottleneck, ensures the locality and determinism of the access pattern during the search process, and simplifies the implementation complexity of the FPGA's internal search logic.
[0072] Step 104: Response message sending request, based on FPGA low-difference sequence generator, generate current sequence values uniformly distributed in the unsigned integer space.
[0073] A low-discrepancy sequence generator is a hardware logic module implemented in an FPGA that is used to generate pseudo-random number sequences with low discrepancy characteristics in sequence.
[0074] In the embodiments of this application, Sobol sequences are preferably used as the implementation of low-discrepancy sequences, which have the characteristics of low star discrepancy, uniform distribution in subintervals of arbitrary length, and efficient generation through simple XOR recursion.
[0075] Among them, star bias is a key indicator for measuring distribution uniformity, and it is 1 to 2 orders of magnitude lower than that of traditional pseudo-random binary sequences (PRBS). This is demonstrated through actual testing comparisons (such as...). Figures 2-7 As shown in the figure, under the same number of samples and different frame rate ratios (such as 1:1:1:1, 4:3:2:1, 12111:11:4:5), the scheduling output based on Sobol sequence is significantly better than PRBS in terms of time distribution, showing a tighter statistical fitting curve and smaller dispersion, which directly translates into lower message transmission time jitter and higher test accuracy.
[0076] The current sequence value refers to the output value generated by the low-difference sequence generator for this scheduling decision, which is evenly distributed in a predefined unsigned integer space. This value will be used to determine the message stream to be sent.
[0077] Preferably, step 104 includes the following sub-steps: S41. An FPGA-based low-difference sequence generator calculates the next sequence value, which is uniformly distributed in the unsigned integer space, based on the pre-stored direction number and the previously generated sequence value, using a preset low-difference sequence recursion algorithm.
[0078] The orientation number refers to a set of pre-computed parameters used in the generation of low-dissimilarity sequences to control the uniformity of the sequences.
[0079] In this embodiment, the low-difference sequence generator inside the FPGA starts at each time a decision is needed, such as every clock cycle or each time a message transmission request arrives. This generator internally stores optimized direction numbers (denoted as...). (where c is the index), which can be pre-calculated and stored in the FPGA's ROM. The generator calculates the next sequence value based on the previously generated sequence value, combined with the direction number, and finally through a preset recursive algorithm. The preset recursive algorithm utilizes XOR operations and a direction number table to generate a pseudo-random number sequence with highly uniform distribution characteristics along a specified dimension.
[0080] Preferably, the preset low-difference sequence recursion algorithm is as follows: ; in, The sequence value generated previously. For the next sequence value, Let c be the number of directions to be pre-stored, and c be the number of trailing zeros in the binary representation of n. This indicates a bitwise XOR operation.
[0081] Preferably, the number of directions can be implemented in hardware through a simple right-shift operation, which greatly simplifies the internal logic implementation of the FPGA and reduces resource consumption. The following calculation method can be used: ; Where k is the number of bits to right shift in binary.
[0082] It should be noted that the relevant parameters for the number of directions can be referenced from publicly available low-difference sequence direction number libraries, such as the paper published by Joe & Kuo in 2008. In the FPGA implementation, the direction number table is stored in read-only memory (ROM) for fast table lookup. Actual measurements on high-performance FPGAs such as the Xilinx VU29P show that multiple (e.g., 4) sequence values can be output within a single clock cycle, with fewer logic levels on the critical path (e.g., a maximum of 5 levels), and relaxed timing, fully meeting the stringent real-time requirements for scheduling decisions at 400G / 800G and even 1.6T network rates.
[0083] S42. Constrain the next sequence value within the valid range of the unsigned integer space, and use the constrained next sequence value as the current sequence value.
[0084] In this embodiment, since the bit width of the low-difference sequence generator may be consistent with the bit width of the integer mapping (i.e., the bit width of the unsigned integer space), the next sequence value generated by its recursion naturally falls within that space. If there is a potential situation where the bit width is inconsistent (e.g., using an extended bit width within the generator), then it is necessary to perform constraint operations such as truncation or modulo operation on the next sequence value to ensure that its output value strictly falls within the valid range of the specified unsigned integer space. After constraint, the value is determined as the current sequence value used for this stream selection.
[0085] Preferably, the constraint processing specifically includes: if the internal bit width of the sequence generator is greater than the target space bit width, then performing a modulo operation (modulo 2) on the next sequence value. N The value obtained after this constraint processing is determined as the current sequence value used for this scheduling decision. This ensures that each value generated by the low-difference sequence generator strictly falls within the preset unsigned integer space corresponding to the frame rate ratio mapping, thereby ensuring the correctness and consistency of the stream selection logic. (Where N is the integer mapping bit width) or the lower N bits are directly truncated. If the bit widths are consistent, the next sequence value naturally falls within the valid range, requiring no additional operation.
[0086] In other words, by introducing Sobol low-discrepancy sequences into the field of high-speed message scheduling, and through the aforementioned recursive and constraint process, highly uniformly distributed sequence values within a preset integer space are generated in real time at each scheduling moment. Compared to traditional pseudo-random sequences, low-discrepancy sequences exhibit superior uniformity in statistical characteristics, ensuring that the generated sequence values display excellent distribution characteristics on both macroscopic and microscopic time scales. By directly impacting the source of scheduling decisions, this fundamentally guarantees the proportional accuracy of multiple message flows over long-term statistics and the uniformity of transmission within short time intervals, thereby reducing message transmission jitter and improving the accuracy and reliability of network testing. Furthermore, this generator requires only a simple XOR chain and minimal storage, resulting in efficient hardware implementation with low resource consumption. This aligns with the parallel processing characteristics of FPGAs and meets the real-time requirements of high-speed scenarios.
[0087] Step 105: Based on the current sequence value and the configuration tuple, determine the identifier of the current message stream to be sent by range matching.
[0088] In this embodiment, the current sequence value is used as a lookup key to match the sequence of configuration tuples stored in the FPGA and sorted in ascending order by the right boundary value of the interval, in order to determine the message stream to be sent this time.
[0089] Preferably, step 105 includes the following sub-steps: S51. Using a binary search algorithm, the current sequence value is compared sequentially with the right boundary value of each message stream interval to obtain the sequence comparison result.
[0090] In this embodiment, a binary search algorithm is used to map the random index generated by the low-difference sequence to a preset frame rate ratio range in real time and accurately, thereby completing the conversion from uniform random numbers to deterministic ratio stream scheduling at the hardware level.
[0091] To improve search efficiency and meet the needs of high-speed scenarios, a binary search algorithm is used to search in the configuration tuple sequence: starting from the configuration tuple in the middle of the sequence, the right boundary value of the stored interval is compared with the current sequence value. If the current sequence value is less than or equal to the right boundary value of the interval, the search continues in the left half of the sequence; otherwise, the search continues in the right half.
[0092] Preferably, the binary search algorithm is used in an iterative process. Each comparison will narrow the search range until a boundary value that meets the conditions is found or the search is determined to have failed, thereby reducing the search time complexity from O(N) to O(log N), where N is the number of message streams.
[0093] S52. Based on the sequence comparison results, obtain the right boundary value of the minimum interval.
[0094] In this embodiment of the application, the goal of binary search is to find the first element in the configuration tuple sequence whose right boundary value of the interval is greater than or equal to the current sequence value. Then, the right boundary value is the smallest right boundary value of the interval that covers the current sequence value.
[0095] Preferably, step S52 further includes the following sub-steps: S521. Sort all right boundary values of intervals greater than the current sequence value in the configuration tuple in ascending order of numerical value to obtain the candidate right boundary sequence.
[0096] In fact, since the configuration tuple sequence itself is stored in ascending order of right boundary values, the binary search algorithm, through comparison and branching during operation, is essentially locating the minimum element in a candidate set, which contains all right boundary values greater than the current sequence value.
[0097] S522. Select the interval right boundary value with the smallest value from the candidate right boundary sequence as the minimum interval right boundary value.
[0098] In this embodiment of the application, the element finally located by the binary search algorithm has its stored right boundary value as the minimum value in the candidate right boundary sequence, and this minimum value is used as the search result.
[0099] S53. Use the message stream identifier corresponding to the determined right boundary value of the minimum interval as the current message stream identifier to be sent.
[0100] In this embodiment, after finding the right boundary value of the minimum interval, the matching message stream identifier is extracted from the configuration tuple storing the right boundary value. This identifier is the message stream number that should be sent at this moment, determined based on the current sequence value and the preset frame rate ratio.
[0101] This means that even in scenarios with large-scale concurrent message streams, FPGAs can determine the stream identifier within a constant and extremely short number of clock cycles, directly supporting the system's line-rate processing capabilities in high-speed networks such as 800G and even 1.6T, which is key to overcoming performance bottlenecks. At the same time, the logical structure rules of binary search are easily optimized in FPGAs through pipeline technology, achieving an optimal balance between search speed, hardware resource utilization, and scheduling determinism. This ensures that the system maintains extremely low scheduling jitter and extremely high proportional accuracy even under high concurrency and high throughput requirements.
[0102] Step 106: Generate a message based on the current message stream identifier to be sent.
[0103] In this embodiment, the identifier of the current message stream to be sent is used as an index or addressing basis to access the message stream information table pre-stored or configured in real time in the FPGA. This retrieves the message stream information required to generate a complete frame of message data for that stream. Then, the message assembly engine within the FPGA generates compliant complete message data according to a preset protocol format based on this information and outputs it to the physical layer interface or transmission queue, ready for transmission. By combining precise stream selection with efficient message assembly, compliant and testable network traffic can be generated while meeting complex frame rate ratio requirements. The entire process is completed entirely within the FPGA chip, eliminating the need for continuous bandwidth supply from external large-capacity memory. This fundamentally eliminates the performance bottleneck of traditional solutions, achieving high uniformity, low latency, and dynamically adjustable multi-message stream generation.
[0104] Preferably, the message flow information includes, but is not limited to, the destination media access control address, the source media access control address, the Internet Protocol address, the port number, the protocol type, the payload template, and the message length.
[0105] The default protocol format can be Ethernet frame format, and no specific limitation is made here.
[0106] More preferably, when the test scenario requires dynamic adjustment of the frame rate ratio of each message stream, the embodiments of this application support flexible and rapid rate reconfiguration without downtime or interruption of existing message transmission. Specifically, this includes: In response to the rate adjustment command issued by the host computer, the adjusted frame rate ratio and integer mapping bit width of each message stream are reacquired. Based on the adjusted frame rate ratio, the interval mapping and partitioning process in step 102 above is re-executed to calculate the right boundary value of the interval corresponding to each message stream in the new unsigned integer space. Based on the newly determined right boundary value of the interval and its corresponding message flow identifier, construct a new sequence of configuration tuples; The new configuration tuple sequence is sent to the FPGA through the configuration interface to overwrite or update the original configuration tuple stored on the FPGA, thus completing the dynamic switching of the scheduling strategy.
[0107] During this process, the low-difference sequence generator inside the FPGA runs continuously, and the generated sequence values are immediately matched and searched based on the updated interval boundaries, thereby achieving a smooth transition and instantaneous switching of the scheduling ratio. This avoids the delay introduced by the need to pre-store and load a large amount of message sequence data in traditional solutions, shortens the response time of rate adjustment to the microsecond level, and improves the flexibility and automation of the test system. It is especially suitable for high-order test scenarios that require real-time simulation of dynamic changes in network traffic, adaptive load testing, or fault recovery verification.
[0108] The implementation principle of this application embodiment is as follows: By mapping the expected frame rate ratio of each message stream to a unified unsigned integer space and allocating continuous numerical intervals, a configuration tuple consisting of the right boundary of the interval and the stream identifier is constructed. When a message needs to be sent, a low-difference sequence generator implemented inside the FPGA generates a sequence value uniformly distributed in this integer space. Using this sequence value as an index, an efficient binary search algorithm is used to match the interval with the configuration tuple to quickly determine the identifier of the message stream to be sent. Finally, a specific message is generated and sent based on this identifier. By transforming the complex dynamic frame rate ratio control problem into a hardware search problem based on deterministic mathematical mapping and uniform sequence sampling, high-precision, low-jitter, and highly flexible high-speed multi-stream message generation is achieved while overcoming the limitations of external memory bandwidth. This solves the problems of slow configuration response and uneven message time distribution in traditional schemes, as well as the shortcomings of existing on-chip scheduling methods in terms of dynamic scalability and proportional accuracy optimization. Example 2
[0109] Please see Figure 2 This application provides an FPGA message flow scheduling system based on low-difference sequences, comprising: The parameter acquisition module 201 is used to respond to the multi-message stream generation command and acquire the frame rate ratio and integer mapping bit width of each message stream.
[0110] The mapping configuration module 202 is used to map the frame rate ratio to the unsigned integer space corresponding to the integer mapping bit width, and to determine the right boundary value of the interval and the packet stream identifier of each packet stream in the unsigned integer space.
[0111] The configuration storage module 203 is used to construct a configuration tuple based on the right boundary value of the interval and the corresponding message stream identifier, and send it to the FPGA for storage.
[0112] The sequence generation module 204 is used to respond to message sending requests. It is an FPGA-based low-difference sequence generator that generates current sequence values that are uniformly distributed in the unsigned integer space.
[0113] The stream selection module 205 is used to determine the current message stream identifier to be sent by range matching based on the current sequence value and the configuration tuple.
[0114] The message generation module 206 is used to generate messages based on the identifier of the current message stream to be sent.
[0115] In this embodiment, the sequence generation module 204 is specifically implemented as a low-difference sequence generator on the FPGA chip, such as a Sobol sequence, and the flow selection module 205 is specifically implemented as a hardware search logic based on a binary search algorithm. The two work together to complete high-speed and uniform flow scheduling decisions by using the configuration tuples stored in the on-chip Block RAM in the configuration storage module 203, thereby achieving the beneficial effects described in Embodiment 1.
[0116] Since the above is a system corresponding to a low-difference sequence-based FPGA message flow scheduling method, its implementation principle is the same as that of a low-difference sequence-based FPGA message flow scheduling method. For the sake of convenience and brevity, those skilled in the art can clearly understand that the specific working process of the system and modules described above can be referred to the corresponding process in the aforementioned method embodiments, and will not be repeated here. Example 3
[0117] An electronic device according to an embodiment of the present invention includes: a memory and a processor, wherein the memory stores a computer program; when the computer program is executed by the processor, the processor performs an FPGA message flow scheduling method based on low-difference sequences as described in any of the above embodiments.
[0118] The memory can be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. The memory has storage space for program code used to perform any of the method steps described above. For example, the storage space for program code may include individual program codes for implementing the various steps in the methods described above. This program code can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, compact discs (CDs), memory cards, or floppy disks. The program code may be compressed, for example, in a suitable form. When run by a computing processing device, this code causes the computing processing device to perform the various steps in the methods described above. Example 4
[0119] This invention provides a computer-readable storage medium storing a computer program thereon, which, when executed, implements an FPGA message flow scheduling method based on low-difference sequences as described in any embodiment of this application.
[0120] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0121] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units through some interfaces, and may be electrical, mechanical, or other forms.
[0122] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0123] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0124] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0125] It should be noted that the terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this disclosure.
[0126] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article, unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.
[0127] The embodiments described in this specific implementation are preferred embodiments of this application and are not intended to limit the scope of protection of this application. Identical components are represented by the same reference numerals. Therefore, all equivalent changes made to the structure, shape, and principle of this application should be included within the scope of protection of this application.
Claims
1. A method for scheduling FPGA message streams based on low-difference sequences, characterized in that, include: In response to the multi-message stream generation command, obtain the frame rate ratio and integer mapping bit width of each message stream; The frame rate ratio is mapped to an unsigned integer space corresponding to the integer mapping bit width, and the right boundary value of the interval and the packet stream identifier of each packet stream in the unsigned integer space are determined. Based on the right boundary value of the interval and the corresponding message stream identifier, a configuration tuple is constructed and sent to the FPGA for storage. In response to the message sending request, a low-difference sequence generator based on FPGA generates the current sequence value that is uniformly distributed in the unsigned integer space; Based on the current sequence value and the configuration tuple, the identifier of the current message stream to be sent is determined by range matching search. A message is generated based on the current message stream identifier to be sent.
2. The FPGA message flow scheduling method based on low-difference sequences according to claim 1, characterized in that, The step of mapping the frame rate ratio to an unsigned integer space corresponding to the integer mapping bit width, and determining the right boundary value of the interval and the packet stream identifier of each packet stream in the unsigned integer space, includes: Based on the frame rate ratio, calculate the proportion of each message stream in the total frame rate; Based on the proportion and the integer mapping bit width, the corresponding unsigned integer space is divided into multiple consecutive numerical intervals according to the proportion, wherein each message stream corresponds to a numerical interval, and the width of each numerical interval is proportional to the proportion of the corresponding message stream. The end value of the interval allocated to each message stream is determined as the right boundary value of the interval of the message stream, and a predefined unique number is used as the message stream identifier of the message stream.
3. The FPGA message flow scheduling method based on low-difference sequences according to claim 1, characterized in that, The step of constructing a configuration tuple based on the right boundary value of the interval and the corresponding message flow identifier includes: The right boundary value of the interval is combined with its corresponding message flow identifier to obtain a configuration record; The configuration records of each message stream are sorted in ascending order according to the right boundary value of the interval to obtain a sequence of configuration tuples.
4. The FPGA message flow scheduling method based on low-difference sequences according to claim 1, characterized in that, The FPGA-based low-discrepancy sequence generator generates current sequence values uniformly distributed in the unsigned integer space, including: An FPGA-based low-difference sequence generator calculates the next sequence value, which is uniformly distributed in the unsigned integer space, based on the pre-stored direction number and the previously generated sequence value, using a preset low-difference sequence recursion algorithm. The next sequence value is constrained to the valid range of the unsigned integer space, and the constrained next sequence value is used as the current sequence value.
5. The FPGA message flow scheduling method based on low-difference sequences according to claim 4, characterized in that, The preset low-discrepancy sequence recursion algorithm is as follows: ； in, The sequence value generated previously. For the next sequence value, Let c be the number of directions to be pre-stored, and c be the number of trailing zeros in the binary representation of n. This indicates a bitwise XOR operation.
6. The FPGA message flow scheduling method based on low-difference sequences according to claim 1, characterized in that, The step of determining the current message stream identifier to be sent by range matching based on the current sequence value and the configuration tuple includes: The current sequence value is compared with the right boundary value of the interval of each message stream by means of a binary search algorithm to obtain the sequence comparison result; Based on the sequence comparison results, the right boundary value of the minimum interval is obtained; Use the packet stream identifier corresponding to the determined minimum interval right boundary value as the current packet stream identifier to be sent.
7. The FPGA message flow scheduling method based on low-difference sequences according to claim 6, characterized in that, The process of obtaining the right boundary value of the minimum interval based on the sequence comparison result includes: Arrange all right boundary values of intervals in the configuration tuple that are greater than the current sequence value in ascending order of numerical value to obtain a candidate right boundary sequence; The smallest right boundary value of the interval is selected from the candidate right boundary sequence as the minimum right boundary value of the interval.
8. An FPGA message stream scheduling system based on low-difference sequences, characterized in that, include: The parameter acquisition module is used to respond to the multi-message stream generation command and obtain the frame rate ratio and integer mapping bit width of each message stream; The mapping configuration module is used to map the frame rate ratio to an unsigned integer space corresponding to the integer mapping bit width, and to determine the right boundary value of the interval and the packet stream identifier of each packet stream in the unsigned integer space; A configuration storage module is configured to construct a configuration tuple based on the right boundary value of the interval and the corresponding message stream identifier, and send it to the FPGA for storage. The sequence generation module is used to respond to message sending requests. Based on an FPGA-based low-difference sequence generator, it generates current sequence values that are uniformly distributed in the unsigned integer space. The stream selection module is used to determine the current message stream identifier to be sent by range matching based on the current sequence value and the configuration tuple; The message generation module is used to generate a message based on the current message stream identifier to be sent.
9. An electronic device, characterized in that, The system includes a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor causes the processor to perform the steps of the FPGA message flow scheduling method based on low-difference sequences as described in any one of claims 1-7.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the FPGA message flow scheduling method based on low-difference sequences as described in any one of claims 1-7.